JP2014011418A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for enhancing the performance of a semiconductor device.SOLUTION: An IGBT 50 includes a pcollector region 3 and an ndrift region 1, and a first transistor TR1 and a second transistor TR2 are formed on the ndrift region 1. The first transistor TR1 and second transistor TR2 are connected with an emitter electrode 12, and the pcollector region 3 is connected with a collector electrode 13. When the first transistor TR1 and second transistor TR2 are in the on state, a current consisting of electrons and holes flows through the first transistor TR1, but the current does not flow through the second transistor TR2. When the first transistor TR1 and second transistor TR2 are switched from on state to off state, a current consisting of holes flows through the first transistor TR1 and second transistor TR2.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and particularly to a semiconductor device including an insulated gate bipolar transistor and a technique effective when applied to the manufacturing.

  An insulated gate bipolar transistor (IGBT) is a semiconductor element mainly used as a current control device in the field of power electronics. This IGBT has three terminals consisting of a collector electrode provided on the back surface, an emitter electrode and a gate electrode provided on the front surface, and has a structure in which a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a bipolar transistor are compromised.

  The IGBT can flow a large current by utilizing the excessive accumulation effect of minority carriers. Therefore, as compared with a power device having another structure such as a power MISFET, it has a feature that a large current can flow in the on state and a high breakdown voltage can be maintained in the off state.

  Japanese Patent Laid-Open No. 2000-164859 (Patent Document 1) provides a p-type collector region, an n-type drift region, a p-type base region, and an n-type emitter region between a collector electrode and an emitter electrode. Furthermore, a technique is described for an IGBT in which a gate electrode is provided so as to be in contact with a base region through a gate insulating film.

In such an IGBT, a voltage required to turn on the IGBT is applied to the gate electrode while a voltage (collector voltage) is applied between the collector electrode and the emitter electrode. At this time, an inversion layer is formed in the p-type base region near the gate insulating film, and electrons begin to flow from the emitter electrode toward the collector electrode through the inversion layer. The impurity concentration in the n-type drift region is about 10 ¹⁴ (cm ⁻³ ), which is very low compared to the impurity concentration in silicon normally used as a conductor, so that the current when electrons start to flow is small. . However, when holes in the p-type collector region start to flow into the n-type drift region due to the diffusion current, electrons and holes are attracted to each other by the Coulomb attractive force in the n-type drift region. An excessive charge of 10 ¹⁶ (cm ⁻³ ) or more is accumulated. Such an effect is referred to as an excessive accumulation effect, and the resistance of the n-type drift region is reduced by the excessive accumulation effect, so that a large current can flow through the IGBT.

  On the other hand, when the IGBT is in an OFF state, as described above, since the impurity concentration of the n-type drift region is very low, no current flows and a high breakdown voltage can be maintained.

  For such IGBTs, various devices have been devised to promote the excessive accumulation effect, and one of the devices is the use of the IE (Injection Enhancement) effect. The IE effect is to increase the concentration of charges accumulated in the n-type drift region by making it difficult for holes to be discharged from the emitter electrode side when the IGBT is on.

  Japanese Patent Laying-Open No. 2005-209811 (Patent Document 2) describes a technique for increasing the concentration of charges accumulated in an n-type drift region by reducing the area of the emitter region as an IE effect. Has been. Japanese Patent Application Laid-Open No. 2008-288386 (Patent Document 3) discloses that an IE effect is utilized by using an n-type barrier region (hole barrier layer) between an n-type drift region and a p-type base region. Describes a technique for increasing the concentration of charges accumulated in the n-type drift region by providing. By using such an IE effect, the resistance on the emitter electrode side with respect to the drift region is increased, but the resistance of the drift region is further decreased. Therefore, the collector voltage (in order to flow the collector current determined by the rating) ( ON voltage) can be lowered.

  There is a latch-up problem as a problem that has a trade-off relationship with promoting the IE effect. This is a problem that if the concentration of holes in the drift region becomes too high due to the IE effect, a pnp parasitic bipolar transistor constituted by an inversion layer or the like is turned on and latched up. Japanese Patent Laid-Open No. 2001-127286 (Patent Document 4) describes a technique for forming a second emitter region that can flow only holes when the IGBT is in an ON state as a solution to this problem. Yes. Japanese Patent Laid-Open No. 2004-221370 (Patent Document 5) describes that when the IGBT is in an on state, a current composed of holes flows in the second emitter region and the IE effect is reduced. Describes a technique of inserting an n-type barrier region (hole barrier layer) into the second emitter region.

JP 2000-164859 A JP 2005-209811 A JP 2008-288386 A JP 2001-127286 A JP 2004-221370 A

  According to the study of the present inventor, the following has been found.

  If the area of the emitter region is further reduced or the impurity concentration of the n-type barrier region is increased to increase the IE effect, the on-voltage is reduced, but the IGBT is switched from the on state to the off state. There is a problem that power consumption (switching loss) increases. This is because when the IGBT is switched from the on state to the off state by lowering the voltage applied to the gate electrode to a voltage lower than the threshold voltage, holes accumulated at a high concentration in the drift region are emitted from the emitter electrode. It is a problem that occurs because it is difficult to be discharged to the side.

  For example, in the technique described in Patent Document 4 in which the second emitter region that allows only holes to flow when the IGBT is in the on state is formed, the IE effect when the IGBT is in the on state is reduced. The problem of reduced on-voltage cannot be solved. On the other hand, in the technique described in Patent Document 5 in which an n-type barrier region is inserted into the second emitter region, holes cannot be effectively discharged from the emitter electrode when the IGBT is in the off state. The switching loss problem cannot be solved. As a result, it is impossible to achieve both a reduction in on-voltage and a reduction in switching loss, which degrades the performance of the semiconductor device.

  An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

The semiconductor device according to a typical embodiment, p ⁺ collector region, and, n formed on the top surface side of the p ⁺ collector region ^- has a drift region, n ^- on the drift region, the first transistor And an IGBT in which a second transistor is formed. An emitter electrode is connected to the first transistor and the second transistor, and a collector electrode is connected to the p ⁺ collector region. When the first transistor and the second transistor are in the ON state, a current consisting of electrons and holes flows from the collector electrode to the emitter electrode through the first transistor, but no current flows through the second transistor. On the other hand, when the first transistor and the second transistor are switched from the on state to the off state, a current consisting of holes flows from the n ⁻ drift region through the first transistor and the second transistor to the emitter electrode.

In addition, a method of manufacturing a semiconductor device according to a representative embodiment includes a p ⁺ collector region and a substrate provided with an n ⁻ drift region formed on the upper surface side of the p ⁺ collector region and separated from each other. One transistor and a second transistor are formed. First, a semiconductor substrate including an n 2 ⁻ drift region and a semiconductor layer is prepared, and a pair of first trenches and a pair of second trenches are formed so as to penetrate the semiconductor layer. Next, a gate insulating film and a gate electrode are formed inside the pair of first trenches and the pair of second trenches. Next, a p ⁺ channel region, an n ⁺⁺ emitter region, and a p ⁺⁺ emitter region are formed in the first region sandwiched between the pair of first trenches, and in the second region sandwiched between the pair of second trenches, A p ^- channel region and a p ⁺⁺ emitter region are formed. Further, the distance between the pair of second trenches and W (m), p ^- the impurity concentration of the channel region and N _a (cm ^-3), the elementary charge and q (C), p ^- the dielectric constant of the channel region When ε (F / m) and the band gap of the p ⁻ channel region are V (eV), W <2 × 10 ⁻³ × (2Vε / (qN _a )) ^1/2 is satisfied.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the representative embodiment, the performance of the semiconductor device can be improved.

2 is a main-portion cross-sectional view of the semiconductor device of First Embodiment; FIG. 1 is a perspective view of a semiconductor device according to a first embodiment. In FIG. 1, it is the figure which showed typically the path | route through which an electric charge flows, when IGBT is an ON state. In FIG. 1, it is the figure which showed typically the path | route through which an electric charge flows when IGBT switches from an ON state to an OFF state. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. It is principal part sectional drawing of the semiconductor device of a comparative example. In FIG. 23, it is the figure which showed typically the path | route through which an electric charge flows when IGBT is in an ON state. In FIG. 23, it is the figure which showed typically the path | route through which an electric charge flows, when IGBT switches from an ON state to an OFF state. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 2; FIG. 6 is a perspective view of a semiconductor device according to a second embodiment. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 3; FIG. 6 is a perspective view of a semiconductor device according to a third embodiment. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during a manufacturing step thereof. FIG. 10 is a perspective view of a semiconductor device according to a fourth embodiment. FIG. 10 is a main-portion cross-sectional view of the semiconductor device of Embodiment 5; FIG. 10 is a perspective view of a semiconductor device according to a fifth embodiment. FIG. 25 is a main-portion cross-sectional view of the semiconductor device in Embodiment 5 during the manufacturing process; FIG. 10 is a perspective view of a semiconductor device according to a sixth embodiment. FIG. 20 is a main-portion cross-sectional view of the semiconductor device of Embodiment 7; FIG. 20 is a perspective view of a semiconductor device according to a seventh embodiment. FIG. 20 is a perspective view of a semiconductor device according to an eighth embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
<Semiconductor device>
A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The semiconductor device of the present embodiment is an insulated gate bipolar transistor (IGBT) provided with a first transistor and a second transistor as a MISFET.

  FIG. 1 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment. FIG. 2 is a perspective view of the semiconductor device of the first embodiment. 2 shows a state in which the interlayer insulating film 11 (see FIG. 1) and the emitter electrode 12 (see FIG. 1) are removed (see through) for easy understanding.

As shown in FIGS. 1 and 2, the IGBT 50 which is the semiconductor device of the first embodiment includes an n ⁻ drift region 1, an n ⁺ buffer region 2, a p ⁺ collector region 3, a p ⁺⁺ emitter region 4, a gate. An electrode 5, a gate insulating film 6, a p ⁺ channel region 7, an n ⁺⁺ emitter region 8, a p ⁻ channel region 9, a p well region 10, an interlayer insulating film 11, an emitter electrode 12 and a collector electrode 13 are provided.

The n ⁻ drift region 1 is an n-type semiconductor region (first conductivity type semiconductor region) made of silicon (Si) in which an n-type impurity such as phosphorus (P) or arsenic (As) is diffused. impurity concentration of n ^- drift region 1 is a relatively low concentration, it can be, for example, ^{5 × 10 13 ~5 × 10 14} cm -3 or so. Further, the thickness of the n 2 ⁻ drift region 1 can be set to, for example, about 40 to 300 μm.

The n ⁺ buffer region 2 is formed on the side opposite to the upper surface (first main surface) of the n ⁻ drift region 1, that is, on the lower surface (second main surface) side. For example, phosphorus (P) or arsenic (As ) And other n-type semiconductor regions (first conductivity type semiconductor regions) made of silicon (Si) diffused. The impurity concentration of the n ⁺ buffer region 2 is higher than the impurity concentration of the n ⁻ drift region 1 and can be, for example, about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ . Further, the thickness of the n ⁺ buffer region 2 can be set to about 1 to 20 μm, for example.

The p ⁺ collector region 3 is formed on the side opposite to the upper surface (first main surface) of the n ⁺ buffer region 2, that is, on the lower surface (second main surface) side, and is a p-type impurity such as boron (B). Is a p-type semiconductor region (second conductivity type semiconductor region) made of silicon (Si) diffused. The impurity concentration of the p ⁺ collector region 3 is relatively high, and can be, for example, about 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ . Further, the thickness of the p ⁺ collector region 3 can be set to about 0.1 to 200 μm, for example.

The n ⁺ buffer region 2 is an n-type semiconductor region formed between the n ⁻ drift region 1 and the p ⁺ collector region 3. Further, n ^- without forming the n ⁺ buffer region 2 between the drift region 1 and the p ⁺ collector region 3, n ^- drift region 1 and the p ⁺ collector region 3 is also a contact structure directly Good.

A semiconductor layer SL1 made of, for example, silicon (Si) is formed on the upper surface (first main surface) side of the n ⁻ drift region 1. A p ⁺⁺ emitter region 4, a gate electrode 5, a gate insulating film 6, a p ⁺ channel region 7, an n ⁺⁺ emitter region 8 and a p ⁻ channel region 9 are formed in the semiconductor layer SL1. A trench T is formed in the semiconductor layer SL1 so as to penetrate the semiconductor layer SL1. Specifically, trenches T1, T2, T3, and T4 are formed as the trench T. The thickness of the semiconductor layer SL1 can be set to about 1 to 5 μm, for example.

  The trenches T1 and T2 constitute a pair of trenches formed apart from each other. In plan view, a region sandwiched between the trenches T1 and T2 and the trenches T1 and T2 is defined as a first region AR1. At this time, the first transistor TR1 is formed in a region sandwiched between the trenches T1 and T2 in the trenches T1 and T2 and the semiconductor layer SL1. That is, the first transistor TR1 is formed in the first region AR1 in plan view.

  The trenches T3 and T4 constitute a pair of trenches formed apart from each other. In plan view, a region sandwiched between the trenches T3 and T4 and the trenches T3 and T4 is defined as a second region AR2. At this time, the second transistor TR2 is formed in a region sandwiched between the trenches T3 and T4 in the trenches T3 and T4 and the semiconductor layer SL1. That is, the second transistor TR2 is formed in the second region AR2 in plan view.

  Further, in plan view, a region between the first region AR1 and the second region AR2 is defined as a third region AR3. At this time, the p well region 10 is formed in a region between the trenches T2 and T3 in the semiconductor layer SL1. That is, the p well region 10 is formed in the third region AR3 in plan view.

  As shown in the perspective view of FIG. 2, the trenches T1, T2, T3, and T4 are formed along one direction (the Y direction in FIG. 2).

The p ⁺⁺ emitter region 4 is formed in the semiconductor layer SL1, and is a p-type semiconductor region made of silicon (Si) in which a p-type impurity such as boron (B) is diffused. As p ⁺⁺ emitter region 4, p ⁺⁺ emitter regions 4a, two of 4b are formed. The impurity concentration of the p ⁺⁺ emitter region 4 is higher than the impurity concentration of the p ⁺ collector region 3 and can be, for example, about 1 × 10 ^{18 to} 5 × 10 ²⁰ cm ⁻³ .

The p ⁺⁺ emitter region 4a is formed in the first region AR1 between the trenches T1 and T2 and at a position away from both the trenches T1 and T2. That is, the trench T1, T2 is a both sides of the p ⁺⁺ emitter regions 4a, are formed in each separated from the p ⁺⁺ emitter region 4a position.

The p ⁺⁺ emitter region 4b is formed in the second region AR2 between the trenches T3 and T4 and at a position away from both the trenches T3 and T4. That is, the trench T3, T4 is a both sides of the p ⁺⁺ emitter regions 4b, are formed in each separated from the p ⁺⁺ emitter regions 4b position.

The gate electrode 5 is a pair of electrodes formed on both sides of the p ⁺⁺ emitter region 4. As the gate electrode 5, a pair of gate electrodes 5a and 5b and a pair of gate electrodes 5c and 5d are formed. The gate electrode 5 is made of a polysilicon film in which n-type impurities such as phosphorus (P) and arsenic (As) are diffused at a high concentration, for example, and is a conductor film formed by, for example, a CVD (Chemical Vapor Deposition) method. is there.

Each of the gate electrodes 5a and 5b is an electrode formed inside each of the pair of trenches T1 and T2 in the first region AR1. As described above, since the pair of trenches T1 and T2 are formed on both sides of the p ⁺⁺ emitter region 4a, the gate electrodes 5a and 5b are also formed as a pair of gates formed on both sides of the p ⁺⁺ emitter region 4a. Electrode. However, although not shown, the gate electrodes 5a and 5b are electrically connected to each other at a position on the back side (or front side) of the cross section shown in FIG.

Each of the gate electrodes 5c and 5d is an electrode formed in each of the pair of trenches T3 and T4 in the second region AR2. As described above, since the pair of trenches T3 and T4 are formed on both sides of the p ⁺⁺ emitter region 4b, the gate electrodes 5c and 5d are also formed as a pair of gates formed on both sides of the p ⁺⁺ emitter region 4b. Electrode. However, although not shown, the gate electrodes 5c and 5d are electrically connected to each other at a position on the back side (or near side) of the cross section shown in FIG.

  The gate insulating film 6 covers the surface of the gate electrode 5. As the gate insulating film 6, four gate insulating films 6a, 6b, 6c, and 6d are formed. The gate insulating film 6 is made of, for example, a silicon oxide film, and is an insulating film formed by, for example, a thermal oxidation method or a CVD method before the gate electrode 5 is formed.

  Each of the gate insulating films 6a and 6b is formed on the inner wall of each of the pair of trenches T1 and T2 in the first region AR1, and covers the surface of each of the pair of gate electrodes 5a and 5b.

  Each of the gate insulating films 6c and 6d is formed on the inner wall of each of the pair of trenches T3 and T4 in the second region AR2, and covers the surface of each of the pair of gate electrodes 5c and 5d.

The p ⁺ channel region 7 is formed in a portion of the semiconductor layer SL1 sandwiched between the pair of trenches T1 and T2 in the first region AR1, for example, silicon (p-type impurities such as boron (B) diffused) This is a p-type semiconductor region (second conductivity type semiconductor region) made of Si). The p ⁺ channel region 7 is in contact with any of the p ⁺⁺ emitter region 4a, the gate insulating films 6a and 6b, and the n ⁻ drift region 1. The impurity concentration of the p ⁺ channel region 7 is lower than the impurity concentration of the p ⁺⁺ emitter region 4a, and can be, for example, about 5 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ .

The n ⁺⁺ emitter region 8 is formed in a portion of the semiconductor layer SL1 sandwiched between the pair of trenches T1 and T2 in the first region AR1, and for example, n-type such as phosphorus (P) or arsenic (As). It is an n-type semiconductor region (first conductivity type semiconductor region) made of silicon (Si) in which impurities are diffused. As n ⁺⁺ emitter region 8, n ⁺⁺ emitter region 8a, two of 8b are formed. The n ⁺⁺ emitter region 8a is in contact with any of the emitter electrode 12 (12a), the gate insulating film 6a, and the p ⁺ channel region 7, and the n ⁺⁺ emitter region 8b is connected to the emitter electrode 12 (12a) and the gate insulation. It is in contact with both the film 6b and the p ⁺ channel region 7. The impurity concentration of the n ⁺⁺ emitter region 8 (8a, 8b) is, n ^- a concentration higher than the impurity concentration of the drift region 1, for example, be a ^{1 × 10 18 ~5 × 10 20} cm -3 approximately it can.

In the second region AR2, the p ⁻ channel region 9 is formed in a portion of the semiconductor layer SL1 sandwiched between the pair of trenches T3 and T4. For example, silicon (p-type impurity such as boron (B)) is diffused. This is a p-type semiconductor region (second conductivity type semiconductor region) made of Si). The p ⁻ channel region 9 is in contact with any of the p ⁺⁺ emitter region 4 b, the gate insulating films 6 c and 6 d, and the n ⁻ drift region 1. The impurity concentration of the p ⁻ channel region 9 is lower than the impurity concentration of the p ⁺ channel region 7 and can be, for example, about 1 × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻³ .

The p ⁺⁺ emitter region 4a, the pair of gate electrodes 5a and 5b, the pair of gate insulating films 6a and 6b, the p ⁺ channel region 7 and the n ⁺⁺ emitter regions 8a and 8b constitute a first transistor TR1. The first transistor TR1 is a MISFET including a pair of gate electrodes 5a and 5b, a pair of gate insulating films 6a and 6b, and a p ⁺ channel region 7.

The p ⁺⁺ emitter region 4b, the pair of gate electrodes 5c and 5d, the pair of gate insulating films 6c and 6d, and the p ⁻ channel region 9 constitute a second transistor TR2. The second transistor TR2 is a MISFET including a pair of gate electrodes 5c and 5d, a pair of gate insulating films 6c and 6d, and a p ⁻ channel region 9.

As shown in the perspective view of FIG. 2, the trenches T1, T2, T3, and T4 are formed along one direction (Y direction in FIG. 2). As a result, the p ⁺⁺ emitter region 4 (4a), the p ⁺ channel region 7 and the n ⁺⁺ emitter region 8 (8a, 8b) formed between the pair of trenches T1 and T2 are unidirectional (FIG. 2). In the Y direction). Further, the p ⁺⁺ emitter region 4 (4b) and the p ⁻ channel region 9 formed between the pair of trenches T3 and T4 are formed along one direction (Y direction in FIG. 2). Furthermore, the gate electrode 5 (5a, 5b, 5c, 5d) and the gate insulating film 6 (6a, 6b, 6c, 6d) formed in the trenches T1, T2, T3, T4 are also unidirectional ( It is formed along the Y direction in FIG.

The p well region 10 is formed in the semiconductor layer SL1 in the third region AR3, and is a p type semiconductor region made of silicon (Si) in which a p type impurity such as boron (B) is diffused. The p-well region 10 facilitates movement of holes toward the first transistor TR1 or the second transistor TR2. The impurity concentration of the p-well region 10 can be set to about 5 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ , for example.

The interlayer insulating film 11 is an insulating film formed on the upper surface (first main surface) side of the semiconductor layer SL1. In the interlayer insulating film 11, contact holes CH1 and CH2 are formed in a portion on the p ⁺⁺ emitter region 4 in plan view. Specifically, in the first region AR1, a contact hole CH1 is formed in a portion of the interlayer insulating film 11 on the p ⁺⁺ emitter region 4a. In the second region AR2, the contact hole CH1 is formed. A contact hole CH2 is formed in a portion on the p ⁺⁺ emitter region 4b. For example, a silicon oxide film can be used as the interlayer insulating film 11.

The emitter electrode 12 is an electrode that covers the upper surface of the interlayer insulating film 11 and fills the contact holes CH1 and CH2. The emitter electrode 12 is electrically connected to the p ⁺⁺ emitter region 4 and the n ⁺⁺ emitter region 8 constituting the first transistor TR1, and the p ⁺⁺ emitter region 4 and p ⁻ constituting the second transistor TR2. The channel region 9 is electrically connected.

Of the emitter electrode 12, the portion formed to fill the contact hole CH1 in the first region AR1 is referred to as an emitter electrode 12a, and the portion formed to fill the contact hole CH2 in the second region AR2 is the emitter electrode 12b. And At this time, in the first region AR1, the emitter electrode 12a is electrically connected to the p ⁺⁺ emitter region 4a and the n ⁺⁺ emitter regions 8a and 8b. In the second region AR2, the emitter electrode 12b is p ⁺⁺ Electrically connected to emitter region 4b and p ⁻ channel region 9.

As the emitter electrode 12 (12a, 12b), a laminated conductor film in which a barrier conductor film made of, for example, a titanium tungsten (TiW) film and a conductor film made of, for example, an aluminum (Al) film can be used. By using such a laminated conductor film, the p ⁺⁺ emitter regions 4a and 4b, the n ⁺⁺ emitter regions 8a and 8b and the p ⁻ channel region 9 and the emitter electrode 12 are electrically connected with low resistance. be able to.

  In the semiconductor layer SL1, a recess CC1 is formed at the same position as the contact hole CH1 in plan view, and the emitter electrode 12a is formed so as to fill the recess CC1 and the contact hole CH1. The semiconductor layer SL1 has a recess CC2 at the same position as the contact hole CH2 in plan view, and the emitter electrode 12b is formed to fill the recess CC2 and the contact hole CH2.

The collector electrode 13 is an electrode formed on the lower surface (second main surface) side of the p ⁺ collector region 3. Collector electrode 13 is electrically connected to p ⁺ collector region 3. As the collector electrode 13, a conductor film made of a metal such as aluminum (Al) or an alloy such as aluminum silicon (AlSi) can be used. By using such a conductor film, the collector electrode 13 and the p ⁺ collector region 3 can be electrically connected with low resistance.

  In the first embodiment, the first transistor TR1 and the second transistor TR2 are adjacent to each other along one direction (Y direction in FIG. 2).

  As shown in FIG. 2, in the IGBT 50, first transistors TR11 and TR12 are formed as the first transistor TR1, and second transistors TR21 and TR22 are formed as the second transistor TR2. The first transistor TR11 and the second transistor TR22 are adjacent to each other along one direction (Y direction in FIG. 2), and the first transistor TR12 and the second transistor TR21 are adjacent to each other.

  In the first transistor TR11, trenches T11 and T21 are formed as a pair of trenches T1 and T2, and in the second transistor TR21, trenches T31 and T41 are formed as a pair of trenches T3 and T4. In the first transistor TR12, trenches T12 and T22 are formed as a pair of trenches T1 and T2, and in the second transistor TR22, trenches T32 and T42 are formed as a pair of trenches T3 and T4. Each of the pair of trenches T32 and T42 is formed continuously with each of the pair of trenches T11 and T21 along one direction (the Y direction in FIG. 2). In addition, each of the pair of trenches T12 and T22 is formed continuously with each of the pair of trenches T31 and T41 along one direction (the Y direction in FIG. 2).

As a result, as shown in FIG. 2, the p ⁺⁺ emitter region 4b in the second transistor TR22 is continuous with the p ⁺⁺ emitter region 4a in the first transistor TR11 along one direction (the Y direction in FIG. 2). Is formed. In addition, each of the gate electrodes 5c and 5d in the second transistor TR22 is formed continuously with each of the gate electrodes 5a and 5b in the first transistor TR11 along one direction (Y direction in FIG. 2). In addition, each of the gate insulating films 6c and 6d in the second transistor TR22 is formed continuously with each of the gate insulating films 6a and 6b in the first transistor TR11 along one direction (Y direction in FIG. 2). Yes. The p ⁻ channel region 9 in the second transistor TR22 is adjacent to the p ⁺ channel region 7 and the n ⁺⁺ emitter regions 8a and 8b in the first transistor TR11 along one direction (the Y direction in FIG. 2). Is formed.

  Further, the positional relationship between the first transistor TR12 and the second transistor TR21 adjacent in one direction (the Y direction in FIG. 2) is also between the first transistor TR11 and the second transistor TR22 described above. This is the same as the positional relationship adjacent to each other in one direction (Y direction in FIG. 2).

  With such a configuration, the gate voltage applied to the gate electrodes 5a and 5b of the first transistor TR1 and the gate voltage applied to the gate electrodes 5c and 5d of the second transistor TR2 can be collectively controlled.

  Hereinafter, in this specification, the interval W1 between the pair of trenches T1 and T2 in which each of the gate insulating films 6a and 6b and each of the gate electrodes 5a and 5b is formed is defined as the first transistor TR1. It is defined as the distance between gates. Further, the distance W2 between the pair of trenches T3 and T4 in which each of the gate insulating films 6c and 6d and each of the gate electrodes 5c and 5d is formed is defined as the inter-gate distance of the second transistor TR2. To do.

In the first embodiment, the inter-gate distance W2 of the second transistor TR2 and W (m), p ^- the impurity concentration of the channel region 9 and N _a (cm ^-3), the electrons and holes elementary charge q When (C), the dielectric constant of the p ⁻ channel region 9 is ε (F / m), and the band gap of the p ⁻ channel region 9 is V (eV), the following formula (1)
W <2 × 10 ⁻³ × (2Vε / (qN _a )) ^1/2 (1)
It is preferable to satisfy. Specifically, when the p ⁻ channel region 9 is made of silicon (Si) and the dielectric constant of silicon (Si) is ε _si (F / m), the impurity concentration N _a of the p ⁻ channel region 9 is expressed by the following formula. (2)
W <2 × 10 ⁻³ × (2ε _si / (qN _a )) ^1/2 (2)
It is preferable to perform ion implantation so that the concentration satisfies the above.

  In the first embodiment, as described above, each of the trenches T32 and T42 of the second transistor TR22 extends along one direction (the Y direction in FIG. 2) of the trenches T11 and T21 of the first transistor TR11. Each is formed continuously. Further, each of the trenches T12 and T22 of the first transistor TR12 is formed continuously with each of the trenches T31 and T41 of the second transistor TR21 along one direction (Y direction in FIG. 2). As a result, the interval W1 between the pair of trenches T11 and T21 and the pair of trenches T12 and T22 is equal to the interval W2 between the pair of trenches T31 and T41 and the pair of trenches T32 and T42.

The distance between the pair of trenches T11 and T21 and the pair of trenches T12 and T22 is equal to the distance between the gate insulating films 6a and 6b, that is, the width of the p ⁺ channel region 7. Therefore, when the thickness of the gate insulating films 6a and 6b is smaller than the width of the p ⁺ channel region 7, the inter-gate distance W1 in the first transistor TR1 is substantially equal to the interval between the gate electrodes 5a and 5b.

The distance between the pair of trenches T31 and T41 and the pair of trenches T32 and T42 is equal to the distance between the gate insulating films 6c and 6d, that is, the width of the p ⁻ channel region 9. Therefore, when the thickness of the gate insulating films 6c and 6d is smaller than the width of the p ⁻ channel region 9, the inter-gate distance W2 in the second transistor TR2 is substantially equal to the interval between the gate electrodes 5c and 5d.

<Operation of semiconductor device>
Next, the operation of the IGBT 50 that is the semiconductor device of the first embodiment will be described.

  FIG. 3 is a diagram schematically showing a path through which charges flow when the IGBT is on in FIG. FIG. 4 is a diagram schematically showing a path through which charges flow when the IGBT is switched from the on state to the off state in FIG.

  First, an on operation for turning on the IGBT 50 will be described.

First, a predetermined voltage (collector voltage) is applied to the collector electrode 13 so that the potential of the collector electrode 13 becomes a predetermined positive potential with respect to the potential of the emitter electrode 12. Specifically, for example, the collector voltage Vc is applied to the collector electrode 13 with the emitter electrode 12 grounded. As a result, holes are injected from collector electrode 13 into n ⁻ drift region 1 through p ⁺ collector region 3 and n ⁺ buffer region 2.

  In this state, a predetermined voltage is applied to the gate electrodes 5a, 5b, 5c, and 5d so that the potential of the gate electrodes 5a, 5b, 5c, and 5d becomes a predetermined positive potential with respect to the emitter electrode 12. Specifically, for example, the gate voltage Vg1 is applied to the gate electrodes 5a, 5b, 5c, and 5d with the emitter electrode 12 grounded. The gate voltage Vg1 is a voltage for turning on the first transistor TR1 and the second transistor TR2. For example, the gate voltage Vg1 is higher than both the threshold voltage of the first transistor TR1 and the threshold voltage of the second transistor TR2.

In the first transistor TR1, the gate voltage Vg1 is applied to the gate electrodes 5a and 5b, so that the p ⁺ channel region 7 comes into contact with the gate insulating films 6a and 6b, that is, from the gate insulating films 6a and 6b, for example. In a region of about 10 nm, the inversion layers 7a and 7b are formed (on state). Then, electrons from the emitter electrode 12a is, as shown the path in FIG. 3 as PS1, n ⁺⁺ emitter region 8a, each 8b, and the formed inversion layer 7a, through each of 7b, n ^- drift Injected into region 1 (flowed in).

As described above, since the collector voltage Vc is applied to the collector electrode 13, holes are injected (flowed) from the collector electrode 13 into the n ⁻ drift region 1. As a result, the electrons injected (flowed in) from the emitter electrode 12a into the n ⁻ drift region 1 and the holes injected (flowed in) into the n ⁻ drift region 1 from the collector electrode 13 are n ^−. In order to attract by the Coulomb attractive force in the drift region 1, excess charges of, for example, 10 ¹⁶ (cm ⁻³ ) or more are accumulated in the n ⁻ drift region 1. This excessive accumulation effect, n ^- the resistance value of the drift region 1 is reduced, it is possible to flow a large on-current IGBT. That is, the IGBT 50 is turned on.

In the first transistor TR1, when the gate insulating film 6a of p ⁺ channel region 7, the region in contact with 6b is an inversion layer 7a, the state where 7b is formed (on state), the gate insulating among the p ⁺ channel region 7 A depletion layer (not shown) is formed in a region slightly away from the films 6a and 6b. Therefore, the holes from the n ⁻ drift region 1 are portions other than the inversion layers 7a and 7b and the depletion layer (not shown) in the p ⁺ channel region 7, as shown by the path PS2 in FIG. The light is discharged (flows out) to the emitter electrode 12a through the central portion.

On the other hand, in the second transistor TR2, the gate voltages Vg1 are applied to the gate electrodes 5c and 5d, so that the inversion layers 9a and 9b are formed in the p ⁻ channel region 9 in the region in contact with the gate insulating films 6c and 6d. Is turned on (on state). However, in the second transistor TR2, unlike the first transistor TR1, the n ⁺⁺ emitter regions 8a and 8b are not formed, and the emitter electrode 12b and the inversion layers 9a and 9b are separated from each other. Are not injected (does not flow) into the n ⁻ drift region 1.

In addition, even the second transistor TR2, p ^- when the gate insulating film 6c of the channel region 9, the region in contact with 6d is an inversion layer 9a, state 9b is formed (on state), p ^- of the channel region 9 A depletion layer (not shown) is formed in a region slightly apart from the gate insulating films 6c and 6d.

As described above, in the present specification, the first transistor TR1 being in the ON state means that the inversion layers 7a and 7b are formed in the p ⁺ channel region 7. Further, the first transistor TR1 being in the OFF state means that the inversion layers 7a and 7b have disappeared in the p ⁺ channel region 7. On the other hand, the second transistor TR2 being in the ON state means that the inversion layers 9a and 9b are formed in the p ⁻ channel region 9. Further, the second transistor TR2 being in the OFF state means that the inversion layers 9a and 9b have disappeared in the p ⁻ channel region 9.

Here, the width L _D of the depletion layer when the depletion layer is formed is expressed by the following formula (3).
L _D = 10 ⁻³ × (2ε _si V / (qN _a )) ^1/2 (3)
It is represented by However, in the above formula (3), N _a (cm ⁻³ ) is the impurity concentration of the p ⁻ channel region 9, q (C) is the elementary charge of electrons and holes, and ε _si (F / m) Is the dielectric constant of silicon (Si). Further, at the interface between the gate insulating films 6c and 6d of the p ⁻ channel region 9, the energy band is bent to the extent necessary for forming the inversion layer, and the bending amount of this energy band is V (eV).

Here, the bending amount V of the energy band is about 1 (eV) corresponding to the band gap of silicon (Si). Therefore, the width L _D of the depletion layer formed at the interface with one of the gate insulating films 6c and 6d in the p ⁻ channel region 9 is the following formula (4) where V = 1 (eV) in the above formula (3). )
L _D = 10 ⁻³ × (2ε _si / (qN _a )) ^1/2 (4)
It is represented by If the inter-gate distance W2 of the second transistor TR2 is W (m), W (m) is the width of the depletion layer formed at the interface with each of the gate insulating films 6c and 6d in the p ⁻ channel region 9. When smaller than the sum of L _D , that is, the following formula (5)
W <2L _D (5)
When satisfied, the entire p ⁻ channel region 9 is depleted.

The above formula (2) is a combination of the above formula (5) and the above formula (4). Therefore, when the relationship of the above formula (2) is satisfied, the entire p ⁻ channel region 9 is depleted when the second transistor TR2 is in the on state, and therefore the holes in the n ⁻ drift region 1 are changed to p ^- can be prevented from being discharged through the channel region 9 to the emitter electrode 12b (not flow out). As a result, even when the second transistor TR2 is formed, the characteristics of the IGBT in the on state can be made the same as when the second transistor TR2 is not formed.

In the above formula (2), for example, N _a = 10 ¹⁶ (cm ⁻³ ), q = 1.6 × 10 ⁻¹⁹ (C), and ε _si = 10.4 × 10 ⁻¹⁰ (F / m) Then, the inter-gate distance W becomes less than 0.72 μm.

The gate distance W1, W2 are equal to each other, even if satisfying the above formula (2) when the gate length W2 was is W, the impurity concentration N _a of the p ⁺ channel region 7 p ^- impurity in the channel region 9 if sufficiently higher than the concentration N _a, it does not satisfy the above expression (2) when the gate length W1 was W. That is, the impurity concentration N _a of the p ⁺ channel region 7, p ^- when sufficiently higher than the impurity concentration N _a in the channel region 9, even if the inter-gate distance W1, W2 are equal to each other, the first transistor TR1 is turned on In the state, the entire p ⁺ channel region 7 is not depleted. Therefore, when the first transistor TR1 is in the ON state, holes in the n ⁻ drift region 1 are discharged (flowed out) to the emitter electrode 12a through the p ⁺ channel region 7.

  That is, when the collector voltage is applied to the collector electrode 13 and the first transistor TR1 and the second transistor TR2 are on, holes (positive) are transmitted from the collector electrode 13 to the emitter electrode 12a through the first transistor TR1. Current of negative polarity) and electrons (negative polarity charge) flows. However, no current flows through the second transistor TR2.

  Next, an operation for switching the IGBT 50 from the on state to the off state will be described.

  In a state where a predetermined voltage (collector voltage) Vc is applied to the collector electrode 13, the application of the gate voltage Vg1 to the gate electrodes 5a, 5b, 5c, and 5d is stopped. Specifically, for example, the gate voltage Vg2 for switching the first transistor TR1 and the second transistor TR2 from the on state to the off state is applied to the gate electrodes 5a, 5b, 5c, and 5d with the emitter electrode 12 grounded. Alternatively, the gate electrodes 5a, 5b, 5c, and 5d are grounded. The gate voltage Vg2 is, for example, a voltage lower than both the threshold voltage of the first transistor TR1 and the threshold voltage of the second transistor TR2.

In the first transistor TR1, the application of the gate voltage Vg1 to the gate electrodes 5a and 5b is stopped, so that the inversion layers 7a and 7b formed in the p ⁺ channel region 7 disappear in the ON state, and the emitter Electron injection (flow) from the electrode 12a into the n ⁻ drift region 1 is stopped. Also, the holes accumulated excessively in the n ⁻ drift region 1 in the on state are discharged to the emitter electrode 12a through the p ⁺ channel region 7 as shown by the path PS3 in FIG. Flows out). However, electrons cannot flow through the p ⁺ channel region 7.

On the other hand, in the second transistor TR2, the application of the gate voltage Vg1 to the gate electrodes 5c and 5d is stopped, so that the inversion layers 9a and 9b and the depletion layer formed in the p ⁻ channel region 9 when the transistor is turned on. (Illustration omitted) disappears. Also, the holes accumulated excessively in the n ⁻ drift region 1 in the on state are discharged to the emitter electrode 12b through the p ⁻ channel region 9 as shown by the path PS4 in FIG. (Flows out). However, electrons cannot flow through the p ⁻ channel region 9.

That is, when the first transistor TR1 and the second transistor TR2 are switched from the on state to the off state, the n ⁻ drift region 1 passes through the first transistor TR1 and the second transistor TR2 to the emitter electrodes 12a and 12b. A current composed of holes (positive polarity charges) flows.

<Manufacturing process of semiconductor device>
Next, an example of a manufacturing process of the semiconductor device according to the first embodiment will be described with reference to the drawings. 5 to 22 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of First Embodiment.

  First, the semiconductor substrate 3S is prepared.

In the step of preparing the semiconductor substrate 3S, as shown in FIG. 5, a semiconductor substrate 3S made of an n-type silicon (Si) substrate into which an n-type impurity such as phosphorus (P) is introduced is prepared. Semiconductor substrate 3S is, n mentioned above ^- is a moiety comprising a drift region 1 (see FIG. 1), as will be described later with reference to FIG. 22, in a portion of the back surface (lower surface) side, n ⁺ buffer region 2 (See FIG. 1) and p ⁺ collector region 3 (see FIG. 1) are formed.

With respect to such a semiconductor substrate 3S, for example, a pure silicon (Si) substrate that is not substantially implanted with impurities is irradiated with a high-energy neutron beam to convert some silicon (Si) atoms into phosphorus (P) atoms. By performing nuclear conversion, an n-type Si substrate having an impurity concentration of, for example, about 8 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻³ can be prepared.

  Next, the semiconductor layer SL1 is formed.

In the step of forming the semiconductor layer SL1, a p-type impurity such as boron (B) is introduced from the surface (upper surface) side of the semiconductor substrate 3S, for example, by an ion implantation method. As a result, as shown in FIG. 6, the p-type semiconductor layer SL1 is formed on the surface (upper surface) side portion (upper layer) of the semiconductor substrate 3S, and the surface (upper surface) side portion (upper layer portion) of the semiconductor substrate 3S. The portion other than () becomes the n ⁻ drift region 1. The semiconductor layer SL1 is a portion that becomes the p ⁺⁺ emitter region 4, the p ⁺ channel region 7, the n ⁺⁺ emitter region 8 or the p ⁻ channel region 9 as described with reference to FIG. As described above, the thickness of the semiconductor layer SL1 can be set to, for example, about 1 to 5 μm.

  Next, a silicon oxide film 21 is formed.

  In the step of forming the silicon oxide film 21, as shown in FIG. 7, the silicon oxide film 21 is formed on the semiconductor layer SL1 of the semiconductor substrate 3S. The silicon oxide film 21 can be formed by a wet oxidation method in a state where the substrate temperature of the semiconductor substrate 3S is maintained at about 1000 ° C., for example.

  Next, as shown in FIG. 8, the silicon oxide film 21 is patterned by using a photolithography technique and an etching technique. The patterning of the silicon oxide film 21 is performed so as to form an opening OP in the silicon oxide film 21 by removing the silicon oxide film 21 in a region where a trench T described later is formed (see FIG. 9 described later). As shown in FIG. 8, in the first region AR1, a pair of openings OP1 and OP2 are formed as the opening OP, and in the second region AR2, a pair of openings OP3 and OP4 are formed as the opening OP. The first region AR1 is a region where the first transistor TR1 (see FIG. 1) is formed in plan view, and the second region AR2 is formed with the second transistor TR2 (see FIG. 1) in plan view. It is an area. Further, the area between the first area AR1 and the second area AR2 in the plan view is the third area AR3.

  Next, the trench T is formed.

In the step of forming the trench T, as shown in FIG. 9, the trench T is formed in the semiconductor layer SL1 by etching using the silicon oxide film 21 in which the opening OP is formed as a mask. The trench T is formed so as to penetrate the semiconductor layer SL1 and reach the n ⁻ drift region 1 in the first region AR1 and the second region AR2. In the first region AR1, a pair of trenches T1 and T2 are formed as the trench T, and in the second region AR2, a pair of trenches T3 and T4 are formed as the trench T.

As shown in FIG. 9, the interval between the pair of trenches T1 and T2 is W1, and the interval between the pair of trenches T3 and T4 is W2. At this time, it is preferable that the distance W2 between the pair of trenches T3 and T4 satisfy the following relationship. That is, the distance W2 between W (m), p ^- the impurity concentration of the channel region 9 (see FIG. 1) and N _a (cm ^-3), and the electrons and holes elementary charge and q (C), p ^- When the dielectric constant of the channel region 9 is ε (F / m) and the band gap of the p ⁻ channel region 9 is V (eV), it is preferable that the interval satisfy the above formula (1).

  Further, in the first embodiment, as shown in FIG. 2, the first transistor TR1 and the second transistor TR2 are formed adjacent to each other along one direction (Y direction in FIG. 2). That is, in the step of forming the trench T, as shown in FIG. 2, each of the trenches T32 and T42 of the second transistor TR22 extends along one direction (Y direction in FIG. 2) of the first transistor TR11. Each of the trenches T11 and T21 is formed continuously. Further, each of the trenches T12 and T22 of the first transistor TR12 is formed continuously with each of the trenches T31 and T41 of the second transistor TR21 along one direction (Y direction in FIG. 2). Therefore, as also shown in FIG. 9, the interval W1 between the pair of trenches T1 and T2 is equal to the interval W2 between the pair of trenches T3 and T4.

  Next, the gate insulating film 6 is formed.

In the step of forming the gate insulating film 6, the gate insulating film 6 is formed on the inner wall of the trench T as shown in FIG. The gate insulating film 6 can be a silicon oxide film, for example, and can be formed by oxidizing the semiconductor layer SL1 exposed on the inner wall of the trench T by, for example, a thermal oxidation method. However, the gate insulating film 6 is not limited to the silicon oxide film, and can be variously changed. For example, a silicon oxynitride (SiON) film can be used. Alternatively, the gate insulating film 6 can be a high dielectric constant film having a higher dielectric constant than, for example, a silicon oxide film, and can be a high dielectric film, for example, a hafnium oxide (HfO ₂ ) film.

  In the first embodiment, in the step of forming the gate insulating film 6, as shown in FIG. 2, each of the pair of gate insulating films 6c and 6d is formed on the inner wall of each of the pair of trenches T32 and T42. Are continuously formed along one direction (the Y direction in FIG. 2) with each of the pair of gate insulating films 6a and 6b. Further, on each inner wall of the pair of trenches T12 and T22, each of the pair of gate insulating films 6a and 6b extends along one direction (Y direction in FIG. 2) with each of the pair of gate insulating films 6c and 6d. It is formed continuously.

  Next, a polysilicon film 22 is formed.

  In the step of forming the polysilicon film 22, the polysilicon film 22 is formed on the silicon oxide film 21, as shown in FIG. At this time, the polysilicon film 22 is formed so as to fill the trench T in which the gate insulating film 6 is formed on the inner wall. As the polysilicon film 22, for example, an n-type impurity such as phosphorus (P) or arsenic (As) can be diffused at a high concentration, and can be formed by, for example, a CVD method.

  Next, the gate electrode 5 is formed.

  In the step of forming the gate electrode 5, the polysilicon film 22 formed on the silicon oxide film 21 is removed by the entire surface etch back by dry etching, and the silicon oxide film 21 is removed by the dry etching technique. Thereby, as shown in FIG. 12, the gate electrode 5 having a structure in which the polysilicon film 22 is buried in the trench T is formed. As the gate electrode 5, each of the gate electrodes 5a, 5b, 5c, and 5d is formed in each of the trenches T1, T2, T3, and T4.

  In the first embodiment, as shown in FIG. 2, the pair of gate electrodes is embedded so as to bury each of the pair of trenches T32 and T42 in which the pair of gate insulating films 6c and 6d are formed on the inner wall. Each of 5c and 5d is formed continuously with each of the pair of gate electrodes 5a and 5b along one direction (Y direction in FIG. 2). In addition, each of the pair of gate electrodes 5a and 5b is unidirectional (Y direction in FIG. 2) so as to embed each of the pair of trenches T12 and T22 in which the pair of gate insulating films 6a and 6b is formed on the inner wall ) Along each of the pair of gate electrodes 5c and 5d.

Next, the p ⁺ channel region 7 is formed.

In the step of forming the p ⁺ channel region 7, a resist film R1 is applied on the semiconductor substrate 3S. Then, the resist film R1 is subjected to exposure / development processing using a photolithography technique to pattern the resist film R1 as shown in FIG. The patterning of the resist film R1 is performed so that the second region AR2 and the third region AR3 are covered and the first region AR1 is exposed. Then, a p-type impurity such as boron (B) is introduced into the semiconductor layer SL1 by an ion implantation method using the patterned resist film R1 as a mask. As a result, the p ⁺ channel region 7 is formed in the portion of the semiconductor layer SL1 that is not covered with the resist film R1 in the first region AR1. The p ⁺ channel region 7 is formed between the pair of trenches T1 and T2 such that both sides thereof are in contact with the trenches T1 and T2 and the lower side thereof is in contact with the n ⁻ drift region 1. As described above, the impurity concentration of the p ⁺ channel region 7 can be set to about 5 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ , for example.

Further, by forming the p ⁺ channel region 7, in the first region AR1, the first transistor which is a MISFET including the gate electrodes 5a and 5b, the gate insulating films 6a and 6b, and the p ⁺ channel region 7 in the semiconductor layer SL1. TR1 is formed.

Next, an n ⁺⁺ emitter region 8 is formed.

In the step of forming the n ⁺⁺ emitter region 8, as shown in FIG. 14, n-type impurities are introduced into the semiconductor layer SL1 by ion implantation using the patterned resist film R1 as a mask. Specifically, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced above the p ⁺ channel region 7 which is a p-type semiconductor region so as to completely cancel the p-type semiconductor region. . As a result, an n ⁺⁺ emitter region 8 is formed above the p ⁺ channel region 7 in the portion of the semiconductor layer SL1 that is not covered with the resist film R1 in the first region AR1. The n ⁺⁺ emitter region 8 is formed between the pair of trenches T1 and T2 so that both sides thereof are in contact with the trenches T1 and T2. As described above, the impurity concentration of the n ⁺⁺ emitter region 8 can be, for example, about 1 × 10 ^{18 to} 5 × 10 ²⁰ cm ⁻³ .

Next, the p ⁻ channel region 9 is formed.

In the step of forming the p ⁻ channel region 9, after removing the patterned resist film R 1, a resist film R 2 is applied on the semiconductor substrate 3 S. Then, the resist film R2 is subjected to exposure / development processing using a photolithography technique to pattern the resist film R2 as shown in FIG. The patterning of the resist film R2 is performed so that the first region AR1 and the third region AR3 are covered and the second region AR2 is exposed. Then, a p-type impurity such as boron (B) is introduced into the semiconductor layer SL1 by ion implantation using the patterned resist film R2 as a mask. As a result, the p ⁻ channel region 9 is formed in the portion of the semiconductor layer SL1 that is not covered with the resist film R2 in the second region AR2. The p ⁻ channel region 9 is formed between the pair of trenches T3 and T4 so that both sides thereof are in contact with the trenches T3 and T4. As described above, the impurity concentration of the p ⁻ channel region 9 can be set to about 1 × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻³ , for example.

Further, p ^- by forming the channel region 9, in the second region AR2, the semiconductor layer SL1, gate electrode 5c, 5d, the gate insulating film 6c, 6d, p ^- second transistor is a MISFET including a channel region 9 TR2 is formed.

In the first embodiment, in the step of forming the p ⁺ channel region 7, the n ⁺⁺ emitter region 8 and the p ⁻ channel region 9 by the ion implantation method, as shown in FIG. Ion implantation is performed so that the first transistor TR11 and the second transistor TR22 are adjacent to each other along the Y direction). Further, as shown in FIG. 2, ion implantation is performed so that the first transistor TR12 and the second transistor TR21 are adjacent to each other along one direction (Y direction in FIG. 2). That is, the p ⁻ channel region 9 is formed adjacent to the p ⁺ channel region 7 and the n ⁺⁺ emitter region 8 along one direction (Y direction in FIG. 2).

  Next, the p-well region 10 is formed.

In the step of forming the p-well region 10, after removing the patterned resist film R2, a resist film R3 is applied on the semiconductor substrate 3S. Then, the resist film R3 is subjected to exposure / development processing using a photolithography technique to pattern the resist film R3 as shown in FIG. The patterning of the resist film R3 is performed so that the first region AR1 and the second region AR2 are covered and the third region AR3 is exposed. Then, a p-type impurity such as boron (B) is introduced into the semiconductor layer SL1 by ion implantation using the patterned resist film R3 as a mask. As a result, the p well region 10 is formed in a portion of the semiconductor layer SL1 that is not covered with the resist film R3 in the third region AR3. The p well region 10 is formed so that both sides thereof are in contact with the trenches T2 and T3. As described above, the impurity concentration of the p-well region 10 can be set to about 5 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ , for example.

Note that the steps of forming the p ⁺ channel region 7, the n ⁺⁺ emitter region 8, the p ⁻ channel region 9 and the p well region 10 are not limited to the above-described order, and may be performed in any order. . In addition, with respect to the process of forming the p ⁺ channel region 7, the n ⁺⁺ emitter region 8, the p ⁻ channel region 9 and the p well region 10, for example, 1050 ° C. after each step or after all the steps are completed. The implanted impurities can be activated by performing a heat treatment to the extent.

  Next, recesses CC1 and CC2 are formed.

In the step of forming the recesses CC1 and CC2, after removing the patterned resist film R3, a resist film R4 is applied on the semiconductor substrate 3S. Then, the resist film R4 is subjected to exposure / development processing using a photolithography technique to pattern the resist film R4 as shown in FIG. The patterning of the resist film R4 is performed so that the portion of the first region AR1 where the p ⁺⁺ emitter region 4a is formed and the portion of the second region AR2 where the p ⁺⁺ emitter region 4b is formed are exposed. Is called. Then, using the patterned resist film R4 as a mask, recesses CC1 and CC2 are formed in the semiconductor layer SL1 by using a photolithography technique and an etching technique. In the first region AR1, the recess CC1 is formed so as to penetrate the n ⁺⁺ emitter region 8 and reach the p ⁺ channel region 7. At this time, in the first region AR1, the recess CC1 is formed, and the n ⁺⁺ emitter region 8 is divided by the recess CC1, thereby forming two n ⁺⁺ emitter regions 8a and 8b. Further, the p ⁺ channel region 7 is exposed at the bottom surface of the recess CC1, and the p ⁻ channel region 9 is exposed at the bottom surface of the recess CC2.

  In the first embodiment, in the step of forming the recesses CC1 and CC2, as shown in FIG. 2, the recess CC2 in the second transistor TR22 extends along one direction (Y direction in FIG. 2). It is formed continuously with the recess CC1 in the first transistor TR11. Further, the recess CC1 in the first transistor TR12 is formed continuously with the recess CC2 in the second transistor TR21 along one direction (Y direction in FIG. 2).

  Next, an interlayer insulating film 11 is formed.

  In the step of forming the interlayer insulating film 11, after removing the patterned resist film R4, the interlayer insulating film 11 is formed on the semiconductor substrate 3S as shown in FIG. As the interlayer insulating film 11, an insulating film made of, for example, a silicon oxide film can be formed by, for example, a CVD method.

  Next, contact holes CH1 and CH2 are formed.

In the step of forming the contact holes CH1 and CH2, as shown in FIG. 19, the contact holes CH1 and CH2 are formed in the interlayer insulating film 11 by using a photolithography technique and an etching technique. Contact hole CH1 is formed in a portion where p ⁺⁺ emitter region 4a is formed in first region AR1, and contact hole CH2 is formed in a portion where p ⁺⁺ emitter region 4b is formed in second region AR2. . Therefore, the contact hole CH1 is formed at a position overlapping the recess CC1 in plan view, and the contact hole CH2 is formed at a position overlapping the recess CC2 in plan view.

Next, the p ⁺⁺ emitter region 4 is formed.

In the step of forming the p ⁺⁺ emitter region 4, as shown in FIG. 20, the p ⁺ channel region 7 exposed on the bottom surface of the recess CC1 and the recess CC2 are formed by ion implantation using the interlayer insulating film 11 as a mask. A p-type impurity such as boron (B) is introduced into the p ⁻ channel region 9 exposed at the bottom of the substrate. Thus, in the first region AR1, the exposed portion on the bottom surface of the recessed portion CC1 of the semiconductor layer SL1, as p ⁺⁺ emitter region 4, p ⁺⁺ emitter region 4a is formed. Further, in the second region AR2, the exposed portion on the bottom surface of the recessed portion CC2 of the semiconductor layer SL1, as p ⁺⁺ emitter region 4, p ⁺⁺ emitter regions 4b are formed.

  Next, the emitter electrode 12 is formed.

  In the step of forming the emitter electrode 12, as shown in FIG. 21, the emitter electrode 12 is formed in the contact holes CH1 and CH2, the recesses CC1 and CC2, and on the interlayer insulating film 11. Specifically, first, a barrier conductor film made of, for example, titanium tungsten (TiW) is formed by sputtering, for example, inside the contact holes CH1, CH2, the recesses CC1, CC2, and on the interlayer insulating film 11. Next, a conductor film made of, for example, an aluminum (Al) film is formed on the barrier conductor film by, for example, a sputtering method, thereby forming the emitter electrode 12 made of a laminated conductor film. Thereby, the emitter electrode 12a is formed inside the contact hole CH1 and the recess CC1 in the first region AR1, and the emitter electrode 12b is formed inside the contact hole CH2 and the recess CC2 in the second region AR2.

As a result, in first region AR1, emitter electrode 12a formed inside contact hole CH1 and recess CC1 is electrically connected to p ⁺⁺ emitter region 4a and n ⁺⁺ emitter regions 8a, 8b. On the other hand, in second region AR2, emitter electrode 12b formed inside contact hole CH2 and recess CC2 is electrically connected to p ⁻ channel region 9. The p ⁺ channel region 7 is in contact with the n ⁺⁺ emitter regions 8a and 8b, the gate insulating films 6a and 6b, and the n ⁻ drift region 1, and each of the n ⁺⁺ emitter regions 8a and 8b includes an emitter electrode 12a, It is in contact with each of gate insulating films 6a and 6b and p ⁺ channel region 7. Further, p ⁻ channel region 9 is in contact with emitter electrode 12b, gate insulating films 6c and 6d, and n ⁻ drift region 1.

  In the first embodiment, in the step of forming the emitter electrodes 12a and 12b, as shown in FIG. 2, the emitter electrode 12b of the second transistor TR22 extends along one direction (Y direction in FIG. 2). Thus, it is formed continuously with the emitter electrode 12a of the first transistor TR11. Further, the emitter electrode 12a of the first transistor TR12 is formed continuously with the emitter electrode 12b of the second transistor TR21 along one direction (Y direction in FIG. 2).

Next, the back surface is ground to form an n ⁺ buffer region 2 and a p ⁺ collector region 3.

  First, in the step of grinding the back surface, the back surface (lower surface) of the semiconductor substrate 3S is ground so that the thickness of the semiconductor substrate 3S becomes a predetermined thickness. The thickness of the semiconductor substrate 3S after grinding depends on, for example, the withstand voltage of the IGBT to be formed. When the withstand voltage is 3.3 kV, for example, the thickness is about 300 μm and the withstand voltage is 1.2 kV, for example. The thickness can be about 120 μm, and when the withstand voltage is 600 V, for example, the thickness can be 60 μm.

Next, in the step of forming the n ⁺ buffer region 2 and the p ⁺ collector region 3, for example, boron (B) is formed on the portion where the p ⁺ collector region 3 is formed from the back surface (lower surface) side of the semiconductor substrate 3S by, for example, ion implantation. ) Or the like is introduced, and an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the portion where the n ⁺ buffer region 2 is to be formed. Thereafter, the back surface (lower surface) of the semiconductor substrate 3S is subjected to, for example, an instantaneous annealing process (heat treatment) of, for example, about several hundred μm using a laser annealing apparatus, and the introduced impurities and the pn junction are activated. Thus, as shown in FIG. 22, the p ⁺ collector region 3 and the n ⁺ buffer region 2 are formed in order from the back surface (lower surface) to the front surface (upper surface) on the back surface (lower surface) side portion of the semiconductor substrate 3S. Is done. As a result, n ^- the opposite side, i.e. the lower surface (second main surface) side and the upper surface of the drift region 1 (first main surface), n ⁺ buffer region 2 is formed, n ⁺ lower surface of the buffer region 2 (second A p ⁺ collector region 3 is formed on the (main surface) side.

The n ⁺ buffer region 2 and the p ⁺ collector region 3 are formed by performing ion implantation and annealing (heat treatment) on one of the n ⁺ buffer region 2 and the p ⁺ collector region 3 and then forming the other. You can also.

Further, for example, an epitaxial growth method can be used instead of the ion implantation method and the annealing treatment (heat treatment). In this case, instead of the semiconductor substrate 3S, for example, a laminated substrate in which an n ⁺ buffer region 2 and an n ⁻ drift region 1 are sequentially formed on a semiconductor substrate composed of a p ⁺ collector region 3 is prepared. The same process as described with reference to FIGS. 7 to 22 is performed on the substrate.

  Thereafter, a conductor film made of a metal such as aluminum (Al) or an alloy such as aluminum silicon (AlSi) is formed as the collector electrode 13 on the back surface (lower surface) of the semiconductor substrate 3S. As described above, the IGBT 50 which is the semiconductor device according to the first embodiment as shown in FIGS. 1 and 2 can be manufactured.

<On-voltage and switching loss in IGBT>
Next, the relationship between the on-voltage and switching loss in the IGBT will be described in comparison with a semiconductor device of a comparative example.

  FIG. 23 is a fragmentary cross-sectional view of a semiconductor device of a comparative example. FIG. 24 is a diagram schematically showing a path through which charges flow when the IGBT is on in FIG. FIG. 25 is a diagram schematically showing a path through which charges flow when the IGBT is switched from the on state to the off state in FIG.

In Figure 23, n of IGBT150 a semiconductor device of Comparative Example ^- drift region 1, n ⁺ buffer region 2, p ⁺ collector region 3, n of each of the above IGBT 50 ^- drift region 1, n ⁺ buffer region 2, This corresponds to the p ⁺ collector region 3. The p ⁺⁺ emitter region 4a, gate electrodes 5a, 5b, gate insulating films 6a, 6b, and p ⁺ channel region 7 of the IGBT 150 are respectively connected to the p ⁺⁺ emitter region 4a, gate electrodes 5a, 5b, and gate insulation of the IGBT 50. The films 6a and 6b correspond to the p ⁺ channel region 7. Further, the n ⁺⁺ emitter regions 8a and 8b, the p well region 10, the interlayer insulating film 11, the emitter electrode 12a, and the collector electrode 13 of the IGBT 150 are respectively connected to the n ⁺⁺ emitter regions 8a and 8b and the p well region 10 of the IGBT 50, This corresponds to the interlayer insulating film 11, the emitter electrode 12a, and the collector electrode 13. The first transistor TR1 of the IGBT 150 corresponds to the first transistor TR1 of the IGBT 50.

  However, the IGBT 150 which is the semiconductor device of the comparative example is not provided with the second transistor.

Also in the semiconductor device (IGBT 150) of the comparative example, the inversion layers 7a and 7b are formed in the p ⁺ channel region 7 by applying the collector voltage Vc to the collector electrode 13 and applying the gate voltage Vg1 to the gate electrodes 5a and 5b. (ON state). Then, electrons from the emitter electrode 12a is, as shown the path in FIG. 24 as PS1, n ⁺⁺ emitter regions 8a, 8b respectively, and the formed inversion layer 7a, through 7b, n ^- drift region 1 Injected into (flowed into). The electrons injected (flowed in) from the emitter electrode 12a into the n ⁻ drift region 1 and the holes injected (flowed in) into the n ⁻ drift region 1 from the collector electrode 13 are n ⁻ drift region 1. It attracts by Coulomb attraction. Therefore, excessive charges are accumulated in the n ⁻ drift region 1, and a large on-current can flow through the IGBT 150.

Further, when the first transistor TR1 is turned on, n ^- holes from the drift region 1, as shown the path as PS2 in Figure 24, the inversion layer 7a of the p ⁺ channel region 7, 7b and depletion It is discharged (flows out) to the emitter electrode 12a through a portion other than the layer (not shown), that is, a portion on the center side.

On the other hand, when the first transistor TR1 is switched from the on state to the off state, that is, when the application of the gate voltage Vg1 to the gate electrodes 5a and 5b is stopped, the first transistor TR1 is excessively accumulated in the n ⁻ drift region 1. Holes are ejected (flowed out) through the p ⁺ channel region 7 to the emitter electrode 12a, as shown by the path PS3 in FIG. However, electrons cannot flow through the p ⁺ channel region 7.

However, in the semiconductor device (IGBT 150) of the comparative example, power consumption (switching loss) when the first transistor TR1 is switched from the on state to the off state is large. This is because the amount of holes flowing through the p ⁺ channel region 7 is not so large only in the path PS3 shown in FIG. 25, so that holes cannot be efficiently discharged.

  In order to reduce such a switching loss, a transistor different from the first transistor TR1 is formed, and holes flow through the different transistors when the first transistor TR1 and the different transistors are switched from the on state to the off state. It is also possible. However, when the first transistor TR1 and the different transistor are in the ON state, holes flow through the different transistors and the area of the emitter region is substantially increased, so that the IE effect is reduced and the excessive accumulation effect is reduced. There is a problem that it ends up.

  When a transistor different from the first transistor TR1 is formed, an n-type barrier region serving as a hole barrier layer is formed in the different transistor, and when the first transistor TR1 and the different transistor are in an on state, It is also conceivable to suppress the flow of holes through the different transistors. However, when the n-type barrier region is formed, holes cannot be efficiently discharged when the first transistor TR1 and the different transistors are switched from the on state to the off state.

<Main features and effects of the present embodiment>
On the other hand, the IGBT 50 which is the semiconductor device of the first embodiment includes a second transistor TR2 in addition to the first transistor TR1. In the second transistor TR2, regions corresponding to the n ⁺⁺ emitter regions 8a and 8b formed in the first transistor TR1 are not formed. For this reason, the second transistor TR2 does not flow current when the second transistor TR2 is in the on state, but flows current composed of holes when the second transistor TR2 is switched from the on state to the off state.

That is, in the semiconductor device (IGBT 50) according to the first embodiment, when the first transistor TR1 and the second transistor TR2 are in the ON state, the collector electrode 13 passes through the p ⁺ channel region 7 of the first transistor TR1 to the emitter electrode 12a. , A current consisting of holes (positive polarity charge) and electrons (negative polarity charge) flows. However, when the first transistor TR1 and the second transistor TR2 are on, no current flows through the p ⁻ channel region 9 of the second transistor TR2. Therefore, the characteristics of the semiconductor device (IGBT 50) of the first embodiment in the on state are the same as the characteristics of the semiconductor device (IGBT 150) of the comparative example in the on state. Thereby, the IE effect in the ON state can be ensured, and the excessive accumulation effect can be ensured. As a result, the resistance of the n ⁻ drift region 1 can be reduced, and the collector voltage for flowing the collector current determined by the rating, that is, the on-voltage can be reduced.

On the other hand, in the semiconductor device (IGBT 50) according to the first embodiment, when the first transistor TR1 and the second transistor TR2 are switched from the on state to the off state, the first transistor TR1 and the second transistor TR1 from the n ⁻ drift region 1 are switched. A current consisting of holes (positive polarity charges) flows through the transistor TR2 to the emitter electrodes 12a and 12b. Thereby, power consumption (switching loss) when the first transistor TR1 and the second transistor TR2 are switched from the on state to the off state can be reduced.

That is, according to the semiconductor device (IGBT 50) of the first embodiment, the on-voltage can be reduced and the switching loss can be reduced. Therefore, in order to reduce the on-voltage, for example, by reducing the area (planar area) of the p ⁺⁺ emitter region 4a or the area (planar area) of the p ⁺ channel region 7 of the first transistor TR1, the IE effect is enhanced. Even when the on-voltage is reduced, the switching loss can be reduced. In other words, it is possible to achieve both reduction in on-voltage and reduction in switching loss that are in a trade-off relationship, and it is possible to improve the performance of a semiconductor device made of IGBT.

In the first embodiment, the area ratio between the area (planar area) of the p ⁺ channel region 7 and the area (plane area) of the p ⁻ channel region 9 is preferably determined by the following method, for example. Can be determined. First, the area (emitter diameter) of the p ⁺⁺ emitter regions 4a and 4b is determined, and the ON voltage can be reduced most by the IE effect with respect to the determined area (emitter diameter) of the p ⁺⁺ emitter regions 4a and 4b. Thus, the area (planar area) of the p ⁺ channel region 7 is determined. Then, p ⁺ channel region 7 or p ^- from the area of the plan channel region 9 is formed (flat area) of the remaining area obtained by subtracting the area (plane area) of the p ⁺ channel region 7, p ^- channel region 9 Let it be the area (flat area).

  In the first embodiment, even when the conductivity types of the n-type semiconductor region and the p-type semiconductor region are interchanged between the p-type and the n-type, the semiconductor of the first embodiment The same effect as the apparatus can be obtained (the same applies to the following embodiments).

  In the first embodiment, the example in which the semiconductor material constituting the semiconductor substrate 3S and each semiconductor region is silicon (Si) has been described. However, the semiconductor material is not limited to silicon (Si), and other various semiconductor materials such as silicon carbide (SiC) can be used (the same applies to the following embodiments). However, when using another semiconductor material instead of silicon (Si) and determining the inter-gate distance W based on the above formula (1), the dielectric constant ε is the dielectric constant of each semiconductor material, and the band gap V Is the band gap of each semiconductor material.

Further, in the first embodiment, in order to prevent holes from flowing through the second transistor TR2 when the second transistor TR2 is in the ON state, when the inter-gate distance W2 of the second transistor TR2 is set to W. In addition, it has been explained that it is preferable that the inter-gate distance W satisfies the above formula (1). However, even when the inter-gate distance W does not satisfy the above equation (1), the second transistor TR2 is turned on by making the impurity concentration of the p ⁻ channel region 9 lower than the impurity concentration of the p ⁺ channel region 7, for example. It can be adjusted so that almost no holes flow through the p ⁻ channel region 9 of the second transistor TR2 when in the state. Therefore, even when the inter-gate distance W does not satisfy the above formula (1), the switching loss can be further reduced as compared with the case where the second transistor TR2 is not formed.

(Embodiment 2)
<Semiconductor device>
Next, a semiconductor device according to the second embodiment of the present invention will be described. In the first embodiment described above, the first transistor and the second transistor are adjacent to each other along one direction. In contrast, in the second embodiment, the first transistor and the second transistor are formed at positions separated from each other across the p-well region, and are not adjacent to each other.

  FIG. 26 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment. FIG. 27 is a perspective view of the semiconductor device of the second embodiment.

As shown in FIG. 26, the IGBT 50a that is the semiconductor device of the second embodiment has substantially the same structure as the IGBT 50 that is the semiconductor device of the first embodiment. That, IGBT50a, like the IGBT 50, n ^- drift region 1, n ⁺ buffer region 2, p ⁺ collector region 3, p ⁺⁺ emitter regions 4 (4a, 4b), the gate electrode 5 (5a, 5b, 5c 5d) and a gate insulating film 6 (6a, 6b, 6c, 6d). Similarly to the IGBT 50, the IGBT 50a includes a p ⁺ channel region 7, an n ⁺⁺ emitter region 8 (8a, 8b), a p ⁻ channel region 9, a p well region 10, an interlayer insulating film 11, and an emitter electrode 12 (12a, 12b) and a collector electrode 13 are provided.

As shown in FIG. 27, also in the second embodiment, trenches T1, T2, T3, and T4 are formed along one direction (Y direction in FIG. 27). Therefore, the p ⁺⁺ emitter region 4 (4a, 4b), the p ⁺ channel region 7, the n ⁺⁺ emitter region 8 (8a, 8b), and the p ⁻ channel region 9 are along one direction (the Y direction in FIG. 27). Is formed. Further, the gate electrode 5 (5a, 5b, 5c, 5d) and the gate insulating film 6 (6a, 6b, 6c, 6d) are also formed along one direction (Y direction in FIG. 27).

Also in the second embodiment, similarly to the first embodiment, the gate-to-gate distance W2 of the second transistor TR2 is set to W (m), and the impurity concentration of the p ⁻ channel region 9 is set to N _a (m ⁻³ ). When the electron and hole elementary charges are q (C) and the dielectric constant and band gap of the p ⁻ channel region 9 are ε (F / m) and V (eV), respectively, It is preferable to satisfy.

  However, in the second embodiment, the first transistor TR1 and the second transistor TR2 are not adjacent to each other along one direction (Y direction in FIG. 27). That is, each of the trenches T3 and T4 of the second transistor TR2 is not formed continuously with each of the trenches T1 and T2 of the first transistor TR1 along one direction (Y direction in FIG. 27). Each of the trenches T3 and T4 of the second transistor TR2 is formed at a position separated from the trenches T1 and T2 of the first transistor TR1 along a direction intersecting the Y direction of FIG. 27 (X direction of FIG. 27). Yes. Further, the inter-gate distance W1 of the first transistor TR1, that is, the interval between the trenches T1 and T2, may not be equal to the inter-gate distance W2 of the second transistor TR2, that is, the interval between the trenches T3 and T4. FIG. 27 shows a case where the inter-gate distance W1 of the first transistor TR1 is not equal to the inter-gate distance W2 of the second transistor TR2.

  Therefore, the inter-gate distance W1 in the first transistor TR1 and the inter-gate distance W2 in the second transistor TR2 can be individually designed as follows. That is, the inter-gate distance W1 can be designed as a distance necessary for reducing the on-voltage. Regarding the inter-gate distance W2, the current flowing through the second transistor TR2 is reduced when the second transistor TR2 is in the on state, and the current flowing through the second transistor TR2 is increased when the second transistor TR2 is in the off state. It can be designed as a necessary distance.

  Although not shown, the gate electrodes 5a and 5b are electrically connected to each other at a position on the back side (or the near side) of the cross section shown in FIG. 26, and the gate electrodes 5c and 5d are also shown in FIG. 26 are electrically connected to each other at a position on the back side (or near side) of the cross section shown in FIG. In addition, the gate electrodes 5 (5a, 5b, 5c, 5d) formed at positions separated along the X direction in FIG. 27 can be electrically connected to each other. With such a configuration, the gate voltage applied to the gate electrodes 5a and 5b of the first transistor TR1 and the gate voltage applied to the gate electrodes 5c and 5d of the second transistor TR2 can be collectively controlled.

  Since the operation of the semiconductor device (IGBT 50a) of the second embodiment is the same as the operation of the semiconductor device (IGBT 50) of the first embodiment, description thereof is omitted.

<Manufacturing process of semiconductor device>
Regarding the manufacturing process of the semiconductor device of the second embodiment, the process of patterning the silicon oxide film 21, the process of forming the trench T, the p ⁺ channel region 7, the n ⁺⁺ emitter region 8 and the p ⁻ channel region 9 Steps other than the step of forming the layer by ion implantation are the same as those of the semiconductor device manufacturing process of the first embodiment, and the description thereof is omitted.

  The step of patterning the silicon oxide film 21 and the step of forming the trench T can be performed in substantially the same manner as the steps described in Embodiment 1 with reference to FIGS. However, in the second embodiment, unlike the first embodiment, the pair of trenches T3 and T4 are formed at positions separated from the pair of trenches T1 and T2 along the X direction in FIG. Therefore, each of the pair of trenches T3 and T4 is not formed continuously with each of the pair of trenches T1 and T2 along the Y direction in FIG.

  The step of forming the gate insulating film 6 can be performed in substantially the same manner as the step described with reference to FIG. However, in the second embodiment, unlike the first embodiment, each of the pair of gate insulating films 6c and 6d is separated from each of the pair of gate insulating films 6a and 6b along the X direction in FIG. Formed in position. Therefore, each of the pair of gate insulating films 6c and 6d is not formed continuously with each of the pair of gate insulating films 6a and 6b along the Y direction in FIG.

  The step of forming the gate electrode 5 can be performed in substantially the same manner as the step described with reference to FIGS. 11 and 12 in the first embodiment. However, in the second embodiment, unlike the first embodiment, each of the pair of gate electrodes 5c and 5d is located at a position separated from each of the pair of gate electrodes 5a and 5b along the X direction in FIG. It is formed. Therefore, each of the pair of gate electrodes 5c and 5d is not formed continuously with each of the pair of gate electrodes 5a and 5b along the Y direction in FIG.

The step of forming p ⁺ channel region 7, n ⁺⁺ emitter region 8 and p ⁻ channel region 9 by ion implantation is substantially the same as the step described with reference to FIGS. 13, 14, and 15 in the first embodiment. The same can be done. However, in the second embodiment, unlike the first embodiment, in the step of forming the p ⁺ channel region 7, the n ⁺⁺ emitter region 8 and the p ⁻ channel region 9 by the ion implantation method, the Y direction in FIG. The ion implantation is performed so that the first transistor TR1 and the second transistor TR2 are not adjacent to each other. That is, p ⁻ channel region 9 is formed so as not to be adjacent to p ⁺ channel region 7 and n ⁺⁺ emitter regions 8a and 8b along the Y direction in FIG.

<Main features and effects of the present embodiment>
In the semiconductor device (IGBT 50a) of the second embodiment, as in the semiconductor device (IGBT 50) of the first embodiment, when the first transistor TR1 and the second transistor TR2 are in the on state, holes are transmitted through the first transistor TR1. Electrons flow, but no current flows through the second transistor TR2. Further, when the first transistor TR1 and the second transistor TR2 are switched from the on state to the off state, holes flow through the first transistor TR1 and the second transistor TR2. Therefore, similarly to the semiconductor device (IGBT 50) of the first embodiment, both reduction of on-voltage and reduction of switching loss can be achieved.

  In addition, unlike the semiconductor device (IGBT 50) of the first embodiment, the semiconductor device (IGBT 50a) of the second embodiment has a first transistor TR1 and a second transistor TR2 along one direction (Y direction in FIG. 27). And are not adjacent. Therefore, the inter-gate distance W1 of the first transistor TR1 may not be equal to the inter-gate distance W2 of the second transistor TR2. Therefore, the inter-gate distance W1 of the first transistor TR1 and the inter-gate distance W2 of the second transistor TR2 can be individually designed.

(Embodiment 3)
<Semiconductor device>
Next, a semiconductor device according to the third embodiment of the present invention will be described. The semiconductor device according to the third embodiment is the same as the semiconductor device according to the first embodiment except that an n barrier region is formed between the p ⁺ channel region and the n ⁻ drift region. The description of is omitted.

  FIG. 28 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment. FIG. 29 is a perspective view of the semiconductor device of the third embodiment.

As shown in FIG. 28, in IGBT 50b which is the semiconductor device of the third embodiment, n barrier region 14 is formed between p ⁺ channel region 7 and n ⁻ drift region 1 in first region AR1. Yes. The n barrier region 14 is an n type semiconductor region (first conductivity type semiconductor region) made of silicon (Si) in which an n type impurity such as phosphorus (P) or arsenic (As) is diffused. The impurity concentration of the n barrier region 14 can be set to, for example, about 5 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ .

By forming the n barrier region 14, when the first transistor TR1 is in the ON state, holes accumulated excessively in the n ⁻ drift region 1 are discharged to the emitter electrode 12a through the p ⁺ channel region 7 ( (Flowing out) can be suppressed. Therefore, the degree of the IE effect can be adjusted by adjusting the impurity concentration of the n barrier region 14.

  As shown in FIG. 29, in the third embodiment, as in the first embodiment, the first transistor TR1 and the second transistor TR2 are adjacent to each other along one direction (the Y direction in FIG. 29). ing.

  Since the operation of the semiconductor device (IGBT 50b) of the third embodiment is substantially the same as the operation of the semiconductor device (IGBT 50) of the first embodiment, description thereof is omitted.

However, in the third embodiment, when the first transistor TR1 is in the on state, the holes accumulated excessively in the n ⁻ drift region 1 by the n barrier region 14 are discharged to the emitter electrode 12a through the first transistor TR1. To be suppressed.

<Manufacturing process of semiconductor device>
30 and 31 are fragmentary cross-sectional views of the semiconductor device of the third embodiment during the manufacturing steps thereof.

Regarding the manufacturing process of the semiconductor device according to the third embodiment, the manufacturing process of the semiconductor device according to the first embodiment is performed except for the process of forming the n barrier region 14 and the process of forming the p ⁺ channel region 7. The description is omitted.

In the third embodiment, for example, after forming the gate electrode 5 and before forming the p ⁺ channel region 7, the n barrier region 14 is formed as shown in FIG.

Specifically, a resist film R1 is applied on the semiconductor substrate 3S. Then, the resist film R1 is patterned by subjecting the applied resist film R1 to exposure / development processing using a photolithography technique. The patterning of the resist film R1 is performed so that the second region AR2 and the third region AR3 are covered and the first region AR1 is exposed. Then, an n-type impurity is introduced into the semiconductor layer SL1 by ion implantation using the patterned resist film R1 as a mask. Thus, the n barrier region 14 is formed in a portion of the semiconductor layer SL1 that is not covered with the resist film R1 in the first region AR1. The n barrier region 14 is formed between the pair of trenches T1 and T2 such that both sides thereof are in contact with the trenches T1 and T2 and the lower side thereof is in contact with the n ⁻ drift region 1. As described above, the impurity concentration of the n barrier region 14 can be, for example, about 5 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ .

Next, the p ⁺ channel region 7 is formed. As shown in FIG. 31, a p-type impurity is introduced into the semiconductor layer SL1 by ion implantation using the patterned resist film R1 as a mask. As a result, the p ⁺ channel region 7 is formed above the n barrier region 14 in the portion of the semiconductor layer SL1 that is not covered with the resist film R1 in the first region AR1. The impurity concentration of p ⁺ channel region 7 can be the same as in the first embodiment.

<Main features and effects of the present embodiment>
In the semiconductor device (IGBT 50b) of the third embodiment, as in the semiconductor device (IGBT 50) of the first embodiment, when the first transistor TR1 and the second transistor TR2 are in the on state, holes are transmitted through the first transistor TR1. Electrons flow, but no current flows through the second transistor TR2. Further, when the first transistor TR1 and the second transistor TR2 are switched from the on state to the off state, holes flow through the first transistor TR1 and the second transistor TR2. Therefore, similarly to the semiconductor device (IGBT 50) of the first embodiment, both reduction of on-voltage and reduction of switching loss can be achieved.

Further, in the semiconductor device (IGBT 50 b) of the third embodiment, unlike the semiconductor device (IGBT 50) of the first embodiment, an n barrier region 14 is formed between the p ⁺ channel region 7 and the n ⁻ drift region 1. Has been. Therefore, the degree of the IE effect can be adjusted by adjusting the impurity concentration of the n barrier region 14, and the on-voltage can be further reduced as compared with the semiconductor device (IGBT 50) of the first embodiment.

(Embodiment 4)
<Semiconductor device>
Next, a semiconductor device according to a fourth embodiment of the present invention will be described. The semiconductor device according to the fourth embodiment is the same as the semiconductor device according to the second embodiment except that an n barrier region is formed between the p ⁺ channel region and the n ⁻ drift region. The description of is omitted.

  FIG. 32 is a perspective view of the semiconductor device of the fourth embodiment.

As shown in FIG. 32, in the IGBT 50c that is the semiconductor device of the fourth embodiment, as in the IGBT 50b that is the semiconductor device of the third embodiment, between the p ⁺ channel region 7 and the n ⁻ drift region 1. An n barrier region 14 is formed.

  As shown in FIG. 32, in the fourth embodiment, as in the second embodiment, the first transistor TR1 and the second transistor TR2 are adjacent to each other along one direction (the Y direction in FIG. 32). Not.

  Since the operation of the semiconductor device (IGBT 50c) of the fourth embodiment is the same as the operation of the semiconductor device (IGBT 50b) of the third embodiment, description thereof is omitted.

<Manufacturing process of semiconductor device>
Regarding the manufacturing process of the semiconductor device of the fourth embodiment, the manufacturing method of the semiconductor device of the second embodiment is the same as the process other than the process of forming the n barrier region 14 and the process of forming the p ⁺ channel region 7. The description is omitted.

In the fourth embodiment, for example, after the gate electrode 5 is formed and before the p ⁺ channel region 7 is formed, the same process as that described in the third embodiment with reference to FIG. Region 14 is formed.

In the fourth embodiment, the p ⁺ channel region 7 is formed by performing the same process as that described with reference to FIG. 31 in the third embodiment.

<Main features and effects of the present embodiment>
In the semiconductor device (IGBT 50c) of the fourth embodiment, as in the semiconductor device (IGBT 50) of the first embodiment, when the first transistor TR1 and the second transistor TR2 are in the on state, holes are transmitted through the first transistor TR1. Electrons flow, but no current flows through the second transistor TR2. Further, when the first transistor TR1 and the second transistor TR2 are switched from the on state to the off state, holes flow through the first transistor TR1 and the second transistor TR2. Therefore, similarly to the semiconductor device (IGBT 50) of the first embodiment, both reduction of on-voltage and reduction of switching loss can be achieved.

  Further, in the semiconductor device (IGBT 50c) of the fourth embodiment, the first transistor TR1 and the second transistor along one direction (the Y direction in FIG. 32), similarly to the semiconductor device (IGBT 50a) of the second embodiment. TR2 is not adjacent. Therefore, the inter-gate distance W1 of the first transistor TR1 may not be equal to the inter-gate distance W2 of the second transistor TR2. Therefore, the inter-gate distance W1 of the first transistor TR1 and the inter-gate distance W2 of the second transistor TR2 can be individually designed.

In the semiconductor device (IGBT 50c) of the fourth embodiment, the n barrier region 14 is provided between the p ⁺ channel region 7 and the n ⁻ drift region 1 as in the semiconductor device (IGBT 50b) of the third embodiment. Is formed. Therefore, the degree of the IE effect can be adjusted by adjusting the impurity concentration of the n barrier region 14, and the on-voltage can be further reduced as compared with the semiconductor device (IGBT 50a) of the second embodiment.

(Embodiment 5)
<Semiconductor device>
Next, a semiconductor device according to a fifth embodiment of the present invention will be described. The semiconductor device according to the fifth embodiment is the same as the semiconductor device according to the first embodiment, except that the p barrier region is formed between the p ⁻ channel region and the n ⁻ drift region. The description of is omitted.

  FIG. 33 is a fragmentary cross-sectional view of the semiconductor device of the fifth embodiment. FIG. 34 is a perspective view of the semiconductor device of the fifth embodiment.

As shown in FIG. 33, in the IGBT 50d which is the semiconductor device of the fifth embodiment, in the second region AR2, between the p ⁻ channel region 9 and the n ⁻ drift region 1 and the gate insulating films 6c and 6d. P barrier region 15 is formed between n 2 ^and drift region 1. The p barrier region 15 is a p type semiconductor region (second conductivity type semiconductor region) made of silicon (Si) in which a p type impurity such as boron (B) is diffused. The impurity concentration of the p barrier region 15 can be, for example, about 5 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ .

By forming the p barrier region 15, when the second transistor TR 2 is in the ON state, electrons are hardly injected as a leakage current from the emitter electrode 12 b through the p ⁻ channel region 9 into the n ⁻ drift region 1 (difficult to flow in). )Become. Further, by forming the p barrier region 15 in the vicinity of the p ⁻ channel region 9, when the second transistor TR2 is switched from the on state to the off state, holes accumulated excessively in the n ⁻ drift region 1 are It becomes easy to be discharged to the emitter electrode 12b through the p ⁻ channel region 9 (easy to flow out).

  As shown in FIG. 34, in the fifth embodiment, as in the first embodiment, the first transistor TR1 and the second transistor TR2 are adjacent to each other along one direction (the Y direction in FIG. 34). ing.

  Since the operation of the semiconductor device (IGBT 50d) of the fifth embodiment is substantially the same as the operation of the semiconductor device (IGBT 50) of the first embodiment, description thereof is omitted.

However, in the fifth embodiment, when the second transistor TR2 is in the ON state, electrons are injected as a leakage current from the emitter electrode 12b through the second transistor TR2 into the n ⁻ drift region 1 by the p barrier region 15. It suppresses that. In the fifth embodiment, when the second transistor TR2 is switched from the on state to the off state, holes accumulated excessively in the n ⁻ drift region 1 by the p barrier region 15 are transferred to the second transistor TR2. To be discharged to the emitter electrode 12b.

<Manufacturing process of semiconductor device>
FIG. 35 is a main-portion cross-sectional view of the semiconductor device in Embodiment 5 during the manufacturing process.

  About the manufacturing process of the semiconductor device of this Embodiment 5, processes other than the process of forming p barrier area | region 15 are the same as the manufacturing process of the semiconductor device of Embodiment 1, The description is abbreviate | omitted.

  In the fifth embodiment, for example, the p barrier region 15 is formed when the semiconductor layer SL1 is formed.

For example, before forming the semiconductor layer SL1, a resist film (not shown) is applied on the semiconductor substrate 3S, and exposure / development processing is performed using a photolithography technique, so that a portion where the p barrier region 15 is formed is formed. The resist film is patterned so as to be exposed. Then, a p-type impurity is introduced into the semiconductor substrate 3S by an ion implantation method using the patterned resist film as a mask. Next, a process similar to the process described with reference to FIG. 6 is performed to form the semiconductor layer SL1. As a result, as shown in FIG. 35, the p-type semiconductor layer SL1 is formed on the surface (upper surface) side portion (upper layer portion) of the semiconductor substrate 3S, and the back surface (lower surface) side portion of the semiconductor layer SL1 is n. ⁻ Drift region 1, and p barrier region 15 is formed between semiconductor layer SL <b> 1 and n ⁻ drift region 1. The impurity concentration of the p barrier region 15 can be set to, for example, about 5 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ .

  Note that the step of forming the p barrier region 15 can be performed, for example, after forming the semiconductor layer SL1 or when forming the p well region 10 (the same applies to the following embodiments).

<Main features and effects of the present embodiment>
In the semiconductor device (IGBT 50d) of the fifth embodiment, as in the semiconductor device (IGBT 50) of the first embodiment, when the first transistor TR1 and the second transistor TR2 are in the on state, holes are transmitted through the first transistor TR1. Electrons flow, but no current flows through the second transistor TR2. Further, when the first transistor TR1 and the second transistor TR2 are switched from the on state to the off state, holes flow through the first transistor TR1 and the second transistor TR2. Therefore, similarly to the semiconductor device (IGBT 50) of the first embodiment, both reduction of on-voltage and reduction of switching loss can be achieved.

Also, in the semiconductor device (IGBT 50d) of the fifth embodiment, unlike the semiconductor device (IGBT 50) of the first embodiment, a p barrier region 15 is formed between the p ⁻ channel region 9 and the n ⁻ drift region 1. Has been. By forming the p barrier region 15, the leakage current flowing through the second transistor TR2 is suppressed when the second transistor TR2 is in the on state, and when the second transistor TR2 is switched from the on state to the off state, The discharge of holes through the two-transistor TR2 can be promoted. Therefore, the on-voltage can be further reduced and the switching loss can be further reduced as compared to the semiconductor device (IGBT 50) of the first embodiment.

(Embodiment 6)
<Semiconductor device>
Next, a semiconductor device according to a sixth embodiment of the present invention will be described. The semiconductor device of the sixth embodiment is the same as the semiconductor device of the second embodiment, except that the p barrier region is formed between the p ⁻ channel region and the n ⁻ drift region. The description of is omitted.

  FIG. 36 is a perspective view of the semiconductor device of the sixth embodiment.

As shown in FIG. 36, in the IGBT 50e that is the semiconductor device of the sixth embodiment, similarly to the IGBT 50d that is the semiconductor device of the fifth embodiment, between the p ⁻ channel region 9 and the n ⁻ drift region 1, A p barrier region 15 is formed between the gate insulating films 6 c and 6 d and the n ⁻ drift region 1.

  As shown in FIG. 36, in the sixth embodiment, as in the second embodiment, the first transistor TR1 and the second transistor TR2 are adjacent to each other along one direction (the Y direction in FIG. 36). Not.

  Since the operation of the semiconductor device (IGBT 50e) of the sixth embodiment is the same as the operation of the semiconductor device (IGBT 50d) of the fifth embodiment, description thereof is omitted.

<Manufacturing process of semiconductor device>
About the manufacturing process of the semiconductor device of this Embodiment 6, about processes other than the process of forming p barrier area | region 15, it is the same as that of the manufacturing process of the semiconductor device of Embodiment 2, The description is abbreviate | omitted.

  In the sixth embodiment, for example, when the semiconductor layer SL1 is formed, the p barrier region 15 is formed by performing the same process as the process described in the fifth embodiment with reference to FIG.

<Main features and effects of the present embodiment>
In the semiconductor device (IGBT 50e) of the sixth embodiment, as in the semiconductor device (IGBT 50) of the first embodiment, when the first transistor TR1 and the second transistor TR2 are in the on state, holes are transmitted through the first transistor TR1. Electrons flow, but no current flows through the second transistor TR2. Further, when the first transistor TR1 and the second transistor TR2 are switched from the on state to the off state, holes flow through the first transistor TR1 and the second transistor TR2. Therefore, similarly to the semiconductor device (IGBT 50) of the first embodiment, both reduction of on-voltage and reduction of switching loss can be achieved.

  Further, in the semiconductor device (IGBT 50e) of the sixth embodiment, the first transistor TR1 and the second transistor along one direction (the Y direction in FIG. 36), similarly to the semiconductor device (IGBT 50a) of the second embodiment. TR2 is not adjacent. Therefore, the inter-gate distance W1 of the first transistor TR1 may not be equal to the inter-gate distance W2 of the second transistor TR2. Therefore, the inter-gate distance W1 of the first transistor TR1 and the inter-gate distance W2 of the second transistor TR2 can be individually designed.

Further, in the semiconductor device (IGBT 50 e) of the sixth embodiment, unlike the semiconductor device (IGBT 50 a) of the second embodiment, a p barrier region 15 is formed between the p ⁻ channel region 9 and the n ⁻ drift region 1. Has been. By forming the p barrier region 15, the leakage current flowing through the second transistor TR2 is suppressed when the second transistor TR2 is in the on state, and when the second transistor TR2 is switched from the on state to the off state, The discharge of holes through the two-transistor TR2 can be promoted. Therefore, compared to the semiconductor device (IGBT 50a) of the second embodiment, the on-voltage can be further reduced and the switching loss can be further reduced.

(Embodiment 7)
<Semiconductor device>
Next, a semiconductor device according to a seventh embodiment of the present invention will be described. Since the n barrier region and the p barrier region are formed in the semiconductor device according to the seventh embodiment in the semiconductor device according to the first embodiment, the description of the portions other than the n barrier region and the p barrier region is as follows. Omitted.

  FIG. 37 is a fragmentary cross-sectional view of the semiconductor device of Seventh Embodiment. FIG. 38 is a perspective view of the semiconductor device according to the seventh embodiment.

As shown in FIG. 37, in the IGBT 50f which is the semiconductor device of the seventh embodiment, the n barrier region 14 is formed between the p ⁺ channel region 7 and the n ⁻ drift region 1 in the first region AR1. Yes. The n barrier region 14 is an n type semiconductor region (first conductivity type semiconductor region) in which an n type impurity such as phosphorus (P) or arsenic (As) is diffused. The impurity concentration of n barrier region 14 can be the same as in the third embodiment.

By forming the n barrier region 14, when the first transistor TR1 is in the ON state, holes accumulated excessively in the n ⁻ drift region 1 are discharged to the emitter electrode 12a through the p ⁺ channel region 7 ( (Flowing out) can be suppressed. Therefore, the degree of the IE effect can be adjusted by adjusting the impurity concentration of the n barrier region 14.

As shown in FIG. 37, in the IGBT 50f which is the semiconductor device of the seventh embodiment, in the second region AR2, between the p ⁻ channel region 9 and the n ⁻ drift region 1 and the gate insulating film 6c. , 6d and n ⁻ drift region 1, p barrier region 15 is formed. The p barrier region 15 is a p type semiconductor region (second conductivity type semiconductor region) made of silicon (Si) in which a p type impurity such as boron (B) is diffused. The impurity concentration of the p barrier region 15 can be the same as in the fifth embodiment.

By forming the p barrier region 15, when the second transistor TR 2 is in the ON state, electrons are hardly injected as a leakage current from the emitter electrode 12 b through the p ⁻ channel region 9 into the n ⁻ drift region 1 (difficult to flow in). )Become. Further, by forming the p barrier region 15 in the vicinity of the p ⁻ channel region 9, when the second transistor TR2 is switched from the on state to the off state, holes accumulated excessively in the n ⁻ drift region 1 are It becomes easy to be discharged to the emitter electrode 12b through the p ⁻ channel region 9 (easy to flow out).

  As shown in FIG. 38, in the seventh embodiment, as in the first embodiment, the first transistor TR1 and the second transistor TR2 are adjacent to each other along one direction (the Y direction in FIG. 38). ing.

  Since the operation of the semiconductor device (IGBT 50f) of the seventh embodiment is substantially the same as the operation of the semiconductor device (IGBT 50) of the first embodiment, description thereof is omitted.

However, in the seventh embodiment, when the first transistor TR1 is in the on state, the holes accumulated excessively in the n ⁻ drift region 1 by the n barrier region 14 are discharged to the emitter electrode 12a through the first transistor TR1. To be suppressed.

In the seventh embodiment, when the second transistor TR2 is in the ON state, electrons are injected as a leakage current from the emitter electrode 12b through the second transistor TR2 into the n ⁻ drift region 1 by the p barrier region 15. It suppresses that. In the seventh embodiment, when the second transistor TR2 is switched from the on state to the off state, the holes accumulated excessively in the n ⁻ drift region 1 by the p barrier region 15 are changed to the second transistor TR2. To be discharged to the emitter electrode 12b.

<Manufacturing process of semiconductor device>
Regarding the manufacturing process of the semiconductor device of the seventh embodiment, the processes other than the process of forming the p barrier region 15, the process of forming the n barrier region 14, and the process of forming the p ⁺ channel region 7 are performed. This is the same as the manufacturing method of the semiconductor device of Embodiment 1, and the description thereof is omitted.

  In the seventh embodiment, for example, when the semiconductor layer SL1 is formed, the p barrier region 15 is formed by performing the same process as that described in the fifth embodiment with reference to FIG.

In the seventh embodiment, for example, after the gate electrode 5 is formed and before the p ⁺ channel region 7 is formed, the same process as that described with reference to FIG. 30 in the third embodiment is performed. An n-type impurity is introduced into the semiconductor layer SL1 by ion implantation using the patterned resist film R1 as a mask. Thus, the n barrier region 14 is formed in a portion of the semiconductor layer SL1 that is not covered with the resist film R1 in the first region AR1.

Further, in the seventh embodiment, the same process as that described with reference to FIG. 31 in the third embodiment is performed, and the semiconductor layer SL1 is formed by ion implantation using the patterned resist film R1 as a mask. Type impurities are introduced. As a result, the p ⁺ channel region 7 is formed above the n barrier region 14 in the portion of the semiconductor layer SL1 that is not covered with the resist film R1 in the first region AR1.

<Main features and effects of the present embodiment>
Also in the semiconductor device (IGBT 50f) of the seventh embodiment, as in the semiconductor device (IGBT 50) of the first embodiment, when the first transistor TR1 and the second transistor TR2 are in the on state, holes are transmitted through the first transistor TR1. Electrons flow, but no current flows through the second transistor TR2. Further, when the first transistor TR1 and the second transistor TR2 are switched from the on state to the off state, holes flow through the first transistor TR1 and the second transistor TR2. Therefore, similarly to the semiconductor device (IGBT 50) of the first embodiment, both reduction of on-voltage and reduction of switching loss can be achieved.

Further, in the semiconductor device (IGBT 50f) of the seventh embodiment, the n barrier region 14 is provided between the p ⁺ channel region 7 and the n ⁻ drift region 1 as in the semiconductor device (IGBT 50b) of the third embodiment. Is formed. Therefore, the degree of the IE effect can be adjusted by adjusting the impurity concentration of the n barrier region 14, and the on-voltage can be further reduced as compared with the semiconductor device (IGBT 50) of the first embodiment.

Further, in the semiconductor device (IGBT 50f) of the seventh embodiment, the p barrier region 15 is provided between the p ⁻ channel region 9 and the n ⁻ drift region 1 as in the semiconductor device (IGBT 50d) of the fifth embodiment. Is formed. By forming the p barrier region 15, the leakage current flowing through the second transistor TR2 is suppressed when the second transistor TR2 is in the on state, and when the second transistor TR2 is switched from the on state to the off state, The discharge of holes through the two-transistor TR2 can be promoted. Therefore, the on-voltage can be further reduced and the switching loss can be further reduced as compared with the semiconductor device (IGBT 50b) of the third embodiment.

(Embodiment 8)
<Semiconductor device>
Next, a semiconductor device according to an eighth embodiment of the present invention will be described. Since the n barrier region and the p barrier region are formed in the semiconductor device of the second embodiment, the semiconductor device of the eighth embodiment is described for portions other than the n barrier region and the p barrier region. Omitted.

  FIG. 39 is a perspective view of the semiconductor device of the eighth embodiment.

As shown in FIG. 39, in the IGBT 50g which is the semiconductor device of the eighth embodiment, between the p ⁺ channel region 7 and the n ⁻ drift region 1 similarly to the IGBT 50b which is the semiconductor device of the third embodiment. An n barrier region 14 is formed.

Further, as shown in FIG. 39, in the IGBT 50g which is the semiconductor device of the eighth embodiment, as in the IGBT 50d which is the semiconductor device of the fifth embodiment, the p ⁻ channel region 9 and the n ⁻ drift region 1 A p barrier region 15 is formed between the gate insulating films 6 c and 6 d and the n ⁻ drift region 1.

  As shown in FIG. 39, in the eighth embodiment, as in the second embodiment, the first transistor TR1 and the second transistor TR2 are adjacent to each other along one direction (the Y direction in FIG. 39). Not.

  Since the operation of the semiconductor device (IGBT 50g) of the eighth embodiment is the same as the operation of the semiconductor device (IGBT 50f) of the seventh embodiment, description thereof is omitted.

<Manufacturing process of semiconductor device>
As for the manufacturing process of the semiconductor device of the eighth embodiment, the processes other than the process of forming the p barrier region 15, the process of forming the n barrier region 14, and the process of forming the p ⁺ channel region 7 are performed. This is the same as the manufacturing method of the semiconductor device of Embodiment 2, and the description thereof is omitted.

  In the eighth embodiment, for example, when the semiconductor layer SL1 is formed, the same process as that described in the fifth embodiment with reference to FIG. 35 is performed to form the p barrier region 15.

In the eighth embodiment, for example, after forming the gate electrode 5 and before forming the p ⁺ channel region 7, the same process as that described with reference to FIG. 30 in the third embodiment is performed. An n barrier region 14 is formed.

Further, in the eighth embodiment, the same process as that described with reference to FIG. 31 in the third embodiment is performed to form the p ⁺ channel region 7.

<Main features and effects of the present embodiment>
Also in the semiconductor device (IGBT 50g) of the eighth embodiment, as in the semiconductor device (IGBT 50) of the first embodiment, when the first transistor TR1 and the second transistor TR2 are in the on state, holes are transmitted through the first transistor TR1. Electrons flow, but no current flows through the second transistor TR2. Further, when the first transistor TR1 and the second transistor TR2 are switched from the on state to the off state, holes flow through the first transistor TR1 and the second transistor TR2. Therefore, similarly to the semiconductor device (IGBT 50) of the first embodiment, both reduction of on-voltage and reduction of switching loss can be achieved.

  Further, in the semiconductor device (IGBT 50g) of the eighth embodiment, the first transistor TR1 and the second transistor along one direction (the Y direction in FIG. 39), similarly to the semiconductor device (IGBT 50a) of the second embodiment. TR2 is not adjacent. Therefore, the inter-gate distance W1 of the first transistor TR1 may not be equal to the inter-gate distance W2 of the second transistor TR2. Therefore, the inter-gate distance W1 of the first transistor TR1 and the inter-gate distance W2 of the second transistor TR2 can be individually designed.

Further, in the semiconductor device (IGBT 50g) of the eighth embodiment, the n barrier region 14 is provided between the p ⁺ channel region 7 and the n ⁻ drift region 1 as in the semiconductor device (IGBT 50c) of the fourth embodiment. Is formed. Therefore, the degree of the IE effect can be adjusted by adjusting the impurity concentration of the n barrier region 14, and the on-voltage can be further reduced as compared with the semiconductor device (IGBT 50a) of the second embodiment.

Further, in the semiconductor device (IGBT 50g) of the eighth embodiment, the p barrier region 15 is provided between the p ⁻ channel region 9 and the n ⁻ drift region 1 as in the semiconductor device (IGBT 50e) of the sixth embodiment. Is formed. By forming the p barrier region 15, the leakage current flowing through the second transistor TR2 is suppressed when the second transistor TR2 is in the on state, and when the second transistor TR2 is switched from the on state to the off state, The discharge of holes through the two-transistor TR2 can be promoted. Therefore, the on-voltage can be further reduced and the switching loss can be further reduced as compared with the semiconductor device (IGBT 50c) of the fourth embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the example in which the gate electrode is formed in the trench has been described. However, the present invention is not limited to the case in which the gate electrode is formed in the trench. The present invention can also be applied to a case where a channel region is formed in a region sandwiched between the pair of gate electrodes after the pair of gate electrodes is formed thereon.

  The present invention is effective when applied to a semiconductor device and a manufacturing method thereof.

1 n ⁻ drift region 2 n ⁺ buffer region 3 p ⁺ collector region 3S semiconductor substrate 4, 4 a, 4 b p ⁺⁺ emitter region 5, 5 a to 5 d gate electrode 6, 6 a to 6 d gate insulating film 7 p ⁺ channel region 7 a 7b Inversion layer 8, 8a, 8b n ⁺⁺ Emitter region 9 p ^- channel region 9a, 9b Inversion layer 10 p well region 11 Interlayer insulating film 12, 12a, 12b Emitter electrode 13 Collector electrode 14 n barrier region 15 p barrier region 21 Silicon oxide film 22 Polysilicon film 50, 50a to 50g IGBT
AR1 First region AR2 Second region AR3 Third region CC1, CC2 Recessed portion CH1, CH2 Contact hole OP, OP1-OP4 Opening PS1-PS4 Path R1-R4 Resist film SL1 Semiconductor layers T, T1, T11, T12, T2, T21 , T22, T3, T31, T32, T4, T41, T42 Trench TR1, TR11, TR12 First transistor TR2, TR21, TR22 Second transistor W1, W2 Distance between gates

Claims (15)

A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type formed on one main surface side of the first semiconductor layer;
A first transistor formed on the other main surface side of the first semiconductor layer and including a first gate electrode;
A second transistor formed on the other main surface side of the first semiconductor layer and including a second gate electrode electrically connected to the first gate electrode;
An emitter electrode electrically connected to the first transistor and the second transistor;
A collector electrode electrically connected to the second semiconductor layer;
Have
When the first transistor and the second transistor are in an on state, a current having a first polarity charge and a second polarity charge flows from the collector electrode through the first transistor to the emitter electrode. No current flows through the second transistor;
When the first transistor and the second transistor are switched from the on state to the off state, the charge from the second polarity is transferred from the first semiconductor layer to the emitter electrode through the first transistor and the second transistor. A semiconductor device characterized in that a current flows. The semiconductor device according to claim 1,
The first transistor includes:
A first emitter region of the second conductivity type in contact with the emitter electrode;
A pair of first gate electrodes formed on both sides of the first emitter region;
A pair of first gate insulating films each covering a surface of the pair of first gate electrodes;
A first channel region of the second conductivity type in contact with the first emitter region and the first gate insulating film;
A second emitter region of the first conductivity type in contact with the emitter electrode, the first gate insulating film and the first channel region;
Have
The second transistor is
A third emitter region of the second conductivity type in contact with the emitter electrode;
A pair of second gate electrodes formed on both sides of the third emitter region and spaced apart from each other by a first interval;
A pair of second gate insulating films each covering a surface of the pair of second gate electrodes;
A second channel region of the second conductivity type in contact with the emitter electrode and the second gate insulating film;
Have
Said first interval is W (m), the impurity concentration of the second channel region and N _a (cm ^-3), the elementary charge and q (C), the dielectric constant of the second channel region epsilon (F / M), and when the band gap of the second channel region is V (eV), W <2 × 10 ⁻³ × (2Vε / (qN _a )) ^1/2 is satisfied . The semiconductor device according to claim 1,
A third semiconductor layer formed on the other main surface side of the first semiconductor layer;
The first transistor includes:
A pair of first trenches that are formed apart from each other so as to penetrate the third semiconductor layer;
A pair of first gate insulating films each formed on an inner wall of each of the pair of first trenches;
A pair of first gate electrodes, each of which is formed so as to fill each of the pair of first trenches, each of which is formed on the inner wall with each of the pair of first gate insulating films;
A first emitter region of the second conductivity type formed in a first region sandwiched between the pair of first trenches and in contact with the emitter electrode;
A first channel region of the second conductivity type formed in the first region and in contact with the first emitter region and the first gate insulating film;
A second emitter region of the first conductivity type formed in the first region and in contact with the emitter electrode, the first gate insulating film and the first channel region;
Have
The second transistor is
A pair of second trenches formed to be spaced apart from each other at a first interval so that each penetrates the third semiconductor layer;
A pair of second gate insulating films each formed on the inner wall of each of the pair of second trenches;
A pair of second gate electrodes, each of which is formed so as to embed each of the pair of second trenches, each of which is formed with an inner wall of each of the pair of second gate insulating films;
A third emitter region of the second conductivity type formed in a second region sandwiched between the pair of second trenches and in contact with the emitter electrode;
A second channel region of the second conductivity type formed in the second region and in contact with the emitter electrode and the second gate insulating film;
Have
Said first interval is W (m), the impurity concentration of the second channel region and N _a (cm ^-3), the elementary charge and q (C), the dielectric constant of the second channel region epsilon (F / M), and when the band gap of the second channel region is V (eV), W <2 × 10 ⁻³ × (2Vε / (qN _a )) ^1/2 is satisfied . The semiconductor device according to claim 2,
The first emitter region, the pair of first gate electrodes, the pair of first gate insulating films, the first channel region, and the second emitter region are formed along a first direction in plan view. ,
The pair of first gate electrodes are formed apart from each other at the first interval,
The third emitter region is formed continuously with the first emitter region along the first direction,
Each of the pair of second gate electrodes is formed continuously with each of the pair of first gate electrodes along the first direction,
Each of the pair of second gate insulating films is formed continuously with each of the pair of first gate insulating films along the first direction,
The semiconductor device, wherein the second channel region is formed adjacent to the first channel region and the second emitter region along the first direction. The semiconductor device according to claim 3,
The pair of first trenches are formed apart from each other at the first interval along the first direction,
The first emitter region, the pair of first gate electrodes, the pair of first gate insulating films, the first channel region, and the second emitter region are formed along the first direction in plan view. And
Each of the pair of second trenches is formed continuously with each of the pair of first trenches along the first direction,
The third emitter region is formed continuously with the first emitter region along the first direction,
Each of the pair of second gate insulating films is formed continuously with each of the pair of first gate insulating films along the first direction,
Each of the pair of second gate electrodes is formed continuously with each of the pair of first gate electrodes along the first direction,
The semiconductor device, wherein the second channel region is formed adjacent to the first channel region and the second emitter region along the first direction. The semiconductor device according to claim 3,
A semiconductor device, wherein a first barrier region of the first conductivity type is formed between the first channel region and the first semiconductor layer. The semiconductor device according to claim 5,
A semiconductor device, wherein a first barrier region of the first conductivity type is formed between the first channel region and the first semiconductor layer. The semiconductor device according to claim 3,
A semiconductor device, wherein a second barrier region of the second conductivity type is formed between the second channel region and the first semiconductor layer. The semiconductor device according to claim 5,
A semiconductor device, wherein a second barrier region of the second conductivity type is formed between the second channel region and the first semiconductor layer. The semiconductor device according to claim 6,
A semiconductor device, wherein a second barrier region of the second conductivity type is formed between the second channel region and the first semiconductor layer. The semiconductor device according to claim 7,
A semiconductor device, wherein a second barrier region of the second conductivity type is formed between the second channel region and the first semiconductor layer. (A) preparing a semiconductor substrate including a first semiconductor layer of a first conductivity type and a second semiconductor layer formed on one main surface side of the first semiconductor layer;
(B) forming a pair of first trenches separated from each other and a pair of second trenches separated from each other at a first interval so as to penetrate the second semiconductor layer;
(C) A pair of first gate insulating films is formed on the inner walls of each of the pair of first trenches, and each of the pair of second gate insulating films is formed on the inner walls of the pair of second trenches. Forming step,
(D) A pair of first gate electrodes is formed so as to embed each of the pair of first trenches in which each of the pair of first gate insulating films is formed on the inner wall, and the pair of second gates is formed on the inner wall. Forming a pair of second gate electrodes so as to embed each of the pair of second trenches in which each of the gate insulating films is formed;
(E) forming a second channel type first channel region in a first region sandwiched between the pair of first trenches;
(F) forming a second channel region of the second conductivity type in a second region sandwiched between the pair of second trenches;
(G) forming the second conductivity type first emitter region so as to be in contact with the first channel region apart from any of the pair of first trenches in the first region;
(H) forming a second emitter region of the first conductivity type so as to be in contact with the first gate insulating film and the first channel region in the first region;
(I) forming the second conductivity type third emitter region so as to be in contact with the second channel region apart from any of the pair of second trenches in the second region;
(J) forming an emitter electrode in the first region so as to be in contact with the first emitter region and the second emitter region, and in the second region so as to be in contact with the third emitter region;
(K) forming a second semiconductor layer of the second conductivity type on the opposite side of the first main surface of the first semiconductor layer;
(L) forming a collector electrode so as to be in contact with the third semiconductor layer;
Have
Said first interval is W (m), the impurity concentration of the second channel region and N _a (cm ^-3), the elementary charge and q (C), the dielectric constant of the second channel region epsilon (F / M), and when the band gap of the second channel region is V (eV), W <2 × 10 ⁻³ × (2Vε / (qN _a )) ^1/2 is satisfied Manufacturing method. A method of manufacturing a semiconductor device according to claim 12,
In the step (b), the pair of first trenches separated from each other at the first interval is formed along the first direction, and each of the pair of second trenches is formed along the first direction. , Continuously with each of the pair of first trenches,
In the step (c), each of the pair of second gate insulating films is formed continuously with each of the pair of first gate insulating films along the first direction,
In the step (d), each of the pair of second gate electrodes is formed continuously with each of the pair of first gate electrodes along the first direction,
In the step (f), the second channel region is formed adjacent to the first channel region and the second emitter region along the first direction,
In the step (i), the third emitter region is formed continuously with the first emitter region along the first direction. A method of manufacturing a semiconductor device according to claim 12,
(M) forming a first barrier region of the first conductivity type between the first channel region and the first semiconductor layer;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device according to claim 12,
(N) forming a second barrier region of the second conductivity type between the second channel region and the first semiconductor layer;
A method for manufacturing a semiconductor device, comprising:

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