JP2011090753A - Signal balance control device and optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal balance control device and an optical disk device, which make wobble balance control follow media displacement associated with its rotation, prevent a loss of balance, and also prevent delay in recovering from unrecorded areas and defects. <P>SOLUTION: A balancing circuit 114 includes: a first amplitude detection section 1141 for detecting a first amplitude of an RF component contained in a first channel signal; a second amplitude detection section 1142 for detecting a second amplitude of an RF component contained in a second channel signal; a first multiplier 1143 for multiplying the first channel signal by a second amplitude value detected by the second amplitude detection section; and a second multiplier 1144 for multiplying the second channel signal by a first amplitude value detected by the first amplitude detection section, and performs arithmetic operation for cross-multiplication of RF signal width. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a channel balance of a composite signal including a difference signal component and a sum signal component divided into a plurality of channels in a signal processing system such as an optical or electromagnetic information recording / reproducing apparatus or transmission apparatus. It is related with the signal balance control apparatus which controls and optimizes. In particular, the present invention adjusts the amplitudes of (A + D) and (B + C) signals of, for example, four phenomenon detectors A, B, C, and D in a wobble signal processing system such as an optical disk drive and so on. The present invention relates to a signal balance control device and an optical disc device that optimize in-phase removal of components.

An optical disk drive that records and reproduces an optical disk medium in which a wobble signal or the like is recorded in a groove or radial direction has four phenomenon detectors A, B, C, and D of an optical pickup.
In the optical disk drive, a deviation occurs in the balance between the RF components contained in the A and D system signals (first channel signal) and the B and C system signals (second channel signal) for the following reasons.
This is due to the misalignment of the so-called fields of the four-phenomenon detectors A, B, C, and D of the optical pickup, the lens shift, the deviation of the recording track, and the like.
Since the recording track normally writes data from the inner circumference to the outer circumference, the outer circumference side of this recording track is shaved by the cross-write from the outer circumference side adjacent track, and the track center of the recorded mark row is recorded. There is a tendency to be biased toward the inner peripheral side, and this becomes a bias of the recording track.

In this optical disk drive wobble (or group) signal processing apparatus, the calculation of [G1 * (A + D) −G2 * (B + C)] is performed on the four phenomenon detectors A, B, C, and D ( G1 is a gain of (A + D) system, and G2 is a gain of (B + C) system) to extract a wobble signal.
This type of wobble signal processing apparatus generally has a wobble balance control apparatus for adjusting the gains of G1 and G2 so as to properly remove the common mode of the RF component, and the wobble balance control apparatus includes at least a balance circuit. Is included.

The following two systems are known as wobble balance control devices.
The first is a fixed value adjustment method controlled by an MCU or the like (see Patent Documents 1 to 5).
The second is a feedback control system using negative feedback (see Patent Documents 6 and 7).

JP 2005-302141 A (index: Wobble balance) JP 2005-302140 A (index: Wobble balance, lens shift, Wobble jitter, address error) JP 2002-216379 A (index: Wobble jitter) Japanese Unexamined Patent Publication No. 2000-20968 (index: minimum wobble amplitude of sum signal) JP 10-134386 A (index: maximum wobble amplitude of difference signal) JP 2006-277876 A (Feedback type, independent AGC) JP 2005-353195 A (Feedback type, Balance AGC)

  However, the above-described fixed value adjustment method and feedback control method have the following disadvantages.

  In the fixed value adjustment method, the wobble balance is sequentially adjusted by the MCU based on a static adjustment index such as jitter, and an arbitrary adjustment value (fixed value) is set in the above G1 and G2 to correct the balance. Therefore, it is difficult to dynamically follow the wobble balance control with respect to the circulation fluctuation of the media.

In the feedback control system, since the open loop band cannot be increased from the viewpoint of the stability of the negative feedback loop, the response speed and the recovery speed are slow.
For this reason, the influence of the imbalance is lost when media responds to unrecorded parts or when responding to a defect, and it is appropriate to read the RUB (Recoding Unit Block) at the beginning of the recording or the RUB following the defect. May not work properly.
Specifically, if only one of the (A + D) or (B + C) signal is affected by an adjacent recorded track or affected by a defect, the gain on the side where no RF signal is present Is greatly adjusted, resulting in a significant loss of balance.
In the feedback method that must consider the stability of the feedback loop, the response and recovery are slow, so the above-mentioned imbalance occurs, and the time during which RF common-mode rejection is inappropriate is prolonged. Reading may be hindered.
For this reason, a stable and high-speed wobble balance control method has been required.

Further, the existing balance circuit needs to be mounted as an analog circuit before the A / D converter, and the analog circuit transistor size cannot be reduced in order to maintain analog characteristics such as Gm.
As a result, the existing balance circuit cannot enjoy the benefits of process shrink with respect to the circuit area (chip cost) in LSI.

  The present invention provides a signal balance control device and an optical disc device that can follow wobble balance control in accordance with the circulation fluctuation of a medium and prevent a recovery delay from a loss of balance in an unrecorded area or a defect. There is.

A signal balance control device according to a first aspect of the present invention is formed by signals obtained from a plurality of signal sources, receives a first channel signal and a second channel signal including a difference signal component and a sum signal component, A balance circuit that performs a multiplication operation of an amplitude or level of a predetermined signal component between the first channel signal and the second channel signal, wherein the balance circuit includes a first signal component of a first signal component included in the first channel signal; A first amplitude detector for detecting an amplitude or level; a second amplitude detector for detecting a second amplitude or level of a predetermined signal component included in the second channel signal; and the first channel signal A first multiplier that multiplies the second amplitude value detected by the second amplitude detector, and a second amplitude that is detected by the first amplitude detector is multiplied by the second channel signal. Second power Including a vessel, a.
Note that the above sum signal can be extracted by adding the first channel signal and the second channel signal, such as an RF signal or a SUM signal (pull-in signal) in an optical disc device. Means a signal component that can be suppressed or removed by subtracting the second channel signal,
The difference signal described above can be extracted by subtracting the first channel signal and the second channel signal, such as a wobble signal or a push-pull signal in an optical disc apparatus, and the first channel signal and the second channel signal. Means a signal component that can be suppressed or removed by adding
The above-mentioned predetermined signal component means a signal component used as a control index in the balance adjustment of the first channel signal and the second channel signal. For example, an RF minimum method, a wobble maximum method, a DC balance method, etc. in an optical disc apparatus Suppose that it is selected appropriately according to a desired control index.

An optical disc apparatus according to a second aspect of the present invention is a signal balance control for controlling a signal balance between a first channel signal and a second channel signal according to a signal from a light receiving element of light irradiated on an optical recording medium on which information is recorded. The signal balance control device is formed by signals obtained from a plurality of signal sources, receives the first channel signal and the second channel signal including the difference signal component and the sum signal component, and receives the first channel signal. A balance circuit that performs a multiplication operation on the amplitude or level of the predetermined signal component between the channel signal and the second channel signal, wherein the balance circuit includes a first amplitude or a predetermined signal component included in the first channel signal. A first amplitude detector that detects a level; a second amplitude detector that detects a second amplitude or level of a predetermined signal component included in the second channel signal; A first multiplier for multiplying the first channel signal by the second amplitude value detected by the second amplitude detector; and a first multiplier for detecting the second channel signal detected by the first amplitude detector. A second multiplier that multiplies the amplitude values of the second multiplier and the second multiplier.
Note that the above sum signal can be extracted by adding the first channel signal and the second channel signal, such as an RF signal or a SUM signal (pull-in signal) in an optical disc device. Means a signal component that can be suppressed or removed by subtracting the second channel signal,
The difference signal described above can be extracted by subtracting the first channel signal and the second channel signal, such as a wobble signal or a push-pull signal in an optical disc apparatus, and the first channel signal and the second channel signal. Means a signal component that can be suppressed or removed by adding
The above-mentioned predetermined signal component means a signal component used as a control index in the balance adjustment of the first channel signal and the second channel signal. For example, an RF minimum method, a wobble maximum method, a DC balance method, etc. in an optical disc apparatus Suppose that it is selected appropriately according to a desired control index.

  The present invention is a feedforward type that does not have a negative feedback loop, and it is not necessary to consider the stability of the negative feedback loop. Therefore, it is easy to speed up the response. Therefore, according to the present invention, the wobble balance control can be made to follow the circulation fluctuation of the medium, and the recovery delay from the balance loss in the unrecorded area or the defect can be prevented. Moreover, since perfect balance is realized by the task multiplication operation, the balance adjustment in the conventional fixed value adjustment method can be abolished, and it is the same as the conventional feedback type while being the feed forward type. The above balance accuracy can be realized.

It is a circuit diagram which shows the structure of the signal balance control apparatus which concerns on the 1st Embodiment of this invention. It is a figure which shows the structural example of the 1st RF amplitude detector which concerns on this embodiment, and a 2nd RF amplitude detector. It is a circuit diagram which shows the structure of the signal balance control apparatus which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structural example of the 1st lower limiter which concerns on the 2nd embodiment, a 2nd lower limiter, and a reciprocator. It is a circuit diagram which shows the structure of the signal balance control apparatus which concerns on the 3rd Embodiment of this invention. It is a figure which shows the flowchart of the processing program which concerns on 3rd Embodiment. It is a figure which shows the structural example of the optical recording / reproducing apparatus which can employ | adopt the signal balance control apparatus which concerns on embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The description will be given in the following order. First Embodiment (First Configuration Example of Signal Balance Control Device)
2. Second Embodiment (Second Configuration Example of Signal Balance Control Device)
3. Third Embodiment (Third Configuration Example of Signal Balance Control Device)
4). Fourth Embodiment (Configuration Example of Optical Disc Device)

The signal balance control device 100 of this embodiment is applied to the following optical disc playback device and optical disc recording / playback device (optical disc drive).
The optical disk drive records wobble signals or watermarks formed by arbitrary modulation signals including predetermined physical addresses and additional information and arbitrary periodic waveforms in the groove or radial direction. An optical disc medium.
Access to the optical disk medium is performed by an optical pickup.
The signal balance control device 100 outputs four-phenomenon detectors A, B, C, D of an optical pickup (A, B, C, D in the clockwise direction starting from the upper right and starting from the upper right). And [G1 * (A + D) −G2 * (B + C)] to extract a wobble signal and the like.
The signal balance control device 100 includes a wobble balance control device (balance circuit 114). This wobble balance control device (balance circuit 114) controls the balance of the gains (G1, G2) of the (A + D) signal system and the (B + C) signal system, and the RF signal component existing as an in-phase signal ( (Hereinafter referred to as RF) has a function to properly remove the common mode.
The wobble balance control device (balance circuit 114) realizes perfect balance by performing a so-called task multiplication of RF amplitude between both signal systems, and performs unrecorded or defective (defect) due to negative feedback control. Recovery delay from is eliminated.
In addition, a balance circuit, which has been conventionally mounted as an analog circuit, can be transferred as a logic circuit after the A / D converter, so that the benefits of process shrink can be enjoyed with respect to the circuit area of the LSI.
Hereinafter, a specific configuration and function of the signal balance control device 100 of the present embodiment will be described in detail.

In this embodiment, the amplitudes of the (A + D) and (B + C) signals of the four phenomena (field-shaped) detectors A, B, C, and D of the optical pickup are adjusted to remove in-phase RF components. A wobble balance control apparatus that optimizes the above will be described.
However, the present invention can also be applied to the case of the two-phenomenon detectors E and F (so-called the right of the Japanese letter is the trace direction and the top is the start and the bottom is E and F).

<1. First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a signal balance control apparatus according to the first embodiment of the present invention.
In the following description, the wobble balance control device is described as being synonymous with the balance circuit 114.

The signal balance control device 100 according to the first embodiment includes, for example, a light receiving element 101, a first AC coupling unit 102, a second AC coupling unit 103, and a third unit arranged in an optical pickup (OPU) of an optical disc. An AC coupling unit 104 and a fourth AC coupling unit 105 are included.
The signal balance control device 100 includes a first adder 106 and a second adder 107. The signal balance control apparatus 100 preferably includes a first variable gain unit (hereinafter referred to as GCA) 108, a second GCA 109, a first anti-aliasing filter (hereinafter referred to as AAF) 110, and a second AAF 111. it can.
The signal balance control apparatus 100 includes a first analog / digital converter (hereinafter referred to as ADC) 112, a second ADC 113, a balance circuit 114, a calculator 115, a band pass filter (BPF) 116, and a wobble PLL circuit 117. Have.
The signal balance control device 100 includes an auto gain control (AGC) circuit 118, a demodulation unit 119, a decode unit 120, and a timing generator 121.

  The first AAF 110 and the second AAF 111 are formed by, for example, a low-pass filter (LPF).

  Here, a basic signal definition in the signal balance control apparatus 100 of the present embodiment will be described.

[Definition of input signal]
The (A + D) operation is performed on the output of the four phenomenon detectors (A, B, C, D) of the optical pickup OPU, the first GCA 108 adjusts the gain to a predetermined gain, and the first LPF (AAF) 110 uses the band. This is limited and digitized by the first ADC 112 to obtain the signal Sad (t) of the first channel (ch).
The (B + C) calculation is performed on the output of the four phenomenon detector (A, B, C, D) of the optical pickup OPU, the second GCA 109 adjusts to a predetermined gain, and the second LPF (AAF) 111 uses the band. This is limited and digitized by the second ADC 113 to obtain a second channel signal Sbc (t).
The (A + D) A / D output signal Sad (t) of the first channel and the (B + C) A / D output signal Sbc (t) of the second channel can be defined as follows.

[Equation 1]
Sad (t) = Rad * rf (t) + Wad * wob (t)
Sbc (t) = Rbc * rf (t) − Wbc * wob (t)

Here, rf (t) represents a normalized RF signal (± 1). Rad indicates the absolute value of the RF amplitude of the first channel (A + D). Rbc indicates the absolute value of the RF amplitude of the second channel (B + C).
wob (t) indicates a normalized wobble signal (± 1). Wad indicates the absolute value of the wobble amplitude of the first channel (A + D). Wbc indicates the absolute value of the wobble amplitude of the second channel (B + C).
[End of definition]

The light receiving element 101 is divided into four divided light receiving elements 101-A, 101-B, 101-C, and 101-D.
The divided light receiving element 101-A outputs the first RF signal RF1 to the first AC coupling unit 102, and the divided light receiving element 101-B outputs the second RF signal RF2 to the second AC coupling unit 103. The divided light receiving element 101 -C outputs the third RF signal RF 3 to the third AC coupling unit 104, and the divided light receiving element 101 -D outputs the fourth RF signal RF 4 to the fourth AC coupling unit 105.

First to fourth AC coupling portions 102 to 105 are constituted by capacitors, for example.
The first to fourth AC coupling units 102 to 105 respectively output the direct current components of the first, second, third, and fourth RF signals RF1 to RF4 output from the light receiving element 101 of the optical pickup (OPU). Remove.

  The first adder 106 includes the first RF signal 1 from which the direct current component has been removed by the first AC coupling unit 102 and the fourth RF from which the direct current (DC) component has been removed by the fourth AC coupling unit 105. The signal RF4 is added and output to the first GCA 108.

  The second adder 107 includes the second RF signal 2 from which the direct current component has been removed by the second AC coupling unit 103 and the third RF signal from which the direct current (DC) component has been removed by the third AC coupling unit 104. The signal RF3 is added and output to the second GCA 109.

  The first GCA 108 adjusts the level of the output signal of the first adder 106 in accordance with the variation in the output level of the light receiving element 101 of the optical pickup OPU, and outputs it to the first AAF 110.

  The second GCA 109 adjusts the level of the output signal of the second adder 107 in accordance with the variation in the output level of the light receiving element 101 of the optical pickup OPU, and outputs it to the second AAF 111.

  The first AAF 110 limits the output band of the first GCA 108, prevents aliasing of out-of-band components, and outputs the result to the first ADC 112.

  The second AAF 111 limits the output band of the second GCA 109, prevents aliasing of out-of-band components, and outputs the result to the second ADC 113.

  The first AAF 110 and the second AAF 111 are for preventing aliasing, and a secondary LPF is used in this embodiment. The order is arbitrary.

  The first ADC 112 samples and quantizes the output of the first AAF 110 and outputs it to the balance circuit 114.

  The second ADC 113 samples and quantizes the output of the first AAF 111 and outputs it to the balance circuit 114.

The first ADC 112 and the second ADC 113 are driven by the same sampling clock CLK.
In this embodiment, the sampling clock CLK is generated by the wobble PLL circuit 117 based on the reproduced wobble signal. However, in the embodiment of the present invention, since it is not necessary that CLK is synchronized with the wobble signal, asynchronous sampling using a fixed clock may be used.

  The balance circuit 114 includes a first channel (A + D) A / D output signal Sad (t) of the first ADC 112 and a second channel (B + C) A / D output signal Sbc (t) of the second ADC 113. It has a function of performing multiplication of RF amplitudes.

  The balance circuit 114 of this embodiment is formed as a feed-forward type tacking balance circuit.

  The balance circuit 114 includes a first RF amplitude detector 1141, a second RF amplitude detector 1142, a first multiplier 1143, and a second multiplier 1144.

  The first RF amplitude detector 1141 detects the RF amplitude absolute value Rad of the first channel of the RF component included in the (A + D) A / D output signal Sad (t) of the first channel of the first ADC 112, The detected RF amplitude absolute value Rad is output to the second multiplier 1144.

  The second RF amplitude detector 1142 detects the RF amplitude absolute value Rbc of the second channel of the RF component included in the (B + C) A / D output signal Sbc (t) of the second channel of the second ADC 113, The detected RF amplitude absolute value Rbc is output to the first multiplier 1143.

  FIG. 2 is a diagram illustrating a configuration example of the first RF amplitude detector and the second RF amplitude detector according to the present embodiment.

The first RF amplitude detector 1141 includes a high-pass filter (HPF) 201, a peak hold (PH) circuit 202, a bottom hold (BH) circuit 203, and an arithmetic unit 204.
The second RF amplitude detector 1142 includes an HPF 205, a peak hold (PH) circuit 206, a bottom hold (BH) circuit 207, and an arithmetic unit 208.

The input stages of the first and second RF amplitude detectors 1141 and 1142 include the (A + D) A / D output signal Sad (t) of the first channel and the (B + C) A / D output signal of the second channel. It is possible to have HPFs 201 and 205 for suppressing the DC component of Sbc (t), reducing the wobble component, and extracting the RF component.
The droop time constants (or release time constants) of the PH circuits 202 and 206 and the BH circuits 203 and 207 are preferably sufficiently higher than the wobble signal throughput, and the minimum RF repetition period. The time constant is set so as to realize a sufficiently lower throughput.
The attack time constant is set to a value (for example, about 1/10) sufficiently smaller than the droop time constant.

The PH circuits 202 and 206 have a function of peak-holding the HPF output or input signal.
The BH circuits 203 and 207 have a function of bottom-holding the HPF output or input signal.
The arithmetic units 204 and 208 have a function of taking the difference between the outputs of the PH circuits 202 and 206 and the outputs of the BH circuits 203 and 207 to obtain an RF amplitude value.

  For example, the above configuration can be configured as follows.

  The first and second RF amplitude detectors 1141 and 1142 are an absolute value circuit such as an HPF, an FWR (full wave rectifier circuit) that takes an absolute value of an RF signal component output from the HPF, and an output of the absolute value circuit. Can be configured by an LPF or PH circuit that smoothes the signal.

Further, the first RF amplitude detector 1141 is realized as the sum (or average value) of the output of the amplitude detector relating to the RF component included in the A signal and the output of the amplitude detector relating to the RF component included in the D signal. .
The second RF amplitude detector 1142 is realized as the sum (or average value) of the output of the amplitude detection unit related to the RF component included in the B signal and the output of the amplitude detection unit related to the RF component included in the C signal.

  The first multiplier 1143 takes the first channel (A + D) A / D output signal Sad (t) of the first ADC 112 and the second channel RF amplitude absolute value Rbc from the second RF amplitude detector 1142 as a task. Multiplication and multiplication are performed to obtain the first channel wobble signal Wob1 (t) shown below.

[Equation 2]
Wob1 (t) = Rad * Rbc * rf (t) + Rbc * Wad * wob (t)

  The second multiplier 1144 takes the second channel (A + D) A / D output signal Sbc (t) of the second ADC 113 and the RF amplitude absolute value Rab of the first channel from the first RF amplitude detector 1141 as a task. Multiplication and multiplication are performed to obtain the second channel wobble signal Wob2 (t) shown below.

[Equation 3]
Wob2 (t) = Rad * Rbc * rf (t) − Rad * Wbc * wob (t)

  Then, the arithmetic unit 115 calculates the difference between the first channel wobble signal Wob1 (t) and the second channel wobble signal Wob2 (t) to obtain the following wobble signal Wobout (t).

[Equation 4]
Wobout (t) = (Rbc * Wad + Rad * Wbc) * wob (t)

As a result of the above multiplication, the first term (RF component) of the wch signal Wob1 (t) of the first channel and the wobble signal Wob2 (t) of the second channel is obtained regardless of the imbalance of the first channel and the second channel. The amplitudes are perfectly matched and the RF component is completely removed in real time.
As a result, only the wobble component is extracted.

  Next, the operation according to the above configuration will be described.

The light receiving element 101 is divided into four, and the first RF signal RF1 is output from the divided light receiving element 101-A to the first AC coupling unit 102.
Similarly, the second RF signal RF2 is output from the divided light receiving element 101-B to the second AC coupling unit 103.
A third RF signal RF3 is output from the split light receiving element 101-C to the third AC coupling unit 104.
The fourth RF signal RF4 is output to the fourth AC coupling unit 105 from the divided light receiving element 101-D.

In the first to fourth AC coupling units 102 to 105, the direct current components of the first, second, third, and fourth RF signals RF1 to RF4 output from the light receiving element 101 of the optical pickup (OPU) are respectively provided. Removed.
Then, in the first adder 106, the first RF signal RF1 from which the direct current component has been removed by the first AC coupling unit 102 and the fourth direct current (DC) component from which the fourth AC coupling unit 105 has been removed. Are added to the first GCA 108 and output to the first GCA 108.
Further, in the second adder 107, the second RF signal RF2 from which the direct current component is removed by the second AC coupling unit 103 and the third direct current (DC) component from which the direct current (DC) component is removed by the third AC coupling unit 104. The RF signal RF3 is added and output to the second GCA 109.

In the first GCA 108, the level of the output signal of the first adder 106 is adjusted according to the variation in the output level of the light receiving element 101 of the optical pickup (OPU) and is output to the first AAF 110.
Similarly, in the second GCA 109, the level of the output signal of the second adder 107 is adjusted according to the variation in the output level of the light receiving element 101 of the optical pickup (OPU) and is output to the second AAF 111.

In the first AAF 110, the output band of the first GCA 108 is limited, the aliasing of the out-of-band component is prevented, and the first AAF 110 is output to the first ADC 112.
Further, in the second AAF 111, the output band of the second GCA 109 is limited, the aliasing of the out-of-band component is prevented, and the output is output to the second ADC 113.

Then, the output of the first AAF 110 is sampled and quantized by the first ADC 112 and input to the balance circuit 114 as the (A + D) A / D output signal Sad (t) of the first channel of the digital signal. The
Similarly, the output of the second AAF 111 is sampled and quantized by the second ADC 113, and is input to the balance circuit 114 as the (B + C) A / D output signal Sbc (t) of the second channel of the digital signal. Is done.

In the balance circuit 114, the first RF amplitude detector 1141 calculates the RF amplitude absolute value Rad of the first channel included in the (A + D) A / D output signal Sad (t) of the first channel of the first ADC 112. Detected. The detected RF amplitude absolute value Rad is supplied to the second multiplier 1144.
Further, the second RF amplitude detector 1141 detects the RF amplitude absolute value Rbc of the second channel included in the (B + C) A / D output signal Sbc (t) of the second channel of the second ADC 113. The detected RF amplitude absolute value Rbc is supplied to the first multiplier 1143.

In the first multiplier 1143, the (A + D) A / D output signal Sad (t) of the first channel of the first ADC 112 and the RF amplitude absolute value Rbc of the second channel by the second RF amplitude detector 1142 are obtained. The first channel wobble signal Wob1 (t) is obtained by multiplication with the task. The first channel wobble signal Wob1 (t) is supplied to the first input terminal (+) of the arithmetic unit.
In the second multiplier 1144, the (B + C) A / D output signal Sbc (t) of the second channel of the second ADC 113 and the RF amplitude absolute value Rad of the first channel by the first RF amplitude detector 1141 are obtained. Multiplying by multiplication is performed to obtain a second channel wobble signal Wob2 (t). The second channel wobble signal Wob2 (t) is supplied to the second input terminal (−) of the computing unit 115.
Then, the difference between the first channel wobble signal Wob1 (t) and the second channel wobble signal Wob2 (t) is calculated by the arithmetic unit 115, the RF component is completely removed in real time, and only the wobble component is extracted. Wobout (t) is obtained.

Unnecessary band components are removed from the wobble signal Wobout (t) obtained by the arithmetic unit 115 by the BPF 116 and supplied to the wobble PLL circuit 117, which is used to generate the sampling clock CLK of the first ADC 112 and the second ADC 113. .
The wobble signal Wobout (t) obtained by the arithmetic unit 115 is subjected to processing such as demodulation and decoding via the AGC 118, and is applied to, for example, address and timing generation at the time of writing.

According to the wobble balance control device 100 of the first embodiment, perfect balance is realized by performing so-called task multiplication of RF amplitude between the (A + D) signal system and the (B + C) signal system. Recovery delay from unrecorded or defective due to negative feedback control is eliminated.
In addition, the balance circuit, which is normally mounted in an analog manner, can be moved to the logic side after the ADC, and the benefits of process shrink can be enjoyed with respect to the circuit area in the LSI.

In the first embodiment, since the wobble signal Wobout (t) is muted to zero in an unrecorded portion where no RF exists, it is difficult to reproduce the wobble signal in the unrecorded portion.
An embodiment in which this limitation is improved so that it can be applied to the entire optical disk drive is a second embodiment shown below.

<2. Second Embodiment>
FIG. 3 is a circuit diagram showing a configuration of a signal balance control apparatus according to the second embodiment of the present invention.

  The signal balance control device 100A according to the second embodiment is different from the signal balance control device 100 according to the first embodiment in the following points.

In the signal balance control apparatus 100A, in the balance circuit 114A, a signal processing unit 1145 is disposed between the outputs of the first and second RF amplitude detectors 1141 and 1142 and the first and second multipliers 1143 and 1144. .
The signal processing unit 1145 performs predetermined processing on the RF amplitude absolute value Rad of the first channel of the first RF amplitude detector 1141 and the RF amplitude absolute value Rbc of the second channel of the second RF amplitude detector 1142 to perform the first processing. Control signal G1 and second control signal G2 are generated.
The first multiplier 1143 multiplies the first channel (A + D) A / D output signal Sad (t) of the first ADC 112 by the second control signal G2.
The second multiplier 1144 multiplies the second control (B + C) A / D output signal Sbc (t) of the second ADC 113 by the first control signal G1.
As a result, the balance circuit 114A performs control based on the RF amplitude between the (A + D) A / D output signal Sad (t) of the first channel and the (B + C) A / D output signal Sbc (t) of the second channel. Performs signal multiplication.

The signal processing unit 1145 that performs this predetermined processing functions as a gain normalization unit.
The signal processing unit 1145 sets the lower limit of each of the outputs of the first and second RF amplitude detectors 1141 and 1142 or the average value (or sum) of the outputs of the first and second RF amplitude detectors 1141 and 1142. It includes a lower limiter that limits any positive value to a non-zero positive value.

More specifically, the signal processing unit 1145 includes a first lower limit limiter 11451 and a second lower limit limiter 11452.
Further, the signal processing unit 1145 includes an adder 11453, an inverse number 11454, a third multiplier 11455, and a fourth multiplier 11456.

The first lower limiter 11451 has a function of limiting the lower limit of the output of the first RF amplitude detector 1141 to a positive value that is not zero with an arbitrary threshold.
The first lower limiter 11451 outputs the RF amplitude absolute value Rad0 with the lower limit restricted to the adder 11453 and the third multiplier 11455.

The second lower limiter 11452 has a function of limiting the lower limit of the output of the second RF amplitude detector 1142 to a positive value that is not zero with an arbitrary threshold.
Second lower limiter 11452 outputs RF amplitude absolute value Rbc0 with the lower limit restricted to adder 11453 and fourth multiplier 11456.

  The adder 11453 obtains an RF amplitude value obtained by adding the RF amplitude absolute value Rad0 of the first lower limiter 11451 and the RF amplitude absolute value Rbc0 of the second lower limiter 11452, and outputs the RF amplitude value to the reciprocator 11454. To do.

  The reciprocal unit 11454 calculates the reciprocal of the output (RF amplitude value) of the supplied adder 11453, and outputs it to the third multiplier 11455 and the fourth multiplier 11456 as a signal G0.

The third multiplier 11455 multiplies the output Rad0 of the first lower limiter 11451 and the output signal G0 of the reciprocator 11454 to obtain the first control signal G1, and the first control signal G1 is used as the second multiplier. 1144.
The fourth multiplier 11456 multiplies the output Rbc0 of the second lower limiter 11452 and the output signal G0 of the reciprocator 11454 to obtain the second control signal G2, and uses the second control signal G2 as the first multiplier. 1143 is output.

FIG. 4 is a diagram illustrating a configuration example of the first lower limiter, the second lower limiter, and the reciprocator according to the second embodiment.
In the configuration of FIG. 4, a shift-down unit 11457 that shifts down by 1 bit and obtains an average value of the output of the adder 11453 (1/2) is disposed at the output unit of the adder 11453. Note that this shift-down function may be integrated with an LUT 221 described later.

The first lower limiter 11451 has a comparator 211 and a multiplexer 212.
The comparator 211 compares the RF amplitude absolute value Rad of the first RF amplitude detector 1141 with the threshold value Vth, and outputs the result to the multiplexer 212 as a signal S211.
The multiplexer 212 selects the RF amplitude absolute value Rad or the threshold value Vth in accordance with the signal S211, and outputs the RF amplitude absolute value Rad or the threshold value Vth to the adder 11453 and the third multiplier 11455 as the RF amplitude absolute value Rad0.
The first lower limit limiter 11451 outputs the RF amplitude absolute value Rad as the RF amplitude absolute value Rad0 when the RF amplitude absolute value Rad is larger than the threshold value Vth, and outputs the threshold Vth as the RF amplitude absolute value Rad0 when it is smaller. To do.

The second lower limiter 11452 includes a comparator 213 and a multiplexer 214.
The comparator 213 compares the RF amplitude absolute value Rbc of the second RF amplitude detector 1142 with the threshold value Vth, and outputs the result to the multiplexer 214 as a signal S213.
The multiplexer 214 selects the RF amplitude absolute value Rbc or the threshold value Vth according to the signal S213 and outputs the RF amplitude absolute value Rbc or the threshold value Vth to the adder 11453 and the fourth multiplier 11456 as the RF amplitude absolute value Rbc0.
The second lower limiter 11452 outputs the RF amplitude absolute value Rbc as the RF amplitude absolute value Rbc0 when the RF amplitude absolute value Rbc is larger than the threshold Vth, and outputs the threshold Vth as the RF amplitude absolute value Rbc0 when smaller. To do.

The reciprocal unit 11454 includes a first look-up table (LUT) 221, a second LUT 222, a third LUT 223, and subtracters or anti-phase adders 224 and 225.
The first LUT 221 has a function of logarithmically converting the output of the adder.
The third LUT 223 has a function of logarithmically converting the target gain K.
The subtracters or anti-phase adders 224 and 225 have a function of subtracting the output of the first LUT 221 from the output of the third LUT 223.
The second LUT 222 has a function of exponentially converting the outputs of the subtracters or anti-phase adders 224 and 225 and outputting the result as a signal G0.

  For example, the above configuration can be configured as follows.

  The reciprocal unit 11454 includes a first LUT 221 for logarithmically converting the output of the adder 11453, a subtractor or anti-phase adders 224 and 225 for subtracting the output of the first LUT 221 from the logarithmic (dB) conversion value of the target gain K, , And a second LUT 222 that exponentially converts the output.

  The reciprocal unit 11454 is configured as a single LUT having a first input that provides a target gain K (linear or logarithmic (dB) conversion value) and a second input that connects the output of the adder 11453. Is also possible.

Further, the adder 11453 and the reciprocator 11454 are configured as follows.
These are a first input connecting the output of the first lower limiter 11451, a second input connecting the output of the second lower limiter 11452, and a target gain K (linear or logarithmic (dB) conversion value). Can be configured as a single LUT with a third input providing

The example in which the signal processing unit 1145 of the balance circuit 114A according to the second embodiment is configured with hardware (HW) has been described above.
Hereinafter, more specific processing of the balance circuit 114A according to the second embodiment will be described.

The first RF amplitude detector 1141 detects the RF amplitude absolute value Rad of the first channel.
This RF amplitude absolute value Rad is input to the first lower limiter 11451, and the lower limit of amplitude is limited by the threshold value Vth as follows.

[Equation 5]
Rad0 = Rad (Rad ≧ Vth)
Rad0 = Vth (Rad <Vth)

The second RF amplitude detector 1142 detects the RF amplitude absolute value Rbc of the second channel.
This RF amplitude absolute value Rbc is input to the second lower limiter 11452, and the amplitude lower limit is limited by the threshold value Vth as follows.

[Equation 6]
Rbc0 = Rbc (Rbc ≧ Vth)
Rbc0 = Vth (Rbc <Vth)

The first and second lower limit limiters 11451 and 11452 can read the wobble signal of the unrecorded portion by preventing Wobout (t) from being muted to zero in the unrecorded portion where no RF exists. To.
Further, the first and second lower limiters 11451 and 11452 prevent the occurrence of zero division divergence due to signal loss such as a defect during normalization described later.
An example of RTL for the first and second lower limit limiters 11451 and 11452 is shown below.

module lowlim (in, vth, out);
input (N: 0) in;
input (N: 0) vth;
output (N: 0) out;
if (in <vth)
assign out = vth;
else
assign out = in;
endmodule

The threshold value Vth is determined to be, for example, about 1/8 or less of the average RF amplitude in the steady state.
The outputs Rad0 and Rbc0 of the first and 11452 are input to the adder 11453, and an average value RFamp of the RF amplitude is obtained as shown below.

[Equation 7]
RFamp = (Rad0 + Rbc0) / 2
RFamp = (Rad + Rbc) / 2 (Rad ≧ Vth .and. Rbc ≧ Vth); steady state
RFamp = (Rad + Vth) / 2 (Rad ≧ Vth .and. Rbc <Vth);
RFamp = (Vth + Rbc) / 2 (Rad <Vth .and.Rbc ≧ Vth);
RFamp = Vth (Rad <Vth .and. Rbc <Vth); unrecorded state

  Note that the one-sided state refers to a portion where recording exists only in the adjacent track. The same applies hereinafter.

  The RF amplitude average value RFamp is input to the reciprocator 11454. In the inverse number 11454, a coefficient G0 for normalizing the overall gain of the wobble balance control apparatus 100A is generated.

  The output signal G0 of the reciprocal unit 11454 is determined as follows when the target gain is K.

[Equation 8]
G0 = K / RFamp
G0 = 2 * K / (Rad + Rbc) (Rad ≧ Vth .and.Rbc ≧ Vth); steady state
G0 = 2 * K / (Rad + Vth) (Rad ≧ Vth .and.Rbc <Vth);
G0 = 2 * K / (Vth + Rbc) (Rad <Vth .and. Rbc ≧ Vth);
G0 = K / Vth (Rad <Vth .and. Rbc <Vth); unrecorded state

  The output Rad0 of the first lower limit limiter 11451 is multiplied by the output signal G0 of the reciprocator 11454 to obtain a first balance control gain G1 as a first control signal shown below.

[Equation 9]
G1 = G0 * Rad0
G1 = 2 * K * Rad / (Rad + Rbc) (Rad ≧ Vth .and. Rbc ≧ Vth); steady state
G1 = 2 * K * Rad / (Rad + Vth) (Rad ≧ Vth .and.Rbc <Vth);
G1 = 2 * K * Vth / (Vth + Rbc) (Rad <Vth .and.Rbc ≧ Vth);
G1 = K (Rad <Vth .and. Rbc <Vth); unrecorded state

  The output Rbc0 of the second lower limiter 11452 is multiplied by the output signal G0 of the reciprocator 11454 to obtain a second balance control gain G2 as a second control signal shown below.

[Equation 10]
G2 = G0 * Rbc0
G2 = 2 * K * Rbc / (Rad + Rbc) (Rad ≧ Vth .and.Rbc ≧ Vth); steady state
G2 = 2 * K * Vth / (Rad + Vth) (Rad ≧ Vth .and.Rbc <Vth);
G2 = 2 * K * Rbc / (Vth + Rbc) (Rad <Vth .and.Rbc ≧ Vth);
G2 = K (Rad <Vth .and. Rbc <Vth); unrecorded state

  The first multiplier 1143 multiplies the above-mentioned Sad (t) and the second balance control gain G2 by multiplication and obtains the first channel wobble signal Wob1 (t) shown below.

[Equation 11]
Wob1 (t) = G2 * Sad (t)
Wob1 (t) = 2 * K * [Rad * Rbc * rf (t) + Rbc * Wad * wob (t)] / (Rad + Rbc)
; (Rad ≧ Vth .and. Rbc ≧ Vth); Steady state
Wob1 (t) = 2 * K * [Rad * Vth * rf (t) + Vth * Wad * wob (t)] / (Rad + Vth)
; (Rad ≧ Vth .and. Rbc <Vth);
Wob1 (t) = 2 * K * [Rad * Rbc * rf (t) + Rbc * Wad * wob (t)] / (Vth + Rbc)
; (Rad <Vth .and. Rbc ≧ Vth); one-sided writing state
Wob1 (t) = K * [Rad * rf (t) + Wad * wob (t)]
; (Rad <Vth .and. Rbc <Vth); Unrecorded state

  The second multiplier 1144 multiplies the above-described Sbc (t) and the first balance control gain G1 by multiplication and obtains the second channel wobble signal Wob2 (t) shown below.

[Equation 12]
Wob2 (t) = G1 * Sbc (t)
Wob2 (t) = 2 * K * [Rad * Rbc * rf (t) − Rad * Wbc * wob (t)] / (Rad + Rbc)
; (Rad ≧ Vth .and. Rbc ≧ Vth); Steady state
Wob2 (t) = 2 * K * [Rad * Rbc * rf (t) − Rad * Wbc * wob (t)] / (Rad + Vth)
; (Rad ≧ Vth .and. Rbc <Vth);
Wob2 (t) = 2 * K * [Vth * Rbc * rf (t) − Vth * Wbc * wob (t)] / (Vth + Rbc)
; (Rad <Vth .and. Rbc ≧ Vth); one-sided writing state
Wob2 (t) = K * [Rbc * rf (t) − Wbc * wob (t)]
; (Rad <Vth .and. Rbc <Vth); Unrecorded state

  Then, the arithmetic unit 115 obtains the difference between the first channel wobble signal Wob1 (t) and the second channel wobble signal Wob2 (t), and in the steady state in which the lower limiter is not operating, as shown below. A wobble signal Wobout (t) containing no components is obtained.

[Equation 13]
Wobout (t) = Wob1 (t)-Wob2 (t)
Wobout (t) = 2 * K * [(Rbc * Wad + Rad * Wbc) / (Rad + Rbc)] * wob (t)
; (Rad ≧ Vth .and. Rbc ≧ Vth); Steady state
Wobout (t) = 2 * K * [Rad * (Vth−Rbc) * rf (t) + (Vth * Wad + Rad * Wbc) * wob (t)] / (Rad + Vth)
; (Rad ≧ Vth .and. Rbc <Vth);
Wobout (t) = 2 * K * [Rbc * (Rad−Vth) * rf (t) + (Rbc * Wad + Vth * Wbc) * wob (t)] / (Vth + Rbc)
; (Rad <Vth .and. Rbc ≧ Vth); one-sided writing state
Wobout (t) = K * [(Rad−Rbc) * rf (t) − (Wad + Wbc) * wob (t)]
; (Rad <Vth .and. Rbc <Vth); Unrecorded state
Wobout (t) ≒ K * (Wad + Wbc) * wob (t)
; (Rad ≒ 0 .and. Rbc ≒ 0); Unrecorded state

As a result of the above-described multiplication by multiplication, in the steady state (Rad ≧ Vth .and. Rbc ≧ Vth), the first of Wob1 (t) and Wob2 (t) is the same regardless of any imbalance of balance between the first channel and the second channel. The amplitude of the term (RF component) is completely matched. Then, the RF component is completely removed in real time, and only the wobble component is extracted.
In addition, when the RF signal is greatly out of balance, such as a portion where recording is present only in the adjacent track (one-write state), the wobble signal on the side where the RF amplitude with a good S / N ratio is sufficiently small is extracted.
Further, a fixed gain is obtained in a portion where no RF exists, such as an unrecorded portion or a defect portion.

<3. Third Embodiment>
FIG. 5 is a circuit diagram showing a configuration of a signal balance control device according to the third embodiment of the present invention.

  The signal balance control device 100B according to the third embodiment is different from the signal balance control device 100A according to the second embodiment in the following points.

The signal balance control device 100A of the second embodiment is arranged between the outputs of the first and second RF amplitude detectors 1141 and 1142 and the first and second multipliers 1143 and 1144 in the balance circuit 114A. The signal processing unit 1145 was formed of hardware.
On the other hand, in the balance circuit 114B of the signal balance control device 100B of the third embodiment, the processing procedure of the signal processing unit 1145B is formed by firmware (FW).

The signal processing unit 1145B that performs the predetermined processing includes a first data capturing unit 231, a second data capturing unit 232, an MCU 233 as a control unit, a first control register 234, and a second control register. 235, a memory 236, and a timer circuit 237.
As the control unit, a DSP can be applied instead of the MCU.
The first data capturing unit 231, the second data capturing unit 232, the MCU (or DSP) 233, the first control register 234, the second control register 235, and the memory 236 are connected to the bus 238. ing.

The first data capturing unit 231 has a function of delivering the output signal of the first RF amplitude detector 1141 to the MCU 233.
The second data capturing unit 232 has a function of delivering the output signal of the second RF amplitude detector 1142 to the MCU 233.

  The MCU 233 performs predetermined processing on the data acquired from the first data fetching unit 231 and the second data fetching unit 232 in accordance with a program stored in the memory 236, and performs first control data. G1 and second control data G2 are obtained.

The first control register 234 writes the first control data G1 from the MCU 233.
The second control register 235 writes the second control data G2 from the MCU 233.

In the balance circuit 114B, the first multiplier 1143 multiplies the first control (A + D) A / D output signal Sad (t) of the first ADC 112 by the second control data G2.
The second multiplier 1144 multiplies the second control (B + C) A / D output signal Sbc (t) of the second ADC 113 by the first control data G1.
As a result, the balance circuit 114B performs control based on the RF amplitude between the (A + D) A / D output signal Sad (t) of the first channel and the (B + C) A / D output signal Sbc (t) of the second channel. Data multiplication is performed.

When applied to an analog processing system, the first and second data capturing units 231 and 232 can be configured to include an ADC.
Similarly, the outputs of the first and second control registers 234 and 235 are connected to the first and second control digital analog converters (DAC).
And a first GCA that multiplies the output of the second control DAC by the (A + D) signal, and a second GCA that multiplies the value of the first control DAC by the (B + C) signal, It is also possible to configure so that RF amplitude multiplication is performed between the (A + D) signal and the (B + C) signal.
In this case, the first GCA forms a first multiplier and the second GCA forms a second multiplier.

The signal processing unit 1145B that performs the predetermined processing includes the following conditional branch step processing.
The conditional branch step arbitrarily sets a lower limit of each of the outputs of the first and second RF amplitude detectors 1141 and 1142 or the average value (or sum) of the outputs of the first and second RF amplitude detectors 1141 and 1142. To a positive value that is not zero.

The signal processing unit 1145B based on the firmware includes the following processing as step processing processed by the MCU 233.
That is, the processing of the MCU 233 includes a first conditional branch step, a second conditional branch step, an addition step, a division step, a first multiplication step, and a second multiplication step.

The first conditional branching step limits the lower limit of the output of the first RF amplitude detector 1141 to a positive value that is not zero with an arbitrary threshold Vth.
The second conditional branch step limits the lower limit of the output of the second RF amplitude detector 1142 to a positive non-zero value with an arbitrary threshold Vth.
The addition step adds the outputs of the first conditional branch step and the second conditional branch step to obtain an RF amplitude value.
The division step calculates the reciprocal of the RF amplitude value.
In the first multiplication step, the reciprocal of the RF amplitude value is multiplied by the value in the first branch condition step to obtain first control data.
In the second multiplication step, the reciprocal of the RF amplitude value is multiplied by the value in the second branch condition step to obtain first control data.

The example in which the signal processing unit 1145B of the balance circuit 114B according to the third embodiment is configured by firmware (FW) has been described above.
Hereinafter, more specific processing of the balance circuit 114B according to the third embodiment will be described with reference to FIG.
FIG. 6 is a diagram showing a flowchart of a processing program according to the third embodiment.

The first RF amplitude detector 1141 detects the RF amplitude absolute value Rad of the first channel.
The second RF amplitude detector 1142 detects the RF amplitude absolute value Rbc of the second channel.
On the data bus 238 of the MCU 233, a memory 236 storing a processing program, first and second data fetching units 231 and 232, and first and second control registers 234 and 235 are arranged. ing.
Further, the MCU 233 can include a timer circuit 237 that generates an interrupt signal for periodically starting a processing program (task). Preferably, it is desirable to start the task about 8 times per one rotation of the disk.

In step ST11, the MCU 233 acquires the RF amplitude absolute value Rad of the first channel from the first data capturing unit 231.
The MCU 233 acquires the RF amplitude absolute value Rbc of the second channel from the second data capturing unit 232.
In steps ST12 and ST13, the MCU 233 compares the RF amplitude absolute value Rad with the threshold value Vth, and limits the lower limit of the RF amplitude absolute value Rad as follows.

[Formula 14]
Rad = Rad (Rad ≧ Vth)
Rad = Vth (Rad <Vth)

  In steps ST14 and ST15, the MCU 233 compares the RF amplitude absolute value Rbc with the threshold value Vth, and limits the lower limit of the RF amplitude absolute value Rbc as follows.

[Equation 15]
Rbc = Rbc (Rbc ≧ Vth)
Rbc = Vth (Rbc <Vth)

The lower limit processing described above prevents Wobout (t) from being muted to zero in an unrecorded portion where there is no RF so that the Wobble signal in the unrecorded portion can be read.
Further, it prevents the occurrence of zero-divergence due to signal loss such as defect during normalization described later.
The lower limit value Vth is set to a sufficiently small value with respect to the RF steady amplitude, for example, about 1/8 or less of the RF steady amplitude.

  In step ST16, the MCU 233 obtains the RF average amplitude RFamp from the above Rad and Rbc as shown below.

[Equation 16]
RFamp = (Rad + Rbc) / 2 (Rad ≧ Vth .and. Rbc ≧ Vth); steady state
RFamp = (Rad + Vth) / 2 (Rad ≧ Vth .and. Rbc <Vth);
RFamp = (Vth + Rbc) / 2 (Rad <Vth .and.Rbc ≧ Vth);
RFamp = Vth (Rad <Vth .and. Rbc <Vth); unrecorded state

  In step ST17, the MCU 233 obtains the first balance control gain G1 and the second balance control gain G2 from the Rad, Rbc, RFamp and the target gain K.

[Equation 17]
G1 = K * Rad / RFamp
G1 = 2 * K * Rad / (Rad + Rbc) (Rad ≧ Vth .and. Rbc ≧ Vth); steady state
G1 = 2 * K * Rad / (Rad + Vth) (Rad ≧ Vth .and.Rbc <Vth);
G1 = 2 * K * Vth / (Vth + Rbc) (Rad <Vth .and.Rbc ≧ Vth);
G1 = K (Rad <Vth .and. Rbc <Vth); unrecorded state
G2 = K * Rbc / RFamp
G2 = 2 * K * Rbc / (Rad + Rbc) (Rad ≧ Vth .and.Rbc ≧ Vth); steady state
G2 = 2 * K * Vth / (Rad + Vth) (Rad ≧ Vth .and.Rbc <Vth);
G2 = 2 * K * Rbc / (Vth + Rbc) (Rad <Vth .and.Rbc ≧ Vth);
G2 = K (Rad <Vth .and. Rbc <Vth); unrecorded state

  In step ST18, the MCU 233 writes the first balance control gain G1 and the second balance control gain G2 into the first control register 234 and the second control register 235. Preferably, a defect hold step (not shown) can be added to steps ST12 to ST18.

  The first multiplier 1143 multiplies the above-mentioned Sad (t) and the second balance control gain G2 by multiplication and obtains the following first channel wobble signal Wob1 (t).

[Equation 18]
Wob1 (t) = G2 * Sad (t)
Wob1 (t) = 2 * K * [Rad * Rbc * rf (t) + Rbc * Wad * wob (t)] / (Rad + Rbc)
; (Rad ≧ Vth .and. Rbc ≧ Vth); Steady state
Wob1 (t) = 2 * K * [Rad * Vth * rf (t) + Vth * Wad * wob (t)] / (Rad + Vth)
; (Rad ≧ Vth .and. Rbc <Vth);
Wob1 (t) = 2 * K * [Rad * Rbc * rf (t) + Rbc * Wad * wob (t)] / (Vth + Rbc)
; (Rad <Vth .and. Rbc ≧ Vth); one-sided writing state
Wob1 (t) = K * [Rad * rf (t) + Wad * wob (t)]
; (Rad <Vth .and. Rbc <Vth); Unrecorded state

  The second multiplier 1144 multiplies the above-described Sbc (t) and the first balance control gain G1 by multiplication to obtain a second channel wobble signal Wob2 (t) shown below.

[Equation 19]
Wob2 (t) = G1 * Sbc (t)
Wob2 (t) = 2 * K * [Rad * Rbc * rf (t) − Rad * Wbc * wob (t)] / (Rad + Rbc)
; (Rad ≧ Vth .and. Rbc ≧ Vth); Steady state
Wob2 (t) = 2 * K * [Rad * Rbc * rf (t) − Rad * Wbc * wob (t)] / (Rad + Vth)
; (Rad ≧ Vth .and. Rbc <Vth);
Wob2 (t) = 2 * K * [Vth * Rbc * rf (t) − Vth * Wbc * wob (t)] / (Vth + Rbc)
; (Rad <Vth .and. Rbc ≧ Vth); one-sided writing state
Wob2 (t) = K * [Rbc * rf (t) − Wbc * wob (t)]
; (Rad <Vth .and. Rbc <Vth); Unrecorded state

  Then, the arithmetic unit 115 calculates the difference between the first channel wobble signal Wob1 (t) and the second channel wobble signal Wob2 (t) to obtain a Wobble signal Wobout (t) as shown below.

[Equation 20]
Wobout (t) = Wob1 (t)-Wob2 (t)
Wobout (t) = 2 * K * [(Rbc * Wad + Rad * Wbc) / (Rad + Rbc)] * wob (t)
; (Rad ≧ Vth .and. Rbc ≧ Vth); Steady state
Wobout (t) = 2 * K * [Rad * (Vth−Rbc) * rf (t) + (Vth * Wad + Rad * Wbc) * wob (t)] / (Rad + Vth)
; (Rad ≧ Vth .and. Rbc <Vth);
Wobout (t) = 2 * K * [Rbc * (Rad−Vth) * rf (t) + (Rbc * Wad + Vth * Wbc) * wob (t)] / (Vth + Rbc)
; (Rad <Vth .and. Rbc ≧ Vth); one-sided writing state
Wobout (t) = K * [(Rad−Rbc) * rf (t) − (Wad + Wbc) * wob (t)]
; (Rad <Vth .and. Rbc <Vth); Unrecorded state
Wobout (t) ≒ K * (Wad + Wbc) * wob (t)
; (Rad ≒ 0 .and. Rbc ≒ 0); Unrecorded state

As a result of the above-described multiplication by multiplication, in the steady state (Rad ≧ Vth .and. Rbc ≧ Vth), the first of Wob1 (t) and Wob2 (t) is the same regardless of any imbalance in balance between the first channel and the second channel. The amplitude of the term (RF component) is completely matched. Then, the RF component is completely removed in real time, and only the wobble component is extracted.
In addition, when the RF signal is greatly out of balance such as in a portion where recording exists only in the adjacent track (one-write state), a wobble signal on the side where the RF amplitude with a good S / N ratio is sufficiently small is extracted.
In addition, a fixed gain is obtained in a portion where there is no RF, such as an unrecorded or defective portion.

According to the above first to third embodiments, the following effects can be obtained.
In the present embodiment, RF amplitude task multiplication is performed between the (A + D) signal system and the (B + C) signal system in the wobble balance control device in the wobble signal processing system of the optical disk drive.
As a result, complete balance can be realized without using the negative feedback control loop, and recovery delays from unrecorded areas and defects caused by the negative feedback control can be eliminated.
In this embodiment, since it is a feedforward type configuration that does not use negative feedback, it is not necessary to consider loop stability in negative feedback control, and the response speed of the wobble balance control device of this embodiment Can be determined only by the time constants of the first and second amplitude detectors.
For this reason, it becomes possible to increase the response speed of the balance control, and it becomes easy to follow the circular fluctuation, the single writing, and the defect. As a result, it is possible to recover quickly from the influence of the imbalance of the medium such as a medium in which unrecorded parts are mixed or at the time of a defect response, thereby improving the readability.

  In addition, according to the present embodiment, it is possible to transfer a balance circuit, which is conventionally mounted as an analog circuit in the previous stage of A / D, as a logic circuit in the subsequent stage of A / D, and in terms of circuit area (chip cost), It is possible to enjoy the benefits of shrinking.

  Note that the above-described apparatus can be applied to an optical recording / reproducing apparatus (optical disk apparatus) such as a Blu-ray disc (registered trademark) on which a semiconductor laser having a wavelength of 400 nm is mounted.

<4. Fourth Embodiment>
FIG. 7 is a diagram showing a configuration example of an optical disc apparatus that can employ the signal balance control apparatus according to the embodiment of the present invention.

  The optical recording / reproducing apparatus 300 includes a recording medium (for example, an optical disc) 301, an optical pickup (optical head) 310, a signal processing system 320, a servo control unit 330, and a drive circuit 340.

The optical head 310 is driven by a laser driving circuit, a laser diode 311 for recording / reproducing digital data, a light receiving element 312 for detecting laser light emitted by the laser diode 311, an optical A system 613, an objective lens 314, and the like.
The light receiving element 312 corresponds to the light receiving element 101 in each of the above-described embodiments.

The signal processing system 320 includes the signal balance control devices 100, 100A, and 100B of the first to third embodiments described above.
Further, the signal processing system 320 includes a servo error signal detection device, and the tracking error signal TE and the photo signal which are servo system signals are output from the output signals of the optical pickups such as A, B, C and D. -Extraction processing of the cascade signal FE or the like is performed. In particular, the signal path before the ADC (112, 113) according to the embodiment of the present invention can be shared for the TE signal detector based on the phase difference detection (DPD) method.

  The servo control unit 330 performs servo control based on the tracking error signal TE, the focus error signal FE, and the like obtained in the signal processing system 320 under the control of a system controller (not shown). The drive circuit 340 is controlled.

  The drive circuit 340 drives the tracking mechanism unit of the objective lens 314, for example.

  This optical recording / reproducing apparatus is an example, and it goes without saying that the optical recording apparatus to which the present invention is applied is not limited to the configuration shown in FIG.

  DESCRIPTION OF SYMBOLS 100, 100A, 100B ... Signal balance control apparatus, 101 ... Light receiving element, 102 ... 1st AC coupling part, 103 ... 2nd AC coupling part, 104 ... 3rd AC Coupling unit 105... Fourth AC coupling unit 106... First adder 107. Second adder 108... First variable gain unit (GCA) 109. .. Second GCA, 110... First antialiasing filter (AAF), 111... Second AAF, 112... First analog / digital converter (ADC), 113. 2nd ADC, 114, 114A, 114B ... balance circuit, 1141 ... first RF amplitude detector, 1142 ... second RF amplitude detector, 1143... First multiplier, 1144 ... Second multipliers 1145 and 114 B ... signal processing unit, 11451 ... first lower limiter, 11452 ... second lower limiter, 11453 ... adder, 11454 ... reciprocal calculator, 11455 ... third multiplication , 11456... Fourth multiplier, 11456, 115... Operator, 116... Band pass filter (BPF), 117... Wobble PLL circuit, 231. Capture unit, 232... Second data capture unit, 233... MCU (or DSP), 234... First control register, 235... Second control register, 236. Memory, 237... Timer circuit.

Claims (20)

A first signal and a second channel signal formed by signals obtained from a plurality of signal sources, including a difference signal component and a sum signal component, and a predetermined signal component between the first channel signal and the second channel signal. A balance circuit that performs multiplication of the amplitude or level of
The balance circuit is
A first amplitude detector that detects a first amplitude or level of a predetermined signal component included in the first channel signal;
A second amplitude detector for detecting a second amplitude or level of a predetermined signal component included in the second channel signal;
A first multiplier for multiplying the first channel signal by a second amplitude value detected by the second amplitude detector;
A second multiplier that multiplies the second channel signal by the first amplitude value detected by the first amplitude detector; and a signal balance control device. The balance circuit is
A signal processing unit that performs a predetermined process on the first amplitude of the first amplitude detection unit and the second amplitude value of the second amplitude detection unit to generate a first control signal and a second control signal. Including
A first multiplier for multiplying the first channel signal by the second control signal;
A second multiplier for multiplying the second channel signal by the first control signal;
The signal balance control apparatus according to claim 1, wherein a task multiplication operation of an amplitude or level of a predetermined signal component is performed between the first channel signal and the second channel signal. The signal processor is
Each of the outputs of the first and second amplitude detection units or the average value or the lower limit of the sum of the outputs of the first and second amplitude detection units is set to a positive value that is not zero with an arbitrary threshold. The signal balance control device according to claim 2, further comprising a lower limiter for limiting. The signal processor is
A first lower limiter that limits the lower limit of the output of the first amplitude detector to a positive value that is not zero with an arbitrary threshold;
A second lower limiter that limits the lower limit of the output of the second amplitude detector to a positive value that is not zero with an arbitrary threshold;
An adder for adding the output of the first lower limiter and the output of the second lower limiter to obtain an amplitude value of a predetermined signal component;
An inverse number for calculating the inverse of the output of the adder;
A third multiplier for multiplying the output of the first lower limiter and the output of the reciprocator to obtain a first control signal, and outputting the first control signal to the second multiplier;
A fourth multiplier that multiplies the output of the second lower limiter and the output of the reciprocator to obtain a second control signal, and outputs the second control signal to the first multiplier; The first multiplier multiplies the first channel signal by the second control signal;
The second multiplier multiplies the second channel signal by the first control signal,
The signal balance control apparatus according to claim 3, wherein a task of multiplying an amplitude or level of a predetermined signal component is performed between the first channel signal and the second channel signal. The signal processor is
A first data capturing section for capturing an output signal of the first amplitude detection section;
A second data capturing section for capturing an output signal of the second amplitude detection section;
The data acquired from the first data fetching unit and the second data fetching unit are subjected to predetermined processing in accordance with a program to obtain first control data and second control data. A control unit;
A first control register for writing the first control data from the control unit;
A second control register for writing the second control data from the control unit,
The first multiplier multiplies the first channel signal by the second control data,
The second multiplier multiplies the second channel signal by the first control data,
The signal balance control apparatus according to claim 3, wherein a task of multiplying an amplitude or level of a predetermined signal component is performed between the first channel signal and the second channel signal. The signal processor is
Each of the outputs of the first and second amplitude detectors or the average value or the lower limit of the sum of the outputs of the first and second amplitude detectors is set to a positive value that is not zero with an arbitrary threshold. The signal balance control device according to claim 3, further comprising a conditional branch step process for limiting. The program processed by the control unit is
1 conditional branching step for limiting the lower limit of the output of the first amplitude detection unit to a positive non-zero value with an arbitrary threshold;
A second conditional branching step for limiting the lower limit of the output of the second amplitude detector to a positive value that is not zero with an arbitrary threshold;
An addition step of adding the processing results of the first conditional branch step and the second conditional branch step to obtain an amplitude value of a predetermined signal component;
A division step of calculating the reciprocal of the amplitude value of the predetermined signal component;
A first multiplication step of multiplying a reciprocal of the amplitude value of the predetermined signal component by a value of the first branch condition step to obtain the first control data;
The signal balance control device according to claim 5, further comprising: a second multiplication step of multiplying a reciprocal of an amplitude value of the predetermined signal component by a value obtained by the second branch condition step to obtain the second control data. . The first and second data capturing units are
The signal balance control device according to claim 5, comprising an analog-digital converter. The signal processor is
A first control digital-analog converter (DAC) connected to the output of the first control register;
A second control DAC connected to the output of the second control register;
The balance circuit is
A first variable gain section (GCA) as a first multiplier for multiplying the first channel signal by the output of the second control DAC;
The signal balance control apparatus according to claim 5, further comprising: a second GCA serving as a second multiplier that multiplies the second channel signal by an output of the first control DAC. A first analog-digital converter (ADC) that converts the first channel signal from an analog signal to a digital signal and supplies the signal to the balance circuit;
10. The signal balance control device according to claim 1, further comprising: a second ADC that converts the second channel signal from an analog signal into a digital signal and supplies the second signal to the balance circuit. The first amplitude detector and the second amplitude detector are:
Includes an absolute value circuit that takes the absolute value of the input signal,
The signal balance control device according to claim 1. The first amplitude detector and the second amplitude detector are:
A peak-hold circuit for peak-holding an input signal;
A bottom-hold circuit for bottom-holding the input signal;
The signal balance control device according to claim 1, further comprising: an arithmetic unit that obtains an amplitude value by taking a difference between an output of the peak hold circuit and an output of the bottom hold. The first amplitude detector and the second amplitude detector are:
The high-pass filter (HPF) which suppresses DC component of the said input signal, extracts AC component, and supplies it to the said peak hold circuit and the said bottom hold circuit or the said absolute value circuit is included. The signal balance control device described. The first amplitude detector and the second amplitude detector are:
12. A low-pass filter (LPF) or a smoothing circuit that extracts a DC component by suppressing an AC component of the input signal or the absolute value circuit output, and outputs the DC component as an amplitude value. The signal balance control device according to 1. The signal balance control device according to any one of claims 1 to 14, wherein the plurality of signal sources are obtained from a plurality of light receiving elements that receive return light or transmitted light of light incident on an optical medium. The light receiving element is
A first composite signal and a second composite signal that are divided into two phenomena and include a difference signal component and a sum signal component;
The first channel signal is
Obtained as the first composite signal,
The second channel signal is
The signal balance control device according to claim 15, obtained as the second composite signal. The light receiving element is
Outputting a first composite signal, a second composite signal, a third composite signal, and a fourth composite signal that are divided into four phenomena and include a difference signal component and a sum signal component;
The first channel signal is
Obtained by adding the first composite signal and the fourth composite signal;
The second channel signal is
The signal balance control device according to claim 15, obtained by adding the second composite signal and the third composite signal. A first analog-digital converter (ADC) that converts the first channel signal from an analog signal to a digital signal and supplies the signal to the balance circuit;
18. The signal balance control device according to claim 16, further comprising: a second ADC that converts the second channel signal from an analog signal into a digital signal and supplies the second signal to the balance circuit. The light receiving element is
Outputting a first composite signal, a second composite signal, a third composite signal, and a fourth composite signal that are divided into four phenomena and include a difference signal component and a sum signal component;
A first ADC that converts the first composite signal from an analog signal to a digital signal to generate a first digital composite signal;
A second ADC that converts the second composite signal from an analog signal to a digital signal to generate a second digital composite signal;
A third ADC that converts the third composite signal from an analog signal to a digital signal to generate a third digital composite signal;
A fourth ADC that converts the fourth composite signal from an analog signal to a digital signal and generates a fourth digital composite signal;
The first channel signal is
Obtained by adding the first digital composite signal and the fourth digital composite signal;
The second channel signal is
The signal balance control device according to claim 15, obtained by adding the second digital composite signal and the third digital composite signal. A signal balance control device for controlling a signal balance between the first channel signal and the second channel signal according to a signal from a light receiving element of light irradiated on an optical recording medium on which information is recorded;
The signal balance control device
A first signal and a second channel signal formed by signals obtained from a plurality of signal sources, including a difference signal component and a sum signal component, and a predetermined signal component between the first channel signal and the second channel signal. A balance circuit that performs multiplication of the amplitude or level of
The balance circuit is
A first amplitude detector that detects a first amplitude or level of a predetermined signal component included in the first channel signal;
A second amplitude detector for detecting a second amplitude or level of a predetermined signal component included in the second channel signal;
A first multiplier for multiplying the first channel signal by a second amplitude value detected by the second amplitude detector;
A second multiplier that multiplies the second channel signal by the first amplitude value detected by the first amplitude detector;

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