JP2000113406A - Decision feedback equalizer, signal processing lsi and magnetic disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a decision feedback equalizer capable of reduction of decoding errors and high-speed operation of a feedback loop. SOLUTION: An anterior equalizer 100 adaptively equalizes an input signal while a discriminator 300 obtains a decoded result for the signal equalized by the anterior equalizer 100. An output signal corrector 600 obtains a corrected output signal from the input signal of the discriminator 300; an interference corrector 500 forms an interference correction signal by the decoded signal from the discriminator 300 and the corrected output signal obtained from the output signal corrector 600; and the interference correction signal is fed back to the anterior stage of the discriminator 300.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decision feedback equalizer, and more particularly, to decoding an analog signal representing coded binary data reproduced through a magnetic recording medium into original coded binary data. The present invention relates to a decision feedback equalizer suitable for performing the above, a signal processing LSI using the decision feedback equalizer, and a magnetic disk device using the signal processing LSI.

[0002]

2. Description of the Related Art Conventionally, a peak detection method has been widely used as a decoding method of a magnetic recording / reproducing signal in a magnetic recording / reproducing apparatus. However, as the recording density of magnetic recording increases and the transfer speed increases, the 1-bit detection window in the peak detection method becomes very large compared to the half width of the reproduced waveform, and the reliability of signal detection decreases. There was a problem of doing.

Therefore, recently, in order to enhance the reliability of signal detection, a decision feedback equalizer has been used in a decoding circuit instead of the peak detection method. The decision feedback equalizer is described in, for example, “KD Fisher, et al.,“ An Adap
tive RAM-DFE for Storage Channels ", IEEE Trans.on
Comm., Vol. 39, no. 11, Nov. 1991 ”, the reproduced signal is converted into a waveform having the minimum phase transition by the forward equalizer provided in the equalizer. Next, a reproduced signal is identified by detecting a bit string by a determiner and negatively feeding back interference caused by the bit string to a preceding stage. Higher density magnetic recording can be realized in comparison.

[0004]

However, in the decision feedback equalizer, a decoding error due to waveform interference that cannot be corrected by the forward equalizer becomes a problem. For this decoding error, for example, a high-precision signal obtained by using waveform equalization again inside the interference corrector is fed back to the signal at the preceding stage of the decision unit, so that it is corrected by the forward equalizer. It is possible to reduce the error decoding rate by removing the waveform interference that could not be performed. However, the incorporation of complicated arithmetic and delay circuits that require multiplication in the interference corrector causes a new problem of limiting the high-speed operation of the feedback loop.

SUMMARY OF THE INVENTION An object of the present invention is to provide a decision feedback equalizer capable of reducing decoding errors and operating a feedback loop at high speed, a signal processing LSI using the decision feedback equalizer, and a signal processing LSI using the same. An object of the present invention is to provide a magnetic disk drive using the same.

[0006]

(1) In order to solve the above object, the present invention provides a forward equalizer for adaptively equalizing an input signal, and decoding of a signal equalized by the forward equalizer. In a decision feedback equalizer having a decision unit for obtaining a result and an interference compensator for feeding back an interference compensation signal to a stage preceding the decision unit based on a signal decoded by the decision unit, correction is performed by an input signal of the decision unit. An output signal corrector for obtaining an output signal, wherein the interference corrector generates an interference correction signal based on a signal decoded by the determiner and a corrected output signal obtained by the output signal corrector; To return to the previous stage. With such a configuration, decoding errors can be reduced, and a high-speed operation of the feedback loop can be performed.

(2) In the above (1), preferably,
The output signal compensator includes three multipliers and an adder for adding outputs of the multipliers, and an output of the adder is equal to a second derivative of the equalized signal. It is. With this configuration, the determination capability of the equalizer can be improved.

(3) In the above (2), preferably,
The output signal corrector is provided with coefficient control means for changing the setting of the load of the multiplier.

(4) In the above (1), preferably,
The interference corrector multiplies a signal decoded by the output signal selector with a signal decoded by the determiner and an output signal selector that selects a corrected output signal equalized by the output signal corrector. It is provided with a plurality of multipliers and an adder for adding outputs of these multipliers.

(5) In the above (1), preferably,
The output signal selector is configured to select a signal decoded by the determiner before a specific time and a corrected output signal equalized by the output signal corrector after a specific time.

(6) In order to achieve the above object, the present invention provides an amplifying means for amplifying an input signal, a waveform equalizing means for equalizing a waveform of the signal amplified by the amplifying means, and a waveform equalizing means. In a signal processing LSI having a decoder for decoding a signal whose waveform has been equalized by the means, the waveform equalizer includes a forward equalizer for adaptively equalizing an analog reproduced signal and an equalizer using the forward equalizer. A determiner that obtains a decoding result for the reproduced signal, an interference corrector that feeds back an interference correction signal to a stage preceding the determiner based on a signal decoded by the determiner, and a correction output signal that is input signal of the determiner. And an interference signal compensator, wherein the interference compensator generates an interference compensation signal based on the signal decoded by the determiner and the compensation output signal obtained by the output signal compensator. It is obtained so as to return to the previous stage of the decision unit. With such a configuration, decoding errors can be reduced, and a high-speed operation of the feedback loop can be performed.

(7) In order to achieve the above object, the present invention provides a magnetic disk mechanism for detecting and outputting a signal from a magnetic disk, and a magnetic disk control circuit for decoding a signal output from the magnetic disk mechanism. Wherein the magnetic disk control circuit comprises a signal processing LSI having a waveform equalizing means for waveform equalization, wherein the waveform equalizing means comprises a signal processing LSI for adaptively equalizing an analog reproduced signal. And a determiner that obtains a decoding result for a reproduced signal equalized by the forward equalizer, and an interference corrector that feeds back an interference correction signal to a stage preceding the determiner by a signal decoded by the determiner. And an output signal corrector that obtains a corrected output signal from the input signal of the determiner. The interference corrector includes a signal decoded by the determiner and the output signal. And generates an interference correction signal by the correction output signal obtained by the signal corrector, is obtained so as to return to the previous stage of the decision unit. With such a configuration,
Since the decoding error can be reduced and the feedback loop can operate at high speed, the reliability of the high-density magnetic disk device can be improved.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a decision feedback equalizer according to an embodiment of the present invention will be described below with reference to FIGS. First, the configuration of the decision feedback equalizer according to the present embodiment will be described with reference to FIG.

The decision feedback equalizer of the present embodiment includes a forward equalizer 100, a subtractor 200, a determiner 300, a coefficient correction signal generation circuit 400, an interference corrector 500, and an output signal corrector. 600. In the present embodiment, an output signal corrector 600 is newly added due to the configuration.

The forward equalizer 100 converts the input signal x (t) into a waveform having a minimum phase transition, and its detailed configuration will be described later with reference to FIG. Subtractor 20
0 subtracts the output signal of the interference corrector 500 from the output signal r (n) of the forward equalizer 100, and outputs an output signal s (n) from which waveform interference has been removed. The determiner 300 converts the output signal s (n) of the subtractor 200 into an output signal y1 (n) decoded into binary data.

The coefficient correction signal generation circuit 400
Then, an equalization error is calculated from the input signal s (n) and the output signal y1 (n), and the coefficient correction signal b (n) is transmitted to the forward equalizer 100, the interference corrector 500, and the output signal corrector 600. Output and change each internal coefficient. Interference corrector 500 subtracts an interference correction signal for removing waveform interference left in output signal r (n) of forward equalizer 100 from output signal y1 (n) of determiner 300 via subtractor 200. It returns, and its detailed configuration will be described later with reference to FIG. The output signal corrector 600 includes the interference corrector 5
00, the remaining components are extracted, and are fed back to the interference corrector 500 to equalize the signals before and after the 0 cross point so as to widen the eye pattern. 3 will be described later.

Next, the configuration and operation of the forward equalizer 100 will be described with reference to FIG. The forward equalizer 100
A signal x (t) read from a magnetic medium is input, and the input signal x (t) is converted into a waveform r (n) having a minimum phase transition.
And outputs a signal r (n) from which partial interference has been removed.

The forward equalizer 100 includes M delay units 110
, 110-2,..., 110-M and M + 1 multipliers 120-1, 120-2,.
, One adder 130 and one coefficient control circuit 140
And constitute an FIR type equalizer.

The signal x input to the forward equalizer 100
(T) is delayed by a fixed period by the delay units 110-1,..., 110-M, and the multipliers 120-1,.
− (M + 1) input signals x (n), x (n−1),
.., X (n−M).

The multipliers 120-1,..., 120- (M +
1) are inputs x (n), x (n-1),..., X (n-
M), and outputs signals x ′ (n), x ′ (n−1),..., X ′ (n−M) obtained by multiplying the weights of the respective multipliers. Each of the multipliers 120-1,..., 120-
The load of (M + 1) is changed by the coefficient control circuit 140.

The adder 130 includes multipliers 120-1,.
Signals x '(n), x' output from 120- (M + 1)
The sum r (n) of (n−1),..., X ′ (n−M) is output. The coefficient control circuit 140 includes multipliers 120-1,.
120- (M + 1) input signals x (n),..., X
(N−M) and the coefficient correction signal b (n) are input, and the setting of the load of the multipliers 120-1,..., 120− (M + 1) is changed. Multipliers 120-1,..., 120- (M + 1)
Holds the set load.

As described above, the output r of the forward equalizer 100
(N) is a signal in which the waveform interference of the reproduction signal x (t) has been partially corrected. Output r (n) of forward equalizer 100
Is a signal s (n) from which the output of the interference corrector 500 is subtracted by the subtractor 200 to remove the waveform interference, and the decision unit 300 decodes the signal into the original binary data, and outputs the output signal y1 (n ) Is generated.

Next, referring to FIG. 3, an output signal corrector 60 will be described.
The configuration and operation of 0 will be described. Output signal compensator 6
00 denotes three delay units 611, 612, 680, three multipliers 621, 622, 623, and two adders 63.
0, 650, two determiners 640, 660, and one coefficient control circuit 670.

The signal s (n) output from the subtractor 200
Are delayed by a constant period by delay units 611 and 612, and input signals s (n), s (n-1), and s to the multipliers
(N-2).

The multipliers 621,..., 623 output the input signal s
Signals s '(n), s' obtained by multiplying (n), s (n-1), and s (n-2) by the weights of the respective multipliers
(N-1) and s' (n-2) are output. Multiplier 62
, 623 are set by the coefficient control circuit 670 and hold the set loads. The coefficient control circuit 670 receives the coefficient correction signal b (n) output from the coefficient correction signal generation circuit 400 and the signals s (n) to s (n−2) input to the multipliers 621,. , 623,... 623 are changed.

The adder 630 outputs the signals s '(n) and s'
The sum of (n-1) and s' (n-2) is output. The determiner 640 makes a threshold value determination on the output of the adder 630 and outputs the determination result to the adder 650. Adder 65
In the case of 0, the delay 680 adds the signal s (n-1) obtained by delaying the input s (n) by a certain period and the output of the decision unit 64. The determiner 660 generates a corrected output signal y2 (n) from the output of the adder 650.

As described above, the corrected output signal y2 (n) of the output signal corrector 600 is a higher-precision output signal than the output signal y1 (n). Therefore, the interference corrector 500
Is left in the output signal r (n) of the forward equalizer 100 based on not only the output signal y1 (n) output from the determiner 300 but also the high-precision output signal output from the output signal corrector 600. Since an interference correction signal for removing waveform interference can be fed back via the subtractor 200, decoding errors can be reduced. Also, the output signal corrector 600 is
00 is not incorporated on the fastest operating part (critical loop) of the feedback loop that feeds back the output of the signal 00 to the input of the decision unit 300 using the interference corrector 500. Since it is provided outside, the high-speed operation of the feedback loop by the interference corrector 500 is not hindered.

Here, in particular, by setting the weight of the multiplier so that the output of the adder 630 becomes the second derivative of the input s of the determiner, the determination ability of the equalizer is improved.

The output signal corrector 600 shown in FIG.
Generates a signal using two delay units 611 and 612, but the number of taps may be increased. In that case, the delay unit 680 is adjusted so that the output signal of the center tap and the input timing of the adder 650 match. Also, without providing the determiner 640 shown in FIG. 3, the output of the adder 630 is directly input to the adder 650, and the determiner 660
The correction output signal y2 (n) may be output from the output of the adder 650.

Next, the configuration and operation of the interference corrector 500 will be described with reference to FIG. The interference corrector 500
One output signal selector 510, (R + 1) multipliers 520-1, 520-2,..., 520- (R + 1);
It is composed of one adder 530 and one coefficient control circuit 540.

The output signal y1 output from the decision unit 300
(N) and the corrected output signal y2 (n) output from the output signal corrector are output by the output signal selector 510 to output signals y (n), y (n−1),. ). In addition, about the structure of the output signal selector 510,
This will be described later with reference to FIG.

Multipliers 520-1, 520-2,..., 52
0− (R + 1) are input y (n), y (n−1),.
Signals y ′ (n), y ′ (n−1),..., y ′ (n) obtained by multiplying y (n−R) by the weight of each multiplier.
-R) is output. Multipliers 520-1, 520-2,
, 520- (R + 1) is applied to the coefficient control circuit 540.
Will be changed by Multipliers 520-1, 520-2,
.., 520- (R + 1) hold the set load. The coefficient control circuit 540 includes a coefficient correction signal generation circuit 40
0 and the coefficient correction signal b (n) output from the multiplier 520-
, 520- (R + 1), the signal y (n),..., Y (n−R) is input to the multiplier 5
, 520- (R + 1) are changed. The adder 530 includes a multiplier 520-
, 520- (R + 1) output signals y '(n), y' (n-1), ..., y '(nR) are output.

Here, the output signal selector 5 will be described with reference to FIG.
The configuration and operation of No. 10 will be described. The output signal selector 510 delays the output signal y1 (n) by a constant period, and outputs S delay units 511-1,..., 511-S and delays the output signal y2 (n) by a constant period. Delay unit 512
,.., 511-R.

, 511-S
Are selected as output signals y (n),..., Y (ns), and (RS) delayers 512- (S +
1),..., 512-R are output signals y (n−S +
1),..., Y (nR).

The corrected output signal y2 of the output signal corrector 600
(N) is an output signal with higher precision than the output signal y1 (n), but has a larger delay amount than the output signal y1 (n). Therefore, the delay units 512-1,.
Since the output signal of 12-S has an excessively large delay amount, when used in the interference corrector 500, the operation of the feedback loop can be sent. Therefore, the interference corrector 500 uses the output signal y1 (n) having a small delay amount and the corrected output signal y2 (n) which is slightly delayed but has high accuracy in order to enable high-speed operation of the feedback loop. In addition, an interference correction signal for removing waveform interference is generated.

The output signal corrector 510 can arbitrarily set the number of delay units for the output signal y1 and the corrected output signal y2, and corrects the shift of the input between y1 and y2 for the same input signal. The delay device may be eliminated.

Next, the equalization result of the decision feedback equalizer according to the embodiment of the present invention and the conventional decision feedback equalizer will be compared and described with reference to FIG. In the figure, the equalized signal indicated by the solid line is the equalization result of the decision feedback equalizer according to the present embodiment, and the equalized signal indicated by the dotted line is the equalization result of the conventional decision feedback equalizer. It is. Note that the conventional decision feedback equalizer does not include the output signal corrector 600 shown in FIG.

The input signal is a Lorentz waveform imitating a reproduced waveform of a magnetic disk. The ratio of the coefficients of the multipliers 621, 622, and 623 of the output signal corrector 600 shown in FIG. : 1).
Note that the determiner 640 is not provided.

The equalized signal of the decision feedback equalizer according to the present embodiment is compared with the equalized signal of the conventional decision feedback equalizer,
The equalized signal eye pattern before and after the zero crossing point of the signal is spread. By widening the eye pattern of the equalized signal in this manner, a decision error in the decision unit 660 decreases,
The decoding error rate can be reduced. In the illustrated example, the decision feedback equalizer according to the present embodiment is about 0.2 [d equivalent to a required SN ratio in comparison with a conventional decision feedback equalizer.
B].

As described above, by providing an output signal compensator at a stage preceding the interference compensator of the decision feedback equalizer, the decision error rate of the output signal can be reduced, and inappropriate negative feedback due to a decision error can be obtained. Signal output can be suppressed, and decoding performance can be improved.

Here, the configuration of another example of the forward equalizer used in the decision feedback equalizer according to the present embodiment will be described with reference to FIGS. First, referring to FIG.
The configuration of the forward equalizer 100A according to another example will be described.

The forward equalizer 100A includes M delay units 110-1, 110-2,..., 110-M shown in FIG.
M + 1 multipliers 120-1, 120-2, ..., 120
− (M + 1), one adder 130A, one coefficient control circuit 140, and P
-1, 150-2, ..., 110-P, and P multipliers 1
, 160-P, and one coefficient control circuit 170 to constitute an IIR equalizer.

As in FIG. 2, the signal x (t) input to the forward equalizer 100A is divided into delay units 110-1,.
The multiplier 120 delays by a fixed period by 10-M.
-1,..., 120- (M + 1) input signal x (n),
x (n−1),..., x (n−M). Multiplier 120
-1,..., 120- (M + 1) are input x (n), x
Signals x ′ (n), x ′ (n−n) obtained by multiplying (n−1),..., X (n−M) by the weight of each multiplier.
1),..., X ′ (n−M) are output. The load of each of the multipliers 120-1,..., 120- (M + 1) is changed by the coefficient control circuit 140.

The output signal r (n) of the adder 130A
, 150-P are delayed by a constant period by the delay units 150-1,..., 150-P, and become input signals to the multipliers 160-1,. Multipliers 160-1,..., 160-P
Outputs a signal obtained by multiplying the input signal by the weight of each multiplier. Each multiplier 160-1,
, 160-P are changed by the coefficient control circuit 170. The adder 130A includes multipliers 120-1,
, 120- (M + 1) and the signal output from the multiplier 16
0-1,..., 160-P output r (n)
Is output.

The delay units 110-1 and 110-1 shown in FIG.
, 110-M, the number of delay units 110-1,..., 110-M shown in FIG.
By setting the number of the delay units 150-1,..., 150-P to three, the circuit scale can be made similar to that of the example shown in FIG.

As described above, the output r (n) of the forward equalizer 100A is a signal in which the waveform interference of the reproduced signal x (t) has been partially corrected.

Next, the configuration of the forward equalizer 100B according to the second other example will be described with reference to FIG. In the present embodiment, the forward equalizer 100B is configured by an analog equalizer 180. In this case, the analog equalizer 180 is designed such that the output r (n) of the forward equalizer 100B is converted into a waveform having a minimum phase transition, similarly to the example shown in FIG. 2 or FIG. ing.

As described above, according to the present embodiment, the output signal corrector that outputs the highly accurate corrected output signal y2 (n) is provided outside the optimum operation section (critical loop) of the feedback loop. Therefore, the high-speed operation of the feedback loop by the interference corrector is not hindered, and the interference correction signal for removing the waveform interference by the interference corrector using the high-precision correction output signal y2 (n). Can be generated and fed back via a subtractor, so that decoding errors can be reduced.

Next, the configuration of a signal processing LSI using the decision feedback equalizer according to the present embodiment will be described with reference to FIG. Signal processing LSI 1000B according to the present embodiment
Is composed of an automatic gain control amplifier (AGC) 900, a signal processing circuit 1000A, and a decoder circuit (DEC) 920. The signal processing circuit 1000A includes a decision feedback equalizer 1000 described above and a coefficient control circuit setting unit 7
00.

As shown in FIG. 1, the decision feedback equalizer 1000 includes a forward equalizer 100, a subtractor 200, a determiner 300, a coefficient correction signal generation circuit 400, and an interference corrector 500. , And an output signal corrector 600. The coefficient control circuit setting unit 700 includes the output signal corrector 60
The coefficient is set in the multipliers 621, 622, and 623 of 0 (FIG. 3). The input of the equalization error of the determination result leading to the determination error is performed, and the setting of the multiplier and the determiner is performed. The change of the set value is caused by an input from the outside of the signal processing circuit 1000A, or is automatically adjusted inside the signal processing circuit 1000A by the output or input of the equalization error and the decision feedback equalizer 1000. You.

The signal read from the magnetic head is amplified by an automatic gain control amplifier (AGC) 900 and then input to a signal processing circuit 1000A. The signal processing circuit 1000A equalizes the waveform of the input signal and outputs a signal as shown in FIG. Decoder circuit (DEC) 9
20 decodes the waveform-equalized signal into a binary digital signal.

Next, the configuration of a magnetic disk drive using the decision feedback equalizer according to the present embodiment will be described with reference to FIG. The magnetic disk mechanism 2000 includes a magnetic disk 2100 on which data is written and a spindle 2200 for rotating the magnetic disk 2100.
A magnetic head 2300 for reading data from the disk 2100, an arm 2400 for supporting the magnetic head 2300, a voice coil motor 2500 for moving the magnetic head 2300, and a spindle 2200
And a read / write amplifier 2700 for amplifying a signal from the magnetic head.

The magnetic disk control circuit 1000C
Is an interface (I / F) 1100 for connecting to an information processing device PC such as a host, a hard disk controller (HDC) 1200 for controlling data transfer and format, and a microcomputer (CPU) 13.
00, and a signal processing LSI 1000 including a decision feedback equalizer for processing a signal from the read / write amplifier 2700.
B, a spindle control circuit (SMC) 1400 for controlling the spindle motor 2500, and a voice coil motor control circuit (VCMC) 1500 for controlling the voice coil motor 2600.

Here, the signal processing LSI 1000B has the configuration shown in FIG. 9, and includes therein the decision feedback equalizer 1000 according to the present embodiment. Therefore,
Since the equalization accuracy can be improved without deteriorating the operation speed of the decision feedback equalizer, decoding errors can be reduced, and the reliability of signal detection can be improved even in a magnetic disk device with a higher recording density. be able to.

[0055]

According to the present invention, the decoding error of the decision feedback equalizer can be reduced, and the high speed operation of the feedback loop can be realized. Further, the reliability of signal detection of the magnetic disk device can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a decision feedback equalizer according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a forward equalizer used in a decision feedback equalizer according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of an output signal corrector used in a decision feedback equalizer according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of an interference corrector used in a decision feedback equalizer according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of an output signal selector used for an interference corrector of a decision feedback equalizer according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a comparison between equalization results of a decision feedback equalizer according to an embodiment of the present invention and a conventional decision feedback equalizer.

FIG. 7 is a block diagram illustrating a configuration of a forward equalizer according to a first other example used in the decision feedback equalizer according to the embodiment of the present invention;

FIG. 8 is a block diagram showing a configuration of a forward equalizer according to a second other example used in the decision feedback equalizer according to the embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a signal processing LSI using a decision feedback equalizer according to an embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a magnetic disk drive using a decision feedback equalizer according to an embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100: forward equalizer 200: subtractor 300: determiner 400: coefficient correction signal generation circuit 500: interference corrector 600: output signal corrector 700: coefficient control circuit setting unit 1000: decision feedback equalizer 1000A: signal Processing circuit 1000B ... Signal processing LSI 1000C ... Magnetic disk device 2000 ... Magnetic disk mechanism

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04B 3/06 H04B 3/06 A (72) Inventor Hiroshi Kimura 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Prefecture Stock Company. (72) Inventor Masuo Umemoto 1-280 Higashi-Koigakubo, Kokubunji-shi, Tokyo In-house Hitachi, Ltd.Central Research Laboratories (72) Inventor Yoichi Uehara 5--20, Josuihoncho, Kodaira-shi, Tokyo Hitachi Semiconductor Co., Ltd. (72) Inventor Takashi Nara 5--20-1, Kamimizu Honmachi, Kodaira-shi, Tokyo Hitachi Semiconductor Co., Ltd. (72) Inventor Nobuaki Nakai 5-chome, Kamimihoncho, Kodaira-shi, Tokyo 20 No. 1 F-term in the Semiconductor Division, Hitachi, Ltd. (Reference) 5D031 AA04 DD01 DD05 HH11 HH13 5D044 BC01 CC04 FG01 FG05 FG16 5J023 DB05 DC04 DD05 5K046 BA05 BA06 EE02 EE10 EE23

Claims (7)

[Claims] 1. A forward equalizer for adaptively equalizing an input signal, a determiner for obtaining a decoding result for a signal equalized by the forward equalizer, and a determiner based on a signal decoded by the determiner A decision feedback equalizer having an interference compensator that feeds back an interference compensation signal at the preceding stage, comprising: an output signal compensator that obtains a compensation output signal from an input signal of the decision unit; A decision feedback equalizer for generating an interference correction signal based on the signal decoded by the decoder and the corrected output signal obtained by the output signal corrector, and feeding back the signal to a stage preceding the determiner. 2. The decision feedback equalizer according to claim 1, wherein said output signal corrector includes three multipliers, and an adder for adding outputs of said multipliers. A decision feedback equalizer characterized in that the output is equal to the second derivative of the equalized signal. 3. A decision feedback equalizer according to claim 2, wherein said output signal corrector comprises coefficient control means for changing a setting of a load of said multiplier. vessel. 4. The decision feedback equalizer according to claim 1, wherein said interference corrector selects an output signal selected by said determiner and a corrected output signal equalized by said output signal corrector. A decision feedback equalizer comprising: a signal selector; a plurality of multipliers for multiplying a signal selected by the output signal selector; and an adder for adding outputs of the multipliers. . 5. The decision feedback equalizer according to claim 4, wherein the output signal selector is a signal decoded by the determiner before a specific time and the output signal corrector after a specific time. A decision feedback equalizer characterized by selecting a corrected output signal equalized by: 6. Amplifying means for amplifying an input signal, waveform equalizing means for equalizing the waveform of the signal amplified by the amplifying means, and decoder means for decoding a signal equalized in waveform by the waveform equalizing means. In the signal processing LSI having the following, the waveform equalizer includes: a forward equalizer that adaptively equalizes an analog reproduced signal; a determiner that obtains a decoding result of the reproduced signal equalized by the forward equalizer; An interference corrector that feeds back an interference correction signal to a stage preceding the determiner based on a signal decoded by the determiner; and an output signal corrector that obtains a corrected output signal based on an input signal of the determiner. A detector that generates an interference correction signal based on the signal decoded by the determiner and the corrected output signal obtained by the output signal corrector, and feeds back the signal to a preceding stage of the determiner. Signal processing LSI that. 7. A magnetic disk mechanism for detecting and outputting a signal from a magnetic disk, and a magnetic disk control circuit for decoding a signal output from the magnetic disk mechanism, wherein the magnetic disk control circuit has a waveform or the like. In a magnetic disk drive including a signal processing LSI having a waveform equalizing means for performing equalization, the waveform equalizing means includes: a front equalizer for adaptively equalizing an analog reproduction signal; A decision unit that obtains a decoding result for the reproduced signal, an interference compensator that feeds back an interference compensation signal to a stage preceding the decision unit based on the signal decoded by the decision unit, and a corrected output signal that is acquired based on an input signal of the decision unit An output signal corrector, wherein the interference corrector is a signal decoded by the determiner and a corrected output signal obtained by the output signal corrector. And it generates an interference correction signal, the magnetic disk device characterized by returning to the previous stage of the decision unit.