JP2011087969A - Imaging device and imaging system, and control method and program thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a sense of incompatibility such as steps of an image caused by difference of non-linearity of a plurality of A/D convertor by a simple configuration and an easy processing. <P>SOLUTION: The imaging device includes: a detection part 101 wherein a plurality of pixels are divided into a first pixel group 101a and a second pixel group 101b; and a signal processing part 106 including a read-out circuit part 103 including a first read-out circuit 103a and a second read-out circuit 103b, an A/D convert part 104 including a first A/D convertor 104a and a second A/D convertor 104b, and a digital data processing circuit 105. The control part controls the device so as to carry out operation wherein operation to add a direct current potential to analog electric signals of predetermined pixels outputted from the read-out circuit and input them into the A/D converting part to output the digital data to the digital data processing circuit, and operation to average a plurality of digital data of the outputted predetermined pixels by the digital data processing circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an imaging apparatus, an imaging system, a control method thereof, and a program thereof. More specifically, the present invention relates to a radiation imaging apparatus and a radiation imaging system, a control method thereof, and a program thereof, which are preferably used for still image shooting such as general shooting in medical diagnosis and moving image shooting such as fluoroscopic shooting. In the present invention, radiation is a beam having energy of the same degree or more, for example, X-rays, in addition to α-rays, β-rays, γ-rays, etc., which are beams formed by particles (including photons) emitted by radiation decay. , Particle beams, cosmic rays, etc. are also included.

  In recent years, a radiation imaging apparatus using a flat panel detector (hereinafter abbreviated as FPD) made of a semiconductor material has been put into practical use as an imaging apparatus used for medical image diagnosis and nondestructive inspection using X-rays. Such a radiation imaging apparatus is used as a digital imaging apparatus for still image shooting such as general shooting or moving image shooting such as fluoroscopic shooting in medical image diagnosis, for example.

  In such a radiation imaging apparatus, the above-described detector, a driving circuit for driving the detector, a reading circuit for reading an analog electric signal from the detector, and converting the analog electric signal into a digital signal An A / D converter. From the A / D converter, digitized image signals at the time of photographing and image signals for correction are respectively output. When it is desired to output an image signal from the imaging apparatus in a shorter time, the imaging apparatus is provided with a plurality of A / D converters.

  However, the A / D converter generates nonlinearity that does not become an ideal linear characteristic in the conversion characteristic (A / D conversion characteristic) between the input analog electric signal and the output digital signal. There is a case. In particular, in an imaging apparatus having a plurality of A / D converters, the non-linearity of each A / D converter is different, and an image created from a digital signal may have a sense of incongruity such as a step. When such a sense of incongruity such as a level difference occurs, it is desirable to suppress non-linearity or correct the influence of non-linearity.

  In Patent Document 1, a reference signal synchronized with an output signal of an A / D conversion unit as address data is stored at an address designated by an output of the A / D conversion unit, and the A / D conversion unit is matched with the reference signal. An A / D conversion circuit for correcting the output signal is disclosed. Thus, it is disclosed that it is possible to reduce image discomfort caused by the non-linearity of the A / D conversion means, and to realize high image quality.

  Japanese Patent Application Laid-Open No. 2004-228688 has a correction unit that corrects the output signals of a plurality of A / D conversion units in accordance with the output signal of any one of the plurality of A / D conversion units. An A / D conversion circuit is disclosed. Thus, it is disclosed that it is possible to reduce image discomfort caused by a difference in non-linearity among a plurality of A / D conversion means and to realize high image quality.

Japanese Patent Laying-Open No. 2005-210480 Japanese Patent Laid-Open No. 2005-210396

  In Patent Document 1 and Patent Document 2, the uncomfortable feeling caused by the non-linearity of the A / D converter is suppressed by correcting the digital output from the A / D converter as described above. However, when performing corrections as in Patent Documents 1 and 2, there is a problem that an enormous circuit is required to correct the digital output. In addition, a process for acquiring conversion data for correcting the non-linearity of each A / D converter in advance and a process for performing digital correction for each digital output are required, resulting in a complicated system. Had problems.

  In view of the above problems, the present invention provides an image pickup apparatus or an image pickup device that can reduce a sense of incongruity such as a step in an image due to a difference in nonlinearity of a plurality of A / D converters with a simple configuration and simple processing. It is an object to provide a system.

As a result of intensive studies to solve the above-mentioned problems, the inventors of the present application have come up with the following aspects of the invention.
An imaging apparatus according to the present invention includes a plurality of pixels for converting radiation or light into an analog electrical signal in a matrix, and the plurality of pixels are divided into at least a first pixel group and a second pixel group. A detection unit; a first readout circuit electrically connected to the first pixel group; and a second readout circuit electrically connected to the second pixel group; A readout circuit unit for reading out the output analog electrical signal, a first A / D converter electrically connected to the first readout circuit, and a second A electrically connected to the second readout circuit A signal including an A / D converter that converts an analog electrical signal output from the readout circuit unit into digital data and outputs the digital data, and a digital data processing circuit that processes the digital data Control unit and control for controlling the signal processing unit The readout circuit further includes reset means for outputting a reset signal to the A / D converter, and the control unit is configured such that the first and second readout circuits are predetermined. A first DC potential is applied to a plurality of reset signals within a period for reading out the analog electric signals of pixels in a row, and the first DC potential is output to the A / D converter. Data is converted into a plurality of first reset data, and the plurality of first reset data output from the A / D converter within the period is subjected to an averaging process, and the analog of the pixel within the period The first DC potential is applied to an electrical signal and output to the A / D converter, and the A / D converter converts the first pixel data, which is digital data, A plurality of the first average-processed A first signal processing operation for subtracting the reset data to obtain corrected first pixel data; and the A / D conversion by applying a second DC potential to a plurality of reset signals within the period The A / D converter converts into a plurality of second reset data which is digital data within the period, and the plurality of second outputs output from the A / D converter within the period. The reset data is added and averaged, and the second DC potential is applied to the analog electric signal of the pixel within the period and output to the A / D converter. The A / D converter is digital data. A second pixel data that is converted into certain second pixel data, and the second pixel data is subtracted from the plurality of second reset data that has undergone the averaging process to obtain corrected second pixel data; Signal processing operations including signal processing operations; The signal processing unit is configured so that the signal processing unit performs an average processing operation for averaging the corrected first pixel data and the corrected second pixel data by the digital data processing circuit. Control.

  The control method of the imaging apparatus according to the present invention includes a plurality of pixels for converting radiation or light into an analog electric signal in a matrix, and the plurality of pixels are at least in the first pixel group and the second pixel group. A divided detection unit; a first readout circuit electrically connected to the first pixel group; and a second readout circuit electrically connected to the second pixel group; A readout circuit unit that reads out an analog electrical signal output in units of rows, a first A / D converter that is electrically connected to the first readout circuit, and a second electrical circuit that is electrically connected to the second readout circuit. An A / D converter that converts the analog electrical signal output from the readout circuit unit into digital data and outputs the digital data; a digital data processing circuit that processes the digital data; A signal processing unit including Is a method for controlling an imaging apparatus further comprising reset means for outputting a reset signal to the A / D converter, wherein the first and second readout circuits read out the analog electrical signals of pixels in a predetermined row. A first DC potential is applied to a plurality of reset signals and output to the A / D converter, and the A / D converter converts into a plurality of first reset data which is digital data within the period. And adding and averaging the plurality of first reset data output from the A / D converter within the period, and applying the first DC potential to the analog electric signal of the pixel within the period. Output to the A / D converter, the A / D converter converts the first pixel data which is digital data, and a plurality of the first resets subjected to the averaging process with the first pixel data Subtract data from A first signal processing operation for acquiring first pixel data after correction; a second DC potential is applied to a plurality of reset signals within the period; and the A / D converter outputs the second DC potential. A D converter converts the digital data into a plurality of second reset data within the period, and performs an averaging process on the plurality of second reset data output from the A / D converter within the period. , Applying the second DC potential to the analog electric signal of the pixel within the period and outputting the same to the A / D converter, and the A / D converter converts it into second pixel data which is digital data A second signal processing operation for obtaining the corrected second pixel data by subtracting the second pixel data and the plurality of second reset data subjected to the averaging process; First pixel data and the corrected second pixel An average processing operation for averaging data by the digital data processing circuit is performed.

  The program according to the present invention includes a plurality of pixels for converting radiation or light into an analog electrical signal in a matrix, and the plurality of pixels are divided into at least a first pixel group and a second pixel group. And a first readout circuit electrically connected to the first pixel group and a second readout circuit electrically connected to the second pixel group, and output from the detection unit in units of rows A read circuit unit for reading the analog electric signal, a first A / D converter electrically connected to the first read circuit, and a second A / D electrically connected to the second read circuit A signal converter including a D converter, an A / D converter that converts an analog electrical signal output from the readout circuit unit into digital data, and a digital data processing circuit that processes the digital data And the readout circuit includes A program for causing a computer to execute control of an image pickup apparatus that further includes reset means for outputting a reset signal to the / D converter, wherein the first and second readout circuits output analog electric signals of pixels in a predetermined row. A first DC potential is applied to a plurality of reset signals within a period for reading and output to the A / D converter, and the A / D converter includes a plurality of first data that are digital data within the period. Converting to reset data, adding and averaging the plurality of first reset data output from the A / D converter within the period, and converting the first DC power into the analog electric signal of the pixel within the period. And outputs to the A / D converter, the A / D converter converts the first pixel data which is digital data, and a plurality of the average processed with the first pixel data. First Subtracting reset data to obtain corrected first pixel data; applying a second DC potential to a plurality of reset signals within the period and outputting to the A / D converter; The A / D converter converts into a plurality of second reset data which is digital data within the period, and adds the plurality of second reset data output from the A / D converter within the period A second pixel in which the averaging process is performed, and the second DC potential is applied to the analog electric signal of the pixel within the period and output to the A / D converter, and the A / D converter is digital data. Subtracting the second pixel data and the plurality of second reset data that have undergone the averaging process to obtain corrected second pixel data, and 1 pixel data and the corrected And a step of averaging the second pixel data by the digital data processing circuit.

  According to the present invention, it is possible to provide an imaging device or an imaging system capable of reducing a sense of incongruity such as a step in an image due to a difference in nonlinearity of a plurality of A / D converters with a simple configuration and simple processing. Is possible.

1 is a conceptual block diagram of an imaging apparatus according to the present invention. 1 is a conceptual diagram of an imaging system including a conceptual equivalent circuit diagram of an imaging apparatus according to a first embodiment of the present invention. 3 is a timing chart for explaining the operation of the imaging apparatus according to the first embodiment of the present invention. It is a block diagram for demonstrating operation | movement of the signal processing means which concerns on the 1st Embodiment of this invention. It is a characteristic view for demonstrating the influence by the difference in the A / D conversion characteristic of an A / D converter. It is explanatory drawing which shows the effect of this invention. It is a conceptual diagram of the radiation imaging system using the imaging device of this invention.

Hereinafter, embodiments to which the present invention can be suitably applied will be described with reference to the drawings.
FIG. 1 is a conceptual block diagram of an imaging apparatus according to an embodiment of the present invention. The imaging apparatus 100 in FIG. 1 drives a detection unit 101 having a plurality of pixels in a matrix to convert radiation or light into an analog electrical signal, and drives the detection unit 101 to output an analog electrical signal from the detection unit 101. And a driving circuit 102. In this embodiment, for simplification of description, the detection unit 101 has a form having pixels of 8 rows and 8 columns, and a first pixel group 101a and a second pixel group 101b that form a set of four pixel columns. It is divided into A pixel signal which is an analog electric signal output from a pixel of the first pixel group 101a is read by the first reading circuit 103a which is electrically connected. A pixel signal 113 which is an analog electric signal output from the pixel of the first readout circuit 103a is converted into digital data 114 by the first A / D converter 104a which is electrically connected. Similarly, an analog electrical signal from the second pixel group 101b is read and converted into digital data by the second readout circuit 103b and the second A / D converter 104b that are electrically connected. The digital data from the first and second A / D converters 104a and 104b is subjected to signal processing, digital multiplex processing, offset correction, and the like described later by the digital data processing circuit 105, and is output as a digital image signal. The The signal processing unit 106 includes a readout circuit unit 103 including first and second readout circuits 103a and 103b, an A / D conversion unit 104 including first and second A / D converters 104a and 104b, And a data processing circuit 105. The imaging apparatus 100 includes a power supply unit 107 that applies a corresponding bias to the signal processing unit 106. The power supply unit 107 supplies reference voltages Vref1, Vref2, and Vref3 to the reading circuit unit 103. The imaging apparatus 100 further includes a control unit 108 for controlling at least one of the signal processing unit 106 and the power supply unit 107. The control unit 108 supplies a control signal 118 to the power supply unit 107. The control unit 108 supplies control signals 116, 117, and 120 to the reading circuit unit 103. The control unit 108 supplies a drive control signal 119 to the drive circuit 102, and the drive circuit 102 supplies a drive signal 111 to the detection unit 101 based on the drive control signal 119. Further, the control unit 108 supplies the readout circuit unit 103 with an offset control signal 140 that can change a DC potential added to a signal output from a differential amplifier described later.

  FIG. 2A is a conceptual diagram of an imaging system including a conceptual equivalent circuit diagram of the imaging apparatus according to the embodiment of the present invention. In addition, the same thing as the structure demonstrated using FIG. 1 is provided with the same number, and detailed description is omitted. The detection unit 101 includes a plurality of pixels 201 arranged in a matrix. In FIG. 2A, 8 × 8 pixels 201 are arranged across 8 rows and 8 columns. The pixel 201 includes a conversion element S that converts radiation or light into electric charges, and a switch element T that outputs an electrical signal corresponding to the electric charges. As the conversion element S that converts light into electric charge, a photoelectric conversion element such as a PIN photodiode that is disposed on an insulating substrate such as a glass substrate and uses amorphous silicon as a main material is preferably used. As a conversion element that converts radiation into electric charge, an indirect type conversion element having a wavelength conversion body that converts radiation into light in a wavelength band that can be detected by the photoelectric conversion element on the radiation incident side of the photoelectric conversion element, A direct conversion element that directly converts radiation into electric charge is preferably used. As the switch element T, a transistor having a control terminal and two main terminals is preferably used, and in the case of a pixel in which the photoelectric conversion element is provided on an insulating substrate, a thin film transistor (TFT) is preferably used. One electrode of the conversion element S is electrically connected to one of the two main terminals of the switch element T, and the other electrode is electrically connected to the bias power source 106a via a common wiring. The switch elements of a plurality of pixels in the row direction, for example, T11 to T18, are electrically connected in common to the drive wiring G1 in the first row, and control the conduction state of the switch elements from the drive circuit 102. The drive signal to be applied is given in units of rows through the drive wiring. The switching elements of a plurality of pixels in the column direction, for example, T11 to T81, while the other main terminals are electrically connected to the signal wiring Sig1 in the first column and are in the conductive state, the conversion element An electric signal corresponding to the electric charge is output to the reading circuit 103 through the signal wiring. A plurality of signal wirings Sig <b> 1 to Sig <b> 8 arranged in the column direction transmit electric signals output from a plurality of pixels of the detection unit 101 to the readout circuit unit 103 in parallel. In the present embodiment, the detection unit 101 is divided into a first pixel group 101a and a second pixel group 101b that form a set of four pixel columns. In the present embodiment, each pixel in the first to fourth columns corresponds to a first pixel included in the first pixel group, and each pixel in the fifth to eighth columns is included in the second pixel group. It corresponds to a pixel. The analog electrical signals output from the first pixel group 101a are read in parallel by the corresponding first readout circuits 103a in the readout circuit 103, and the analog electrical signals output from the second pixel group 101b are Data are read in parallel by the second reading circuit 103b.

  The first readout circuit 103a samples and holds the first amplification circuit unit 202a that amplifies the electrical signal output in parallel from the first pixel group 101a and the electrical signal from the first amplification circuit unit 202a. A first sample-and-hold circuit unit 203a. Similarly, the second readout circuit 103b includes a second amplifier circuit unit 202b and a second sample hold circuit unit 203b. The first and second readout circuits sequentially output the electrical signals read in parallel from the first or second sample and hold circuit unit, respectively, and output them as image signals of serial signals. Multiplexers 204a and 204b. Furthermore, the first and second readout circuits have first and second differential amplifiers 205a and 205b, which are output buffers that output the image signal after impedance conversion. The differential amplifiers 205a and 205b are composed of a differential amplifier and a variable capacitor. In addition, D / A converters DACa, b are connected to the input terminals of the differential amplifiers 205a, 205b via capacitors, respectively. By supplying the control signal 140 to the D / A converters DACa, b, the DC potential added to the signals output from the differential amplifiers 205a, b can be controlled. The circuit configuration including the D / A converter DACa, b and the capacitor corresponds to the DC potential control circuit of the present invention. An electric signal from the pixel is input to the first differential amplifier 205a or the second differential amplifier 205b via the signal buffer SFS. The noise component is input to the first differential amplifier 205a or the second differential amplifier 205b via the noise buffer SFN. The electrical signal from the pixel and the noise component input to the first differential amplifier 205a are subtracted and output, and input to the first A / D converter 104a. Similarly, the electrical signal from the pixel and the noise component input to the second differential amplifier 205b are subtracted and output, and input to the second A / D converter 104b. A reference voltage Vref3 is input from the power supply unit 107 to the first and second A / D converters 104a and 104b. Here, the reference voltage Vref2 is input to the gates of the signal buffers SFS of the first and second read circuits 103a and 103b from the power supply unit 107 through the reset switch SRS at a predetermined timing. The reference voltage Vref2 is input to the gates of the noise buffers SFN of the first and second readout circuits 103a and 103b from the power supply unit 107 at a predetermined timing via the reset switch SRN. That is, the reset switch SR resets the input of the differential amplifier at a predetermined timing by applying the reference voltage Vref2 to the gate of the buffer SF at a predetermined timing.

  The control circuit 108 gives a control signal 116 to the first and second amplifier circuit sections 202a and 202b. The control circuit 108 supplies a control signal 117a to the reset switches SRS and SRN, and a control signal 117b to the first and second multiplexers, respectively. The control circuit 108 supplies control signals 120s and 120n to the first and second sample and hold circuit units, respectively. Further, the control circuit 108 gives a control signal 129 to the first and second A / D converters, and gives a control signal 130 to the digital data processing circuit 105 to control. The control circuit 108 gives a control signal 140 to the D / A converter connected to the differential amplifier, and controls the DC potential added to the analog electric signal output from the differential amplifier.

  FIG. 2B is an equivalent circuit diagram for explaining the read circuit 103 in detail. The amplifying circuit unit 202 amplifies an electrical signal (pixel signal) read from the pixel and outputs it corresponding to each signal wiring, an integration capacitor Cf, and a reset switch RC that resets the integration capacitor. And an amplifier circuit. The output electric signal is input to the inverting input terminal of the operational amplifier A, and the amplified electric signal is output from the output terminal. The reference voltage Vref1 is input from the power supply unit 107 to the normal rotation input terminal of the operational amplifier A. An integration capacitor Cf is disposed between the inverting input terminal and the output terminal of the operational amplifier A, and a reset switch RC is connected in parallel with the integration capacitor Cf. The sample hold circuit unit 203 includes an odd row signal sample hold circuit, an even row signal sample hold circuit, an odd row noise sample hold circuit, and an even row noise sample hold circuit corresponding to each amplifier circuit. The odd-row signal sample-hold circuit includes a sampling switch SHOS that samples an electrical signal from an odd-row pixel and a sampling capacitor Chos that holds an odd-row pixel signal. The even-row signal sample-hold circuit has a sampling switch SHES that samples even-row pixel signals and a sampling capacitor Ches that holds even-row pixel signals. The odd-numbered noise sample-and-hold circuit has a sampling switch SHON that samples the noise component of the operational amplifier before sampling the odd-numbered pixel signals, and a sampling capacitor Chon that holds the noise signal. The even-row noise sample and hold circuit has a sampling switch SHEN that samples the noise of the operational amplifier before sampling the even-row pixel signals, and a sampling capacitor Chen that holds the noise signal. The multiplexer 204 includes a switch MSOS corresponding to the odd-row signal sample hold circuit, a switch MSES corresponding to the even-row signal sample hold circuit, and a corresponding amplifier circuit. Further, a switch MSON is provided corresponding to each odd-numbered noise sample-hold circuit, and a switch MSON is provided corresponding to each even-numbered noise sample-hold circuit corresponding to each amplifier circuit. Then, by sequentially selecting each switch, an operation of converting a parallel signal of a pixel signal or a noise component into a serial signal is performed.

Next, the operation of the imaging apparatus of the present invention will be described with reference to FIGS. FIG. 3 is a timing chart for explaining the imaging operation of the imaging apparatus according to the embodiment of the present invention.
In the operation of the present invention, the following points should be particularly noted. First, the imaging apparatus of the present invention performs A / D conversion operations a plurality of times (here, twice) for the output operation in units of rows, that is, performs a conversion operation for a single signal a plurality of times. ing. Next, the image pickup apparatus of the present invention performs the A / D conversion operation a plurality of times by applying different DC potentials to the input signal of the A / D converter output from the readout circuit section. The image pickup apparatus of the present invention averages a plurality of digital data obtained by a plurality of A / D conversion operations for one signal and provides one data.

  First, the imaging apparatus 100 performs an output operation of pixels in units of rows. Here, it is assumed that the detection unit 101 is irradiated with radiation or light before the output operation, and charges corresponding to the irradiated radiation or light are generated in each conversion element S. At the beginning of the row-by-row output operation, the control signal 140 is supplied from the control unit 108 to the D / A converter DACa, b, and the DC potential applied to the output of the differential amplifier, which is an analog electric signal output from the readout circuit unit. Is set to the first DC potential. Subsequently, the integration capacitor Cf is reset by the reset switch RC to which the control signal 116 is given from the control unit 108, and the amplifier circuit is reset. Next, control signals 120n and 120oe are given from the control unit 108 to the sample and hold circuit unit. As a result, the sampling switch SHON of the odd-numbered row noise sample and hold circuit is turned on, and the noise component of the amplifier circuit is transferred from the reset amplifier circuit to the sampling capacitor Cho. The sampling switch SHON is turned off and the noise component is held in the sampling capacitor Chon. Next, the drive signal 111 is supplied from the drive circuit 102 to the drive wiring G1 in the first row, and the switch elements T11 to T18 in the first row are turned on. As a result, analog electric signals based on the charges generated in the conversion elements S11 to S14 in the first row are transmitted from each pixel to the first readout circuit 103a in parallel via the signal wirings Sig1 to Sig4. In addition, analog electric signals based on the charges generated in the conversion elements S15 to S18 in the first row are transmitted from each pixel to the second readout circuit 103b in parallel via the signal wirings Sig5 to Sig8. Then, control signals 120s and 120oe are given from the control unit 108 to the sample and hold circuit unit. As a result, the sampling switch SHOS of the odd-row signal sample and hold circuit is turned on, and the read pixel signal is transferred to the sampling capacitor Chos via the amplifier circuit. At this time, the noise component of the amplifier circuit is added to the pixel signal. Then, the sampling switch SHOS is turned off, and the pixel signal to which the noise component is added is held in the sampling capacitor Chos.

  Next, the imaging apparatus 100 performs the following signal processing operation. A control signal 117a is given from the control unit 108 to the reset switches SRS and SRN. Thereby, the reset switches SRS and SRN are turned on, the reference voltage Vref2 is applied to the gates of the buffers SFS and SFN, and the inputs of the differential amplifiers 205a and 205b are reset. That is, the reset switches SRS and SRN are reset means for outputting a reset signal to the A / D converter. At this time, signals obtained by adding the first DC potential by the D / A converters DACa, b to the outputs from the reset differential amplifiers 205a, 205b, respectively, are supplied to the A / D converters 104a, 104b. Entered. That is, the first DC potential is added to the analog electric signal output from the readout circuit unit by the D / A converter DACa, b and input to the A / D converter. Each A / D converter 104a, 104b converts the input signal into digital data Nd1, Nd4 and outputs the digital data to the digital data processing circuit 105. The digital data Nd1 and Nd4 are reset data for each differential amplifier including the first DC potential. Next, the reset switches SRS and SRN are made non-conductive, and at this time, the signals to which the first DC potential is added by the D / A converters DACa and b are respectively converted into the A / D converters 104a and 104b. Is input. The A / D converters 104a and 104b convert the input signals into digital data Sd1 and Sd1 and output them to the digital data processing circuit 105. This operation is referred to as a pseudo data output operation.

  Next, the reset switches SRS and SRN are turned on again to apply the reference voltage Vref2 to the gates of the buffers SFS and SFN, and the inputs of the differential amplifiers 205a and 205b are reset again. At this time, signals obtained by adding the first DC potential to the outputs from the differential amplifiers 205a and 205b by the D / A converters DACa and b are input to the A / D converters 104a and 104b, respectively. . Each of the A / D converters 104 a and 104 b converts the input signal into digital data N (1, 1) and N (1, 5) and outputs the digital data to the digital data processing circuit 105. The digital data N (1,1) and N (1,5) are reset data of each differential amplifier including the first DC potential, like the digital data Nd1 and Nd4. This operation is referred to as a reset data output operation.

  Next, a control signal 117b is given from the control unit 108 to each multiplexer. In response, the switch MSOS1 and the switch MSON1 of the first multiplexer 204a are turned on. Thereby, the pixel signal of the pixel in the first column to which the noise component is added is input to the first differential amplifier 205a via the buffer SFS and the noise component via the buffer SFN. Further, the switch MOS5 and the switch MSON5 of the second multiplexer 204b are turned on simultaneously. Thereby, the pixel signals of the pixels in the fifth column to which the noise component is added are input to the second differential amplifier 205b via the buffer SFS and the noise component via the buffer SFN, respectively. The differential signal is applied to the pixel signal to which the noise component is added and the noise component. Then, the difference-processed pixel signal is amplified and output from the differential amplifier. Thereby, the noise component of each amplifier circuit is removed from the output from the amplifier circuit. The A / D converters 104 a and 104 b convert the output pixel signals into digital data S (1,1) and S (1,5) and output them to the digital data processing circuit 105. The digital data S (1,1) and S (1,5) are data obtained by adding a first DC potential to the pixel signals output from the differential amplifiers 205a and 205b. This operation is referred to as a pixel data output operation.

  Next, the reset data output operation is performed again, and the digital data N (1, 2), N (1, 6) is output to the digital data processing circuit 105 from each A / D converter 104a, 104b. The digital data N (1,2) and N (1,6) are data in which a first DC potential is added to the output from the reset differential amplifiers 205a and 205b.

  Then, pixel data output operation is performed for the second and sixth columns, and the digital data S (1,2), S (1,6) is sent from each A / D converter 104a, 104b to the digital data processing circuit. 105 is output. The digital data S (1,2) and S (1,6) are data obtained by adding a first DC potential to the pixel signals output from the differential amplifiers 205a and 205b.

  Similarly, a reset data output operation, a pixel data output operation for the third and seventh columns, a reset data output operation, and a pixel data output operation for the fourth and eighth columns are sequentially performed. As a result, the digital data processing circuit 105 receives digital data N (1,3) and N (1,7), S (1,3) and S (1,7), N (1,4) and N (1,8). ), S (1,4) and S (1,8), respectively. Here, the digital data N (1,3), N (1,7), N (1,4), N (1,8) are output to the output from the reset differential amplifiers 205a and 205b as the first. This is data with a DC potential added. Also, the digital data S (1,3), S (1,7), S (1,4), S (1,8) are converted into the first DC current from the pixel signals output from the differential amplifiers 205a and 205b. This is data with a place added.

  Thereafter, the pseudo reset data output operation is repeated twice, and digital data Nd2 and Nd5, Sd2 and Sd5, Nd3 and Nd6, and Sd3 and Sd6 are output to the digital data processing circuit 105. These digital data are obtained by adding the first DC potential to the outputs from the differential amplifiers 205a and 205b by the D / A converters DACa and b, respectively, in the same manner as the pseudo reset data output operation. .

  Each data output from each of these A / D converters is subjected to correction processing, which will be described later, in the digital data processing circuit 105, and each corrected pixel data D (1, 1) to D (1, 4). , D (1,5) to D (1,8) are obtained.

  As described above, the first signal processing operation is performed on the pixels in the row unit. In the first signal processing operation, a pseudo reset data output operation, a reset data output operation and a pixel data output operation for each column, and subsequent two pseudo reset data, to which a first DC potential is applied, respectively. Output operation is included. Each digital data output from the A / D converter in the first signal processing operation is generically referred to as first digital data.

  Subsequently, the control signal 140 is supplied from the control unit 108 to the D / A converters DACa, b, the direct current potential of the output of the differential amplifier is set to the second direct current potential, and the first direct current is applied to the pixels in row units. A second signal processing operation similar to the signal processing operation is performed. Specifically, digital data N′d1 and N′d4 are output by the pseudo reset output operation. Next, the digital data N ′ (1,1), N ′ (1,5), N ′ (1,2), N ′ (1,6), N ′ (1) are generated by the reset data output operation for each column. , 3), N ′ (1, 7), N ′ (1, 4), N ′ (1, 8). Further, by the pixel data output operation, digital data S ′ (1,1), S ′ (1,5), S ′ (1,2), S ′ (1,6), S ′ (1,3), S ′ (1,7), S ′ (1,4), S ′ (1,8) are output. Then, digital data N'd2, N'd5, S'd2, S'd5, N'd3, N'd6, S'd3, and S'd6 are output by two pseudo reset data output operations. Then, similarly to the first signal processing operation, the digital data processing circuit 105 performs correction processing, which will be described later, and each corrected pixel data D ′ (1, 1) to D ′ (1, 4), D '(1,5) to D' (1,8) are obtained. Each digital data output from the A / D converter in the second signal processing operation is generically referred to as second digital data.

  Then, for each data corresponding to each pixel, the digital data processing circuit 105 corrects the pixel data D (m, n) after correction by the first signal processing operation and the pixel data D ′ (after correction by the second signal processing operation). m, n) is averaged to generate output data DA (m, n). This operation is referred to as an average processing operation. Then, the pixel-by-row pixel reading operation is achieved by the pixel-by-row output operation and the data processing operation including the first and second signal processing operations and the average processing operation. Then, this pixel-by-row readout operation is repeated, and the readout operation for one image is achieved.

  As described above, in this embodiment, the A / D conversion operation is performed twice while changing the DC potential with respect to the pixel signals of the predetermined pixels included in the same row, and the digital data corresponding to each pixel is obtained. Final output data is obtained by performing the process of averaging each other.

  Here, in the present embodiment, the output operation of the pixels in the second row is performed within a period in which the data processing operation in the first row is performed. First, as in the first row, the integration capacitor Cf is reset by the reset switch RC, and the amplifier circuit is reset. Next, the sampling switch SHEN of the sample and hold circuit for even-numbered row noise is turned on, and the noise component of the amplifier circuit is transferred from the reset amplifier circuit to the sampling capacitor Chen. The sampling switch SHEN is turned off and the noise component is held in the sampling capacitor Chen. Next, the drive signal 111 is supplied from the drive circuit 102 to the drive wiring G2 in the second row, and the switch elements T21 to T28 in the second row are turned on. Thereby, analog electric signals based on the charges generated in the conversion elements S21 to S24 in the second row are transmitted from each pixel to the first readout circuit 103a in parallel via the signal wirings Sig1 to Sig4. In addition, an analog electric signal based on the charges generated in the conversion elements S25 to S28 in the second row is transmitted from each pixel to the second readout circuit 103b in parallel via the signal wirings Sig5 to Sig8. Then, the sampling switch SHES of the even-row signal sample-hold circuit is turned on, and the read pixel signal is transferred to the sampling capacitor Ches via the amplifier circuit. At this time, the noise component of the amplifier circuit is added to the pixel signal. Then, the sampling switch SHES is turned off, and the pixel signal to which the noise component is added is held in the sampling capacitor Chen. In the pixel data output operation of the second row, the switches MSES and the switches MSEN of each multiplexer are sequentially turned on similarly to the first row. Otherwise, the same operation as the first line is performed. Since such an output operation and a data processing operation are performed, the output operation for the next row unit can be performed within a period in which the signal processing operation for the previous row unit is performed. Therefore, it is possible to reduce the time required for the read operation for one image, compared to the case where the output operation for each row is performed after the data processing operation for the next row.

  Next, correction processing performed by the digital data processing circuit 105 will be described with reference to FIG. FIG. 4A is a block diagram for explaining the correction processing unit 400 included in the digital data processing circuit 105. FIG. 4B is a timing chart for explaining the correction process performed by the reset data processing unit 401, the pixel data processing unit 402, and the adder 403. In this embodiment, the correction processing unit 400 of FIG. 4A is provided for each A / D converter, and in the following description, it is provided corresponding to the first A / D converter 104a. The description will be made assuming that However, this correction processing unit is not limited to the above, and it may be provided to perform correction processing on data after digital multiplexing of data from the first and second A / D converters. Good.

  The correction processing unit 400 includes a reset data processing unit 401, a pixel data processing unit 402, an adder 403, a storage unit 404, an average processing unit 405, and a parallel / serial conversion unit 406. Here, the reset data processing unit 401 includes a plurality of delay elements 411 to 414, an adder 415, and a multiplier 416. The pixel data processing unit 402 includes a plurality of delay elements 421 to 422.

  Based on the control signal 130 from the control unit 108, N_CLK is given to each delay element 411 to 414 of the reset data processing unit 401, and S_CLK is given to each delay element 421 to 422 of the pixel data processing unit 402. Yes. The digital data Nd1 output from the first A / D converter 104a for the first signal processing operation is input to the correction processing unit 400, and is input to the delay element 411 of the reset data processing unit 401 in response to the rising edge of N_CLK. Retained. Next, Sd1 is input to the correction processing unit 400 and held in the delay element 421 of the pixel data processing unit 402 in response to the rising edge of S_CLK. Next, N (1,1) is input to the correction processing unit 400, held in the delay element 411 in response to the rising edge of N_CLK, and Nd1 is held in the delay element 412. Next, S (1,1) is input to the correction processing unit 400 and held in the delay element 421 in response to the rising edge of S_CLK. Next, N (1,2) is input to the correction processing unit 400, held in the delay element 411 in response to the rising edge of N_CLK, N (1,1) is held in the delay element 412, and Nd1 is delayed in the delay element 413. Retained. Next, S (1,2) is input to the correction processing unit 400, held in the delay element 421 in response to the rising edge of S_CLK, and S (1,1) is held in the delay element 422 and added from the delay element 422. S (1,1) is output to the machine 403. Next, N (1,3) is input to the correction processing unit 400, held in the delay element 411 in response to the rising edge of N_CLK, and N (1,2) is held in the delay element 412. ) Is held in the delay element 413, and Nd1 is held in the delay element 414. Outputs from the delay elements 411 to 414 are output to the adder 415 and added, multiplied by ¼ for averaging by the multiplier 416, and output to the adder 403. The adder 403 subtracts the data output from the pixel data processing unit 402 and the data output from the reset data processing unit 401 and outputs corrected pixel data D (1, 1). With this processing, the pixel data D (1,1) becomes S (1,1) − (Nd1 + N (1,1) + N (1,2) + N (1,3)) / 4. Similarly, the pixel data D (1,2) is S (1,2)-(N (1,1) + N (1,2) + N (1,3) + N (1,4)) / 4. That is, in this correction process, first, the readout circuit provides a plurality of reset signals to the A / D converter within the period of the signal processing operation in units of rows. The A / D converter converts a plurality of reset signals into a plurality of reset data. The correction processing unit performs an averaging process on a plurality of reset data output from the A / D converter. Then, the correction processing unit obtains pixel data D (m, n) by performing subtraction processing on the pixel data of the predetermined row output from the A / D converter within the same period and the reset data subjected to the averaging process. To do. Further, in the present embodiment, a total of four reset data, which are near in time and two before and after, are subjected to an averaging process with respect to pixel data to be corrected. This is because the high-frequency noise component in the processed reset data is suppressed by performing the averaging process on the reset data including the high-frequency noise component and the low-frequency 1 / f noise component. That is, it can be considered that the averaging process is performed by applying a low-pass filter (LPF) to the reset data. For this reason, the reset data subjected to the averaging process mainly includes a low-frequency 1 / f noise component. The accuracy of this LPF process improves as the number of reset data to be subjected to the averaging process increases. Then, the 1 / f noise component can be favorably reduced from the pixel data by subtracting the pixel data including the low frequency 1 / f noise component and the reset data subjected to the averaging process. This subtraction process can be considered as a high-pass filter (HPF) applied to the pixel data. That is, this correction process can perform both the LPF process and the HPF process on the pixel data, and a good correction process can be performed. However, the present embodiment is not limited to two at the front and rear, and may be the same number at the front and rear. Each pixel data D (1, 1) to D (1, 4) output from the adder 403 is stored in the storage unit 404. The above processing is similarly performed for the second signal processing operation, and D ′ (1,1) to D ′ (1,4) are also stored in the storage unit 404.

  Next, the average processing unit 405 performs an averaging process on D (1,1) and D ′ (1,1), which are pixel data of the same pixel in the first row and first column, as a set, and the corrected pixel data DA (1, 1) is output. D (1,2) and D ′ (1,2), D (1,3) and D ′ (1,3), D (1,4) and D ′ (1,4) Similarly, the averaging processing unit 405 performs the averaging process. The averaged pixel data is converted into serial data by the parallel-serial converter, and the corrected pixel data is DA (1,1), DA (1,2), DA (1,3), DA (1 , 4) are sequentially output.

  Next, information regarding the non-linearity of the A / D converter will be described. This non-linearity indicates how far the relationship between the actual analog input and digital output (A / D conversion value) deviates from the ideal straight line, and specifically, differential non-linearity (DNL) or integration. Indicated by non-linearity (INL). INL means the deviation of the actual input / output characteristic from the ideal input / output line when looking over the entire input / output characteristic of the A / D converter. DNL means a deviation from an ideal step when each input / output step is viewed individually.

  Hereinafter, the influence due to the difference in the A / D conversion characteristics of the first and second A / D converters will be described with reference to FIGS. The non-linearity of each of the first and second A / D converters 104a and 104b will be described with reference to FIG. Here, a case where the first A / D converter 104a has ideal A / D conversion characteristics and the second A / D converter 104b has nonlinearity deviated from the ideal characteristics is illustrated. ing. In FIG. 5A, the horizontal axis represents the input voltage input to the A / D converter, and the vertical axis represents the digital value (code) output from the A / D converter. In FIG. 5A, an A / D converter with a resolution of 8 bits is assumed for the sake of simplicity.

  FIG. 5B shows the difference in digital value with respect to the input voltage of the first and second A / D converters 104a and 104b. According to FIG. 5B, when the input voltages of the first and second A / D converters 104a and 104b are converted into digital values as they are and output, a maximum of about 30 LSB is output between the two A / D converters. There will be a difference. Therefore, there is a possibility that a density step on the image of about 30 LSB at the maximum occurs between the first and second pixel groups 101a and 101b corresponding to the first and second A / D converters 104a and 104b, respectively. In particular, as in the present embodiment, if the first and second pixel groups are in a form in which the entire detection unit 101 is divided into regions, the density step is visually noticeable at the boundary between the first and second pixel groups. This results in a noticeable result and significantly reduces the quality of the acquired image.

  Therefore, in the present invention, the control unit 108 adds a direct current potential to the output of the differential amplifier connected to the first and second A / D converters, whereby the first and second A / D converters. A process of adding a direct current potential to an analog electric signal that can be input to is performed. For example, it is assumed that a DC potential of 300 mV is set in the first signal processing operation and a signal corresponding to 400 mV is input to the first and second A / D converters. In that case, a step of about −15 LSB occurs between the first pixel group and the second pixel group due to the non-linearity difference of the A / D converter. Subsequently, a DC potential of 500 mV is set in the second signal processing operation, and a signal corresponding to 600 mV is input to the first and second A / D converters. In that case, a step of about +15 LSB occurs between the first pixel group and the second pixel group due to the non-linearity difference of the A / D converter. And the result of the 1st and 2nd signal processing is averaged, and it becomes possible to reduce a level difference. When the characteristics of the two A / D converters are known, the step difference can be effectively reduced by appropriately selecting the DC potential to be added. Therefore, it is preferable that the control unit 108 performs the above-described processing based on information on the non-linearity of the first and second A / D converters 104a and 104b stored in other storage means, for example. Based on the information, the difference between the average value of the digital signal output from the first A / D converter and the average value of the digital signal output from the second A / D converter is reduced. It becomes possible to perform processing. Thereby, it is possible to perform processing for reducing the density step with higher accuracy. However, the present invention is applicable even if the characteristics of the A / D converter are unknown, and an effect of reducing the step can be obtained. When the characteristics of the A / D converter are unknown, it is more desirable to perform the signal processing operation at least four times with different DC potentials on the same row more times. In particular, in the case of four or more times, a special effect is produced in addition to non-linearity error reduction, such as the quantization error of the A / D converter is ½ or less. In addition, it is desirable to apply the present invention to an imaging apparatus using a pipeline type A / D converter that is likely to cause a nonlinear error structurally as an A / D converter.

  However, if the above processing is performed only on the image signal at the time of shooting, an unnecessary signal component is added to the image signal to be acquired, and the accuracy of the obtained image signal may be reduced. Therefore, in the present invention, an image signal for correction for correcting an image signal at the time of shooting, such as an image signal for offset correction for correcting dark output and an image signal for sensitivity correction, and an image at the time of shooting. The signal is acquired by performing substantially the same processing. Then, the digital data processing circuit 105 performs correction processing using the acquired image data for correction and image data at the time of shooting, and outputs the corrected image data. By such processing, the added unnecessary signal components are removed or reduced, so that a sense of incongruity such as a step is reduced and an image with good image quality can be acquired.

  In the present embodiment, the amount of change between the direct current potential output from the differential amplifier in the first signal processing operation and the direct current potential in the second signal processing operation is based on information in a storage means (not shown). In addition, the control circuit 108 may obtain the calculation in real time. Moreover, you may predetermine based on the information regarding each nonlinearity of the 1st and 2nd A / D converter.

  In the present embodiment, the case where there are two A / D converters has been described. Needless to say, the present invention can be applied to a case where there are more A / D converters. Although it is desirable to perform the above processing on all of the plurality of A / D converters, the above processing may be performed only on a part of the plurality of A / D converters.

  As a method for adding a DC potential to the input to the A / D converter, in this embodiment, a D / A converter coupled with a capacitor on the input side of the differential amplifier is used. This is desirable as a configuration for realizing the present problem with a simple configuration, but the present invention is not limited to this. Furthermore, in this embodiment, the DC potential of the analog signal input to the A / D converter is changed, but the same effect can be obtained even if the gain is changed using a differential amplifier having a variable capacitor. be able to. In this embodiment, the averaging process is performed using the pixel data D (m, n) subjected to the addition averaging process and the subtraction process, but the present invention is not limited to this. The effect of the present invention can also be obtained by simply averaging the pixel data S (m, n) and S ′ (m, n). After that, addition averaging processing and subtraction processing may be performed.

  The effects of the present invention will be described with reference to FIGS. 6 (a) and 6 (b). FIG. 6A shows image data not subjected to the main correction process, and FIG. 6B shows image data subjected to the main correction process. Here, an example is shown in which the detection unit is divided into four pixel groups. The image data that has been subjected to the main correction process is a good image with the steps between the pixel groups being inconspicuous compared to the image data that has not been subjected to the main correction process. By reducing the step between the pixel groups in this way, artifacts given to the image can be reduced. As described above, the correction processing unit 400 that performs the main correction process can reduce artifacts caused by a step caused by a difference in non-linearity (INL) of the A / D converter in an acquired image. .

  Next, FIG. 7 shows an application example to a movable radiation imaging system using the imaging apparatus of the present invention. FIG. 7 is a conceptual diagram of an imaging system using a portable imaging device capable of shooting a moving image / still image. In FIG. 7, reference numeral 600 denotes a radiation generation apparatus, 601 denotes a C-arm that functions as a holding unit that can hold the imaging apparatus 100, and 602 denotes a carriage that allows the radiation generation apparatus 600, the imaging apparatus 100, and the C-type arm 601 to move. It is. Reference numeral 603 denotes a bed on which the subject 604 is placed, 605 is a mobile control device having a configuration capable of controlling them, and 606 is a display device capable of displaying an image signal obtained by the imaging device 100. The control device 605 includes a control computer, a control console, a radiation control device, and the like. The image signal obtained by the imaging device 100 can be image-processed and transmitted to the display device 606 and the like. Further, the image data generated by the image processing by the control device 605 can be transferred to a remote place by transmission means such as a telephone line. Thereby, it becomes possible for a remote doctor to diagnose an image based on the transferred image data. Further, the transmitted image data can be recorded on a film or stored in a storage means such as an optical disk.

However, the imaging apparatus 100 may be configured to be removable from the C-type arm 601 and imaging may be performed using a radiation generation apparatus different from the radiation generation apparatus 600 of the C-type arm 601.
As described above, by applying the imaging apparatus of the present invention to a radiation imaging system, it is possible to acquire an image signal having a favorable S / N ratio while achieving a desired frame time.

  In the present invention, the processing steps of the control unit 108 may be realized by a computer included in the control unit 108 executing a program. At that time, the lookup table LUT and the program are stored in the control unit 108. Also, means for supplying a program to a computer, for example, a computer-readable recording medium such as a CD-ROM recording such a program, or a transmission medium such as the Internet for transmitting such a program is also applied as an embodiment of the present invention. Can do. A computer program product such as a computer-readable recording medium in which the above program is recorded can also be applied as an embodiment of the present invention. The above program, recording medium, transmission medium, and computer program product are included in the scope of the present invention. As the recording medium, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

DESCRIPTION OF SYMBOLS 100 Imaging device 101 Conversion part 102 Drive circuit 103 Reading circuit 104 A / D converter 105 Digital data processing circuit 106 Signal processing part 107 Power supply part 108 Control part

Claims (10)

A plurality of pixels for converting radiation or light into analog electrical signals in a matrix, and a plurality of the pixels divided into at least a first pixel group and a second pixel group;
An analog output unit by row from the detection unit, the first readout circuit electrically connected to the first pixel group; and a second readout circuit electrically connected to the second pixel group. Read circuit section for reading electrical signals, first A / D converter electrically connected to the first read circuit, and second A / D converter electrically connected to the second read circuit A signal processing unit including: an A / D conversion unit that converts an analog electrical signal output from the readout circuit unit into digital data and outputs the digital data; and a digital data processing circuit that processes the digital data;
A control unit for controlling the signal processing unit;
An imaging device having
The readout circuit further includes reset means for outputting a reset signal to the A / D converter,
The control unit applies the first DC potential to a plurality of reset signals within a period for the first and second readout circuits to read out the analog electric signals of the pixels in a predetermined row, thereby the A / D conversion unit. And the A / D conversion unit converts the first reset data, which is digital data, within the period, and the plurality of first outputs output from the A / D conversion unit within the period. Reset data is added and averaged, and the first DC potential is applied to the analog electric signal of the pixel within the period and output to the A / D converter. The A / D converter is digital data. A first signal that is converted into first pixel data and subtracts the first pixel data and the plurality of first reset data that have undergone the averaging process to obtain corrected first pixel data Processing operations and multiple resets within the period. A second DC potential is applied to the signal and output to the A / D converter, and the A / D converter converts the signal into a plurality of second reset data that is digital data within the period. The plurality of second reset data output from the A / D conversion unit is added and averaged, and the second DC potential is applied to the analog electric signal of the pixel within the period, so that the A / D Output to the conversion unit, the A / D converter converts to second pixel data which is digital data, and subtracts the second pixel data and the plurality of second reset data subjected to the averaging process A signal processing operation including a second signal processing operation for obtaining corrected second pixel data, the corrected first pixel data, and the corrected second pixel data. Average averaging by digital data processing circuit And management operation, as the signal processing unit performs the image pickup device and controls the signal processing unit.   The imaging apparatus according to claim 1, wherein the signal processing unit further includes a DC potential control circuit that changes the DC potential in accordance with a control signal from the control unit. Storage means for storing information relating to the non-linearity of the first and second A / D converters;
The imaging apparatus according to claim 2, wherein the control unit controls the DC potential control circuit based on information stored in the storage unit.   The control unit controls the DC potential control circuit based on a predetermined amount of change based on information on nonlinearity of the first and second A / D converters. The imaging device described in 1.   The imaging apparatus according to claim 1, wherein the DC potential control circuit includes a D / A converter and a capacitor. The readout circuit unit further includes an amplifier connected to the A / D conversion unit,
The control unit controls the signal processing unit to change the first DC potential and the second DC potential by changing a gain of the amplifier. The imaging device according to any one of 5.   The imaging apparatus according to claim 1, wherein the first and second A / D converters are pipeline type A / D converters. The imaging device according to any one of claims 1 to 7,
A control device for controlling at least the imaging device;
An imaging system including: A plurality of pixels for converting radiation or light into analog electrical signals in a matrix, and a plurality of the pixels divided into at least a first pixel group and a second pixel group; and the first A first readout circuit electrically connected to the pixel group; and a second readout circuit electrically connected to the second pixel group, and reading out an analog electrical signal output in units of rows from the detection unit. A read circuit unit; a first A / D converter electrically connected to the first read circuit; and a second A / D converter electrically connected to the second read circuit; A signal processing unit including an A / D conversion unit that converts an analog electrical signal output from the readout circuit unit into digital data and outputs the digital data; and a digital data processing circuit that processes the digital data, Read circuit reset signal to the A / D converter A method of controlling an image pickup apparatus further comprising a reset means for outputting,
A first DC potential is applied to a plurality of reset signals and output to the A / D converter within a period for the first and second readout circuits to read out analog electric signals of pixels in a predetermined row, An A / D converter converts into a plurality of first reset data which is digital data within the period, and adds and averages the plurality of first reset data output from the A / D converter within the period First pixel data in which the first DC potential is applied to the analog electrical signal of the pixel within the period and output to the A / D converter, and the A / D converter is digital data. A first signal processing operation for obtaining the corrected first pixel data by subtracting the first pixel data and the plurality of first reset data subjected to the averaging process,
A second DC potential is applied to a plurality of reset signals within the period and output to the A / D converter, and the A / D converter includes a plurality of second reset data that is digital data within the period. The second reset data output from the A / D converter within the period is added and averaged, and the second DC potential is applied to the analog electric signal of the pixel within the period. The second pixel data is added to the A / D converter and converted into second pixel data which is digital data, and the second pixel data is subjected to an averaging process. A second signal processing operation for obtaining a corrected second pixel data by subtracting the reset data of
An average processing operation for averaging the corrected first pixel data and the corrected second pixel data by the digital data processing circuit;
The control method characterized by performing. A plurality of pixels for converting radiation or light into analog electrical signals in a matrix, and a plurality of the pixels divided into at least a first pixel group and a second pixel group; and the first A first readout circuit electrically connected to the pixel group; and a second readout circuit electrically connected to the second pixel group, and reading out an analog electrical signal output in units of rows from the detection unit. A read circuit unit; a first A / D converter electrically connected to the first read circuit; and a second A / D converter electrically connected to the second read circuit; A signal processing unit including an A / D conversion unit that converts an analog electrical signal output from the readout circuit unit into digital data and outputs the digital data; and a digital data processing circuit that processes the digital data, Read circuit reset signal to the A / D converter A program for executing the control of the imaging apparatus further comprising a reset means for outputting to the computer,
A first DC potential is applied to a plurality of reset signals and output to the A / D converter within a period for the first and second readout circuits to read out analog electric signals of pixels in a predetermined row, An A / D converter converts into a plurality of first reset data which is digital data within the period, and adds and averages the plurality of first reset data output from the A / D converter within the period First pixel data in which the first DC potential is applied to the analog electrical signal of the pixel within the period and output to the A / D converter, and the A / D converter is digital data. Subtracting the first pixel data and the plurality of first reset data subjected to the averaging process to obtain corrected first pixel data;
A second DC potential is applied to a plurality of reset signals within the period and output to the A / D converter, and the A / D converter includes a plurality of second reset data that is digital data within the period. The second reset data output from the A / D converter within the period is added and averaged, and the second DC potential is applied to the analog electric signal of the pixel within the period. The second pixel data is added to the A / D converter and converted into second pixel data which is digital data, and the second pixel data is subjected to an averaging process. Subtracting the reset data and acquiring the corrected second pixel data;
Averaging the corrected first pixel data and the corrected second pixel data by the digital data processing circuit;
A program that causes a computer to execute control of the imaging apparatus that performs the above.

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