JP2011087385A - Charge pump circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump circuit reduced in charge loss due to parasitic capacitance much more than a conventional one. <P>SOLUTION: Each of step-up stages V constituting the charge pump circuit is comprised of: charge-transfer capacitors 406a to 409a each of which is comprised of a poly-Si layer and a poly-Si layer formed over this poly-Si layer; diode elements 401 to 404 that transfer electric charges stored in the charge-transfer capacitors 406a to 409a in the preceding stage to the their respective step-up stages; and a clock signal generation circuit 400 that supplies the charge-transfer capacitors 406a to 409a with clock signals for controlling the timing of charging/discharging the capacitors. At least either of the poly-Si layers constituting the charge-transfer capacitors 406a to 409a is arranged opposite a conductive layer. The clock signal generation circuit 400 supplies the clock signals also to this conductive layer in addition to the capacitors 406a to 409a. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a charge pump circuit that sequentially boosts and outputs an input voltage at a plurality of boosting stages, and more particularly to a charge pump circuit formed as an integrated circuit on a semiconductor substrate.

  Currently, a charge pump circuit is used for control that requires a voltage higher than the power supply voltage. The charge pump circuit can generate a high voltage of 10 V or higher on the semiconductor substrate. As a technique in which the charge pump circuit is used, for example, there is a writing control to a nonvolatile memory such as a MEMS (Micro Electro Mechanical Systems) microphone or an EEPROM (Electrically Erasable and Programmable Read Only Memory).

FIG. 5 is a diagram for explaining a general charge pump circuit. The illustrated charge pump circuit is a charge pump circuit called a Cockcroft-Walton type charge pump circuit. In the illustrated example, it is configured to have four boosting stages. Each stage of the four boosting stages is denoted as I, II, III, and IV in FIG.
The first boosting stage I includes a diode element 101 and a capacitor 106 having one end connected to the cathode terminal of the diode element 101. Similarly, the second boosting stage II includes a diode element 102 and a capacitor 107. The third boosting stage III is composed of a diode element 103 and a capacitor 108, and the fourth boosting stage IV is composed of a diode element 104 and a capacitor 109.

  The diode elements 101 to 104 are connected to each other in series. The capacitor 106 of the first boost stage I and the capacitor 108 of the third boost stage III are connected in series. The capacitor 107 in the second boost stage II and the capacitor 109 in the fourth boost stage IV are connected in series. The clock signal Φ1 is input to a terminal of the capacitor 106 that is not connected to the diode element 101. A clock signal Φ2 having an inverse correlation system with respect to the clock signal Φ1 is input to a terminal of the capacitor 107 not connected to the diode element 102. The output of the fourth boosting stage IV that is the final stage is connected to the output terminal VOUT via the diode element 105.

  The charge pump circuit described above operates as follows. That is, at the start of the operation, no charges are stored in the capacitors 106 to 109 of the boosting stages I to IV. When the clock signals Φ 1 having opposite phases are low and the clock signal Φ 2 is high, the input signal VIN is input to the capacitor 106 via the diode element 101. Charge is injected into the capacitor 106 by the input signal VIN from the input terminal.

  Subsequently, the clock signal Φ1 becomes high and the clock signal Φ2 becomes Low. At this time, the potential of the node N11 shown in FIG. 5 rises due to the charge corresponding to the amplitude of the clock signal Φ1 and the charge stored in the capacitor 106. When the potential of node N11 rises and becomes higher than the potential of node N12 in FIG. 5, the charge stored in capacitor 106 is transferred to capacitor 107 via diode element 102.

  Further, when the clock signal Φ1 becomes Low and the clock signal Φ2 becomes high, the input signal VIN is input to the capacitor 106 again. At this time, the potential of the node N12 rises due to the charge corresponding to the amplitude of the clock signal Φ2 and the charge stored in the capacitor 107. When the potential of node N12 rises and becomes higher than the potential of node N13 in FIG. 5, the charge stored in capacitor 107 is transferred to capacitor 108 via diode element 103.

  Subsequently, the clock signal Φ1 becomes high and the clock signal Φ2 becomes Low. At this time, the potentials of the nodes N11 and N13 shown in FIG. 5 are increased by the charge corresponding to the amplitude of the clock signal Φ1 and the charges stored in the capacitors 106 and 108. When the potential of the node N11 becomes higher than the potential of the node N12, the charge stored in the capacitor 106 is transferred to the capacitor 107 through the diode element 102. When the potential of the node N13 becomes higher than the potential of the node N14, the electric charge stored in the capacitor 108 is transferred to the capacitor 109 via the diode element 104. As described above, the charge pump circuit operates in accordance with the antiphase clock signals Φ1 and Φ2, thereby obtaining a boosted potential while sequentially transferring charges from the first boost stage I to the fourth boost stage IV. be able to.

  However, in the Cockcroft-Walton type charge pump circuit formed on the semiconductor substrate, in the capacitors 106 to 109, parasitic capacitances 110 and 111 are formed between the lower electrode of the capacitor and the substrate, and between the upper electrode of the capacitor and the conductive layer on the upper electrode. , 112, 113 are generated. The capacitance Cs of the parasitic capacitors 110, 111, 112, and 113 has a large value that cannot be ignored compared to the capacitance C of the capacitors 106 to 109. Therefore, when the clock signals Φ1 and Φ2 are inverted in polarity, a part of the charge stored in the capacitors 106 to 109 of each boosting stage is transferred to the parasitic capacitors 110, 111, 112, and 113, resulting in charge loss. . The charge loss becomes a factor that lowers the boosted potential finally obtained in the charge pump circuit. In FIG. 5, the parasitic capacitance Cs is represented as parasitic capacitances 110 to 113 in the drawing.

  As a conventional technique for preventing charge loss, for example, the clock signal Φ1 is directly input to all the odd-stage boost stage capacitors of the charge pump circuit without passing through other capacitors, and all the even-stage boost stage capacitors are used. There is a circuit for directly inputting the clock signal Φ2. FIG. 6 is a circuit for explaining such a conventional example. The circuit shown in FIG. 6 is described in Non-Patent Document 1. Such a conventional charge pump circuit is called a Dickson type charge pump circuit.

  The charge pump circuit of the prior art shown in FIG. 6 has four boosting stages I to IV as in the charge pump circuit shown in FIG. The boosting stage I is composed of a diode element 201 and a capacitor 206. Further, the boosting stage II is constituted by a diode element 202 and a capacitor 207, the boosting stage III is constituted by a diode element 203 and a capacitor 208, and the boosting stage IV is constituted by a diode element 204 and a capacitor 209.

  In each boosting stage, the cathode terminal of the diode element is connected to one end of the capacitor. The diode elements 201 to 205 are connected in series with the diode elements of the adjacent boosting stages. The output of the diode element 205 is connected to the output terminal VOUT of the charge pump circuit. As described above, the clock signal Φ1 is directly input to the capacitors 206 and 208 of the odd-numbered boosting stages. Further, the clock signal Φ2 is directly inputted to the capacitors 207 and 209 of the even-numbered boosting stage.

  In the charge pump circuit shown in FIG. 6, the operation of transferring charges in order from the capacitor 206 is performed in the same manner as the charge pump circuit shown in FIG. According to the charge pump circuit shown in FIG. 6, the potentials applied to the capacitors 206 to 209 change by the amplitude of the clock signal without being affected by the parasitic capacitances 210 to 213. Charge loss can be reduced as compared with the charge pump circuit shown in FIG. 5, and the input voltage can be boosted efficiently.

J.F.Dickson "On-chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique" IEEE Journal of Solid State Circuits, Vol, SC-11, No. 3, June 1976.

However, in the charge pump circuit shown in FIG. 6, the potential difference generated between the electrodes of the capacitor in the subsequent stage increases as the number of boosting stages increases. For this reason, at least the boosting stage subsequent to the charge pump circuit that outputs a high voltage has a high withstand voltage capacitor with a small capacitance per unit area, or a parasitic capacitance between conductive layers in a standard process having no high withstand voltage element. It must be used as a charge transfer capacitor, and there is a problem that charge loss due to parasitic capacitance increases when a high voltage exceeding the rated voltage allowed by the manufacturing process is generated.
The present invention has been made in view of the above points, and an object of the present invention is to provide a charge pump circuit that can further reduce charge loss due to parasitic capacitance.

  In order to solve the above problems, the charge pump circuit according to claim 1 is a charge pump circuit configured by connecting a boosting stage (for example, the boosting stages I to IV shown in FIG. 1) in a plurality of stages, Each of the boosting stages includes a first electrode (for example, the first poly-Si layer 303 shown in FIG. 2) and a second electrode (for example, the second poly-Si layer 304 shown in FIG. 2) formed on the first electrode. ) And a diode element (for example, a charge transfer capacitor 406a to 409a shown in FIG. 1) and an input signal or a charge accumulated in the capacitor in the previous stage to the capacitor in the self-boosting stage (for example, 1 and a clock signal for controlling the timing of charging and discharging of the capacitor are supplied to the capacitor. Lock signal supply means (for example, the clock signal generation circuit 400 shown in FIG. 1), and at least one of the first electrode and the second electrode of the capacitor is a conductive layer (for example, N− shown in FIG. 2). The clock signal supplying means supplies the clock signal supplied to the capacitor to the conductive layer together with the capacitor.

  According to a second aspect of the present invention, in the first aspect of the present invention, the clock signal supply means is connected to the capacitor and the conductive layer of the first boost stage among the boost stages connected to a plurality of stages. A first clock signal is supplied, and a second clock whose phase with the first clock signal is inverted by 180 degrees is applied to the capacitor and the conductive layer of the second boost stage connected to the first boost stage. A signal is supplied, and the capacitor of the second boost stage is charged at a timing when the capacitor of the first boost stage is discharged.

The invention according to claim 3 is the invention according to claim 1 or 2, wherein the first electrode and the second electrode of the capacitor are conductive layers including at least one of polysilicon and metal. And
According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, the conductive layer includes a first well layer formed on a substrate under the first electrode, and the second electrode. And at least one of conductive layers including at least one of polysilicon and metal formed above.

The invention according to claim 5 is the invention according to any one of claims 1 to 4, wherein the plurality of boosting stages connected to the plurality of stages constitute a Cockcroft-Walton type circuit. (For example, the charge pump circuit shown in FIG. 1).
The invention according to claim 6 is the invention according to any one of claims 1 to 4, wherein the plurality of boosting stages connected to the plurality of stages constitute a Dickson type circuit ( For example, the charge pump circuit shown in FIG.

  The invention according to claim 7 is the invention according to any one of claims 2 to 5, wherein the capacitor is formed on a first well (for example, an N-well 302) formed below the first electrode. The diode element is formed on a second well (eg, N-well 310) formed independently of the first well, and includes a MOS transistor element having a conductivity type different from that of the second well. In the MOS transistor, the drain terminal, the gate terminal, and the second well of the MOS transistor are connected to function as a diode element, and the cathode is included in the self-boosting stage of the first electrode and the second electrode of the capacitor. Connected to either one of them, the charge is input from the anode, and the input charge is input from the cathode to the first voltage boost stage. The boosting stage is connected to a plurality of stages by connecting the cathode of each boosting stage to the anode of the diode element of the next boosting stage. In the boosting stage connected to a plurality of stages, the first clock signal is supplied to the capacitor of the first boosting stage, and the second clock signal is supplied to the capacitor of the second boosting stage, Capacitors in the third and subsequent boost stages are connected to the output of the previous boost stage, and the first clock signal is supplied to the first wells of the odd boost stages. By supplying the second clock signal to the first well of the boosting stage, the first clock signal is supplied to each of the boosting stages. A parasitic capacitor formed by Le and the first electrode, the first electrode, and drives and said capacitor formed by said second electrode with the same clock signal.

  The invention according to claim 8 is the invention according to claim 7, wherein, among the boosting stages connected to a plurality of stages, the odd-numbered boosting stage is formed above the second electrode. The first clock signal is supplied to the conductive layer, and the second clock signal is supplied to the conductive layer formed above the second electrode in the even-numbered boosting stage. In each boosting stage, the capacitor formed by the first electrode and the second electrode, and the parasitic capacitor formed by the conductive layer formed above the second electrode and the second electrode, It is characterized by being driven by the same clock signal.

  According to the first aspect of the present invention, the clock signal supplied to the capacitor can be supplied to the conductive layer facing at least one of the first electrode and the second electrode constituting the capacitor included in each of the boosting stages. . For this reason, the capacitor, the parasitic capacitor generated between at least one of the first electrode and the second electrode, and the conductive layer are charged and discharged at the same timing. Therefore, according to the first aspect of the present invention, it is possible to sufficiently prevent the charge loss caused by the charge discharged from the capacitor being accumulated in the parasitic capacitor.

According to the invention of claim 2, since the second booster stage connected to the first booster stage is charged at the timing when the capacitor of the first booster stage is discharged, charging for charge transfer is performed. The discharge time can be maximized.
According to the invention of claim 3, since the first electrode and the second electrode of the capacitor are conductive layers containing at least one of polysilicon or metal, they are suitable as the first electrode and the second electrode. Capacitors can be formed using materials.

According to the fourth aspect of the present invention, charge loss due to parasitic capacitance generated between the well layer and the wiring layer formed above the second electrode can be suppressed.
According to the fifth aspect of the present invention, it is possible to configure a Cockcroft-Walton type circuit in which a constant voltage is applied between the electrodes of the capacitor regardless of the number of boosting stages. For this reason, a capacitor created by a general process can be used in all of the boosting stages, and the necessity of using a capacitor with a particularly high breakdown voltage can be eliminated.

According to the sixth aspect of the present invention, when a Dickson type circuit is configured, charge loss due to parasitic capacitance between the electrode of the charge transfer capacitor and the adjacent upper and lower conductive layers can be eliminated.
According to the invention of claim 7, since the well under the capacitor and the well under the MOS transistor are formed independently, the parasitic capacitance generated between the well and the lower electrode of the capacitor is independent of the MOS transistor. Can be charged and discharged. Further, in each of the boosting stages connected to the plurality of stages, the capacitor and the parasitic capacitance can be charged / discharged at the same timing, and the charge transfer between the capacitor and the parasitic capacitance can be minimized.

  According to the invention of claim 8, in each of the boosting stages, the parasitic capacitor formed by the first well and the first electrode, and the capacitor formed by the first electrode and the second electrode And the parasitic capacitor formed by the conductive layer formed above the second electrode and the second electrode can be driven by the same clock signal, and can be driven by the first well and the first electrode. Between the parasitic capacitor formed, the capacitor formed by the first electrode and the second electrode, and the parasitic capacitor formed by the conductive layer formed above the second electrode and the second electrode The charge transfer at can be minimized.

It is a figure for demonstrating the whole charge pump circuit of Embodiment 1 of this invention. It is a figure for demonstrating the pressure | voltage rise stage shown in FIG. It is a figure for demonstrating the whole charge pump circuit of Embodiment 2 of this invention. FIG. 4 is a diagram for explaining a charge transfer capacitor and a parasitic capacitance of each boosting stage shown in FIG. 3. It is the figure which showed the general Cockcroft-Walton type charge pump circuit. It is the figure which showed the general Dickson type charge pump circuit.

Embodiments 1 and 2 of the present invention will be described below.
(Embodiment 1)
(1) Configuration of Charge Pump Circuit FIG. 1 is a diagram for explaining the entire charge pump circuit according to the first embodiment of the present invention. The charge pump circuit according to the first embodiment is a four-stage boost charge pump circuit in which four boost stages I, II, III, and IV are connected. The boosting stage I includes a diode element 401 and a capacitor group 406. Further, the boosting stage II is composed of a diode element 402 and a capacitor group 407, and the boosting stage III is composed of a diode element 403 and a capacitor group 408. Further, the boosting stage IV includes a diode element 404 and a capacitor group 409.
In each boosting stage, the capacitor group is connected to the cathode of the diode element. Connection nodes between the diode element and the capacitor group are denoted as N41, N42, N43, and N44, respectively.

Further, the charge pump circuit shown in FIG. 1 includes an output diode element 405. The diode elements 401, 402, 403, 404, and 405 are constituted by diode-connected MOS transistors. The capacitor group 406 includes a charge transfer capacitor (charge transfer capacitor) 406a and parasitic capacitances 406b and 406c.
Similarly, the capacitor group 407 includes a charge transfer capacitor 407a and parasitic capacitors 407b and 407c, and the capacitor group 408 includes a charge transfer capacitor 408a and parasitic capacitors 408b and 408c. The capacitor group 409 includes a charge transfer capacitor 409a and parasitic capacitances 409b and 409c. The capacitor groups 406 to 409 will be described later.

The diode elements 401 to 404 and the output diode element 405 of the boosting stages I to IV are connected in series. The capacitor groups 406 and 408 of the boost stage I and boost stage III (odd number stage) are connected in series with each other. Capacitor groups 407 and 409 of boost stage II and boost stage IV (even number stages) are connected in series with each other.
Each of the diode elements 402 to 405 transfers the charge accumulated in the charge transfer capacitor of the previous boosting stage to the charge transfer capacitor of the self boosting stage. Further, the diode element 401 transfers the electric charge according to the input signal VIN to the electric charge transfer capacitor 406a of the boosting stage I.

The charge pump circuit according to the first embodiment includes a clock signal generation circuit 400. The clock signal generation circuit 400 generates clock signals Φ1 and Φ2. As such a clock signal generation circuit 400, a circuit that generates a general clock signal is used. The clock signal Φ1 is input to a terminal not connected to the diode element 401 of the capacitor group 406 of the boosting stage I. The clock signal Φ2 is input to a terminal not connected to the diode element 402 of the capacitor group 407 of the boosting stage II.
The clock signal Φ1 and the clock signal Φ2 are signals with opposite phases whose phases are inverted from each other. The output of the boosting stage IV is output as an output signal VOUT from the output terminal via the diode element 405. The clock Φ2 can also be input to the input terminal VIN.

(2) Capacitor Group and MOS Transistor FIG. 2 is a diagram for explaining the boosting stage shown in FIG. 1, and is a cross-sectional view of each capacitor group and a diode element. The capacitor groups 406 to 409 include an independent N-well (denoted as N-Well in the figure) 302 formed on the P-type semiconductor substrate 301, a first poly-Si layer 303 formed on the N-well 302, A second poly-Si layer 304 formed on the first poly-Si layer 303 and a metal conductive layer (hereinafter simply referred to as a metal layer) 305 formed on the second poly-Si layer 304 are provided. The first poly-Si layer 303 is a lower electrode of a charge transfer capacitor (for example, the charge transfer capacitor 406a), and the second poly-Si layer 304 is an upper electrode of the charge transfer capacitor.

The second poly-Si layer 304 is connected to the previous boosting stage. The first poly-Si layer 303 is connected to the subsequent boosting stage. Further, the metal layer 305 disposed above the N-well 302 and the charge transfer capacitor 406a is connected to one of signal lines for supplying the clock signal Φ1 or the clock signal Φ2.
In the configuration shown in FIG. 2, capacitors formed by the first poly-Si layer 303 and the second poly-Si layer 304 become charge transfer capacitors 406a, 407a, 408a, 409a. Further, the capacitance generated between the N-well 302 and the first poly-Si layer 303 becomes parasitic capacitances 406b, 407b, 408b, and 409b. The capacitance generated between the second poly-Si layer 304 and the metal layer 305 becomes parasitic capacitances 406c, 407c, 408c, and 409c.

In the first embodiment, the capacitance of the charge transfer capacitors 406a, 407a, 408a, and 409a is C, the capacitance of the parasitic capacitors 406b, 407b, 408b, and 409b is Cs1, and the capacitance of the parasitic capacitors 406c, 407c, 408c, and 409c is Cs2. And
In the capacitor group 406, the clock signal Φ1 is supplied to the terminals of the parasitic capacitors 406b and 406c that are not connected to the charge transfer capacitor 406a. Similarly, in the capacitor group 408, the clock signal Φ1 is supplied to the terminals of the parasitic capacitors 408b and 408c that are not connected to the charge transfer capacitor 408a. In the even-numbered boosting stage, the clock signal Φ2 is supplied to a terminal not connected to the charge transfer capacitor 407a of the parasitic capacitors 407b and 407c and a terminal not connected to the charge transfer capacitor 407a of the parasitic capacitors 409b and 409c. Has been.

  The clock signal Φ1 is supplied to the N-well 302 and the metal layer 305 of the boosting stages I and III, and the clock signal Φ2 is supplied to the N-well 302 and the metal layer 305 of the boosting stages II and IV. To IV, a parasitic capacitance 406b formed by the N-well 302 and the first poly-Si layer 303, a charge transfer capacitor 406a formed by the first poly-Si layer 303 and the second poly-Si layer 304, The parasitic capacitance 406c formed by the two poly Si layer 304 and the metal layer 305 can be driven by the same clock signal.

The MOS transistor 311 shown in FIG. 2 is diode-connected to constitute the diode element (for example, the diode element 401) shown in FIG. The MOS transistor 311 is formed on an N-well 310 independent of the N-well 302, and is configured as a P-type MOS transistor having a conductivity type polarity different from that of the N-well 310.
The cathode of the MOS transistor 311 is connected to one of the first poly-Si layer 303 and the second poly-Si layer 304 of the charge transfer capacitor included in the next boosting stage. Charge is input from the anode of the MOS transistor 311, and the input charge is output from the cathode to one of the first poly-Si layer 303 and the second poly-Si layer 304 included in the other next boosting stage. The By thus connecting the MOS transistor 311 and the charge transfer capacitor, the boosting stage is connected to a plurality of stages.

(3) Operation of Charge Pump Circuit The charge pump circuit according to the first embodiment is similar to the Cockcroft-Walton type charge pump circuit shown in FIG. 5 when the clock signal Φ1 is Low and the clock signal Φ2 is High. As a result, charges are injected into the charge transfer capacitor (hereinafter referred to as accompanying the node N41) 406a and the parasitic capacitors 406c and 408b through the diode element 401. Further, charges are distributed through the diode element 403 from the charge transfer capacitor 407a and the parasitic capacitors 407c and 409b associated with the node N42 to the charge transfer capacitor 408a and the parasitic capacitor 408c associated with the node N43.

  On the other hand, when the clock signal Φ1 is high and the clock signal Φ2 is Low, the charge transfer capacitor 406a and the parasitic capacitors 406c and 408b associated with the node N41 are changed to the charge transfer capacitor 407a and the parasitic capacitors 407c and 409b associated with the node N42. In addition, charge is distributed through the diode element 402. Further, charges are distributed through the diode element 404 from the charge transfer capacitor 408a and parasitic capacitance 408c associated with the node N43 to the charge transfer capacitor 409a and parasitic capacitance 409c associated with the node N44.

As described above, by operating the charge pump circuit according to the anti-phase clock signals Φ1 and Φ2, charges are sequentially transferred between the capacitor groups 406, 407, 408, and 409, and the voltage applied to the input terminal VIN is boosted. Is done. The boosted voltage is output to the outside as VOUT.
As described above, in the first embodiment, the clock signal Φ1 is supplied to one terminal of the parasitic capacitors 406b and 406c and the parasitic capacitors 408b and 408c. The clock signal Φ2 is supplied to one terminal of the parasitic capacitors 407b and 407c and the parasitic capacitors 409b and 409c. For this reason, the charge of each parasitic capacitor is charged and discharged at the same timing as the charge of the charge transfer capacitor attached to the same node. Therefore, in each boosting stage, the charge stored in the charge transfer capacitor of the preceding boosting stage can be transferred to the self boosting stage without loss. As a result, the first embodiment can efficiently generate a desired high voltage.

  In the first embodiment described above, a charge pump circuit is configured using a general Cockcroft-Walton type charge pump circuit. The Cockcroft-Walton type charge pump circuit pays attention to the fact that the potential difference applied between the electrodes of the charge transfer capacitor of each boosting stage is a constant value determined by the clock amplitude regardless of the number of boosting stages. This solves the drawback of the Cockcroft-Walton type charge pump circuit in which charge loss due to parasitic capacitance increases.

  According to the first embodiment, even if the number of boosting stages is further increased in order to generate a high voltage, the voltage applied to the charge transfer capacitor in the subsequent boosting stage does not increase compared to the previous stage. Therefore, it is not necessary to use a capacitor with a particularly high breakdown voltage in the subsequent boosting stage. Using a standard process having no special high breakdown voltage element, the boosted potential can be reduced due to the parasitic capacitance that has become a problem in the conventional circuit. Can be suppressed.

Furthermore, in the first embodiment, two poly-Si layers are used for the electrode layer of the charge transfer capacitor. However, Embodiment 1 is not limited to such a configuration, and one of the two electrode layers is a poly-Si layer, the other is a metal layer, or both of the two electrode layers are metal layers. Good. Even in this case, the same effect as that of the first embodiment described above can be obtained by charging and discharging the parasitic capacitance by applying the same clock signal as that of the charge transfer capacitor.
As described above, the first embodiment is not limited to the configuration in which four boosting stages are provided, and any number of boosting stages can be provided.

(Embodiment 2)
Next, the charge pump circuit according to the second embodiment of the present invention will be described.
(1) Configuration of Charge Pump Circuit FIG. 3 is a diagram for explaining the entire charge pump circuit of the second embodiment. The charge pump circuit shown in FIG. 3 is an embodiment in which the present invention is applied to a Dickson type charge pump circuit.
The illustrated charge pump circuit includes four boosting stages I, II, III, and IV. The boosting stage I includes a diode element 601, a charge transfer capacitor 606 having one end connected to the diode element 601, and a parasitic capacitance 610. The boost stage II includes a diode element 602, a charge transfer capacitor 607 having one end connected to the diode element 602, and a parasitic capacitance 611. The boost stage III has one end connected to the diode element 603 and the diode element 603. A charge transfer capacitor 608 and a parasitic capacitance 612 are included. Further, the boosting stage IV includes a diode element 604, a charge transfer capacitor 609 having one end connected to the diode element 604, and a parasitic capacitance 613.

The input signal VIN is input to the diode element 601 of the boosting stage I. The diode elements 601, 602, 603, and 604 are connected in series, and the diode element 604 is further connected in series with the diode element 605 connected to the output terminal. An output signal VOUT is output from the diode element 605 to the outside. The capacitances of the charge transfer capacitors 606, 607, 608, and 609 are C, and the capacitances of the parasitic capacitors 610, 611, 612, and 613 are Cs3.
In each boosting stage, the charge transfer capacitor is connected to the cathode of the diode element. Connection nodes between the charge transfer capacitor and the diode element are denoted as N61, N62, N63, and N64, respectively.

  The charge pump circuit according to the second embodiment includes a clock signal generation circuit 600. The clock signal generation circuit 600 generates a clock signal Φ1 and a clock signal Φ2 that are in opposite phase relation to each other. The clock signal Φ 1 is supplied to one terminal of the charge transfer capacitor 606 and the parasitic capacitance 610 in the boost stage I. The clock signal Φ1 is also supplied to one terminal of the charge transfer capacitor 608 and the parasitic capacitance 612 of the boost stage III. The clock signal Φ2 is supplied to one terminal of the charge transfer capacitor 607 and the parasitic capacitance 611 in the boosting stage II. The clock signal Φ2 is also supplied to one terminal of the charge transfer capacitor 609 and the parasitic capacitance 613 of the boosting stage IV.

(2) Charge Transfer Capacitor and Parasitic Capacitance FIG. 4 is a diagram for explaining the charge transfer capacitor and the parasitic capacitance of each boosting stage shown in FIG. FIG. The charge transfer capacitor and the parasitic capacitance of the second embodiment are formed in the second metal layer 502 that is the lower electrode of the charge transfer capacitor, the third metal layer 503 that is the upper electrode of the charge transfer capacitor, and the lower layer of the second metal layer. The formed first metal layer 501 is provided.
The third metal layer 503 is supplied with the clock signal Φ1 or the clock signal Φ2. In the charge transfer capacitor, the second metal layer 502 is connected to the cathode terminal of the diode element. The first metal layer 501 is supplied with the same clock signal as the clock signal Φ1 or the clock signal Φ2 supplied from the signal line connected to the third metal layer.

(3) Operation of Charge Pump Circuit Next, the operation of the charge pump circuit shown in FIG. 3 will be described. When the clock signal .PHI.1 is Low and the clock signal .PHI.2 is High, charges are injected through the diode element 601 into the charge transfer capacitor 606 and the parasitic capacitance 610 associated with the node N61 by the input signal VIN. Further, charges are distributed via the diode element 603 from the charge transfer capacitor 607 and the parasitic capacitance 611 associated with the node N62 to the load transfer capacitor 608 and the parasitic capacitance 612 associated with the node N63.

  On the other hand, when the clock signal Φ1 is High and the clock signal Φ2 is Low, the charge transfer capacitor 606 and the parasitic capacitance 610 associated with the node N61 are changed from the charge transfer capacitor 607 and the parasitic capacitance 611 associated with the node N62 to the diode element. Charge is distributed via 602. Further, charges are distributed through the diode element 604 from the charge transfer capacitor 608 and parasitic capacitance 612 associated with the node N63 to the charge transfer capacitor 609 and parasitic capacitance 613 associated with the node N64.

  As described above, by operating the charge pump circuit according to the clock signals Φ1 and Φ2 that are in opposite phase to each other, the charge transfer capacitor of each boost stage and the charge of the parasitic capacitance are sequentially transferred to the next boost stage. Is done. As a result of the charge transfer, charges are accumulated in the charge transfer capacitor C and the parasitic capacitance Cs3 in each boosting stage to a potential determined by the voltage applied to the input terminal VIN and the amplitude voltages of the clocks Φ1 and Φ2, thereby obtaining a boosted potential. The boosted voltage is output to the outside as VOUT. The clock Φ2 can also be input to the input terminal VIN.

The charge pump circuit according to the second embodiment described above incorporates the parasitic capacitance associated with the charge transfer capacitor of each boosting stage as a part of the charge transfer capacitor. Therefore, compared with the conventional Dickson type charge pump circuit shown in FIG. 6, it is advantageous in that the charge loss of the charge transfer capacitor due to the parasitic capacitance associated with the charge transfer capacitor can be eliminated.
In other words, as shown in FIG. 4, the charge transfer capacitor according to the second embodiment is sandwiched between the first metal layer 501 and the third metal layer 503 above and below the second metal layer 502 that is an electrode for holding charges. Composed.

  With this configuration, in the second embodiment, the parasitic capacitance Cs3 generated between the second metal layer 502 and the first metal layer 501 can be regarded as a part of the capacitance C of the charge transfer capacitor. Therefore, the second embodiment can eliminate the loss due to the parasitic capacitance of the charge accumulated in the charge transfer capacitor. For this reason, in Embodiment 2, even when the capacitance value per unit area of the parasitic capacitance is small, an increase in charge loss due to the parasitic capacitance can be suppressed.

  The second embodiment is not limited to the configuration described above. For example, in the second embodiment, as illustrated in FIG. 4, the first metal layer 501 and the second metal layer 502 are used for the electrodes of the charge transfer capacitor. However, it is also possible to use a conductive layer (for example, a poly-Si layer) of a member other than metal for one or both of the electrodes of the charge transfer capacitor of the second embodiment. Even in such a case, the second embodiment can obtain the same effects as those described above.

  The present invention described above is configured by connecting boosting stages to a plurality of stages, and is low in charge loss regardless of which charge pump circuit is applied as long as it is a charge pump circuit capable of generating parasitic capacitance in each boosting stage. A charge pump circuit can be provided. In particular, when applied to a Cockcroft-Walton type charge pump circuit, it is possible to apply a charge pump circuit that does not require the use of a high withstand voltage capacitor regardless of the number of boosting stages.

400, 600 Clock signal generation circuit 401, 402, 403, 404, 405, 601, 602, 603, 604, 605 Diode element 301 P-type semiconductor substrate 302, 310 N-well 303 First poly-Si layer 304 Second poly-Si Layer 305, 501, 502, 503 Metal layer 406, 407, 408, 409 Capacitor group 406a, 407a, 408a, 409a, 606, 607, 608, 609 Charge transfer capacitors 406b, 406c, 407b, 407c, 408b, 408c, 409b, 409c, 610, 611, 612, 613 Parasitic capacitance 311 MOS transistor

Claims (8)

A charge pump circuit configured by connecting a plurality of boosting stages,
Each of the boosting stages includes
A capacitor composed of a first electrode and a second electrode formed on the first electrode;
A diode element for transferring an input signal or a charge accumulated in the capacitor in the previous stage to the capacitor in the self-boosting stage;
A clock signal supply means for supplying a clock signal for controlling the timing of charging and discharging the capacitor to the capacitor;
Including
At least one of the first electrode and the second electrode of the capacitor is disposed to face the conductive layer;
The charge pump circuit, wherein the clock signal supply means supplies the clock signal supplied to the capacitor to the conductive layer together with the capacitor. The clock signal supply means includes
Of the boosting stages connected to a plurality of stages, the first clock signal is supplied to the capacitor and the conductive layer of the first boosting stage, and the second boosting stage connected to the first boosting stage is connected. Supplying the capacitor and the conductive layer with a second clock signal that is 180 degrees out of phase with the first clock signal;
The charge pump circuit according to claim 1, wherein the capacitor of the second boost stage is charged at a timing when the capacitor of the first boost stage is discharged.   3. The charge pump circuit according to claim 1, wherein the first electrode and the second electrode of the capacitor are conductive layers including at least one of polysilicon and metal.   The conductive layer is at least one of a first well layer formed on a substrate below the first electrode, and a conductive layer containing at least one of polysilicon or metal formed above the second electrode. The charge pump circuit according to any one of claims 1 to 3, wherein the charge pump circuit is characterized in that:   5. The charge pump circuit according to claim 1, wherein the plurality of boosting stages connected to the plurality of stages constitute a Cockcroft-Walton type circuit. 6.   5. The charge pump circuit according to claim 1, wherein the plurality of boosting stages connected to the plurality of stages constitute a Dickson type circuit. 6. The capacitor is formed on a first well formed under the first electrode,
The diode element is
A MOS transistor element formed on a second well formed independently of the first well and having a conductivity type different from that of the second well;
The MOS transistor is connected to the drain terminal, the gate terminal, and the second well of the MOS transistor, and functions as a diode element.
A cathode is connected to one of the first electrode and the second electrode of the capacitor included in the self-boosting stage;
An electric charge is input from the anode, and the input electric charge is output from the cathode to one of the first electrode and the second electrode included in the self-boosting stage,
The boosting stage includes
The cathode of each boosting stage is connected to a plurality of stages by being connected to the anode of the diode element of the next boosting stage,
In the boosting stage connected to a plurality of stages,
The first clock signal is supplied to a capacitor of the first boosting stage;
The second clock signal is supplied to a capacitor of the second boosting stage;
The capacitor of the boosting stage after the third stage is connected to the output of the boosting stage of the preceding stage,
The first clock signal is supplied to the first well of the odd-numbered boosting stage, and the second clock signal is supplied to the first well of the even-numbered boosting stage. In each of the above, the parasitic capacitor formed by the first well and the first electrode, and the capacitor formed by the first electrode and the second electrode are driven by the same clock signal. The charge pump circuit according to claim 2.   Among the boosting stages connected to a plurality of stages, in the odd-numbered boosting stages, the first clock signal is supplied to the conductive layer formed above the second electrode, and the even-numbered stages In the boosting stage, the second clock signal is supplied to the conductive layer formed above the second electrode, whereby each of the boosting stages is formed by the first electrode and the second electrode. 8. The capacitor according to claim 7, wherein the capacitor and the parasitic capacitor formed by the conductive layer formed above the second electrode and the second electrode are driven by the same clock signal. Charge pump circuit.

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