JP2011087211A - Demodulation device and method, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve demodulation at any of a plurality of different communication rates that a communication partner determines, and to suppress an increase in a circuit scale. <P>SOLUTION: An A/D conversion unit 103 converts a signal output from an analog detecting circuit 12 into a digital signal. Enable signal generation units 104a to 104N generate enable signals respectively based upon a signal data1. A series/parallel conversion unit 105 outputs data corresponding to the plurality of communication rates respectively to one signal line, and outputs the enable signals in timing to the output of the data. A demodulation arithmetic processing unit 106 operates the data supplied as a signal data4 by the communication rates based upon signals en4a to en4N. A selection unit 107 selects and outputs data corresponding to an enable signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a demodulating apparatus and method, and an electronic apparatus, and in particular, can control a communication rate determined by a communication partner at any of a plurality of different communication rates and suppress an increase in circuit scale. The present invention relates to a demodulation device and method, and an electronic apparatus.

  In recent years, non-contact IC cards (for example, FeliCa (registered trademark)) have become widespread. Various systems have been proposed as demodulation systems in non-contact IC card communications (see, for example, Patent Document 1).

  According to the technique of Patent Document 1, an analog signal obtained by envelope detection or synchronous detection of a signal received by an antenna is sampled by an A / D converter at 13.56 MHz and converted into a digital signal. To do. The down sampler outputs a sample signal obtained by down-sampling the digital signal at a communication rate of 212 kHz or 424 kHz, and the demodulation arithmetic processor uses this sample signal to perform timing synchronization, demodulation processing such as bit decoding, output selection, etc. Is demodulated.

JP2009-1118070

  Incidentally, in the FeliCa communication method described in ISO / IEC18092, a plurality of communication rates are defined. For example, when it is assumed that a non-contact IC card is mounted on a mobile phone or the like, the communication rate by an application is determined later, so that communication at a plurality of communication rates is required.

  Further, when a contactless IC card mounted on a mobile phone or the like communicates with a reader / writer, communication is started from the reader / writer according to the FeliCa standard. Therefore, for the non-contact IC card, the communication rate of the received signal at the start of communication is unknown. For this reason, in the FeliCa communication method, it is necessary to be able to demodulate a signal whose communication rate is unknown.

  However, Patent Document 1 does not show a circuit configuration in the case of handling the plurality of communication rates. Also, if a plurality of communication rates are supported, the analog unit remains the same, and the digital unit simultaneously demodulates all communication rates that are reception candidates, and based on the demodulation results for each rate. The configuration must be selected.

  That is, in the case of supporting a plurality of communication rates, as a configuration of the digital unit, for example, N downsamplers corresponding to N communication rates and N demodulators are arranged in parallel and output by a selector. Need to be selected. In this case, the circuit scale naturally increases by the number of communication rates.

  As described above, the conventional technique has a problem that the circuit scale is increased by the number of communication rates in order to appropriately demodulate the received signal in correspondence with a plurality of communication rates.

  The present invention has been made in view of such a situation, and is a communication rate determined by a communication partner, which can be demodulated at any of a plurality of different communication rates, and suppresses an increase in circuit scale. Is to be able to.

  According to a first aspect of the present invention, there is provided enable generation means for generating enables corresponding to a plurality of predetermined communication rates, respectively, and the plurality of enables corresponding to the generated plurality of communication rates. Each of the data corresponding to the communication rate, and the extracted data output means for outputting each of the extracted data corresponding to each of the enable corresponding to a plurality of communication rates, and outputting from the extracted data output means A demodulating device comprising: an arithmetic processing unit that performs an operation on each of the plurality of data corresponding to the plurality of communication rates for each of the plurality of communication rates and outputs each operation result on one signal line. is there.

  Analog detection means for receiving and analog-detecting a transmission signal modulated by a predetermined modulation method, and sampling the signal output from the analog detection means based on the carrier rate of the transmission signal into a digital signal A / D conversion means for converting, and the enable generation means generates enables corresponding to the plurality of communication rates in synchronization with rising or falling timings of the signal output from the analog detection means, respectively. The extracted data output means can extract data corresponding to the plurality of communication rates from the signal output from the A / D conversion means based on each of the enables.

  In the transmission signal, data to be received by the demodulation device is transmitted as a frame of a predetermined format, the data of the frame is encoded at a plurality of different symbol rates, and the arithmetic processing means The same calculation can be performed on data corresponding to the communication rate.

  The extracted data output means, when there are a plurality of enables corresponding to a plurality of communication rates generated by the enable generation means at the same time, the data to be output and the enable according to a preset priority order Can be selected.

  The priority may be set higher in order from the shortest symbol length when the data is encoded.

  The priority order may be changed sequentially.

  The enable generation unit may include a timing signal generation unit that generates a timing signal corresponding to each of the plurality of communication rates.

  The arithmetic processing means holds the data output from the extracted data output means by a register corresponding to each of the communication rates, and corresponds to the plurality of communication rates with respect to the data held in the register. Based on each of the enables, the calculation can be performed by one calculator.

  Selection means for specifying a communication rate of data modulated and transmitted to the transmission signal and selecting data of the specified communication rate based on a calculation result for each of the plurality of communication rates by the calculation processing means; Can be provided.

  In the first aspect of the present invention, the enable generation means generates enables corresponding to a plurality of predetermined communication rates, respectively, and the extracted data output means sets the enable corresponding to the generated plurality of communication rates. Based on each, extract data corresponding to the plurality of communication rates, respectively, and output each of the extracted data corresponding to each of the enable corresponding to the plurality of communication rates, the arithmetic processing means, It is possible to perform calculation for each of the plurality of communication rates for each of the output data corresponding to the plurality of communication rates, and output each calculation result on one signal line.

  In the first aspect of the present invention, enables corresponding to a plurality of predetermined communication rates are respectively generated, and the plurality of communication rates are based on each of the enables corresponding to the generated plurality of communication rates. Each of the extracted data is output in correspondence with each of the enable corresponding to a plurality of communication rates, and each of the data corresponding to the output of the plurality of communication rates is extracted. On the other hand, calculation is performed for each of the plurality of communication rates, and each calculation result is output on one signal line.

  According to a second aspect of the present invention, analog detection means for receiving and analog-detecting a transmission signal modulated by a predetermined modulation method, and converting the signal output from the analog detection means to a carrier rate of the transmission signal. A / D conversion means for sampling into a digital signal by sampling based on, and an enable corresponding to a plurality of predetermined communication rates in synchronization with the rising or falling timing of the signal output from the analog detection means And generating the plurality of communication rates based on each of the enable corresponding to the plurality of communication rates generated by the enable generation unit from the signal generated from the enable generation unit and the signal output from the A / D conversion unit. Each corresponding data is extracted, and each of the extracted data is applied to a plurality of communication rates. The extracted data output means for outputting corresponding to each of the enable, and the data corresponding to the plurality of communication rates output from the extracted data output means for each of the plurality of communication rates. Communication means for outputting each calculation result on one signal line, and communication of data transmitted after being modulated to the transmission signal based on the calculation results for each of the plurality of communication rates by the calculation processing means. An electronic device that includes a demodulator that includes a selection unit that specifies a rate and selects data of a specified communication rate, and demodulates a transmission signal transmitted from another device using the demodulator.

  In the second aspect of the present invention, a transmission signal modulated by a predetermined modulation method is received and subjected to analog detection, and the output signal is sampled based on the carrier rate of the transmission signal, thereby obtaining a digital signal. The outputs corresponding to a plurality of predetermined communication rates are generated in synchronization with the rising or falling timing of the output signal, and the corresponding signals correspond to the plurality of communication rates. Based on each of the enables, data corresponding to the plurality of communication rates is extracted, respectively, and each of the extracted data is output and output corresponding to each of the enables corresponding to the plurality of communication rates. For each of the data corresponding to the plurality of communication rates, calculation is performed for each of the plurality of communication rates. And each calculation result is output on one signal line, and based on the calculation results for each of the plurality of communication rates, the communication rate of the data modulated and transmitted to the transmission signal is specified and specified. Communication rate data is selected.

  According to the present invention, it is possible to demodulate at any of a plurality of different communication rates at a communication rate determined by a communication partner, and to suppress an increase in circuit scale.

It is a block diagram which shows the structural example of the conventional demodulation function part. It is a block diagram which shows another structural example of the conventional demodulation function part. It is a block diagram which shows the structural example of the demodulation function part which concerns on one embodiment of this invention. It is a block diagram which shows the detailed structural example of an enable production | generation part. It is a figure explaining the waveform of the input signal to an enable production | generation part, and the output signal from an enable production | generation part. It is a block diagram which shows the detailed structural example of the parallel / serial conversion part of FIG. It is a timing chart explaining operation | movement of a parallel / serial conversion part. It is a block diagram which shows the example of a structure at the time of assuming that the structure of a demodulation arithmetic processing part arranges an arithmetic unit in parallel. It is a timing chart for demonstrating operation | movement of the demodulation arithmetic processing part at the time of setting it as the structure shown by FIG. It is a block diagram which shows the detailed structural example of the demodulation arithmetic processing part of FIG. It is a timing chart for demonstrating operation | movement of the demodulation arithmetic processing part shown by FIG. It is a flowchart explaining a demodulation process.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, the demodulation processing of a conventional non-contact IC card will be described. FIG. 1 is a block diagram showing a configuration example of a demodulation function unit mounted on a conventional non-contact IC card or a reader / writer corresponding to the non-contact IC card. The demodulation function unit 10 shown in the figure is an electronic device used as, for example, a non-contact IC card or a reader / writer, and is mounted on a mobile phone or the like. Here, description will be made assuming that the demodulation function unit 10 is mounted on a non-contact IC card.

  For example, the demodulating function unit 10 is configured so that a reader / writer as a communication partner receives and demodulates a transmission signal transmitted by ASK-modulating a 13.56 MHz carrier wave signal. Data transmitted from the reader / writer to the non-contact IC card by the transmission signal is encoded by the Manchester encoding method. Therefore, the plurality of communication rates described above can be realized by changing the Manchester encoded symbol rate.

  The demodulation function unit 10 in FIG. 1 includes an antenna 11, an analog detection circuit 12, an A / D conversion unit 13, a downsampler 14, and a demodulation calculation processing unit 15.

  The analog detection circuit 12 supplies an analog signal obtained by performing envelope detection or synchronous detection on the signal received by the antenna 11 to the A / D conversion unit 13.

  The A / D conversion unit 13 samples the analog signal output from the analog detection circuit 12 at, for example, 13.56 MHz, converts the analog signal into a digital signal, and supplies the digital signal to the downsampler 14.

  The downsampler 14 outputs a downsampled signal obtained by downsampling the digital signal output from the A / D converter 13 at, for example, a communication rate of 212 kHz.

  The demodulation calculation processing unit 15 performs demodulation processing such as frame synchronization and bit decoding based on the downsample signal output from the downsampler 14. Then, based on the processing result data output from the demodulation calculation processing unit 15, transaction processing in the non-contact IC card is executed.

  By the way, the communication rate of the signal transmitted / received between the non-contact IC card and the reader / writer can use a plurality of communication rates. For example, in the FeliCa communication method described in ISO / IEC18092, communication rates such as a communication rate of 212 kHz and a communication rate of 424 kHz are defined. This is because an appropriate communication rate can be adopted according to the contents of application (transaction) processing executed in the non-contact IC card or the reader / writer.

  The plurality of communication rates described above can be realized by changing the Manchester encoded symbol rate.

  Further, when a contactless IC card mounted on a mobile phone or the like communicates with a reader / writer, communication is started from the reader / writer according to the FeliCa standard. Therefore, for the non-contact IC card, the communication rate of the received signal at the start of communication is unknown. For this reason, in the FeliCa communication method, it is necessary to be able to demodulate a signal whose communication rate is unknown.

  Furthermore, since the communication rate employed by the reader / writer is unknown at the beginning of communication for a non-contact IC card, it is required to be able to communicate at any communication rate.

  A non-contact IC card equipped with the demodulation function unit 10 shown in FIG. 1 can demodulate a signal at one communication rate (for example, a communication rate of 212 kHz) and communicate only at the communication rate. Therefore, it is impossible to realize a contactless IC card that can demodulate a signal whose communication rate is unknown and can communicate at any communication rate.

  For example, if the demodulation function unit is configured as shown in FIG. 2, a contactless IC card that can demodulate a signal whose communication rate is unknown and can communicate at any communication rate can be realized. .

  FIG. 2 is a block diagram illustrating another configuration example of the demodulation function unit. In this example, the demodulation function unit 20 is configured so that communication is possible at each of N different communication rates. The demodulation function unit 20 shown in the figure is configured to include an antenna 21, an analog detection circuit 22, and an A / D conversion unit 23 similar to the case of the demodulation function unit 10 of FIG.

  In the demodulation function unit 20 of FIG. 2, unlike the configuration of the demodulation function unit 10 of FIG. 1, a plurality of downsamplers and demodulation calculation processing units are provided. That is, the demodulating function unit 20 includes a down sampler 24a to a down sampler 24N, and a demodulation calculation processing unit 25a to a demodulation calculation processing unit 25N.

  The down sampler 24a outputs a down sample signal obtained by down sampling the digital signal output from the A / D conversion unit 23 at, for example, a communication rate of 212 kHz. The demodulation arithmetic processing unit 25a is configured to perform demodulation processing such as frame synchronization and bit decoding based on the downsample signal output from the downsampler 24a.

  The downsampler 24b outputs a downsample signal obtained by downsampling the digital signal output from the A / D converter 23 at, for example, a communication rate of 424 kHz. The demodulation calculation processing unit 25b performs demodulation processing such as frame synchronization and bit decoding based on the downsample signal output from the downsampler 24b.

  Similarly, the downsampler 24c... Downsampler 24N outputs a downsampled signal obtained by downsampling the digital signal output from the A / D converter 23 at different communication rates. Then, the demodulation calculation processing unit 25c... The demodulation calculation processing unit 25N performs demodulation processing such as frame synchronization and bit decoding based on the downsample signal output from the downsampler 24c. Has been made.

  2 is different from the configuration of the demodulation function unit 10 in FIG. 1 in that a selection unit 26 is provided. That is, the selection unit 26 selects the processing result data corresponding to the most probable communication rate based on the result of frame synchronization in the processing result data output from the demodulation arithmetic processing unit 25a... Is selected and output.

  If the demodulation function unit is configured as shown in FIG. 2, for example, a contactless IC card that can demodulate a signal whose communication rate is unknown and can communicate at any communication rate can be realized. . However, in this case, the circuit scale naturally increases by the number of communication rates. Therefore, by configuring as shown in FIG. 2, the demodulation function unit that is installed in a small device and is assumed to require power-saving operation to solve the above-described plurality of communication rate problems. This is not desirable as a configuration.

  Therefore, the present invention makes it possible to solve the above-described problems of the plurality of communication rates while suppressing an increase in circuit scale as much as possible.

  FIG. 3 is a block diagram illustrating a configuration example of a demodulation function unit according to an embodiment of the present invention. The demodulation function unit 100 shown in the figure is an electronic device used as, for example, a non-contact IC card or a reader / writer, and is mounted on a mobile phone or the like. Here, description will be made assuming that the demodulation function unit 100 is mounted on a non-contact IC card.

  The demodulation function unit 100 shown in the figure is configured to be able to support a plurality of communication rates such as a communication rate of 212 kbps, a communication rate of 424 kbps,. The plurality of communication rates correspond to the communication rates of the FeliCa communication system defined by ISO / IEC 19802, for example. This is because it is possible to adopt an appropriate communication rate with the reader / writer according to the contents of application (transaction) processing executed in the contactless IC card on which the demodulation function unit 100 is mounted.

  For example, the demodulating function unit 100 is configured to receive and demodulate a transmission signal transmitted by a reader / writer, which is a communication partner, by ASK-modulating a 13.56 MHz carrier wave signal. Data transmitted from the reader / writer to the non-contact IC card by the transmission signal is encoded by the Manchester encoding method. Therefore, the plurality of communication rates described above can be realized by changing the Manchester encoded symbol rate.

  Note that the communication rate described above is an integer multiple of the carrier wave period of the signal transmitted from the reader / writer.

  3 includes an antenna 101, an analog detection circuit 102, an A / D conversion unit 103, enable generation units 104a to 104N, a parallel / serial conversion unit 105, a demodulation calculation processing unit 106, and a selection unit. 107. The antenna 101, analog detection circuit 102, and A / D conversion unit 103 of the demodulation function unit 100 are the same as the antenna 11, analog detection circuit 12, and A / D conversion unit 13 of the conventional demodulation function unit 10 (FIG. 1). Is possible.

  The analog detection circuit 102 supplies an analog signal obtained by envelope detection or synchronous detection of the signal received by the antenna 101 to the A / D conversion unit 103.

  The A / D conversion unit 103 samples the analog signal output from the analog detection circuit 102 at, for example, 13.56 MHz, converts the analog signal into a digital signal, and supplies the digital signal to the enable generation unit 104a to the enable generation unit 104N. The sampling rate by the A / D conversion unit 103 usually corresponds to the frequency of the carrier wave of the signal transmitted from the reader / writer. A digital signal output from the A / D conversion unit 103 is referred to as signal data1.

  The enable generation unit 104a to the enable generation unit 104N generate an enable to be supplied to the parallel / serial conversion unit 105 based on the signal data1 output from the A / D conversion unit 103, respectively. The enable generation unit 104a to the enable generation unit 104N are provided as enable generation units corresponding to each of a plurality of communication rates capable of communication in a non-contact IC card or reader / writer in which the demodulation function unit 100 is mounted. In this example, the contactless IC card on which the demodulation function unit 100 is mounted is configured to be able to communicate at N different communication rates. Note that the enable generation unit 104a to the enable generation unit 104N are collectively referred to as the enable generation unit 104 when it is not necessary to distinguish them individually.

  The enable generation unit 104a to the enable generation unit 104N output the signals en2a to en2N, which are the generated enable signals, respectively, and output the signal data1 as it is as the signal data2a to signal data2N.

  FIG. 4 is a block diagram illustrating a detailed configuration example of the enable generation unit 104. For the sake of convenience, only the enable generation unit 104a, the enable generation unit 104b, and the enable generation unit 104c among the enable generation units 104a to 104N are illustrated in FIG.

  The enable generation unit 104a shown in the figure is an enable generation unit corresponding to a communication rate of 212 kbps (212 kHz) among the plurality of communication rates described above. The enable generation unit 104b and the enable generation unit 104c are enable generation units corresponding to a communication rate of 424 kbps (424 kHz) and a communication rate of 847 kbps (847 kHz), respectively.

  Each of the enable generation units 104a to 104c includes a timing generation unit 108a to a timing generation unit 108c and an enable output unit 109a to an enable output unit 109c.

  The timing generation unit 108a to the timing generation unit 108c detect the rising and falling of the signal data1, respectively, indicate the rising and falling timings, generate timing signals corresponding to the respective communication rates, and enable output units 109a to enable output unit 109c. That is, the timing generation unit 108a to the timing generation unit 108c generate timing signals by counting clocks corresponding to 212 kHz, 424 kHz, and 847 kHz, respectively, and supply them to the enable output units 109a to 109c.

  The enable output unit 109a to the enable output unit 109c generate a pulse having a voltage level of “H” after ¼ cycle from the rising and falling of the signal data1, respectively, and the digital signal including the pulse is transmitted as the signal en2a to Output as en2c.

  FIG. 5 is a diagram illustrating waveforms of an input signal to the enable generation unit 104 and an output signal from the enable generation unit 104. Here, the waveforms of the input signal to the enable generation unit 104a and the output signal from the enable generation unit 104a are shown. This figure shows the waveform of the signal data1 output from the A / D conversion unit 103 and input to the enable generation unit 104a as (a) at the top of the figure. In addition, the waveform of the signal data2a output from the enable generation unit 104a is shown as (b) in the center of FIG. Furthermore, the waveform of the signal en2a output from the enable generation unit 104a is shown at (c) at the bottom of the figure. In the waveform diagrams (a) to (c) in the figure, the horizontal axis represents time, and the vertical axis represents voltage level.

  In the example of FIG. 5, it is assumed that the signal data1 is a signal of 212 kbps (212 kHz).

  As shown in the figure, the voltage level of the signal en2a becomes high (“H”) after a quarter cycle from the rising or falling timing of the signal data1. The waveform of the signal data2a and the waveform of the signal data1 are the same.

  As described above, since the enable generation unit 104a corresponds to the communication rate of 212 kbps, the pulse of the signal en2a is generated in synchronization with the cycle of the signal data1. That is, one pulse of the signal en2a is generated during the period when the voltage level is high in the waveform of FIG. 5A, and the pulse of the signal en2a is generated during the period when the voltage level is low in the waveform of FIG. Is generated.

  However, since the enable generation unit 104b corresponds to the communication rate of 424 kbps, two pulses of the signal en2a are generated during the period when the voltage level of the signal data1 is high and during the period when the voltage level is low. . This is because the timing signal generated by the timing generation unit 108a corresponds to the communication rate 212 kbps, and the timing signal generated by the timing generation unit 108b corresponds to the communication rate 424 kbps. Similarly, in the case of the enable generation unit 104c, the enable generation unit 104d,..., The enable generation unit 104N, more pulses are generated.

  On the other hand, even in the case of the enable generation unit 104b to the enable generation unit 104N, the waveforms of the output signals data2b to data2N are the same as the waveform of the signal data1.

  The enable generation units 104a to 104c in FIG. 4 output the signals en2a to en2c and the signals data2a to data2c, respectively, to the parallel / serial conversion unit 105, as described above.

  FIG. 6 is a block diagram illustrating a detailed configuration example of the parallel / serial converter 105 of FIG. As shown in the figure, the parallel / serial conversion unit 105 includes recording units 111 a to 111 c and an output selection unit 112. In the figure, for the sake of convenience, the recording units 111a to 111c are shown, but originally, N recording units corresponding to each of the plurality of communication rates described above are provided.

  The recording unit 111a corresponds to a communication rate of 212 kbps, the recording unit 111b corresponds to a communication rate of 424 kbps, and the recording unit 111c corresponds to a communication rate of 847 kbps. In FIG. 6, a detailed configuration example is disclosed only for the recording unit 111a, but each of the recording unit 111b and the recording unit 111c is configured in the same manner as the recording unit 111a.

  The recording unit 111a includes an AND gate 125a, an OR gate 126a, a register 123a, and a register 124a.

  The AND gate 125a operates with the signal en3a output from the register 123a and a signal obtained by inverting the signal en4a output from the output selection unit 112 as inputs. The OR gate 126a operates with the output signal of the AND gate 125a and the signal en2a output from the enable generation unit 104a as inputs.

  The register 123a delays the output signal of the OR gate 126a by one clock and outputs it as a signal en3a. The register 124a holds (latches) the signal data2a output from the enable generation unit 104a at the timing when the pulse of the signal en2a is supplied, delays it by one clock, and outputs the signal data3a.

  When there is only one enable that is input as the signals en3a, en3b, and en3c at the same time, the output selection unit 112 outputs data corresponding to the communication rate of the enable together with the enable.

  For example, the output selection unit 112 outputs the signal data3a for the communication rate 212kbps onto the signal line that outputs the signal data4 at the timing when the voltage level of the signal en3a for the communication rate 212kbps increases. At that time, the output selection unit 112 simultaneously increases the voltage level of the signal en4a.

  The output selection unit 112 selects an enable according to a preset priority when there are a plurality of simultaneous inputs enabled as the signal en3a, the signal en3b, and the signal en3c, and selects data corresponding to the communication rate of the enable, It is designed to output with enable.

  FIG. 7 is a timing chart for explaining the operation of the parallel / serial converter 105. The horizontal axis of the figure is time, and in this example, the state of each signal in a minute time t1 to t12 expressed in clock units is shown. In the description here, each minute time expressed in units of clocks is appropriately expressed as times t1 to t12.

  In the figure, the state of each signal input to the parallel / serial converter 105 is shown as (a) at the top of the figure. Here, signals en2a to en2c and signals data2a to data2c are shown.

  As described above, the signals en2a to en2c are signals supplied as enable to the parallel / serial converter 105, and the enable pulse width is one clock. Note that the clock cycle corresponds to the sampling rate of the A / D converter 103. In this example, there is a pulse of the signal en2a at time t1, time t5, and time t9. Further, a pulse of the signal en2b exists at time t2, time t5, and time t10, and a pulse of the signal en2c exists at time t3, time t5, and time t9.

  In FIG. 7A, the data of the signal data2a to the signal data2c exist at the timing when the pulses of the signal en2a to the signal en2c exist. As described above, when the signals data2a to data2c are observed as waveforms, the waveform is the same as that of the signal data1, but here, only the timing when the enable pulse is present is represented as data. That is, in the signal data2a, the data a1 exists at the time t1, the data a2 exists at the time t5, and the data a3 exists at the time t9. In the signal data2b, data b1 exists at time t2, data b2 exists at time t5, and data b3 exists at time t10. Further, in the signal data2c, data c1 exists at time t3, data c2 exists at time t5, and data c3 exists at time t9.

  In FIG. 7, the state of each signal output from the recording units 111a to 111c is shown as (b) in the center of the drawing. That is, the signals en3a to en3c and the signals data3a to data3c are shown.

  Further, in FIG. 7, the state of each signal output from the output selection unit 112 is shown as (c) at the bottom of the drawing. That is, a signal en4a to a signal en4c and a signal data4 are shown.

  As described above, the register 123a delays the output signal of the OR gate 126a by one clock and outputs it as the signal en3a. When the initial states of the signals en4a and en3a are “L”, the output of the AND gate 125a becomes “L” at time t1. Therefore, since the output of the OR gate 126a at time t1 is “H”, a pulse of the signal en3a exists at time t2, as shown in FIG. 7B.

  In addition, as described above, the register 124a holds (latches) the signal data2a output from the enable generation unit 104a at the timing when the pulse of the signal en2a is supplied, delays it by one clock, and outputs the signal data3a. . Therefore, in the signal data3a, the data a1 exists at the time t2.

  Similarly, a pulse of the signal en3b exists at time t3, and a pulse of the signal en3c exists at time t4. In the signal data3b, the data b1 exists at time t3, and in the signal data3c, the data c1 exists at time t4.

  In FIG. 7B, for the sake of convenience, it is described that the data a1 and the like exist only at the same time as the enable pulse, but actually, until the next enable pulse is output (data data a1 continues to be output until (a2 is output). The same applies to data b1, data c1, and the like.

  As described above, when only one enable is input as the signal en3a, the signal en3b, and the signal en3c at the same time, the output selection unit 112 outputs the data corresponding to the communication rate of the enable together with the enable. Has been made. Therefore, as shown in FIG. 7C, the signals en4a to en4c have pulses at times t2 to t4, respectively. In the signal data4, data a1 exists at time t2, data b1 exists at time t3, and data c1 exists at time t4.

  On the other hand, the output selection unit 112 selects an enable according to a preset priority order when there are a plurality of enables simultaneously input as the signal en3a, the signal en3b, and the signal en3c, and corresponds to the communication rate of the enable. Data is output together with enable. Here, the priority order is usually set such that the highest (higher) communication rate is the highest priority, and the priority is lowered as the communication rate becomes smaller (lower). That is, the higher priority is set in order from the shortest symbol length when Manchester encoding is performed. In this case, it is assumed that priority is set in the order of a communication rate of 847 kbps, a communication rate of 424 kbps, and a communication rate of 212 kbps.

  As shown in FIGS. 7A and 7B, since a pulse exists in the signal en2a at time t5, the register 123a and the register 124a have the pulse of the signal en3a and the data of the signal data3a at time t6, respectively. a2 is output. At time t5, the signal en2b and the signal en2c also have pulses, so the signal en3b and the signal en3c, and the data b2 of the signal data3b and the data c2 of the signal data3c are output at time t6, respectively. In this case, at time t6, there are a plurality (three) of inputs simultaneously input to the output selection unit 112, so the pulse and data of the signal en3c which is the enable with the highest priority among the three. c2 is selected and output. That is, in FIG. 7C, at time t6, a pulse exists in the signal en4c, and data c1 exists in the signal data4.

  Therefore, at time t6, since the state of the signal en3a is “H” and the state of the signal en4a is “L”, the output of the AND gate 125a becomes “H” and the output of the OR gate 126a is also “H”. It becomes. Therefore, the output of the register 123a at time t7 is set to “H”. Further, the register 124a continues to output the data a2 latched at the time t5 even at the time t7.

  Similarly, the recording unit 111b outputs the pulse of the signal en3b at time t7 and continues to output the data b2 to the signal data3b.

  In this case, at time t7, there are also a plurality (two) of inputs that are simultaneously input to the output selection unit 112, so the pulse of the signal en3b that has the highest priority among the two, Data b2 is selected and output. That is, in FIG. 7C, at time t7, a pulse exists in the signal en4b, and data b2 exists in the signal data4.

  Accordingly, since the state of the signal en3a is “H” and the state of the signal en4a is “L” at time t7, the output of the AND gate 125a becomes “H” and the output of the OR gate 126a is also “H”. It becomes. Therefore, the output of the register 123a at time t8 is set to “H”. Further, the register 124a continues to output the data a2 latched at time t5 even at time t8.

  In this case, since only one enable input to the output selection unit 112 exists at time t8, the pulse of the signal en3a and the data a2 are output. That is, in FIG. 7C, at time t8, a pulse exists in the signal en4a, and data a2 exists in the signal data4.

  Further, as shown in FIG. 7A, at time t9, the signal en2a has a pulse and the signal en2c has a pulse. Therefore, as shown in FIG. 7B, the signal en2a has a signal at time t10. There is a pulse of en3a and a pulse of signal en3c. In this case, since there are a plurality (two) of inputs simultaneously input to the output selection unit 112 at time t10, the pulse of the signal en3c that has the highest priority among the two, and Data c3 is selected and output. That is, in FIG. 7C, at time t10, a pulse exists in the signal en4c and data c3 exists in the signal data4.

  Here, as shown in FIG. 7A, since the pulse of the signal en2b exists at time t10, as shown in FIG. 7B, the pulse of the signal en3a exists at time t11. There is a pulse of signal en3b. In this case, since there are a plurality (two) of inputs simultaneously input to the output selection unit 112 at the time t11, the pulse of the signal en3b which is the enable with the highest priority among the two and Data b3 is selected and output. That is, in FIG. 7C, at time t11, a pulse exists in the signal en4b, and data b3 exists in the signal data4.

  At time t12, there is only one enable input to the output selection unit 112 at the same time, so the pulse of the signal en3a and the data a3 are output. That is, in FIG. 7C, at time t12, the signal en4a has a pulse, and the signal data4 has data a3.

  The parallel / serial converter 105 operates in this way. That is, the parallel / serial converter 105 outputs data corresponding to each of a plurality of communication rates (three in the present example) on one signal line (signal data4), and each data is output. The enable can be output at the timing.

  In other words, the parallel / serial converter 105 extracts data corresponding to each of a plurality of communication rates (three in the present example) from the digital signal output from the A / D converter 103, and extracts them. In other words, the processed data are arranged in series and output.

  In the above-described example, it has been described that the output selection unit 112 selects enable according to a preset priority order. However, for example, the priority order may be set each time. For example, the priority setting is sequentially changed so that the priority set in the output selection unit 112 at a certain time is different from the priority set in the output selection unit 112 at another time. It may be. Note that the priority order may be set by a non-contact IC card on which the demodulation function unit 100 is mounted, or may be set by another device.

  As shown in FIG. 3, the signals en4a to en4N and the signal data4 output from the parallel / serial converter 105 are supplied to the demodulation arithmetic processor 106.

  The demodulation arithmetic processing unit 106 calculates data supplied as the signal data4 for each communication rate based on the signals en4a to en4N. Next, the demodulation arithmetic processing unit 106 will be described.

  FIG. 8 is a diagram for explaining the operation of the demodulation calculation processing unit 106, and is a block diagram illustrating a configuration example in the case where the configuration of the demodulation calculation processing unit 106 is configured such that calculation units are arranged in parallel.

  In the example of FIG. 8, the demodulation calculation processing unit 106 includes registers 141A to 141C and calculators 142A to 142C. The registers 141A to 141C hold (latches) the signals s6A to s6C output from the calculators 142A to 142C at timings when the pulses of the signals en4a to en4c exist, respectively. The registers 141A to 141C delay the latched signal data by one clock and output the delayed data as signals data5A to data5C.

  The calculators 142A to 142C perform predetermined calculations on the data supplied as the signal data4 at the timings when the pulses of the signals en4a to en4c exist, and output signals s6A to s6C as calculation results. . Further, the arithmetic units 142A to 142C have predetermined timings using data supplied as the signal data4 and data supplied as the signals data5A to data5C, respectively, at the timing when the pulses of the signals en4a to en4c exist. The calculation is performed, and the calculation results are output as signal data6A to signal data6C.

  FIG. 9 is a timing chart for explaining the operation when the configuration of the demodulation arithmetic processing unit 106 is configured such that arithmetic units are arranged in parallel as shown in FIG. The horizontal axis of the figure is time, and in this example, the state of each signal in a minute time t1 to t13 expressed in clock units is shown. In the description here, each minute time expressed in clock units is appropriately expressed as times t1 to t13.

  In the figure, the state of the signal for the communication rate of 212 kbps processed by the demodulation arithmetic processing unit 106 is shown as (a-1), (b-1), and (c-1) at the top of the figure. Yes. (A-1) shows the states of the signal en4a and the signal data4 output from the parallel / serial converter 105. (B-1) shows the state of the signal data5A that is the output of the register 141A and the signal s6A that is the input to the register 141A. (C-1) shows the state of the signal en6A and the signal data6A that are the outputs of the computing unit 142A.

  As shown in FIG. 9 (a-1), the signal en4a that is enabled for the communication rate of 212 kbps has pulses at time t1 and time t13.

  As shown in FIG. 9B-1, the calculator 142A performs a predetermined calculation on the data x1 supplied as the signal data4 at time t1, and outputs the calculation result data y8 as the signal s6A. . The data y8 is latched by the register 141A, continuously output from the time t2 to the time t13, and supplied to the calculator 142A. The data y1 is an initial value of the output of the register 141A. Further, at time t13, the calculator 142A performs a predetermined calculation on the data x8 supplied as the signal data4, and outputs the calculation result data y11 as the signal s6A.

  As shown in FIG. 9 (c-1), the calculator 142A performs a predetermined calculation using the data x1 supplied as the signal data4 and the data y1 supplied as the signal data5A at the time t1. The resulting data z1 is output as signal data6A. Then, the calculator 142A outputs a pulse of the signal en6A as enable at time t1. Further, at time t13, the calculator 142A performs a predetermined calculation using the data x8 supplied as the signal data4 and the data y8 supplied as the signal data5A, and outputs the calculation result data z8 as the signal data6A. Then, the calculator 142A outputs a pulse of the signal en6A as enable at time t13.

  In addition, in FIG. 9, the state of the signal for the communication rate 424 kbps processed by the demodulation arithmetic processing unit 106 is shown as (a-2), (b-2), and (c-2) in the center of the drawing. ing. (A-2) shows the states of the signal en4b and the signal data4 output from the parallel / serial converter 105. (B-2) shows the state of the signal data5B that is the output of the register 141B and the signal s6B that is the input to the register 141B. (C-2) shows the state of the signal en6B and the signal data6B which are the outputs of the computing unit 142B.

  As shown in FIG. 9A-2, the signal en4b that is enabled for the communication rate of 424 kbps has pulses at time t2, time t5, and time t10.

  As shown in FIG. 9B-2, the calculator 142B performs a predetermined calculation on the data x2 supplied as the signal data4 at time t2, and outputs the calculation result data y4 as the signal s6B. . The data y4 is latched by the register 141B, continuously output from the time t3 to the time t5, and supplied to the computing unit 142B. Note that the data y2 is an initial value of the output of the register 141B.

  Further, the calculator 142B performs a predetermined calculation on the data x4 supplied as the signal data4 at time t5, and outputs the calculation result data y6 as the signal s6B. The data y6 is latched by the register 141B, continuously output from the time t6 to the time t10, and supplied to the computing unit 142B.

  Further, at time t10, the calculator 142B performs a predetermined calculation on the data x6 supplied as the signal data4, and outputs the calculation result data y9 as the signal s6B. The data y9 is latched by the register 141B, continuously output for the period after time t11, and supplied to the computing unit 142B.

  As shown in FIG. 9 (c-2), the calculator 142B performs a predetermined calculation using the data x2 supplied as the signal data4 and the data y2 supplied as the signal data5B at time t2. The resulting data z2 is output as signal data6B. Then, the calculator 142B outputs a pulse of the signal en6B as enable at time t2.

  Further, the calculator 142B performs a predetermined calculation using the data x4 supplied as the signal data4 and the data y4 supplied as the signal data5B at time t5, and outputs the calculation result data z4 as the signal data6B. Then, the calculator 142B outputs a pulse of the signal en6B as enable at time t5.

  Furthermore, the calculator 142B performs a predetermined calculation using the data x6 supplied as the signal data4 and the data y6 supplied as the signal data5B at time t10, and outputs the calculation result data z6 as the signal data6B. Then, the calculator 142B outputs a pulse of the signal en6B as enable at time t10.

  Also, in FIG. 9, the state of the signal for the communication rate 847 kbps processed by the demodulation arithmetic processing unit 106 is shown as (a-3), (b-3), and (c-3) at the bottom of the figure. Has been. (A-3) shows the states of the signal en4c and the signal data4 output from the parallel / serial converter 105. (B-3) shows the state of the signal data5C that is the output of the register 141C and the signal s6C that is the input to the register 141C. (C-3) shows the state of the signal en6C and the signal data6C which are the outputs of the computing unit 142C.

  As shown in FIG. 9A-3, the signal en4c that is enabled for the communication rate 847 kbps has pulses at time t3, time t7, and time t12.

  As shown in FIG. 9B-3, the calculator 142C performs a predetermined calculation on the data x3 supplied as the signal data4 at time t3, and outputs the calculation result data y5 as the signal s6C. . The data y5 is latched by the register 141C, continuously output from the time t4 to the time t7, and supplied to the computing unit 142C. Note that the data y3 is an initial value of the output of the register 141C.

  The calculator 142C performs a predetermined calculation on the data x5 supplied as the signal data4 at time t7, and outputs the calculation result data y7 as the signal s6C. The data y6 is latched by the register 141C, continuously output from the time t8 to the time t12, and supplied to the calculator 142C.

  Further, at time t12, the calculator 142C performs a predetermined calculation on the data x7 supplied as the signal data4, and outputs the calculation result data y10 as the signal s6C. The data y10 is latched by the register 141C, continuously output for the period after time t13, and supplied to the computing unit 142C.

  As shown in FIG. 9C-3, the calculator 142C performs a predetermined calculation using the data x3 supplied as the signal data4 and the data y3 supplied as the signal data5C at time t3. The resulting data z3 is output as signal data6C. Then, the calculator 142C outputs a pulse of the signal en6C as an enable at time t3.

  Further, at time t7, the calculator 142C performs a predetermined calculation using the data x5 supplied as the signal data4 and the data y5 supplied as the signal data5C, and outputs the calculation result data z5 as the signal data6C. Then, the calculator 142C outputs a pulse of the signal en6C as an enable at time t7.

  Further, the calculator 142C performs a predetermined calculation using the data x7 supplied as the signal data4 and the data y7 supplied as the signal data5C at time t12, and outputs the calculation result data z7 as the signal data6C. Then, the calculator 142C outputs a pulse of the signal en6C as an enable at time t12.

  In this way, the demodulation calculation processing unit 106 calculates the data supplied as the signal data4 for each communication rate based on the signals en4a to en4N.

  However, if the computing units 142A to 142C shown in FIG. 8 can be combined into one computing unit, the circuit scale can be further reduced.

  In the FeliCa communication system described in ISO / IEC 19802, the configuration of frames transmitted and received does not change even if the communication rate is different. Since the demodulation function unit 100 corresponds to, for example, the FeliCa communication method, the calculation processing performed by the demodulation calculation processing unit 106 is the same calculation processing in any case of the communication rate 212 kbps, the communication rate 424 kbps,. can do.

  FIG. 10 is a block diagram illustrating a detailed configuration example of the demodulation calculation processing unit 106 of FIG. In the case of FIG. 8, unlike the case described above with reference to FIG. 8, for example, the arithmetic units 142A to 142C shown in FIG. 8 are collectively configured as one arithmetic unit 153.

  In the example of FIG. 10, the demodulation calculation processing unit 106 includes registers 151 a to 151 c, a selector 152, and a calculator 153. The registers 151a to 151c hold (latch) the signal s6 output from the computing unit 153 at the timing when the pulses of the signals en4a to en4c exist, respectively. The registers 151a to 151c delay the latched signal data by one clock and output the delayed data as signals data7a to data7c.

  The selector 152 selects the output of the register corresponding to each enable communication rate at the timing when the pulses of the signals en4a to en4c exist, and supplies them to the calculator 153.

  The selector 152 supplies the output of the register 151a to the calculator 153 at the timing when the pulse of the signal en4a that is enabled for the communication rate of 212 kbps exists. The selector 152 supplies the output of the register 151b to the arithmetic unit 153 at the timing when the pulse of the signal en4b that is enabled for the communication rate of 424 kbps exists. Further, the selector 152 supplies the output of the register 151c to the calculator 153 at the timing when the pulse of the signal en4c which is enabled for the communication rate 847 kbps exists.

  The calculator 153 performs a predetermined calculation on the data supplied as the signal data4 at a timing when the pulses of the signals en4a to en4c exist, and outputs a signal s6 as a calculation result. The calculator 153 performs a predetermined calculation using the data supplied as the signal data4 and the data supplied as the signal data5 at the timing when the pulses of the signals en4a to en4c exist, and outputs the calculation result as a signal. Output as data6. That is, the arithmetic unit 153 outputs the calculation result data for each communication rate as the signal data6 on one signal line.

  FIG. 11 is a timing chart for explaining the operation of the demodulation arithmetic processing unit 106 shown in FIG. The horizontal axis of the figure is time, and in this example, the state of each signal in a minute time t1 to t13 expressed in clock units is shown. In the description here, each minute time expressed in clock units is appropriately expressed as times t1 to t13.

  In the figure, the state of each signal input to the demodulation arithmetic processing unit 106 is shown as (a) at the top of the figure. That is, the states of the signal en4a, the signal en4b, the signal en4c, and the signal data4 output from the parallel / serial conversion unit 105 are illustrated.

  As shown in FIG. 11A, the signal en4a that is enabled for the communication rate of 212 kbps has pulses at time t1 and time t13. Further, the signal en4b, which is an enable signal for the communication rate 424 kbps, has pulses at time t2, time t5, and time t10. Further, the signal en4c that is enabled for the communication rate 847 kbps has pulses at time t3, time t7, and time t12.

  Data x1 to data x8 are output as signal data4 at the timing of each enable pulse.

  Further, (b) in the center of FIG. 11 shows the states of the signals data7a to data7c that are the outputs of the registers 151a to 151c and the signal s6 that is the input to the registers 151a to 151c.

  As shown in FIG. 11B, the calculator 153 performs a predetermined calculation on the data x1 supplied as the signal data4 at time t1, and outputs the calculation result data y8 as the signal s6. The data y8 is latched by the register 151a and is continuously supplied to the selector 152 for a period from time t2 to time t13, and is supplied to the arithmetic unit 153 at the timing when the pulse of en4a exists. The data y1 is an initial value of the output of the register 151a. Further, at time t13, the calculator 153 performs a predetermined calculation on the data x8 supplied as the signal data4, and outputs the calculation result data y11 as the signal s6.

  The calculator 153 performs a predetermined calculation on the data x2 supplied as the signal data4 at time t2, and outputs the calculation result data y4 as the signal s6. The data y4 is latched by the register 151b and continuously supplied to the selector 152 for a period from time t3 to time t5, and is supplied to the calculator 153 at the timing when the pulse of en4b exists. The data y2 is an initial value of the output 151b.

  Further, at time t5, the calculator 153 performs a predetermined calculation on the data x4 supplied as the signal data4, and outputs the calculation result data y6 as the signal s6. The data y6 is latched by the register 151b and continuously supplied to the selector 152 for a period from time t6 to time t10, and is supplied to the calculator 153 at the timing when the pulse of en4b exists.

  Further, at time t10, the calculator 153 performs a predetermined calculation on the data x6 supplied as the signal data4, and outputs the calculation result data y9 as the signal s6. The data y9 is latched by the register 151b and continuously supplied to the selector 152 for a period after time t11, and is supplied to the calculator 153 at the timing when the pulse of en4b exists.

  Further, the calculator 153 performs a predetermined calculation on the data x3 supplied as the signal data4 at time t3, and outputs the calculation result data y5 as the signal s6. The data y5 is latched by the register 151c and is continuously supplied to the selector 152 for a period from time t4 to time t7, and is supplied to the calculator 153 at the timing when the pulse of en4c exists. The data y3 is an initial value of the output of the register 151c.

  Further, at time t7, the calculator 153 performs a predetermined calculation on the data x5 supplied as the signal data4, and outputs the calculation result data y7 as the signal s6. The data y6 is latched by the register 151c and supplied to the selector 152 continuously from the time t8 to the time t12, and is supplied to the calculator 153 at the timing when the pulse of en4c exists.

  Further, at time t12, the calculator 153 performs a predetermined calculation on the data x7 supplied as the signal data4, and outputs the calculation result data y10 as the signal s6. The data y10 is latched by the register 151c and continuously supplied to the selector 152 for a period after time t13, and is supplied to the calculator 153 at the timing when the pulse en4c is present.

  The selector 152 selects the signal data7a, which is the output of the register 151a, and outputs it as the signal data5 at a timing when a pulse is present in the signal en4a that is enabled for the communication rate 212 kbps. That is, at time t1 and time t13, data y1 and data y8 are output as signal data5, respectively.

  The selector 152 selects the signal data7b, which is the output of the register 151b, and outputs it as the signal data5 at a timing when a pulse is present in the signal en4b that is enabled for the communication rate of 424 kbps. That is, at time t2, time t5, and time t10, data y2, data y4, and data y6 are output as signal data5, respectively.

  Further, the selector 152 selects the signal data7c, which is the output of the register 151c, and outputs it as the signal data5 at a timing when a pulse is present in the signal en4c that is enabled for the communication rate 847 kbps. That is, at time t3, time t7, and time t12, data y3, data y5, and data y7 are output as signal data5, respectively.

  Further, at the bottom of FIG. 11, (c) shows the states of the signals en6a to en6c and the signal data6 which are the outputs of the computing unit 153.

  The arithmetic unit 153 performs a predetermined calculation using data supplied as the signal data4 and data supplied as the signal data5 at a timing when the pulses of the signals en4a to en4c exist, and the calculation result is set as the signal data6. Output.

  That is, as shown in FIG. 11C, the calculator 153 performs a predetermined calculation using the data x1 supplied as the signal data4 and the data y1 supplied as the signal data5 at time t1, The resulting data z1 is output as signal data6. Then, the arithmetic unit 153 outputs a pulse of the signal en6a as an enable at time t1. Further, at time t13, the calculator 153 performs a predetermined calculation using the data x8 supplied as the signal data4 and the data y8 supplied as the signal data5, and outputs the calculation result data z8 as the signal data6. Then, the calculator 153 outputs a pulse of the signal en6a as enable at time t13.

  Processing such as these calculations performed at time t1 and time t13 is performed as demodulation processing for a communication rate of 212 kbps.

  Further, at time t2, the calculator 153 performs a predetermined calculation using the data x2 supplied as the signal data4 and the data y2 supplied as the signal data5, and outputs the calculation result data z2 as the signal data6. Then, the arithmetic unit 153 outputs a pulse of the signal en6b as an enable at time t2.

  Furthermore, the calculator 153 performs a predetermined calculation using the data x4 supplied as the signal data4 and the data y4 supplied as the signal data5 at time t5, and outputs the calculation result data z4 as the signal data6. Then, the calculator 153 outputs a pulse of the signal en6b as an enable at time t5.

  Further, at time t10, the calculator 153 performs a predetermined calculation using the data x6 supplied as the signal data4 and the data y6 supplied as the signal data5, and outputs the calculation result data z6 as the signal data6. Then, the calculator 153 outputs a pulse of the signal en6b as an enable at time t10.

  Processing such as these calculations performed at time t2, time t5, and time t10 is performed as demodulation processing for a communication rate of 424 kbps.

  Further, at time t3, the calculator 153 performs a predetermined calculation using the data x3 supplied as the signal data4 and the data y3 supplied as the signal data5, and outputs the calculation result data z3 as the signal data6. Then, the calculator 153 outputs a pulse of the signal en6c as an enable at time t3.

  Further, at time t7, the calculator 153 performs a predetermined calculation using the data x5 supplied as the signal data4 and the data y5 supplied as the signal data5, and outputs the calculation result data z5 as the signal data6. Then, the arithmetic unit 153 outputs a pulse of the signal en6c as an enable at time t7.

  Further, at time t12, the calculator 153 performs a predetermined calculation using the data x7 supplied as the signal data4 and the data y7 supplied as the signal data5, and outputs the calculation result data z7 as the signal data6. Then, the calculator 153 outputs a pulse of the signal en6c as an enable at time t12.

  Processing such as these calculations performed at time t3, time t7, and time t12 is performed as demodulation processing for a communication rate of 847 kbps.

  In this way, the demodulation calculation processing unit 106 can calculate the data supplied as the signal data4 for each communication rate based on the signals en4a to en4N.

  Since the data present in the signal data6 output from the demodulation arithmetic processing unit 106 is output at the same timing as the enable corresponding to each communication rate, the selection unit 107 selects and outputs the data corresponding to the enable. To be able to.

  That is, the demodulation arithmetic processing unit 106 of the present invention described above with reference to FIG. 10 can perform processing equivalent to the configuration shown in FIG. That is, the demodulation calculation processing unit 106 performs calculation on the data x1 and x8 for the communication rate 212 kbps supplied as the signal data4, and performs the same calculation on the data x2, x4, and x6 for the communication rate 424 kbps. Apply. Further, the demodulation calculation processing unit 106 performs the same calculation on the data x3, x5, and x7 for the communication rate 847 kbps supplied as the signal data4.

  As described above, the demodulation calculation processing unit 106 according to the present invention described above with reference to FIG. 10 can, for example, combine the calculators 142A to 142C shown in FIG. 8 into one calculator. Yes, the circuit scale can be further reduced.

  Returning to FIG. 3, the selection unit 107 selects data to be output based on the content of data present in the signal data 6 that is the output of the demodulation calculation processing unit 106. The contents of the data present in the signal data6 include, for example, the demodulation result of the preamble of the frame by the demodulation calculation processing unit 106, the calculation result of CRC, and the like.

  For example, when demodulation processing for a communication rate of 424 kbps or demodulation processing for a communication rate of 847 kbps is performed on a frame transmitted at a communication rate of 212 kbps, the demodulation result of the frame preamble, the CRC calculation result, etc. are inappropriate. It will be something. On the other hand, when demodulation processing for a communication rate of 212 kbps is performed on a frame transmitted at a communication rate of 212 kbps, the demodulation result of the preamble of the frame, the calculation result of the CRC, and the like are appropriate.

  The selection unit 107 determines, for example, whether the demodulation result of the frame preamble and the CRC calculation result are appropriate for each communication rate data, and selects only the communication rate data determined to be appropriate. Output.

  In addition, the selection unit 107 determines whether the communication rate of the reader / writer is determined by determining whether the demodulation result of the preamble of the frame, the calculation result of the CRC, or the like is appropriate for each communication rate data. Become. After the communication rate of the reader / writer is determined, for example, only the enable generation unit 104 corresponding to the communication rate of the reader / writer operates in the demodulation process of the received frame.

  For example, after the communication rate of the reader / writer is found to be 212 kbps, only the enable generation unit 104a of the enable generation units 104a to 104N operates, and the enable generation unit 104b to the enable generation unit 104N do not operate. It is made like that.

  By doing so, the non-contact IC card equipped with the demodulation function unit 100 can be demodulated even for a signal whose communication rate is unknown, and can communicate at any communication rate. can do.

  Further, in the present invention, by providing the parallel / serial conversion unit 105, the demodulation calculation processing unit 106, and the selection unit 107, it is possible to solve the problem of a plurality of communication rates while suppressing an increase in circuit scale as much as possible.

  Next, demodulation processing by the demodulation function unit 100 of the present invention will be described with reference to the flowchart of FIG.

  In step S21, the analog detection circuit 102 performs analog detection on the signal received by the antenna 101. At this time, for example, an analog signal obtained by performing envelope detection or synchronous detection on the signal received by the antenna 101 is supplied to the A / D conversion unit 103.

  In step S22, the A / D conversion unit 103 performs A / D conversion on the analog signal output accompanying the processing in step S21. At this time, the A / D conversion unit 103 samples the analog signal output from the analog detection circuit 12, for example, 13.56 MHz, converts the analog signal into a digital signal, and supplies the digital signal to the enable generation unit 104a to the enable generation unit 104N. . Note that the sampling rate by the A / D conversion unit 103 normally corresponds to the frequency of the carrier wave of the signal transmitted from the reader / writer.

  In step S23, the enable generation unit 104 generates an enable corresponding to each communication rate.

  At this time, for example, the rise and fall of the signal data1 are detected, a pulse having a voltage level of “H” is generated after a ¼ period from the rise and fall, and the digital signal composed of the pulse is converted into the signals en2a to en2a. It is output as signal en2N.

  Thereby, for example, the enable is generated as described above with reference to FIG.

  In step S24, the parallel / serial converter 105 extracts data corresponding to each communication rate from the digital signal obtained by the process of step S22, and corresponds to each of the enables generated by the process of step S23. Output on one signal line.

  At this time, for example, as described above with reference to FIG. 7, the parallel / serial conversion unit 105 transmits data corresponding to each of a plurality of communication rates (three in this example) to one signal line (signal output on data4), and enable is output at the timing when each data is output.

  In step S25, the demodulation arithmetic processing unit 106 performs arithmetic processing on each of the data output by the processing in step S24 for each enable corresponding to the communication rate. At this time, for example, as described above with reference to FIG. 9, based on the enable corresponding to each communication rate, the selector 152 supplies data to the calculator 153, and the calculator 153 performs the calculation. Then, the calculator 153 outputs calculation result data for each communication rate as a signal data6 on one signal line.

  In step S26, the selection unit 107 selects data with an appropriate communication rate. At this time, for example, for each communication rate data, for example, it is determined whether the demodulation result of the frame preamble, the CRC calculation result, etc. are appropriate, and only the communication rate data determined to be appropriate are selected. Is output.

  In this way, the demodulation process is executed. By doing so, the contactless IC card equipped with the demodulation function unit 100 can demodulate a signal whose communication rate is unknown, and can communicate at any communication rate. can do.

  Note that the series of processes described above in this specification includes processes that are performed in parallel or individually even if they are not necessarily processed in time series, as well as processes that are performed in time series in the order described. Is also included.

  The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  100 demodulation function unit, 101 antenna, 102 analog detection circuit, 103 A / D conversion unit, 104a to 104N enable generation unit, 105 parallel / serial conversion unit, 106 demodulation operation processing unit, 107 selection unit, 108a to 108c timing generation unit , 109a to 109c enable output unit, 111a to 111c recording unit, 112 output selection unit, 151a to 151c register, 152 selector, 153 computing unit

Claims (11)

Enable generation means for respectively generating enables corresponding to a plurality of predetermined communication rates;
Data corresponding to the plurality of communication rates is extracted based on each of the enables corresponding to the generated plurality of communication rates, and each of the extracted data is enabled to correspond to a plurality of communication rates. Extraction data output means for outputting corresponding to each,
Arithmetic processing for performing calculation for each of the plurality of communication rates for each of the data corresponding to the plurality of communication rates output from the extracted data output means, and outputting each calculation result on one signal line And a demodulator. Analog detection means for receiving and analog-detecting a transmission signal modulated by a predetermined modulation method;
A / D conversion means for converting the signal output from the analog detection means into a digital signal by sampling based on the carrier rate of the transmission signal; and
The enable generation means generates enables corresponding to the plurality of communication rates in synchronization with rising or falling timings of the signal output from the analog detection means,
The demodulator according to claim 1, wherein the extracted data output means extracts data corresponding to the plurality of communication rates from the signal output from the A / D conversion means based on each of the enables. In the transmission signal, data to be received by the demodulation device is transmitted as a frame of a predetermined format,
The frame data is encoded at a plurality of different symbol rates;
The arithmetic processing means includes:
The demodulation device according to claim 2, wherein the same calculation is performed on data corresponding to any communication rate. The extracted data output means, when there are a plurality of enables corresponding to a plurality of communication rates generated by the enable generation means at the same time, the data to be output and the enable according to a preset priority order The demodulator according to claim 1. The demodulator according to claim 4, wherein the priority is set higher in descending order of the symbol length when the data is encoded. The demodulator according to claim 4, wherein the priority is sequentially changed. The enable generation means includes
The demodulation device according to claim 1, further comprising a timing signal generation unit that generates a timing signal corresponding to each of the plurality of communication rates. The arithmetic processing means includes:
The data output from the extracted data output means is held by a register corresponding to each of the communication rates,
The demodulator according to claim 7, wherein the arithmetic operation is performed by one arithmetic unit on the data held in the register based on each of the enable corresponding to the plurality of communication rates. Selection means for specifying a communication rate of data modulated and transmitted to the transmission signal and selecting data of the specified communication rate based on a calculation result for each of the plurality of communication rates by the calculation processing means; The demodulator according to claim 1. The enable generation means generates enables corresponding to a plurality of predetermined communication rates,
Extracted data output means extracts data corresponding to the plurality of communication rates based on each of the generated enable corresponding to the plurality of communication rates, and extracts each of the extracted data to a plurality of communication Output corresponding to each of the enable corresponding to the rate,
An arithmetic processing unit that performs an operation for each of the plurality of communication rates for each of the output data corresponding to the plurality of communication rates, and outputs each operation result on one signal line; Including demodulation methods. Analog detection means for receiving and analog-detecting a transmission signal modulated by a predetermined modulation method;
A / D conversion means for converting the signal output from the analog detection means into a digital signal by sampling based on the carrier rate of the transmission signal;
Enable generation means for generating enables corresponding to a plurality of predetermined communication rates in synchronization with the rising or falling timing of the signal output from the analog detection means;
Extracting data corresponding to the plurality of communication rates based on each of the enables corresponding to the plurality of communication rates generated by the enable generation unit from the signal output from the A / D conversion unit, Extracted data output means for outputting each of the extracted data corresponding to each of the enable corresponding to a plurality of communication rates;
Arithmetic processing for performing calculation for each of the plurality of communication rates for each of the data corresponding to the plurality of communication rates output from the extracted data output means, and outputting each calculation result on one signal line Means,
Selection means for specifying a communication rate of data modulated and transmitted to the transmission signal and selecting data of the specified communication rate based on a calculation result for each of the plurality of communication rates by the calculation processing means; A demodulator comprising
An electronic device that demodulates a transmission signal transmitted from another device using the demodulation device.

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