JP2011082555A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2011082555A
JP2011082555A JP2010283248A JP2010283248A JP2011082555A JP 2011082555 A JP2011082555 A JP 2011082555A JP 2010283248 A JP2010283248 A JP 2010283248A JP 2010283248 A JP2010283248 A JP 2010283248A JP 2011082555 A JP2011082555 A JP 2011082555A
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chip
chips
terminals
main surface
wiring
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JP5297445B2 (en
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Mitsuaki Katagiri
光昭 片桐
Masayuki Shirai
優之 白井
義之 ▲角▼
Yoshiyuki Sumi
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a means capable of reducing the manufacturing cost of a multi-chip module having a plurality of kinds of chips, differing in terminal pitch, mounted on a wiring board. <P>SOLUTION: Ratios of chip areas of two kinds of chips 2A and 2C, mounted on a principal surface of a package substrate 100, to the numbers of terminals thereof are compared with each other to mount the chip 2A having the larger ratio on the substrate in a flip-chip manner and to mount the chip 2C having the smaller ratio on the back of the chip 2A and connect it to the substrate in a wire-bonding manner. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置に関し、特に、配線基板上に端子ピッチの異なる複数種類の半導体チップを実装したマルチチップモジュール(Multi-Chip Module;ＭＣＭ)に適用して有効な技術に関する。   The present invention relates to a semiconductor device, and more particularly, to a technique effective when applied to a multi-chip module (MCM) in which a plurality of types of semiconductor chips having different terminal pitches are mounted on a wiring board.

フラッシュメモリやＤＲＡＭ(Dynamic Random Access Memory)などのメモリＬＳＩを大容量化する対策の一つとして、これらのメモリＬＳＩが形成された半導体チップ（メモリチップ）を積層して単一のパッケージに封止したメモリ・モジュール構造が種々提案されている。   As a measure to increase the capacity of memory LSIs such as flash memory and DRAM (Dynamic Random Access Memory), semiconductor chips (memory chips) on which these memory LSIs are formed are stacked and sealed in a single package Various memory module structures have been proposed.

例えば特許文献１（特開平４−３０２１６４号公報）は、一つのパッケージ内に同一機能、同一サイズの複数の半導体チップを絶縁層を介して階段状に積層し、それぞれの半導体チップの階段状部分に露出したボンディングパッドとパッケージのインナーリードとをワイヤを介して電気的に接続したパッケージ構造を開示している。   For example, Patent Document 1 (Japanese Patent Laid-Open No. 4-302164) discloses that a plurality of semiconductor chips having the same function and the same size are stacked in a step shape through an insulating layer in one package, and stepped portions of the respective semiconductor chips. Discloses a package structure in which the exposed bonding pads and the inner leads of the package are electrically connected via wires.

特許文献２（特開平１１−２０４７２０号公報）は、絶縁性基板上に熱圧着シートを介して第１の半導体チップを搭載し、この第１の半導体チップ上に熱圧着シートを介して、外形寸法が第１の半導体チップよりも小さい第２の半導体チップを搭載し、第１および第２の半導体チップのボンディングパッドと絶縁性基板上の配線層とをワイヤを介して電気的に接続し、第１および第２の半導体チップとワイヤとを樹脂により封止したパッケージ構造を開示している。   Patent Document 2 (Japanese Patent Application Laid-Open No. 11-204720) discloses that a first semiconductor chip is mounted on an insulating substrate via a thermocompression sheet, and an outer shape is formed on the first semiconductor chip via a thermocompression sheet. A second semiconductor chip having a size smaller than that of the first semiconductor chip is mounted, and the bonding pads of the first and second semiconductor chips and the wiring layer on the insulating substrate are electrically connected via wires; A package structure is disclosed in which first and second semiconductor chips and wires are sealed with resin.

また、半導体チップの主面に半田バンプをアレイ状に配置し、ボンディングパッドと半田バンプとをＣｕ（銅）などからなる配線を介して電気的に接続することによって、接続端子（半田バンプ）のピッチをボンディングパッドのピッチよりも広くするウエハレベルＣＳＰ(Chip Size Package)、あるいはウエハプロセス・パッケージ（ＷＰＰ）などと呼ばれる技術が知られている。この技術を利用すれば、半導体チップの端子ピッチを実質的に広くすることができるので、配線のラインアンドスペースを狭くした高価なビルドアップ基板を使用しなくとも、配線のピッチが広い安価な樹脂基板を使ってメモリ・モジュールを製造することができる。なお、ウエハレベルＣＳＰについては、例えば非特許文献１（株式会社技術調査会発行（２０００年５月２８日発行）の「エレクトロニクス実装技術：２０００臨時増刊号」８１頁〜１１３頁）や、特許文献３（特許国際公開ＷＯ／２３６９６号公報）などに記載がある。   In addition, solder bumps are arranged in an array on the main surface of the semiconductor chip, and the bonding pads and the solder bumps are electrically connected via wiring made of Cu (copper) or the like, so that the connection terminals (solder bumps) A technique called a wafer level CSP (Chip Size Package) or a wafer process package (WPP) that makes the pitch wider than the pitch of bonding pads is known. If this technology is used, the terminal pitch of the semiconductor chip can be substantially widened, so that an inexpensive resin with a wide wiring pitch can be used without using an expensive build-up board with a narrow line and space of wiring. A memory module can be manufactured using the substrate. As for the wafer level CSP, for example, Non-Patent Document 1 (“Electronic Packaging Technology: 2000 Special Issue 2000” issued on May 28, 2000, published on May 28, 2000), pages 81 to 113), Patent Document 3 (Patent International Publication WO / 23696).

特開平４−３０２１６４号公報JP-A-4-302164 特開平１１−２０４７２０号公報JP-A-11-204720 特許国際公開ＷＯ／２３６９６号公報Patent International Publication WO / 23696

株式会社技術調査会発行（２０００年５月２８日発行）、「エレクトロニクス実装技術：２０００臨時増刊号」８１頁〜１１３頁Published by Technical Research Committee, Inc. (issued on May 28, 2000), "Electronics Packaging Technology: 2000 Special Issue", pages 81-113

本発明者らは、一つのパッケージ内に複数個の半導体チップ（以下、単にチップという）を実装したマルチチップモジュールを開発している。   The present inventors have developed a multi-chip module in which a plurality of semiconductor chips (hereinafter simply referred to as chips) are mounted in one package.

本発明者らが開発中のマルチチップモジュールは、ＤＲＡＭ(Dynamic Random Access Memory)やフラッシュメモリなどのメモリＬＳＩが形成されたチップと、高速マイクロプロセッサ（ＭＰＵ：超小型演算処理装置）が形成されたチップとを単一の樹脂パッケージ内に封止することにより、複数個のメモリチップを樹脂封止した従来のメモリ・モジュールよりも汎用性の高いシステムを実現しようとするものである。   The multi-chip module under development by the present inventors was formed with a chip on which a memory LSI such as DRAM (Dynamic Random Access Memory) or flash memory was formed, and a high-speed microprocessor (MPU: ultra-compact processing unit). By sealing the chips in a single resin package, a system with higher versatility than a conventional memory module in which a plurality of memory chips are sealed with resin is to be realized.

また、本発明者らは、このマルチチップモジュールの製造コストを低減するために、配線のピッチが広い安価な樹脂基板上にチップを実装することを検討している。そのためには、前述したウエハレベルＣＳＰ技術を利用し、チップの端子ピッチを実質的に広くする必要がある。   In addition, the present inventors are considering mounting a chip on an inexpensive resin substrate having a wide wiring pitch in order to reduce the manufacturing cost of the multichip module. For this purpose, it is necessary to substantially widen the terminal pitch of the chip by using the wafer level CSP technology described above.

ところが、ＤＲＡＭやフラッシュメモリなどのメモリＬＳＩが形成されたチップのように、端子数が比較的少ないチップの場合は問題はないが、マイクロプロセッサが形成されたチップのように、端子数が多いチップの場合は、ウエハレベルＣＳＰ技術を利用しても、チップの端子ピッチを実質的に広くするには限界ある。   However, there is no problem in the case of a chip having a relatively small number of terminals, such as a chip in which a memory LSI such as a DRAM or a flash memory is formed, but a chip having a large number of terminals, such as a chip in which a microprocessor is formed. In this case, even if the wafer level CSP technology is used, there is a limit to substantially widen the terminal pitch of the chip.

例えば、現状の配線基板製造技術を使って安価な樹脂基板に形成することのできる配線の最小ピッチは０．５ｍｍである。一方、例えばチップサイズが４．６６ｍｍ×８．２２ｍｍで端子数が６４ピン、端子ピッチが０．０８ｍｍのＤＲＡＭにウエハプロセス・パッケージ技術を利用して０．５ｍｍピッチの半田バンプを形成する場合は、最大で１２８ピンの半田バンプが形成できるので問題はない。しかし、例えばチップサイズが６．８４ｍｍ×６．８４ｍｍで端子数が２５６ピン、端子ピッチが０．０８ｍｍのマイクロプロセッサに０．５ｍｍピッチの半田バンプを形成しようとすると、最大でも１６９ピンの半田バンプしか形成できないので、このチップをフリップチップ方式で実装しようとすると、配線ピッチが０．４ｍｍ以下の高価なビルドアップ基板が必要となってしまう。   For example, the minimum pitch of wiring that can be formed on an inexpensive resin substrate using the current wiring board manufacturing technology is 0.5 mm. On the other hand, for example, when forming a solder bump with a pitch of 0.5 mm using a wafer process / package technology on a DRAM having a chip size of 4.66 mm × 8.22 mm, 64 pins, and a terminal pitch of 0.08 mm. There is no problem because a solder bump of 128 pins at the maximum can be formed. However, for example, if solder bumps with a pitch of 0.5 mm are formed on a microprocessor with a chip size of 6.84 mm × 6.84 mm, 256 pins, and a terminal pitch of 0.08 mm, a solder bump with a maximum of 169 pins will be formed. Since this chip can only be formed, an expensive build-up substrate having a wiring pitch of 0.4 mm or less is required when this chip is to be mounted by the flip chip method.

本発明の目的は、配線基板上に端子ピッチの異なる複数種類のチップを実装するマルチチップモジュールの製造コストを低減することのできる技術を提供することにある。   An object of the present invention is to provide a technique capable of reducing the manufacturing cost of a multichip module in which a plurality of types of chips having different terminal pitches are mounted on a wiring board.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。   Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

本発明の好ましい一態様である半導体装置は、
表面、前記表面に形成された複数の配線、前記表面に形成され、かつ、前記複数の配線と電気的に接続され、かつ、第１ピッチで配置された複数の第１ボンディングパッド、および前記表面において前記複数の第１ボンディングパッドよりも前記表面の周縁部側に配置され、かつ、第２ピッチで配置された複数の第２ボンディングパッドを有する配線基板と、
第１集積回路、および前記配線基板の前記複数の第１ボンディングパッドと同じピッチで配置された複数の第１端子が形成された第１主面を有し、前記第１主面が前記配線基板の前記表面と対向するように、前記配線基板の前記表面上に搭載された第１半導体チップと、
前記第１半導体チップの前記複数の第１端子と、前記配線基板の前記複数の第１ボンディングパッドとを、それぞれ電気的に接続する複数のバンプ電極と、
第２集積回路、および複数の第２端子が形成された第２主面を有し、前記第２主面とは反対側の第２裏面が前記第１半導体チップの前記第１主面とは反対側の第１裏面と対向するように、前記第１半導体チップ上に積層された第２半導体チップと、
前記第２半導体チップの前記複数の第２端子と、前記配線基板の前記複数の第２ボンディングパッドとを、それぞれ電気的に接続する複数のワイヤと、
を含み、
前記複数の第１端子は、平面視において、前記第１半導体チップの前記第１主面における第１辺に沿って配置されており、
前記複数の第２端子は、平面視において、前記第２半導体チップの前記第２主面における第２辺に沿って配置されており、
前記複数の第２端子数の数は、前記複数の第１端子数の数よりも多く、
前記第２半導体チップの前記複数の第２端子のうち、前記第２辺に沿って互いに隣り合う第２端子間のピッチは、前記第１半導体チップの前記複数の第１端子のうち、前記第１辺に沿って互いに隣り合う第１端子間のピッチよりも狭いものである。 A semiconductor device which is a preferable embodiment of the present invention includes:
Surface, a plurality of wirings formed on the surface, a plurality of first bonding pads formed on the surface and electrically connected to the plurality of wirings and arranged at a first pitch, and the surface A wiring board having a plurality of second bonding pads arranged at a second pitch and arranged on the peripheral edge side of the surface from the plurality of first bonding pads;
A first integrated circuit; and a first main surface on which a plurality of first terminals arranged at the same pitch as the plurality of first bonding pads of the wiring substrate are formed, and the first main surface is the wiring substrate A first semiconductor chip mounted on the surface of the wiring board so as to face the surface of
A plurality of bump electrodes that electrically connect the plurality of first terminals of the first semiconductor chip and the plurality of first bonding pads of the wiring board;
A second integrated circuit and a second main surface on which a plurality of second terminals are formed, and a second back surface opposite to the second main surface is the first main surface of the first semiconductor chip. A second semiconductor chip stacked on the first semiconductor chip so as to face the first back surface on the opposite side;
A plurality of wires that electrically connect the plurality of second terminals of the second semiconductor chip and the plurality of second bonding pads of the wiring board;
Including
The plurality of first terminals are arranged along a first side of the first main surface of the first semiconductor chip in plan view,
The plurality of second terminals are arranged along a second side of the second main surface of the second semiconductor chip in plan view,
The number of the plurality of second terminals is greater than the number of the plurality of first terminals,
Among the plurality of second terminals of the second semiconductor chip, the pitch between the second terminals adjacent to each other along the second side is the first of the plurality of first terminals of the first semiconductor chip. The pitch is narrower than the pitch between the first terminals adjacent to each other along one side.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下の通りである。   The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

本発明の好ましい一態様によれば、複数個のチップの上に他のチップを積層して樹脂封止したマルチチップモジュールの製造コストを低減することができる。   According to a preferred aspect of the present invention, it is possible to reduce the manufacturing cost of a multi-chip module in which other chips are stacked on a plurality of chips and sealed with resin.

本発明の一実施形態である半導体装置の平面図である。It is a top view of the semiconductor device which is one embodiment of the present invention. 本発明の一実施形態である半導体装置の断面図である。It is sectional drawing of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の平面図である。It is a top view of the semiconductor device which is one embodiment of the present invention. 本発明の一実施形態である半導体装置の製造に用いるマルチ配線基板の平面図である。It is a top view of the multi-wiring board used for manufacture of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造に用いるマルチ配線基板の平面図である。It is a top view of the multi-wiring board used for manufacture of the semiconductor device which is one Embodiment of this invention. 図５に示すマルチ配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the multi-wiring board shown in FIG. 図５に示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi-wiring board shown in FIG. 図５に示すマルチ配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the multi-wiring board shown in FIG. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造に用いる半導体チップの平面図である。It is a top view of the semiconductor chip used for manufacture of the semiconductor device which is one embodiment of the present invention. 本発明の一実施形態である半導体装置の製造に用いる半導体チップの平面図である。It is a top view of the semiconductor chip used for manufacture of the semiconductor device which is one embodiment of the present invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造に用いる半導体チップの平面図である。It is a top view of the semiconductor chip used for manufacture of the semiconductor device which is one embodiment of the present invention. 本発明の一実施形態である半導体装置の製造方法を示す半導体ウエハの斜視図である。It is a perspective view of the semiconductor wafer which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示す半導体ウエハの側面図である。It is a side view of the semiconductor wafer which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の平面図である。It is a top view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の他の実施形態である半導体装置の製造に用いる半導体チップの平面図である。It is a top view of the semiconductor chip used for manufacture of the semiconductor device which is other embodiment of this invention. 本発明の他の実施形態である半導体装置の製造方法を示す半導体ウエハの要部拡大断面図である。It is a principal part expanded sectional view of the semiconductor wafer which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi wiring board which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi wiring board which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. ＤＲＡＭが形成された半導体チップの端子配列を示す平面図である。It is a top view which shows the terminal arrangement | sequence of the semiconductor chip in which DRAM was formed. マイクロプロセッサが形成された半導体チップの端子配列を示す平面図である。It is a top view which shows the terminal arrangement | sequence of the semiconductor chip in which the microprocessor was formed. 本発明の一実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is one Embodiment of this invention. 本発明の他の実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大平面図である。It is a principal part enlarged plan view of the multi-wiring board which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi wiring board which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi wiring board which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施形態である半導体装置の製造方法を示すマルチ配線基板の要部拡大断面図である。It is a principal part expanded sectional view of the multi wiring board which shows the manufacturing method of the semiconductor device which is other embodiment of this invention. 本発明の他の実施形態である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is other embodiment of this invention. 図３８のＡ−Ａ’線に沿った断面図である。It is sectional drawing along the A-A 'line | wire of FIG. 図３８のＢ−Ｂ’線に沿った断面図である。It is sectional drawing along the B-B 'line | wire of FIG. 本発明の他の実施形態である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is other embodiment of this invention. 図４１のＡ−Ａ’線に沿った断面図である。It is sectional drawing along the A-A 'line | wire of FIG. 図４１のＢ−Ｂ’線に沿った断面図である。FIG. 42 is a cross-sectional view taken along line B-B ′ of FIG. 41. 本発明の他の実施形態である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is other embodiment of this invention. 図４４のＡ−Ａ’線に沿った断面図である。FIG. 45 is a cross-sectional view taken along line A-A ′ of FIG. 44. 本発明の他の実施形態である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is other embodiment of this invention. 図４６のＡ−Ａ’線に沿った断面図である。FIG. 47 is a cross-sectional view taken along line A-A ′ of FIG. 46. 本発明の他の実施形態である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is other embodiment of this invention. 図４８のＡ−Ａ’線に沿った断面図である。FIG. 49 is a cross-sectional view taken along line A-A ′ of FIG. 48. 図４８のＢ−Ｂ’線に沿った断面図である。FIG. 49 is a cross-sectional view taken along line B-B ′ of FIG. 48.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

（実施の形態１）
図１は、本実施形態の半導体装置の上面を示す平面図、図２は、この半導体装置の断面図、図３は、この半導体装置の下面を示す平面図である。 (Embodiment 1)
1 is a plan view showing the upper surface of the semiconductor device of the present embodiment, FIG. 2 is a cross-sectional view of the semiconductor device, and FIG. 3 is a plan view showing the lower surface of the semiconductor device.

本実施形態の半導体装置は、パッケージ基板１の主面上に３個のチップ２Ａ、２Ｂ、２Ｃを実装し、これらのチップ２Ａ、２Ｂ、２Ｃをモールド樹脂３で封止したマルチチップモジュール（ＭＣＭ）である。３個のチップ２Ａ〜２Ｃのうち、２個のチップ２Ａ、２Ｂは、パッケージ基板１の主面上に並べて配置され、それらの主面に形成された複数個のＡｕバンプ４を介してパッケージ基板１の配線５と電気的に接続されている。すなわち、チップ２Ａ、２Ｂのそれぞれは、フリップチップ方式によって実装されている。   In the semiconductor device of this embodiment, three chips 2A, 2B, and 2C are mounted on the main surface of the package substrate 1, and these chips 2A, 2B, and 2C are sealed with a mold resin 3 (MCM). ). Of the three chips 2A to 2C, the two chips 2A and 2B are arranged side by side on the main surface of the package substrate 1, and the package substrate via a plurality of Au bumps 4 formed on those main surfaces. 1 wiring 5 is electrically connected. That is, each of the chips 2A and 2B is mounted by a flip chip method.

チップ２Ａ、２Ｂの主面（下面）とパッケージ基板１の主面との隙間には、アンダーフィル樹脂（封止樹脂）６が充填されている。チップ２Ａは、例えばＤＲＡＭが形成されたシリコンチップであり、チップ２Ｂは、例えばフラッシュメモリが形成されたシリコンチップである。   An underfill resin (sealing resin) 6 is filled in a gap between the main surfaces (lower surfaces) of the chips 2 </ b> A and 2 </ b> B and the main surface of the package substrate 1. The chip 2A is a silicon chip on which a DRAM is formed, for example, and the chip 2B is a silicon chip on which a flash memory is formed, for example.

チップ２Ｃは、２個のチップ２Ａ、２Ｂを跨ぐように配置され、接着剤７によってチップ２Ａ、２Ｂの上面に接着されている。チップ２Ｃの主面に形成されたボンディングパッド１３は複数本のＡｕワイヤ８によってパッケージ基板１のボンディングパッド９と電気的に接続されている。すなわち、チップ２Ｃは、ワイヤボンディング方式によって実装されている。チップ２Ｃは、例えば高速マイクロプロセッサ（ＭＰＵ：超小型演算処理装置）が形成されたシリコンチップである。このチップ２Ｃの端子ピッチは、上記２個のチップ２Ａ、２Ｂの端子ピッチよりも狭い。   The chip 2C is disposed so as to straddle the two chips 2A and 2B, and is bonded to the upper surfaces of the chips 2A and 2B with an adhesive 7. The bonding pads 13 formed on the main surface of the chip 2C are electrically connected to the bonding pads 9 of the package substrate 1 by a plurality of Au wires 8. That is, the chip 2C is mounted by a wire bonding method. The chip 2C is a silicon chip on which, for example, a high-speed microprocessor (MPU: ultracompact processing unit) is formed. The terminal pitch of the chip 2C is narrower than the terminal pitch of the two chips 2A and 2B.

上記３個のチップ２Ａ、２Ｂ、２Ｃを実装するパッケージ基板１は、ガラス繊維を含んだエポキシ樹脂（ガラス・エポキシ樹脂）のような汎用樹脂を主体として構成された多層配線基板であり、その主面（上面）、下面および内部に４〜６層程度の配線５が形成されている。   The package substrate 1 on which the three chips 2A, 2B, and 2C are mounted is a multilayer wiring substrate mainly composed of a general-purpose resin such as an epoxy resin (glass / epoxy resin) containing glass fibers. On the surface (upper surface), lower surface, and inside, about 4 to 6 layers of wiring 5 are formed.

パッケージ基板１の下面には、上記配線５と電気的に接続された複数の電極パッド１０がアレイ状に配置されており、それぞれの電極パッド１０には、マルチチップモジュール（ＭＣＭ）の外部接続端子を構成する半田バンプ１１が接続されている。マルチチップモジュール（ＭＣＭ）は、これらの半田バンプ１１を介して電子機器の配線基板などに実装される。パッケージ基板１の主面および下面には、配線５とチップ２Ａ、２Ｂとの接続部、ボンディングパッド９、電極パッド１０などの表面を除き、エポキシ系樹脂やアクリル系樹脂などからなるソルダレジスト１２がコーティングされている。   A plurality of electrode pads 10 electrically connected to the wiring 5 are arranged in an array on the lower surface of the package substrate 1, and each electrode pad 10 has an external connection terminal of a multichip module (MCM). The solder bumps 11 constituting the above are connected. The multichip module (MCM) is mounted on a wiring board of an electronic device through these solder bumps 11. A solder resist 12 made of an epoxy resin, an acrylic resin, or the like is formed on the main surface and the lower surface of the package substrate 1 except for the connection portion between the wiring 5 and the chips 2A and 2B, the bonding pad 9, the electrode pad 10, and the like. It is coated.

上記マルチチップモジュール（ＭＣＭ）の寸法の一例を説明すると、パッケージ基板１の外形寸法は、縦×横＝１３ｍｍ×１３ｍｍ、厚さ０．３ｍｍである。パッケージ基板１に実装されたチップ２Ａ、２Ｂ、２Ｃの厚さは、それぞれ０．１５ｍｍ、並んで配置された２個のチップ２Ａ、２Ｂの間隔は、２０μｍ〜１００μｍである。チップ２Ａ、２Ｂ、２Ｃを封止するモールド樹脂３の厚さは、０．６６ｍｍ、モールド樹脂３の上面から半田バンプ１１の下端までの距離、すなわちマルチチップモジュール（ＭＣＭ）の実装高さは、１．４６８ｍｍである。   An example of the dimensions of the multichip module (MCM) will be described. The external dimensions of the package substrate 1 are vertical × horizontal = 13 mm × 13 mm and thickness 0.3 mm. The thicknesses of the chips 2A, 2B, 2C mounted on the package substrate 1 are each 0.15 mm, and the distance between the two chips 2A, 2B arranged side by side is 20 μm to 100 μm. The thickness of the mold resin 3 for sealing the chips 2A, 2B, and 2C is 0.66 mm, and the distance from the upper surface of the mold resin 3 to the lower end of the solder bump 11, that is, the mounting height of the multichip module (MCM) is 1.468 mm.

また、チップ２Ａの主面に形成されたＡｕバンプ４のピッチは、０．０８ｍｍ、チップ２Ｂの主面に形成されたＡｕバンプ４のピッチは、０．１５ｍｍである。一方、チップ２Ｃの主面に形成されたボンディングパッド１３のピッチは、０．０６５ｍｍである。すなわち、マイクロプロセッサが形成されたチップ２Ｃの端子ピッチは、ＤＲＡＭが形成されたチップ２Ａの端子ピッチおよびフラッシュメモリが形成されたチップ２Ｂの端子ピッチよりも狭い。   The pitch of the Au bumps 4 formed on the main surface of the chip 2A is 0.08 mm, and the pitch of the Au bumps 4 formed on the main surface of the chip 2B is 0.15 mm. On the other hand, the pitch of the bonding pads 13 formed on the main surface of the chip 2C is 0.065 mm. That is, the terminal pitch of the chip 2C on which the microprocessor is formed is narrower than the terminal pitch of the chip 2A on which the DRAM is formed and the terminal pitch of the chip 2B on which the flash memory is formed.

このように、本実施形態のマルチチップモジュール（ＭＣＭ）は、端子ピッチが比較的広いチップ２Ａ、２Ｂをフリップチップ方式でパッケージ基板１に実装し、端子ピッチが最も狭いチップ２Ｃをチップ２Ａ、２Ｂの上に積層してワイヤボンディング方式で実装する。   Thus, in the multichip module (MCM) of this embodiment, the chips 2A and 2B having a relatively large terminal pitch are mounted on the package substrate 1 by the flip chip method, and the chip 2C having the narrowest terminal pitch is mounted on the chips 2A and 2B. Laminated on top of each other and mounted by wire bonding.

これにより、配線５のピッチが広い安価な汎用樹脂基板にチップ２Ａ、２Ｂ、２Ｃを実装することができるので、マルチチップモジュール（ＭＣＭ）の製造コストを低減することができる。   As a result, the chips 2A, 2B, and 2C can be mounted on an inexpensive general-purpose resin substrate having a wide pitch of the wiring 5, so that the manufacturing cost of the multichip module (MCM) can be reduced.

また、チップ２Ａ、２Ｂの上にチップ２Ｃを積層することにより、パッケージ基板１の実装面積を小さくすることができるので、実装密度の高いマルチチップモジュール（ＭＣＭ）を実現することができる。   In addition, since the mounting area of the package substrate 1 can be reduced by stacking the chip 2C on the chips 2A and 2B, a multichip module (MCM) having a high mounting density can be realized.

次に、上記のように構成された本実施形態の半導体装置の製造方法を図４〜図２６を用いて工程順に説明する。   Next, a method for manufacturing the semiconductor device of the present embodiment configured as described above will be described in the order of steps with reference to FIGS.

図４〜図８は、マルチチップモジュール（ＭＣＭ）の製造に使用する長方形の基板（以下、マルチ配線基板１００という）を示している。図４は、このマルチ配線基板１００の主面（チップ実装面）を示す全体平面図、図５は、裏面を示す全体平面図である。また、図６は、マルチ配線基板１００の一部を示す平面図と側面図、図７は、マルチ配線基板１００の一部を示す断面図、図８は、マルチ配線基板１００の一部（パッケージ基板１個分の領域）を示す拡大平面図である。   4 to 8 show a rectangular substrate (hereinafter referred to as a multi-wiring substrate 100) used for manufacturing a multi-chip module (MCM). 4 is an overall plan view showing the main surface (chip mounting surface) of the multi-wiring substrate 100, and FIG. 5 is an overall plan view showing the back surface. 6 is a plan view and a side view showing a part of the multi-wiring board 100, FIG. 7 is a cross-sectional view showing a part of the multi-wiring board 100, and FIG. It is an enlarged plan view showing an area for one substrate.

マルチ配線基板１００は、前記パッケージ基板１の母体となる基板である。このマルチ配線基板１００を図４、図５に示すダイシングラインＬに沿って格子状に切断（ダイシング）、個片化することにより、複数個のパッケージ基板１が得られる。図に示すマルチ配線基板１００の場合は、その長辺方向が６ブロックのパッケージ基板形成領域に区画され、短辺方向が３ブロックのパッケージ基板形成領域に区画されているので、３×６＝１８個のパッケージ基板１が得られる。   The multi-wiring substrate 100 is a substrate that is a base of the package substrate 1. The multi-wiring substrate 100 is cut (diced) in a lattice shape along the dicing lines L shown in FIGS. In the case of the multi-wiring substrate 100 shown in the drawing, the long side direction is partitioned into six block package substrate forming regions, and the short side direction is partitioned into three block package substrate forming regions, so that 3 × 6 = 18. Individual package substrates 1 are obtained.

上記マルチ配線基板１００は、ガラス・エポキシ樹脂のような汎用樹脂を主体として構成された多層配線基板である。マルチ配線基板１００の主面には、配線５およびボンディングパッド９が形成されており、裏面には、電極パッド１０が形成されている。また、マルチ配線基板１００の内層には、複数層の配線５が形成されている。パッケージ基板１を、安価な汎用樹脂を使って製造することにより、マルチチップモジュール（ＭＣＭ）の製造原価を低減することができる。   The multi-wiring board 100 is a multilayer wiring board mainly composed of a general-purpose resin such as glass / epoxy resin. Wiring 5 and bonding pad 9 are formed on the main surface of multi-wiring substrate 100, and electrode pad 10 is formed on the back surface. In addition, a plurality of layers of wirings 5 are formed in the inner layer of the multi-wiring substrate 100. By manufacturing the package substrate 1 using an inexpensive general-purpose resin, the manufacturing cost of the multichip module (MCM) can be reduced.

マルチ配線基板１００の主面の配線５およびボンディングパッド９と、裏面の電極パッド１０は、マルチ配線基板１００の両面に貼り付けたＣｕ箔をエッチングすることによって形成される。マルチ配線基板１００の主面の配線５のうち、ソルダレジスト１２で覆われていない領域、すなわちチップ２Ａ、２ＢのＡｕバンプ４が接続される領域の表面には、ＮｉおよびＡｕのメッキが施されている。また、ボンディングパッド９の表面および電極パッド１０の表面にも、ＮｉおよびＡｕのメッキが施されている。これらのメッキは、無電解メッキ法で形成することもできるが、無電解メッキ法で形成したメッキ層は膜厚が薄く、ボンディングパッド９上にＡｕワイヤ４を接続したときに十分な接着強度が確保し難いので、上記ＮｉおよびＡｕのメッキは、無電解メッキ法よりも膜厚を厚くすることのできる電解メッキ法で形成される。   The wiring 5 and the bonding pad 9 on the main surface of the multi-wiring substrate 100 and the electrode pad 10 on the back surface are formed by etching Cu foil attached to both surfaces of the multi-wiring substrate 100. Of the wiring 5 on the main surface of the multi-wiring substrate 100, Ni and Au are plated on the surface of the region not covered with the solder resist 12, that is, the region where the Au bumps 4 of the chips 2A and 2B are connected. ing. The surface of the bonding pad 9 and the surface of the electrode pad 10 are also plated with Ni and Au. These platings can also be formed by an electroless plating method, but the plating layer formed by the electroless plating method has a thin film thickness and has a sufficient adhesive strength when the Au wire 4 is connected to the bonding pad 9. Since it is difficult to ensure, the Ni and Au plating is formed by an electrolytic plating method capable of making the film thickness thicker than the electroless plating method.

配線５、ボンディングパッド９および電極パッド１０の表面に電解メッキ法でＮｉおよびＡｕのメッキを施す場合は、配線５、ボンディングパッド９および電極パッド１０がマルチ配線基板１００の全域で導通した状態でメッキ処理を行い、次いで、ダイシングラインＬ上の配線５をルータで切断した後、各パッケージ基板形成領域の導通試験を行う。そのため、図６および図７に示したように、マルチ配線基板１００の主面のダイシングラインＬには、この領域の配線５をルータで切断したときの溝１０１が残っている。   When the surfaces of the wiring 5, the bonding pad 9 and the electrode pad 10 are plated with Ni and Au by electrolytic plating, the plating is performed in a state where the wiring 5, the bonding pad 9 and the electrode pad 10 are conductive throughout the entire area of the multi-wiring substrate 100. Then, after the wiring 5 on the dicing line L is cut by a router, a continuity test is performed on each package substrate forming region. Therefore, as shown in FIGS. 6 and 7, a groove 101 is left in the dicing line L on the main surface of the multi-wiring substrate 100 when the wiring 5 in this region is cut by a router.

図８に示すように、パッケージ基板形成領域の周辺部には、チップ実装領域を囲むように複数のボンディングパッド１３が形成されている。ボンディングパッド１３は、パッケージ基板形成領域の４辺に沿って２列に配置されている。ボンディングパッド１３とチップ実装領域との間には、チップ実装領域を囲むようにダム領域１６が設けられている。このダム領域１６は、ソルダレジスト１２が形成されていない領域であり、その内側および外側のソルダレジスト１２が形成された領域よりも表面の高さが低くなっているため、チップ２Ａ、２Ｂの下部にアンダーフィル樹脂６を充填する際、このアンダーフィル樹脂６がパッケージ基板形成領域の周辺部、すなわちボンディングパッド１３が形成された領域に流れるのを防ぐ機能を持っている。   As shown in FIG. 8, a plurality of bonding pads 13 are formed at the periphery of the package substrate formation region so as to surround the chip mounting region. The bonding pads 13 are arranged in two rows along the four sides of the package substrate formation region. A dam region 16 is provided between the bonding pad 13 and the chip mounting region so as to surround the chip mounting region. The dam region 16 is a region where the solder resist 12 is not formed and has a lower surface height than the regions where the inner and outer solder resists 12 are formed. When the underfill resin 6 is filled, the underfill resin 6 has a function of preventing the underfill resin 6 from flowing to the periphery of the package substrate forming region, that is, the region where the bonding pads 13 are formed.

上記マルチ配線基板１００を使ってマルチチップモジュール（ＭＣＭ）を製造するには、図９（パッケージ基板２個分の領域を示す断面図）および図１０（パッケージ基板１個分の領域を示す拡大平面図）に示すように、マルチ配線基板１００の主面のチップ実装領域に樹脂テープ６ａを貼り付ける。樹脂テープ６ａは、例えば粒径３μｍ程度のシリカを分散させた熱硬化型エポキシ系樹脂からなるもので、あらかじめ２個のチップ（チップ２Ａ、２Ｂ）とほぼ同じ寸法となるように裁断しておく。樹脂テープ６ａは、樹脂中に導電性の微粉末を分散させた異方性導電性樹脂（ＡＣＦ）などで構成することもできる。   In order to manufacture a multi-chip module (MCM) using the multi-wiring substrate 100, FIG. 9 (sectional view showing a region for two package substrates) and FIG. 10 (enlarged plane showing a region for one package substrate). As shown in the figure, a resin tape 6a is affixed to the chip mounting region on the main surface of the multi-wiring substrate 100. The resin tape 6a is made of, for example, a thermosetting epoxy resin in which silica having a particle diameter of about 3 μm is dispersed, and is cut in advance so as to have almost the same dimensions as the two chips (chips 2A and 2B). . The resin tape 6a can also be made of an anisotropic conductive resin (ACF) in which conductive fine powder is dispersed in a resin.

なお、大気中に放置したマルチ配線基板１００には大気中の水分が浸入しているため、そのまま樹脂テープ６ａを貼り付けると、両者の接着性が低下する虞れがある。従って、マルチ配線基板１００の主面に樹脂テープ６ａを貼り付ける際には、その直前にマルチ配線基板１００をベークして水分を除去しておくことが望ましい。ベーク条件は、例えば１２５℃、２時間程度である。また、上記ベーク処理に続いてマルチ配線基板１００をプラズマ処理し、その表面を活性化することにより、樹脂テープ６ａとマルチ配線基板１００との接着性をさらに向上させることができる。   In addition, since the moisture in the atmosphere has entered the multi-wiring substrate 100 left in the atmosphere, if the resin tape 6a is applied as it is, there is a possibility that the adhesiveness between the two may decrease. Therefore, when the resin tape 6a is affixed to the main surface of the multi-wiring board 100, it is desirable that the multi-wiring board 100 be baked immediately before that to remove moisture. The baking conditions are, for example, about 125 ° C. and about 2 hours. Moreover, the adhesiveness of the resin tape 6a and the multi-wiring board 100 can further be improved by carrying out the plasma processing of the multi-wiring board 100 following the said baking process, and activating the surface.

次に、図１１および図１２に示すように、マルチ配線基板１００の主面に貼り付けた樹脂テープ６ａの上に２個のチップ２Ａ、２Ｂをフェイスダウン方式で搭載する。このとき、チップ２Ａとチップ２Ｂの隙間は、２０μｍ〜１００μｍ程度に設定する。   Next, as shown in FIGS. 11 and 12, the two chips 2A and 2B are mounted on the resin tape 6a attached to the main surface of the multi-wiring substrate 100 in a face-down manner. At this time, the gap between the chip 2A and the chip 2B is set to about 20 μm to 100 μm.

図１３に示すように、ＤＲＡＭが形成されたチップ２Ａの主面には、あらかじめボールボンディング法を用いてＡｕバンプ４を形成しておく。また、図１４に示すように、フラッシュメモリが形成されたチップ２Ｂの主面にも、同様の方法でＡｕバンプ４を形成しておく。これらのＡｕバンプ４は、ウエハプロセスの最終工程で形成する。すなわち、通常のウエハプロセスが完了した後、ウエハのボンディングパッド上にボールボンディング法を用いてＡｕバンプ４を形成し、その後、ウエハをダイシングすることによって、個片化されたチップ２Ａ、２Ｂを得る。   As shown in FIG. 13, Au bumps 4 are formed in advance on the main surface of the chip 2A on which the DRAM is formed by using a ball bonding method. Further, as shown in FIG. 14, Au bumps 4 are also formed in the same manner on the main surface of the chip 2B on which the flash memory is formed. These Au bumps 4 are formed in the final step of the wafer process. That is, after the normal wafer process is completed, Au bumps 4 are formed on the bonding pads of the wafer using a ball bonding method, and then the wafer is diced to obtain individual chips 2A and 2B. .

通常、ＤＲＡＭのボンディングパッドは、チップの中央に一列に配置されるが、フラッシュメモリのボンディングパッドは、チップの短辺に沿って２列に配置される。そのため、ＤＲＡＭのボンディングパッドは、フラッシュメモリのそれに比べてパッドのピッチが狭くなり、それに伴ってパッドの径も小さくなる（例えばフラッシュメモリの端子ピッチが１５０μｍの場合、ＤＲＡＭのそれは８５μｍ程度である）。従って、ＤＲＡＭのボンディングパッド上にＡｕバンプ４を形成するときは、径の細い（例えば直径２０μｍ）のＡｕ線を使用し、フラッシュメモリのボンディングパッド上にＡｕバンプ４を形成するときは、径の太い（例えば直径３０μｍ）のＡｕ線を使用するのが通常である。   Usually, DRAM bonding pads are arranged in a row at the center of the chip, whereas flash memory bonding pads are arranged in two rows along the short side of the chip. Therefore, the bonding pad of the DRAM has a smaller pad pitch than that of the flash memory, and the pad diameter is accordingly reduced (for example, when the terminal pitch of the flash memory is 150 μm, that of the DRAM is about 85 μm). . Accordingly, when forming the Au bump 4 on the bonding pad of the DRAM, an Au wire having a thin diameter (for example, 20 μm in diameter) is used, and when forming the Au bump 4 on the bonding pad of the flash memory, the diameter is small. It is usual to use a thick Au wire (for example, 30 μm in diameter).

しかし、本実施形態のマルチチップモジュール（ＭＣＭ）は、２個のチップ２Ａ、２Ｂの上に第３のチップ２Ｃを積層するので、チップの厚さおよびＡｕバンプ４の径を２個のチップ２Ａ、２Ｂで同じにすることによって、両者の実装高さを揃える必要がある。従って、本実施形態では、フラッシュメモリのボンディングパッド上にＡｕバンプ４を形成するときに使用するＡｕ線は、ＤＲＡＭのボンディングパッド上にＡｕバンプ４を形成するときに使用するＡｕ線と同じ径（例えば直径２０μｍ）のものを使用する。この場合、ソルダレジスト１２の厚さ（例えば２５μｍ）を考慮すると、細いＡｕ線を使って形成したＡｕバンプ４は、ボンディングパッドとの接触面積が少なくなる。そこで本実施形態では、Ａｕバンプ４とボンディングパッドとの接触面積を確保するために、Ａｕバンプ４の上にＡｕバンプ４を重ねてボンディングする多段バンプ構造を採用する。   However, since the multichip module (MCM) of this embodiment laminates the third chip 2C on the two chips 2A and 2B, the thickness of the chip and the diameter of the Au bump 4 are set to the two chips 2A. It is necessary to make the mounting height of both the same by making 2B the same. Therefore, in the present embodiment, the Au wire used when forming the Au bump 4 on the bonding pad of the flash memory has the same diameter as the Au wire used when forming the Au bump 4 on the bonding pad of the DRAM ( For example, those having a diameter of 20 μm) are used. In this case, considering the thickness of the solder resist 12 (for example, 25 μm), the Au bump 4 formed using a thin Au wire has a small contact area with the bonding pad. Therefore, in this embodiment, in order to secure a contact area between the Au bump 4 and the bonding pad, a multi-stage bump structure in which the Au bump 4 is stacked on the Au bump 4 and bonded is adopted.

次に、図１５に示すように、２個のチップ２Ａ、２Ｂの上に底面が平坦なヒートツール１０２を押し当てる。ヒートツール１０２の加圧圧力は、例えば１５ｋｇ／１０ｍｍ２、温度は例えば２３５℃である。これにより、樹脂テープ６ａが溶融し、チップ２Ａ、２Ｂとマルチ配線基板１００の隙間、およびチップ２Ａとチップ２Ｂの隙間にアンダーフィル樹脂６が充填されると共に、チップ２Ａ、２ＢのＡｕバンプ４とマルチ配線基板１００の配線５（図１５には示さない）とが電気的に接続される。 Next, as shown in FIG. 15, a heat tool 102 having a flat bottom surface is pressed onto the two chips 2A and 2B. The pressurizing pressure of the heat tool 102 is, for example, 15 kg / 10 mm 2 , and the temperature is, for example, 235 ° C. As a result, the resin tape 6a is melted, and the gaps between the chips 2A and 2B and the multi-wiring substrate 100 and the gaps between the chips 2A and 2B are filled with the underfill resin 6, and the Au bumps 4 of the chips 2A and 2B Wiring 5 (not shown in FIG. 15) of multi-wiring board 100 is electrically connected.

このように、本実施形態では、チップ２Ａ、２Ｂとほぼ同じ寸法に加工した樹脂テープ６ａを溶融させることによって、チップ２Ａ、２Ｂとマルチ配線基板１００の隙間、およびチップ２Ａとチップ２Ｂの隙間にアンダーフィル樹脂６を充填する。この方法によれば、例えばチップ２Ａ、２Ｂの周辺にディスペンサを使って液状のアンダーフィル樹脂を供給する充填方法に比べた場合、アンダーフィル樹脂６がチップ２Ａ、２Ｂの周囲にはみ出す量を少なくすることができるので、チップ２Ａ、２Ｂを囲むように配置されたマルチ配線基板１００上のボンディングパッド９がアンダーフィル樹脂６で覆われることはない。   As described above, in this embodiment, the resin tape 6a processed to have substantially the same dimensions as the chips 2A and 2B is melted, so that the gaps between the chips 2A and 2B and the multi-wiring substrate 100 and the gaps between the chips 2A and 2B are obtained. Underfill resin 6 is filled. According to this method, for example, when compared with a filling method in which a liquid underfill resin is supplied around the chips 2A and 2B using a dispenser, the amount of the underfill resin 6 protruding around the chips 2A and 2B is reduced. Therefore, the bonding pads 9 on the multi-wiring substrate 100 arranged so as to surround the chips 2A and 2B are not covered with the underfill resin 6.

次に、図１６および図１７に示すように、２個のチップ２Ａ、２Ｂの上にチップ２Ｃを搭載する。図１８に示すように、マイクロプロセッサが形成されたチップ２Ｃの主面には、その４辺に沿ってボンディングパッド１３が形成されている。ボンディングパッド１３の数は、チップ２Ａやチップ２Ｂに形成されたボンディングパッドの数よりも多い。   Next, as shown in FIGS. 16 and 17, the chip 2C is mounted on the two chips 2A and 2B. As shown in FIG. 18, bonding pads 13 are formed along the four sides of the main surface of the chip 2C on which the microprocessor is formed. The number of bonding pads 13 is larger than the number of bonding pads formed on the chip 2A and the chip 2B.

チップ２Ｃは、マルチ配線基板１００とチップ２Ｃとを接続するＡｕワイヤ８の長さが出来るだけ均一になるよう、各パッケージ基板形成領域の中央に配置する。また、チップ２Ｃの裏面には、あらかじめチップ２Ｃと同じ寸法に裁断されたテープ状の接着剤７を貼り付けておく。チップ２Ｃの裏面にテープ状の接着剤７を貼り付けるには、例えば図１９および図２０に示すように、通常のウエハプロセスが完了したウエハ１４の裏面にダイシングテープ１５を貼り付ける際、ウエハ１４とダイシングテープ１５との間にテープ状の接着剤７を挟み込み、この状態でウエハ１４をダイシングすることによってチップ２Ｃを得る。その後、チップ２Ｃの裏面のダイシングテープ１５を除去すると、チップ２Ｃの裏面にチップ２Ｃと同寸法の接着剤７が残る。接着剤７は、例えばポリイミド樹脂系の接着剤を使用する。   The chip 2C is arranged at the center of each package substrate forming region so that the length of the Au wire 8 connecting the multi-wiring substrate 100 and the chip 2C is as uniform as possible. A tape-like adhesive 7 cut in advance to the same dimensions as the chip 2C is attached to the back surface of the chip 2C. In order to affix the tape-like adhesive 7 to the back surface of the chip 2C, for example, as shown in FIGS. 19 and 20, when the dicing tape 15 is affixed to the back surface of the wafer 14 after the normal wafer process is completed, the wafer 14 A chip-like adhesive 7 is sandwiched between the wafer 14 and the dicing tape 15, and the wafer 14 is diced in this state to obtain the chip 2C. Thereafter, when the dicing tape 15 on the back surface of the chip 2C is removed, the adhesive 7 having the same dimensions as the chip 2C remains on the back surface of the chip 2C. For example, a polyimide resin adhesive is used as the adhesive 7.

次に、マルチ配線基板１００を加熱炉内で１８０℃、１時間程度加熱する。この加熱処理により、接着剤７が軟化し、チップ２Ａ、２Ｂの上にチップ２Ｃが接着される。   Next, the multi-wiring board 100 is heated in a heating furnace at 180 ° C. for about 1 hour. By this heat treatment, the adhesive 7 is softened, and the chip 2C is bonded onto the chips 2A and 2B.

次に、図２１および図２２に示すように、マルチ配線基板１００のボンディングパッド９とチップ２Ｃのボンディングパッド１３（図２１、２２には示さない）とをＡｕワイヤ８で接続する。Ａｕワイヤ８の接続は、例えば超音波振動と熱圧着とを併用したワイヤボンダを使用して行う。   Next, as shown in FIGS. 21 and 22, the bonding pads 9 of the multi-wiring substrate 100 and the bonding pads 13 (not shown in FIGS. 21 and 22) of the chip 2 </ b> C are connected by Au wires 8. The Au wire 8 is connected using, for example, a wire bonder that uses both ultrasonic vibration and thermocompression bonding.

次に、図２３および図２４に示すように、マルチ配線基板１００をモールド金型（図示せず）に装着し、マルチ配線基板１００の主面全体を一括して樹脂封止する。モールド樹脂３は、例えば粒径７０μｍ〜１００μｍ程度のシリカを分散させた熱硬化型エポキシ系樹脂からなる。   Next, as shown in FIGS. 23 and 24, the multi-wiring substrate 100 is mounted on a mold (not shown), and the entire main surface of the multi-wiring substrate 100 is collectively sealed with resin. The mold resin 3 is made of a thermosetting epoxy resin in which silica having a particle size of about 70 μm to 100 μm is dispersed, for example.

次に、図２５に示すように、マルチ配線基板１００の裏面の電極パッド９（図２５には示さない）に半田バンプ１１を接続する。半田バンプ１１の接続は、例えば低融点のＰｂ−Ｓｎ共晶合金からなる半田ボールを電極パッド９の表面に供給した後、半田ボールをリフローさせることによって行う。   Next, as shown in FIG. 25, solder bumps 11 are connected to the electrode pads 9 (not shown in FIG. 25) on the back surface of the multi-wiring substrate 100. The solder bumps 11 are connected by, for example, supplying solder balls made of a low melting point Pb—Sn eutectic alloy to the surface of the electrode pad 9 and then reflowing the solder balls.

次に、図２６に示すように、マルチ配線基板１００を前記図４、図５に示すダイシングラインＬに沿って切断、個片化することにより、前記図１〜図３に示した本実施形態のマルチチップモジュール（ＭＣＭ）が完成する。   Next, as shown in FIG. 26, the multi-wiring substrate 100 is cut along the dicing line L shown in FIGS. Multichip module (MCM) is completed.

（実施の形態２）
本実施形態の半導体装置の製造方法を図２７〜図３７を用いて工程順に説明する。 (Embodiment 2)
A manufacturing method of the semiconductor device of this embodiment will be described in the order of steps with reference to FIGS.

前記実施の形態１では、ＤＲＡＭが形成されたチップ２Ａの主面およびフラッシュメモリが形成されたチップ２Ｂの主面にそれぞれＡｕバンプ４を形成したが、本実施形態では、Ａｕバンプ４に代えて半田バンプ２０を使用する。また、ＤＲＡＭが形成されたチップ２Ａとフラッシュメモリが形成されたチップ２Ｂの組み合わせに代えて、ＤＲＡＭが形成されたチップ２Ａを２個使用する。   In the first embodiment, the Au bumps 4 are formed on the main surface of the chip 2A on which the DRAM is formed and on the main surface of the chip 2B on which the flash memory is formed. However, in this embodiment, the Au bump 4 is used instead. Solder bumps 20 are used. Further, instead of the combination of the chip 2A on which the DRAM is formed and the chip 2B on which the flash memory is formed, two chips 2A on which the DRAM is formed are used.

また、本実施形態では、マルチ配線基板１００の主面に実装する２種類のチップ２Ａ、２Ｃのそれぞれの端子数に対するチップ面積の比（この比をグリッドアレイ指数と称する）を比較し、このグリッドアレイ指数が小さい方のチップは、ワイヤボンディング方式で実装し、グリッドアレイ指数が大きい方のチップは、フリップチップ方式で実装する。すなわち、第１チップの端子数、第２チップの端子数をそれぞれＮ１、Ｎ２とし、第１チップの主面の面積、第２チップの主面の面積をそれぞれＳ１、Ｓ２とした場合に、ＳＱＲＴ（Ｓ１／Ｎ１）＞ＳＱＲＴ（Ｓ２／Ｎ２）（ＳＱＲＴは平方根を表す）の関係が成立した場合は、第１チップをフリップチップ方式で実装し、第２チップをワイヤボンディング方式で実装する。ここで、チップの端子数とは、チップの主面に半田バンプをアレイ状に配置したときの半田バンプピッチである。同様に、端子数あるいは面積が異なる３種類以上のチップを実装する場合には、それらのチップのグリッドアレイ指数を算出し、グリッドアレイ指数が最も小さいチップをワイヤボンディング方式で実装し、その他のチップは、フリップチップ方式で実装する。 In the present embodiment, the ratio of the chip area to the number of terminals of each of the two types of chips 2A and 2C mounted on the main surface of the multi-wiring substrate 100 (this ratio is referred to as a grid array index) is compared. The chip with the smaller array index is mounted by the wire bonding method, and the chip with the larger grid array index is mounted by the flip chip method. That is, the number of terminals of the first chip and the number of terminals of the second chip are N 1 and N 2 , respectively, and the area of the main surface of the first chip and the area of the main surface of the second chip are S 1 and S 2 , respectively. In this case, if the relationship SQRT (S 1 / N 1 )> SQRT (S 2 / N 2 ) (SQRT represents a square root) is established, the first chip is mounted by the flip chip method, and the second chip is mounted. Mount by wire bonding method. Here, the number of terminals of the chip is a solder bump pitch when solder bumps are arranged in an array on the main surface of the chip. Similarly, when three or more types of chips having different numbers of terminals or areas are mounted, the grid array index of those chips is calculated, the chip having the smallest grid array index is mounted by the wire bonding method, and the other chips. Is mounted by flip chip method.

ＤＲＡＭが形成されたチップ２Ａのサイズは、一例として４．６６ｍｍ×８．２２ｍｍ、チップ２Ａの中央に一列に配置された端子（ボンディングパッド）の数は６４ピン、端子のピッチは０．０８ｍｍである。一方、マイクロプロセッサが形成されたチップ２Ｃのサイズは、一例として６．８４ｍｍ×６．８４ｍｍ、チップ２Ｃの４辺に配置された端子数は２５６ピン、端子のピッチは０．０６５ｍｍである。この場合、２種類のチップ２Ａ、２Ｃのグリッドアレイ指数を計算すると、マイクロプロセッサが形成されたチップ２Ｃの方が小さい。従って、本実施形態では、チップ２Ｃをワイヤボンディング方式で実装し、チップ２Ａをフリップチップ方式で実装する。   The size of the chip 2A on which the DRAM is formed is, for example, 4.66 mm × 8.22 mm, the number of terminals (bonding pads) arranged in a row in the center of the chip 2A is 64 pins, and the terminal pitch is 0.08 mm. is there. On the other hand, the size of the chip 2C on which the microprocessor is formed is, for example, 6.84 mm × 6.84 mm, the number of terminals arranged on the four sides of the chip 2C is 256 pins, and the terminal pitch is 0.065 mm. In this case, when the grid array index of the two types of chips 2A and 2C is calculated, the chip 2C in which the microprocessor is formed is smaller. Therefore, in this embodiment, the chip 2C is mounted by the wire bonding method, and the chip 2A is mounted by the flip chip method.

図２７は、ＤＲＡＭが形成されたチップ２Ａの主面に半田バンプ２０を形成した状態を示す平面図である。図示のように、半田バンプ２０は、チップ２Ａの主面にアレイ状に配置されている。ボンディングパッド１３と半田バンプ２０とは、Ｃｕ配線２１を介して電気的に接続されている。Ｃｕ配線２１は、ボンディングパッド１３のピッチを半田バンプ２０のピッチに変換するインターポーザとして機能し、これによって半田バンプ２０のピッチをボンディングパッド１３のピッチよりも広くすることができる。   FIG. 27 is a plan view showing a state in which solder bumps 20 are formed on the main surface of the chip 2A on which the DRAM is formed. As shown in the figure, the solder bumps 20 are arranged in an array on the main surface of the chip 2A. The bonding pad 13 and the solder bump 20 are electrically connected via the Cu wiring 21. The Cu wiring 21 functions as an interposer that converts the pitch of the bonding pads 13 into the pitch of the solder bumps 20, whereby the pitch of the solder bumps 20 can be made wider than the pitch of the bonding pads 13.

上記Ｃｕ配線２１および半田バンプ２０は、ウエハレベルＣＳＰ技術を利用し、ウエハプロセスの最終工程で形成される。すなわち、図２８に示すように、Ｃｕ配線２１は、ウエハ１４の表面保護膜２２上にポリイミド樹脂などの有機絶縁膜２３を形成した後、この有機絶縁膜２３上に電解メッキ法などを用いて形成される。Ｃｕ配線２１とボンディングパッド１３は、ボンディングパッド１３上の有機絶縁膜２３に形成したスルーホール２４を通じて電気的に接続される。また、半田バンプ２０は、Ｃｕ配線２１の一端である電極パッド２１ａの表面にスクリーン印刷法で半田ペーストを印刷し、次に、ウエハ１４を加熱してこの半田ペーストを溶融させることによって形成される。半田バンプ２０は、例えば２重量％のＳｎを含むＰｂ−Ｓｎ合金（液相線温度３２０℃〜３２５℃）などで構成される。   The Cu wiring 21 and the solder bump 20 are formed in the final step of the wafer process using wafer level CSP technology. That is, as shown in FIG. 28, the Cu wiring 21 is formed by forming an organic insulating film 23 such as a polyimide resin on the surface protective film 22 of the wafer 14 and then using an electrolytic plating method or the like on the organic insulating film 23. It is formed. The Cu wiring 21 and the bonding pad 13 are electrically connected through a through hole 24 formed in the organic insulating film 23 on the bonding pad 13. The solder bump 20 is formed by printing a solder paste on the surface of the electrode pad 21a, which is one end of the Cu wiring 21, by a screen printing method, and then heating the wafer 14 to melt the solder paste. . The solder bump 20 is made of, for example, a Pb—Sn alloy (liquidus temperature 320 ° C. to 325 ° C.) containing 2% by weight of Sn.

次に、図２９に示すように、マルチ配線基板１００のそれぞれのパッケージ基板形成領域に２個のチップ２Ａ、２Ａをフェイスダウン方式で位置決めした後、マルチ配線基板１００を加熱して半田バンプ２０をリフローすることにより、チップ２Ａ、２Ａの半田バンプ２０とマルチ配線基板１００の配線５とを電気的に接続する。   Next, as shown in FIG. 29, after positioning the two chips 2A and 2A in the respective package substrate formation regions of the multi-wiring board 100 by the face-down method, the multi-wiring board 100 is heated to form the solder bumps 20. By reflowing, the solder bumps 20 of the chips 2A and 2A and the wiring 5 of the multi-wiring substrate 100 are electrically connected.

次に、図３０に示すように、２個のチップ２Ａ、２Ａの上にチップ２Ｃを搭載する。チップ２Ａ、２Ａとチップ２Ｃとの接着は、前記実施の形態１と同様、チップ２Ｃの裏面に貼り付けた接着剤７を使用する。   Next, as shown in FIG. 30, the chip 2C is mounted on the two chips 2A and 2A. For bonding the chips 2A, 2A and the chip 2C, the adhesive 7 attached to the back surface of the chip 2C is used as in the first embodiment.

図３１は、チップ２Ａの端子配列を示す平面図、図３２は、チップ２Ｃの端子配列を示す平面図である。図示のように、チップ２ＡのＤＱピンは、チップの主面の特定の箇所に集中して配置されており、チップ２ＣのＤＱピンも同様である。そこで、チップ２Ａ、２Ａの上にチップ２Ｃを搭載するときは、チップ２Ａ、２Ａとチップ２Ｃの共通するＤＱピンが最も近接するような位置にチップ２Ａ、２Ａ、２Ｃを配置するとよい。このようにすると、図３３に示すように、ＤＱピン同士を接続するＡｕワイヤ８の長さをほぼ等しくすることができるので、Ａｕワイヤ８の引き回し効率が向上する。図３４は、ＤＲＡＭが形成された４個のチップ２Ａの上にマイクロプロセッサが形成された１個のチップ２Ｃを搭載する時の最適な配置の例を示している。   FIG. 31 is a plan view showing the terminal arrangement of the chip 2A, and FIG. 32 is a plan view showing the terminal arrangement of the chip 2C. As shown in the drawing, the DQ pins of the chip 2A are concentrated on a specific portion of the main surface of the chip, and the DQ pins of the chip 2C are the same. Therefore, when the chip 2C is mounted on the chips 2A and 2A, the chips 2A, 2A and 2C may be arranged at positions where the DQ pins common to the chips 2A and 2A and the chip 2C are closest to each other. In this way, as shown in FIG. 33, the lengths of the Au wires 8 connecting the DQ pins can be made substantially equal, so that the routing efficiency of the Au wires 8 is improved. FIG. 34 shows an example of an optimal arrangement when mounting one chip 2C formed with a microprocessor on four chips 2A formed with DRAM.

次に、図３５に示すように、チップ２Ａ、２Ａの周辺部にディスペンサなどを使って液状のアンダーフィル樹脂６を供給した後、アンダーフィル樹脂６を加熱、硬化させることによって、チップ２Ａ、２Ａとマルチ配線基板１００の隙間、およびチップ２Ａとチップ２Ｂの隙間にアンダーフィル樹脂６を充填する。   Next, as shown in FIG. 35, after supplying the liquid underfill resin 6 to the peripheral portions of the chips 2A and 2A using a dispenser or the like, the underfill resin 6 is heated and cured, whereby the chips 2A and 2A. The underfill resin 6 is filled in the gap between the multi-wiring substrate 100 and the gap between the chip 2A and the chip 2B.

次に、図３６に示すように、マルチ配線基板１００をモールド金型（図示せず）に装着し、マルチ配線基板１００の主面全体を一括して樹脂封止した後、図３７に示すように、マルチ配線基板１００の裏面の電極パッド９に半田バンプ１１を接続する。図示は省略するが、その後、前記実施の形態１と同様の方法でマルチ配線基板１００を切断することにより、本実施形態のマルチチップモジュール（ＭＣＭ）が完成する。   Next, as shown in FIG. 36, the multi-wiring substrate 100 is mounted on a mold (not shown), and the entire main surface of the multi-wiring substrate 100 is collectively sealed with resin, and as shown in FIG. Next, the solder bumps 11 are connected to the electrode pads 9 on the back surface of the multi-wiring substrate 100. Although illustration is omitted, the multi-chip module (MCM) of this embodiment is completed by cutting the multi-wiring substrate 100 in the same manner as in the first embodiment.

以上、本発明者によってなされた発明を前記実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。   The invention made by the present inventor has been specifically described based on the above embodiment, but the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

前記実施の形態では、ワイヤボンディング方式で実装するチップ２Ｃをフリップチップ方式で実装するチップ２Ａ（または２Ｂ）の上に配置したが、パッケージ基板１の実装面積が大きくなっても差し支えないような場合は、図３８〜図４０あるいは図４１〜図４３に示すように、ワイヤボンディング方式で実装するチップ２Ｃをフリップチップ方式で実装するチップ２Ａ（または２Ｂ）の横に配置してもよい。図３８〜図４０に示す例は、実施の形態１で用いたチップ２Ａ、２Ｂ、２Ｃを組み合わせた例であり、図４１〜図４３に示す例は、実施の形態２で用いたチップ２Ａ、２Ｃを組み合わせた例である。   In the above embodiment, the chip 2C mounted by the wire bonding method is arranged on the chip 2A (or 2B) mounted by the flip chip method. However, the mounting area of the package substrate 1 may be increased. As shown in FIG. 38 to FIG. 40 or FIG. 41 to FIG. 43, the chip 2C mounted by the wire bonding method may be disposed beside the chip 2A (or 2B) mounted by the flip chip method. The example shown in FIGS. 38 to 40 is an example in which the chips 2A, 2B, and 2C used in the first embodiment are combined, and the example shown in FIGS. 41 to 43 is the chip 2A used in the second embodiment. This is an example of combining 2C.

また、図４４〜図５０に示すように、複数個のチップをパッケージ基板に実装する手段に代えて、パッケージ基板を実装するマザーボード２００に直接実装してもよい。図４４、図４５に示す例は、フリップフロップ方式で実装するチップ２Ａの端子をＡｕバンプ４で構成した例である。また、図４６、図４７に示す例は、フリップフロップ方式で実装するチップ２Ａの端子を半田バンプ２０で構成し、チップの主面にアレイ状に配置した例である。また、図４８〜図５０に示す例は、ワイヤボンディング方式で実装するチップ２Ｃをフリップチップ方式で実装するチップ２Ａの横に配置した例である。   As shown in FIGS. 44 to 50, instead of means for mounting a plurality of chips on a package substrate, they may be directly mounted on a mother board 200 on which the package substrate is mounted. The examples shown in FIGS. 44 and 45 are examples in which the terminals of the chip 2 </ b> A mounted by the flip-flop method are configured by Au bumps 4. The example shown in FIGS. 46 and 47 is an example in which the terminals of the chip 2A mounted by the flip-flop method are configured by the solder bumps 20 and arranged in an array on the main surface of the chip. The example shown in FIGS. 48 to 50 is an example in which the chip 2C mounted by the wire bonding method is arranged beside the chip 2A mounted by the flip chip method.

パッケージ基板上には、コンデンサや抵抗素子など、チップ以外の小型電子部品を実装することもできる。例えば、メモリチップの外周に沿ってチップコンデンサを搭載することにより、メモリチップの駆動時に生じるノイズを低減して高速動作を実現することができる。   Small electronic components other than chips, such as capacitors and resistor elements, can also be mounted on the package substrate. For example, by mounting a chip capacitor along the outer periphery of the memory chip, noise generated when the memory chip is driven can be reduced and high-speed operation can be realized.

本発明は、チップを実装するパッケージ基板としてビルドアップ基板の使用を排除するものではない。ビルドアップ基板の使用する場合でも、本発明を適用することにより、配線ピッチのより広いビルドアップ基板を使用することができるので、配線ピッチの狭い高価なビルドアップ基板を使用する場合に比べてマルチチップモジュールの製造コストを低減することができる。   The present invention does not exclude the use of a build-up substrate as a package substrate for mounting a chip. Even when a build-up board is used, by applying the present invention, a build-up board with a wider wiring pitch can be used. The manufacturing cost of the chip module can be reduced.

本発明は、配線基板上に端子ピッチの異なる複数種類の半導体チップを実装したマルチチップモジュール(ＭＣＭ)に利用することができる。   The present invention can be used for a multichip module (MCM) in which a plurality of types of semiconductor chips having different terminal pitches are mounted on a wiring board.

１ パッケージ基板
２ 半導体ウエハ
２Ａ、２Ｂ、２Ｃ 半導体チップ
３ モールド樹脂（第２封止樹脂）
４ Ａｕバンプ
５ 配線
６ アンダーフィル樹脂（第１封止樹脂）
６ａ 樹脂テープ
７ 接着剤
８ Ａｕワイヤ
９ ボンディングパッド
１０ 電極パッド
１１ 半田バンプ
１２ ソルダレジスト
１３ ボンディングパッド
１４ ウエハ
１５ ダイシングテープ
２０ 半田バンプ
２１ Ｃｕ配線
２１ａ 電極パッド
２２ 表面保護膜
２３ 有機絶縁膜
２４ スルーホール
１００ マルチ配線基板
１０１ 溝
１０２ ヒートツール
２００ マザーボード
Ｌ ダイシングライン DESCRIPTION OF SYMBOLS 1 Package substrate 2 Semiconductor wafer 2A, 2B, 2C Semiconductor chip 3 Mold resin (2nd sealing resin)
4 Au bump 5 Wiring 6 Underfill resin (first sealing resin)
6a Resin tape 7 Adhesive 8 Au wire 9 Bonding pad 10 Electrode pad 11 Solder bump 12 Solder resist 13 Bonding pad 14 Wafer 15 Dicing tape 20 Solder bump 21 Cu wiring 21a Electrode pad 22 Surface protection film 23 Organic insulating film 24 Through hole 100 Multi-wiring board 101 Groove 102 Heat tool 200 Motherboard L Dicing line

Claims (2)

表面、前記表面に形成された複数の配線、前記表面に形成され、かつ、前記複数の配線と電気的に接続され、かつ、第１ピッチで配置された複数の第１ボンディングパッド、および前記表面において前記複数の第１ボンディングパッドよりも前記表面の周縁部側に配置され、かつ、第２ピッチで配置された複数の第２ボンディングパッドを有する配線基板と、
第１集積回路、および前記配線基板の前記複数の第１ボンディングパッドと同じピッチで配置された複数の第１端子が形成された第１主面を有し、前記第１主面が前記配線基板の前記表面と対向するように、前記配線基板の前記表面上に搭載された第１半導体チップと、
前記第１半導体チップの前記複数の第１端子と、前記配線基板の前記複数の第１ボンディングパッドとを、それぞれ電気的に接続する複数のバンプ電極と、
第２集積回路、および複数の第２端子が形成された第２主面を有し、前記第２主面とは反対側の第２裏面が前記第１半導体チップの前記第１主面とは反対側の第１裏面と対向するように、前記第１半導体チップ上に積層された第２半導体チップと、
前記第２半導体チップの前記複数の第２端子と、前記配線基板の前記複数の第２ボンディングパッドとを、それぞれ電気的に接続する複数のワイヤと、
を含み、
前記複数の第１端子は、平面視において、前記第１半導体チップの前記第１主面における第１辺に沿って配置されており、
前記複数の第２端子は、平面視において、前記第２半導体チップの前記第２主面における第２辺に沿って配置されており、
前記複数の第２端子数の数は、前記複数の第１端子数の数よりも多く、
前記第２半導体チップの前記複数の第２端子のうち、前記第２辺に沿って互いに隣り合う第２端子間のピッチは、前記第１半導体チップの前記複数の第１端子のうち、前記第１辺に沿って互いに隣り合う第１端子間のピッチよりも狭いことを特徴とする半導体装置。 Surface, a plurality of wirings formed on the surface, a plurality of first bonding pads formed on the surface and electrically connected to the plurality of wirings and arranged at a first pitch, and the surface A wiring board having a plurality of second bonding pads arranged at a second pitch and arranged on the peripheral edge side of the surface from the plurality of first bonding pads;
A first integrated circuit; and a first main surface on which a plurality of first terminals arranged at the same pitch as the plurality of first bonding pads of the wiring substrate are formed, and the first main surface is the wiring substrate A first semiconductor chip mounted on the surface of the wiring board so as to face the surface of
A plurality of bump electrodes that electrically connect the plurality of first terminals of the first semiconductor chip and the plurality of first bonding pads of the wiring board;
A second integrated circuit and a second main surface on which a plurality of second terminals are formed, and a second back surface opposite to the second main surface is the first main surface of the first semiconductor chip. A second semiconductor chip stacked on the first semiconductor chip so as to face the first back surface on the opposite side;
A plurality of wires that electrically connect the plurality of second terminals of the second semiconductor chip and the plurality of second bonding pads of the wiring board;
Including
The plurality of first terminals are arranged along a first side of the first main surface of the first semiconductor chip in plan view,
The plurality of second terminals are arranged along a second side of the second main surface of the second semiconductor chip in plan view,
The number of the plurality of second terminals is greater than the number of the plurality of first terminals,
Among the plurality of second terminals of the second semiconductor chip, the pitch between the second terminals adjacent to each other along the second side is the first of the plurality of first terminals of the first semiconductor chip. A semiconductor device characterized by being narrower than a pitch between first terminals adjacent to each other along one side. 前記第１半導体チップの前記第１主面には、ＤＲＡＭまたはフラッシュメモリが形成されており、
前記第２半導体チップの前記第２主面には、マイクロプロセッサが形成されていることを特徴とする請求項１記載の半導体装置。 DRAM or flash memory is formed on the first main surface of the first semiconductor chip,
The semiconductor device according to claim 1, wherein a microprocessor is formed on the second main surface of the second semiconductor chip.
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Publication number Priority date Publication date Assignee Title
JPS5737867A (en) * 1980-08-18 1982-03-02 Mitsubishi Electric Corp Semiconductor device
JPS62122359U (en) * 1986-01-24 1987-08-03
WO1998025304A1 (en) * 1996-12-04 1998-06-11 Hitachi, Ltd. Semiconductor device
JPH11219984A (en) * 1997-11-06 1999-08-10 Sharp Corp Semiconductor device package, its manufacture and circuit board therefor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5737867A (en) * 1980-08-18 1982-03-02 Mitsubishi Electric Corp Semiconductor device
JPS62122359U (en) * 1986-01-24 1987-08-03
WO1998025304A1 (en) * 1996-12-04 1998-06-11 Hitachi, Ltd. Semiconductor device
JPH11219984A (en) * 1997-11-06 1999-08-10 Sharp Corp Semiconductor device package, its manufacture and circuit board therefor

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