JP2011082408A

JP2011082408A - Semiconductor device, and method for manufacturing the same

Info

Publication number: JP2011082408A
Application number: JP2009234819A
Authority: JP
Inventors: Kazuhiro Masuda; 員拓増田
Original assignee: Casio Computer Co Ltd
Current assignee: Casio Computer Co Ltd
Priority date: 2009-10-09
Filing date: 2009-10-09
Publication date: 2011-04-21
Anticipated expiration: 2029-10-09
Also published as: JP5226639B2

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a crack of a solder ball generated due to a step part between the upper surface of a sealing film and that of an electrode for external connection. <P>SOLUTION: The upper surface 16a of a sealing film 16 is formed at a high position relative to the upper surfaces 20a of electrodes 20 for external connection, and step parts are formed at boundaries between both the members. A buffer layer 31 is formed on the upper surface 16a of the sealing film 16 and on side faces of the step parts with the electrodes 20 for external connection on the sealing film 16. Regions of the buffer layer 31 corresponding to the step parts are formed into inclined surfaces 31b. Solder balls jointed to the upper surfaces of the electrodes 20 for external connection are formed tightly on the inclined surfaces 31b of the buffer layer 31. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

この発明は、半導体装置およびその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof.

ＣＳＰ（Chip Size Package）といわれる半導体装置を製造する方法として、例えば、次のような製造方法が知られている。半導体ウエハの各半導体形成領域に形成された集積回路に接続される柱状の外部接続用電極の周囲に封止膜を形成する。封止膜は、いったん、外部接続用電極に上面を覆って半導体基板上の全面に塗布される。そして、封止膜の上部を研削して柱状の外部接続用電極の上面を露出する。露出された外部接続用電極の上面に半田ボールを搭載しリフロー処理により外部接続用電極に接合する。 As a method for manufacturing a semiconductor device called CSP (Chip Size Package), for example, the following manufacturing method is known. A sealing film is formed around a columnar external connection electrode connected to an integrated circuit formed in each semiconductor formation region of the semiconductor wafer. The sealing film is once applied to the entire surface of the semiconductor substrate so as to cover the upper surface of the external connection electrode. Then, the upper part of the sealing film is ground to expose the upper surface of the columnar external connection electrode. Solder balls are mounted on the exposed upper surfaces of the external connection electrodes and joined to the external connection electrodes by reflow processing.

上記の方法における封止膜を研削する工程において、外部接続用電極の上面にダレが生じ、このダレのために、外部接続用電極の上面に形成する半田ボールの形状が変形し、回路基板等の外部電子機器の端子との接合強度が不足することがある。この対応として、外部接続用電極の上面に生じたダレを除去する方法が採用されている（例えば、特許文献１参照）。 In the step of grinding the sealing film in the above method, sagging occurs on the upper surface of the external connection electrode, and due to this sagging, the shape of the solder ball formed on the upper surface of the external connection electrode is deformed, and the circuit board or the like In some cases, the bonding strength with the terminal of the external electronic device is insufficient. As a countermeasure for this, a method of removing sagging generated on the upper surface of the external connection electrode is employed (see, for example, Patent Document 1).

特開２００１−１６８１２８号公報JP 2001-168128 A

上記において、外部接続用電極の上面に生じたダレを除去する方法としては、効率の面から、通常、ウエットエッチングによる方法が採用される。このダレ除去のためのウエットエッチングでは、外部接続用電極の上部を除去する。この際、ダレの除去を確実にするため、外部接続用電極の上部が封止膜の上面より明確に低くなるように行う。このため、封止膜の上面と外部接続用電極の上面との間に段差部が生じる。
この後、外部接続用電極上に半田ボールを形成する工程を行うのであるが、上記のような製造方法による場合には、例えば温度サイクル試験などの信頼性試験に於いて半田ボールに亀裂が生じ、あるいはさらに進展して破断が生じることがあった。 In the above, as a method of removing the sag generated on the upper surface of the external connection electrode, a method by wet etching is usually employed from the viewpoint of efficiency. In the wet etching for removing the sagging, the upper portion of the external connection electrode is removed. At this time, in order to ensure the removal of the sagging, the upper part of the external connection electrode is set to be clearly lower than the upper surface of the sealing film. For this reason, a step portion is formed between the upper surface of the sealing film and the upper surface of the external connection electrode.
Thereafter, a process of forming solder balls on the external connection electrodes is performed. However, in the case of the manufacturing method as described above, cracks occur in the solder balls in reliability tests such as a temperature cycle test. In some cases, breakage occurred due to further progress.

本発明者が分析をしたところ、半田ボールに生じる亀裂または破断は、封止膜の上面と外部接続用電極の上面との間の段差部に集中していることが確認された。つまり、従来の半導体装置の構造およびその製造方法では、封止膜の上面と外部接続用電極の上部との間の段差部における封止膜の角部によって外部接続用電極に集中応力が生じ、外部接続用電極に亀裂または破断が生じるという課題がある。 As a result of analysis by the present inventor, it was confirmed that the cracks or breaks generated in the solder balls are concentrated on the step portion between the upper surface of the sealing film and the upper surface of the external connection electrode. That is, in the structure of the conventional semiconductor device and the manufacturing method thereof, concentrated stress is generated in the external connection electrode by the corner portion of the sealing film at the step portion between the upper surface of the sealing film and the upper portion of the external connection electrode. There exists a subject that a crack or a fracture | rupture arises in the electrode for external connection.

請求項１に記載の発明に係る半導体装置は、接続パッドを有する半導体基板と、
前記半導体基板上に形成され、前記接続パッドの一部を露出する開口部を有する絶縁膜と、前記接続パッドに電気的に接続された外部接続用電極と、前記外部接続用電極の外周側面の周囲における前記絶縁膜上に形成され、前記外部接続用電極の上面よりも高い位置に上面を有し、前記外部接続用電極の上面を露出する開口部を有する封止膜と、前記外部接続用電極の上面の中央部を露出する開口部を有し、少なくとも前記外部接続用電極の上面の周縁部およびその周囲の前記封止膜を覆う緩衝層と、を具備することを特徴とする。
請求項２に記載の発明に係る半導体装置は、請求項１に記載の半導体装置において、前記緩衝層の開口部から露出された前記外部接続用電極の上面の中央部上に半田ボールが接合されていることを特徴とする。
請求項３に記載の発明に係る半導体装置は、請求項２に記載の半導体装置において、前記半田ボールは前記外部接続用電極の中央部から、前記外部接続用電極の外周と前記封止膜との境界面よりも外側の領域の前記緩衝層上に亘って形成されていることを特徴とする。
請求項４に記載の発明に係る半導体装置は、請求項１乃至３のいずれか１項に記載の半導体装置において、前記緩衝層は、前記封止膜の角部から外部接続用電極の上面の周縁部に亘り、下降する傾斜面を有し、前記緩衝槽の傾斜面と前記外部接続用電極の上面との成す角は鋭角であることを特徴とする。請求項５に記載の発明に係る半導体装置は、請求項１乃至４のいずれか１項に記載の半導体装置において、前記絶縁膜上に前記接続パッドに接続された配線が形成され、前記外部接続用電極は前記配線上に形成されていることを特徴とする。
請求項６に記載の発明に係る半導体装置は、請求項１乃至５のいずれか１項に記載の半導体装置において、前記緩衝層の開口部から露出された前記外部接続用電極の上面の中央部上にフラックス層または表面処理層が形成されていることを特徴とする。
請求項７に記載の発明に係る半導体装置は、請求項１乃至６のいずれか１項に記載の半導体装置において、前記緩衝層はポリイミド系樹脂、エポキシ系樹脂またはＰＢＯ系樹脂のいずれかにより形成されていることを特徴とする。
請求項８に記載の発明に係る半導体装置は、請求項１乃至７のいずれか１項に記載の半導体装置において、前記緩衝層と前記封止膜との間に接着剤層が設けられていることを特徴とする。
請求項９に記載の発明に係る半導体装置は、請求項１乃至７のいずれか１項に記載の半導体装置において、前記緩衝層と前記封止膜との間に密着力向上膜が設けられていることを特徴とする。
請求項１０に記載の発明に係る半導体装置の製造方法は、請求項１、３、８、９のいずれか１項に記載の半導体装置において、前記封止膜はシリカのフィラーが含まれた、エポキシ樹脂またはポリイミド系樹脂のいずれかにより形成されていることを特徴とする。
請求項１１に記載の発明に係る半導体装置の製造方法は、半導体基板上に、外部接続用電極と、前記外部接続用電極の外周側面の周囲における前記半導体基板上に形成され、前記外部接続用電極の上面よりも高い位置に上面を有し、前記外部接続用電極の上面を露出する開口部を有する封止膜が形成された半導体基板組立体を準備する工程と、少なくとも前記外部接続用電極の上面の周縁部およびその周囲の前記封止膜上に形成され、前記外部接続用電極の上面の中央部を露出する開口部を有する緩衝層を形成する工程と、を具備することを特徴とする。
請求項１２に記載の発明に係る半導体装置の製造方法は、請求項１１に記載の半導体装置の製造方法において、さらに、前記外部接続用電極の上面に接合され、前記緩衝層の少なくとも前記外部接続用電極の上面の外周部に密着した半田ボールを形成する工程を具備することを特徴とする。
請求項１３に記載の発明に係る半導体装置の製造方法は、請求項１２に記載の半導体装置の製造方法において、前記半田ボールを、前記外部接続用電極の外周側面の周囲の前記封止膜上に形成され前記絶縁膜上に密着するように形成することを特徴とする。
請求項１４に記載の発明に係る半導体装置の製造方法は、請求項１１乃至１３のいずれかに１項に記載の半導体装置の製造方法において、前記緩衝層を形成する工程は、スピンコーティング法、スキャン塗布法またはインジェット塗布法により前記封止膜の上面および前記外部接続用電極の上面の全体に前記緩衝層を形成し、その後、前記緩衝層に、前記外部接続用電極の上面の中央部を露出する開口部を形成する工程を含むことを特徴とする。
請求項１５に記載の発明に係る半導体装置の製造方法は、請求項１０乃至１３のいずれか１項に記載の半導体装置の製造方法において、前記緩衝層は、前記封止膜の角部から外部接続用電極の上面の周縁部に亘り、下降する傾斜面を有し、前記緩衝槽の傾斜面と前記外部接続用電極の上面との成す角は鋭角であることを特徴とする。
請求項１６に記載の発明に係る半導体装置の製造方法は、請求項１１乃至１５のいずれか１項に記載の半導体装置の製造方法において、前記緩衝層を形成する工程の後、前記半田ボールを形成する工程の前に、前記外部接続用電極の中央部にフラックス層または表面処理層を形成する工程を含むことを特徴とする。
請求項１７に記載の発明に係る半導体装置の製造方法は、請求項１６に記載の半導体装置の製造方法において、前記半田ボールを形成する工程は、前記外部接続用電極の上面の中央部上に形成された前記フラックス層上または前記表面処理層上に半田ボールを搭載する工程と、前記半田ボールが搭載された半導体基板組立体をリフロー処理して前記半田ボールを前記緩衝層の開口部周縁部に密着する工程とを含むことを特徴とする。
請求項１８に記載の発明に係る半導体装置の製造方法は、請求項１２乃至１７のいずれか１項に記載の半導体装置において、前記緩衝層と前記封止膜との間に接着剤層を形成する工程を含むことを特徴とする。
請求項１９に記載の発明に係る半導体装置の製造方法は、請求項１２乃至１７のいずれか１項に記載の半導体装置において、前記緩衝層と前記封止膜との間に密着力向上膜を形成する工程を含むことを特徴とする。
請求項２０に記載の発明に係る半導体装置の製造方法は、接続パッドを有する半導体基板を準備する工程と、前記半導体基板上に前記接続パッドを露出する開口部を有する絶縁膜を形成する工程と、前記絶縁膜上に、前記接続パッドに接続された配線を形成する工程と、前記配線に接続された外部接続用電極を形成する工程と、その上面が、前記外部接続用電極の上面よりも高い位置となるように封止膜を形成する工程と、前記封止膜の上面上および前記外部接続用電極の上面上に緩衝層を形成する工程と、前記緩衝層における前記外部接続用電極の上面の中央部に対応する領域を除去する工程と、を具備することを特徴とする。
請求項２１に記載の発明に係る半導体装置の製造方法は、請求項１９に記載の半導体装置の製造方法において、さらに、前記外部接続用電極の上面の中央部にフラックスを被着する工程と、前記フラックス上に半田ボールを搭載する工程と、前記外部接続用電極の上面の中央部に半田ボールが搭載された半導体基板をリフロー処理して、前記半田ボールを、少なくとも前記外部接続用電極の上面の周縁部上に形成された前記緩衝層の部分に密着する工程とを具備することを特徴とする。 A semiconductor device according to claim 1 is a semiconductor substrate having a connection pad;
An insulating film formed on the semiconductor substrate and having an opening exposing a part of the connection pad; an external connection electrode electrically connected to the connection pad; and an outer peripheral side surface of the external connection electrode A sealing film formed on the insulating film in the periphery, having an upper surface at a position higher than the upper surface of the external connection electrode, and having an opening that exposes the upper surface of the external connection electrode; and the external connection It has an opening part which exposes the center part of the upper surface of an electrode, and comprises the buffer layer which covers at least the peripheral part of the upper surface of the electrode for external connection, and the surrounding sealing film.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein a solder ball is joined to a central portion of the upper surface of the external connection electrode exposed from the opening of the buffer layer. It is characterized by.
A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the second aspect, wherein the solder ball is formed from the center of the external connection electrode, the outer periphery of the external connection electrode, and the sealing film. It is formed over the buffer layer in a region outside the boundary surface.
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the buffer layer is formed on a top surface of the external connection electrode from a corner of the sealing film. It has an inclined surface that descends over the peripheral edge, and the angle formed by the inclined surface of the buffer tank and the upper surface of the external connection electrode is an acute angle. A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein a wiring connected to the connection pad is formed on the insulating film, and the external connection The working electrode is formed on the wiring.
A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the central portion of the upper surface of the external connection electrode is exposed from the opening of the buffer layer. A flux layer or a surface treatment layer is formed thereon.
A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to any one of the first to sixth aspects, wherein the buffer layer is formed of any one of a polyimide resin, an epoxy resin, and a PBO resin. It is characterized by being.
The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to any one of the first to seventh aspects, wherein an adhesive layer is provided between the buffer layer and the sealing film. It is characterized by that.
A semiconductor device according to a ninth aspect of the present invention is the semiconductor device according to any one of the first to seventh aspects, wherein an adhesion improving film is provided between the buffer layer and the sealing film. It is characterized by being.
The method of manufacturing a semiconductor device according to claim 10 is the semiconductor device according to any one of claims 1, 3, 8, and 9, wherein the sealing film includes a silica filler. It is formed of either epoxy resin or polyimide resin.
According to a eleventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: an external connection electrode; and an external connection electrode formed on the semiconductor substrate around an outer peripheral side surface of the external connection electrode. Preparing a semiconductor substrate assembly having a sealing film having an upper surface at a position higher than the upper surface of the electrode and having an opening exposing the upper surface of the external connection electrode; and at least the external connection electrode Forming a buffer layer having an opening that is formed on a peripheral portion of the upper surface of the substrate and on the sealing film around the periphery and exposes a central portion of the upper surface of the external connection electrode. To do.
A semiconductor device manufacturing method according to a twelfth aspect of the present invention is the semiconductor device manufacturing method according to the eleventh aspect, wherein the semiconductor device is further bonded to the upper surface of the external connection electrode, and at least the external connection of the buffer layer. And forming a solder ball in close contact with the outer peripheral portion of the upper surface of the electrode for use.
A semiconductor device manufacturing method according to a thirteenth aspect of the present invention is the semiconductor device manufacturing method according to the twelfth aspect of the present invention, in which the solder ball is placed on the sealing film around the outer peripheral side surface of the external connection electrode. And formed in close contact with the insulating film.
A method for manufacturing a semiconductor device according to a fourteenth aspect of the present invention is the method for manufacturing a semiconductor device according to any one of the eleventh to thirteenth aspects, wherein the step of forming the buffer layer includes a spin coating method, The buffer layer is formed on the entire top surface of the sealing film and the top surface of the external connection electrode by a scan coating method or an inject coating method, and then the central portion of the top surface of the external connection electrode is formed on the buffer layer. And a step of forming an opening exposing the surface.
A semiconductor device manufacturing method according to a fifteenth aspect of the present invention is the semiconductor device manufacturing method according to any one of the tenth to thirteenth aspects, wherein the buffer layer is externally provided from a corner of the sealing film. It has an inclined surface that descends over the peripheral edge of the upper surface of the connection electrode, and the angle formed by the inclined surface of the buffer tank and the upper surface of the external connection electrode is an acute angle.
A method for manufacturing a semiconductor device according to a sixteenth aspect of the present invention is the method for manufacturing a semiconductor device according to any one of the eleventh to fifteenth aspects, wherein the solder ball is formed after the step of forming the buffer layer. Before the step of forming, a step of forming a flux layer or a surface treatment layer at the center of the external connection electrode is included.
The method for manufacturing a semiconductor device according to claim 17 is the method for manufacturing a semiconductor device according to claim 16, wherein the step of forming the solder ball is performed on a central portion of the upper surface of the external connection electrode. A step of mounting solder balls on the formed flux layer or on the surface treatment layer, and a reflow treatment of the semiconductor substrate assembly on which the solder balls are mounted, so that the solder balls are moved to the periphery of the opening of the buffer layer. And a step of closely contacting the substrate.
The semiconductor device manufacturing method according to claim 18 is the semiconductor device according to any one of claims 12 to 17, wherein an adhesive layer is formed between the buffer layer and the sealing film. Including the step of:
A semiconductor device manufacturing method according to a nineteenth aspect of the present invention is the semiconductor device according to any one of the twelfth to seventeenth aspects, wherein an adhesion improving film is provided between the buffer layer and the sealing film. A step of forming.
A method of manufacturing a semiconductor device according to claim 20 includes a step of preparing a semiconductor substrate having a connection pad, and a step of forming an insulating film having an opening exposing the connection pad on the semiconductor substrate. A step of forming a wiring connected to the connection pad on the insulating film; a step of forming an external connection electrode connected to the wiring; and an upper surface of the wiring is connected to the upper surface of the external connection electrode. Forming a sealing film so as to be higher, forming a buffer layer on the upper surface of the sealing film and on the upper surface of the external connection electrode, and forming the external connection electrode in the buffer layer And a step of removing a region corresponding to the central portion of the upper surface.
The method for manufacturing a semiconductor device according to claim 21 is the method for manufacturing a semiconductor device according to claim 19, further comprising the step of depositing a flux on a central portion of the upper surface of the external connection electrode; A step of mounting solder balls on the flux; and a reflow treatment of a semiconductor substrate on which the solder balls are mounted at the center of the upper surface of the external connection electrodes, so that the solder balls are at least the upper surfaces of the external connection electrodes. And a step of closely contacting a portion of the buffer layer formed on the peripheral edge of the substrate.

この発明によれば、外部接続用電極の上面の周縁部およびその周囲の封止膜を覆う緩衝層を設けたことにより、構造端部に於いて集中的に半田ボールに亀裂または破断が生じるのを防止することができ、信頼性の高い構造を提供することができる。 According to the present invention, by providing the buffer layer covering the peripheral edge portion of the upper surface of the external connection electrode and the surrounding sealing film, the solder ball is intensively cracked or broken at the structure end portion. Can be prevented, and a highly reliable structure can be provided.

この発明の半導体装置の一例としての実施形態１に関する拡大断面図。1 is an enlarged cross-sectional view relating to Embodiment 1 as an example of a semiconductor device of the present invention. 図１に図示された半導体装置を得る前の半導体ウエハの平面図。FIG. 2 is a plan view of a semiconductor wafer before obtaining the semiconductor device illustrated in FIG. 1. 図２の領域Ａの拡大平面図。The enlarged plan view of the area | region A of FIG. 実施形態１の製造方法に関し、最初の工程を説明するための拡大断面図。The expanded sectional view for demonstrating the first process regarding the manufacturing method of Embodiment 1. FIG. 図４に続く工程を説明するための拡大断面図。FIG. 5 is an enlarged cross-sectional view for explaining a process following FIG. 4. 図５に続く工程を説明するための拡大断面図。FIG. 6 is an enlarged cross-sectional view for explaining a process following FIG. 5. 図６に続く工程を説明するための拡大断面図。FIG. 7 is an enlarged cross-sectional view for explaining a process following FIG. 6. 図７に続く工程を説明するための拡大断面図。FIG. 8 is an enlarged cross-sectional view for explaining a process following FIG. 7. 図８に続く工程を説明するための拡大断面図。FIG. 9 is an enlarged cross-sectional view for explaining a process following FIG. 8. 図９に続く工程を説明するための拡大断面図。FIG. 10 is an enlarged cross-sectional view for explaining a process following FIG. 9. 図１０に続く工程を説明するための拡大断面図。FIG. 11 is an enlarged cross-sectional view for explaining a process following FIG. 10. 図１１に続く工程を説明するための拡大断面図。FIG. 12 is an enlarged cross-sectional view for explaining a process following FIG. 11. 図１２に続く工程を説明するための拡大断面図。FIG. 13 is an enlarged cross-sectional view for explaining a process following FIG. 12. 図１３に続く工程を説明するための拡大断面図。FIG. 14 is an enlarged cross-sectional view for explaining a process following FIG. 13. この発明の半導体装置の実施形態２に関する拡大断面図。The expanded sectional view regarding Embodiment 2 of the semiconductor device of this invention. この発明の半導体装置の実施形態３に関する拡大断面図。The expanded sectional view regarding Embodiment 3 of the semiconductor device of this invention.

（実施形態１）
以下、この発明の半導体装置について説明をする。
図１はこの発明の実施形態１に関する半導体装置１０の拡大断面図を示す。図２は、ダイシングによって半導体装置１０を得る前の半導体ウエハ１の平面図を示す。半導体装置１０は、半導体ウエハ１上に行方向および列方向に、マトリクス状に配列されて形成される。半導体装置１０は、後述する最終工程、すなわち、半田ボールを形成した後、半導体ウエハ１をダイシングライン２で切断することにより、同時に多数個が得られる。 (Embodiment 1)
The semiconductor device of the present invention will be described below.
1 is an enlarged sectional view of a semiconductor device 10 according to Embodiment 1 of the present invention. FIG. 2 is a plan view of the semiconductor wafer 1 before the semiconductor device 10 is obtained by dicing. The semiconductor devices 10 are formed on the semiconductor wafer 1 and arranged in a matrix in the row direction and the column direction. A large number of semiconductor devices 10 can be obtained at the same time by cutting the semiconductor wafer 1 along the dicing line 2 after forming a solder ball after the final process described later.

図３は、図２に二点鎖線で図示された半導体装置形成領域Ａ、すなわち、一対の行方向のダイシングライン２と一対の列方向のダイシングライン２により囲まれた領域内の拡大平面図を示す。
半導体装置形成領域Ａ内には、四つの側辺の各側辺に沿って接続パッド３が配列され、接続パッド３が配列された領域の内側には多数の外部接続用電極２０が配列されている。外部接続用電極２０は、通常は、半導体装置形成領域Ａの周側辺から中心に向かう環状に配列されるが、これとは異なるように配列されることもある。 FIG. 3 is an enlarged plan view of the semiconductor device formation region A illustrated by a two-dot chain line in FIG. 2, that is, a region surrounded by a pair of row direction dicing lines 2 and a pair of column direction dicing lines 2. Show.
In the semiconductor device formation region A, connection pads 3 are arranged along each of the four sides, and a large number of external connection electrodes 20 are arranged inside the region where the connection pads 3 are arranged. Yes. The external connection electrodes 20 are usually arranged in an annular shape from the peripheral side of the semiconductor device formation region A toward the center, but may be arranged differently.

各外部接続用電極２０と接続パッド３とは配線１５により接続されている。図示はしないが、各配線１５の外部接続用電極２０に対応する部分には、外部接続用電極２０の直径とほぼ同一サイズか、僅かに大きいサイズのパッド部が形成されており、各外部接続用電極２０は、配線１５のパッド部上に形成される。
以下、図１を参照して半導体装置１０の詳細について説明をするが、図面の明確化のため、図１においては、半導体装置形成領域Ａ内の各側辺近傍にそれぞれ１個の外部接続用電極２０が形成されているものとして説明する。 Each external connection electrode 20 and the connection pad 3 are connected by a wiring 15. Although not shown in the figure, a pad portion having a size substantially the same as or slightly larger than the diameter of the external connection electrode 20 is formed in a portion corresponding to the external connection electrode 20 of each wiring 15. The electrode 20 is formed on the pad portion of the wiring 15.
Hereinafter, the semiconductor device 10 will be described in detail with reference to FIG. 1. For clarity of the drawing, in FIG. 1, one external connection is provided near each side in the semiconductor device formation region A. Description will be made assuming that the electrode 20 is formed.

半導体装置１０は、例えば、シリコン基板などの半導体基板１１を有する。半導体基板１１の主面（上面）側には、集積回路１１ａが形成されている。半導体基板１１の主面上には、集積回路１１ａに接続された複数の接続パッド３が形成されている。接続パッド３は、例えば、アルミニウム系金属で形成されている。また、半導体基板１１の主面上には、接続パッド３の中央部を露出する開口部４ａを有する第１の絶縁膜４が形成されている。第1の絶縁膜４は、酸化シリコン、窒化シリコンなどの無機材料で形成されており、その側面は、半導体基板１１の側面から少し引っ込んだ位置にある。 The semiconductor device 10 includes a semiconductor substrate 11 such as a silicon substrate, for example. An integrated circuit 11 a is formed on the main surface (upper surface) side of the semiconductor substrate 11. On the main surface of the semiconductor substrate 11, a plurality of connection pads 3 connected to the integrated circuit 11a are formed. The connection pad 3 is made of, for example, an aluminum-based metal. A first insulating film 4 having an opening 4 a that exposes the central portion of the connection pad 3 is formed on the main surface of the semiconductor substrate 11. The first insulating film 4 is made of an inorganic material such as silicon oxide or silicon nitride, and its side surface is located slightly recessed from the side surface of the semiconductor substrate 11.

第１の絶縁膜４上に、第２の絶縁膜１２が形成されている。第２の絶縁膜１２は、ポリイミド系樹脂、ＰＢＯ（Poly-Phenylene-Benzobisoxazole；ポリパラフェニレンベンゾビスオキサゾール）系樹脂等の有機樹脂材料によって形成されている。第２の絶縁膜１２にも、接続パッド３の中央部を露出する開口部１２ａが形成されている。第２の絶縁膜１２の開口部１２ａは、第１の絶縁膜４の開口部４ａより小さいサイズに形成され、第１の絶縁膜４の開口部４ａ近傍を覆っている。但し、第２の絶縁膜１２の開口部１２ａは、第１の絶縁膜４の開口部４ａより大きくするか、または同一寸法とすることもできる。第２の絶縁膜１２の側面は、第１の絶縁膜４の側面と同一の位置にあり、第１の絶縁膜４の側面と共に半導体基板１１の側面から少し引っ込んでいる。 A second insulating film 12 is formed on the first insulating film 4. The second insulating film 12 is made of an organic resin material such as polyimide resin or PBO (Poly-Phenylene-Benzobisoxazole) resin. The second insulating film 12 is also formed with an opening 12 a that exposes the central portion of the connection pad 3. The opening 12 a of the second insulating film 12 is formed in a size smaller than the opening 4 a of the first insulating film 4 and covers the vicinity of the opening 4 a of the first insulating film 4. However, the opening 12a of the second insulating film 12 can be made larger than the opening 4a of the first insulating film 4 or have the same dimensions. The side surface of the second insulating film 12 is at the same position as the side surface of the first insulating film 4, and is slightly recessed from the side surface of the semiconductor substrate 11 together with the side surface of the first insulating film 4.

第２の絶縁膜１２上には、一端側が第２の絶縁膜１２の開口部１２ａを介して接続パッド３に接続された配線１５が形成されている。配線１５は、第１の配線１３と第１の配線１３上に形成された第２の配線１４の二層構造を有する。
第１の配線１３および第２の配線１４は、銅系金属により形成することができる。配線１５は、二層構造に限らず、三層以上の積層構造とすることもできる。その場合には、例えば、チタン（Ｔｉ）、タングステン（Ｗ）またはチタンとタングステンの合金などからなる金属層を１層以上介在させる。 On the second insulating film 12, a wiring 15 having one end connected to the connection pad 3 through the opening 12 a of the second insulating film 12 is formed. The wiring 15 has a two-layer structure of a first wiring 13 and a second wiring 14 formed on the first wiring 13.
The first wiring 13 and the second wiring 14 can be formed of a copper-based metal. The wiring 15 is not limited to a two-layer structure, but may have a three-layer or more laminated structure. In that case, for example, one or more metal layers made of titanium (Ti), tungsten (W), an alloy of titanium and tungsten, or the like are interposed.

配線１５のパッド部（図示せず）上には外部接続用電極２０が形成されている。外部接続用電極２０は平坦な上面２０ａを有し、例えば、直径４０〜５００μｍ、高さ４０〜８０μｍの円柱形状を有し、例えば、銅系金属で形成されている。
第２の絶縁膜１２上における外部接続用電極２０の外周側面の周囲領域には、
シリコン酸化物の球状物であるシリカ等のフィラーが含まれた、-エポキシ樹脂またはポリイミド系樹脂からなる封止膜１６が形成されている。封止膜１６の側面は、半導体基板１１の側面と同一位置にあり、第１の絶縁膜４および第２の絶縁膜１２の周囲における半導体基板１１上にも形成され、第１の絶縁膜４の側面および第２の絶縁膜１２の側面を覆っている。 An external connection electrode 20 is formed on a pad portion (not shown) of the wiring 15. The external connection electrode 20 has a flat upper surface 20a and has, for example, a cylindrical shape with a diameter of 40 to 500 μm and a height of 40 to 80 μm, and is made of, for example, a copper-based metal.
In the peripheral region of the outer peripheral side surface of the external connection electrode 20 on the second insulating film 12,
A sealing film 16 made of -epoxy resin or polyimide resin containing a filler such as silica, which is a silicon oxide sphere, is formed. The side surface of the sealing film 16 is located at the same position as the side surface of the semiconductor substrate 11 and is also formed on the semiconductor substrate 11 around the first insulating film 4 and the second insulating film 12. And the side surface of the second insulating film 12 are covered.

封止膜１６の外部接続用電極２０の上面２０ａに対応する領域は除去され、開口部１６ｂとなっている。封止膜１６の上面１６ａは、外部接続用電極２０の上面２０ａよりも高く形成されている。このため、封止膜１６の上面１６ａと外部接続用電極２０の上面２０ａとの境界には段差部が形成されている。この段差部のために、封止膜１６の外部接続用電極２０との境界には角部１６ｃが形成されている。 A region of the sealing film 16 corresponding to the upper surface 20a of the external connection electrode 20 is removed to form an opening 16b. The upper surface 16 a of the sealing film 16 is formed higher than the upper surface 20 a of the external connection electrode 20. For this reason, a step portion is formed at the boundary between the upper surface 16 a of the sealing film 16 and the upper surface 20 a of the external connection electrode 20. Due to this stepped portion, a corner portion 16 c is formed at the boundary between the sealing film 16 and the external connection electrode 20.

封止膜１６の上面１６ａ上には緩衝層３１が形成されている。緩衝層３１は外部接続用電極２０の上面２０ａの中央部を露出する開口部３１ａを有し、この開口部３１ａ以外はべた状のパターンを有する。従って、外部接続用電極２０の上面２０ａの周縁部および封止膜１６の外部接続用電極２０との境界に形成された角部１６ｃは、緩衝層３１によって覆われている。 A buffer layer 31 is formed on the upper surface 16 a of the sealing film 16. The buffer layer 31 has an opening 31a that exposes the central portion of the upper surface 20a of the external connection electrode 20, and has a solid pattern other than the opening 31a. Accordingly, the corner portion 16 c formed at the boundary between the peripheral portion of the upper surface 20 a of the external connection electrode 20 and the external connection electrode 20 of the sealing film 16 is covered with the buffer layer 31.

緩衝層３１は、開口部３１ａ近傍の周縁部、すなわち、封止膜１６の角部１６ｃから外部接続用電極２０の上面２０ａの周縁部に亘り、緩やかに下降する傾斜面３１ｂを有する。即ち、緩衝層３１の斜面と外部接続用電極２０の上面２０ａとの成す角は鋭角である。図１では、傾斜面３１ｂは断面円弧状として図示されている。しかし、これに限らず、傾斜面３１ｂはほぼ直線状の傾斜面としてもよい。
緩衝層３１は、ポリイミド系樹脂、エポキシ系樹脂、ＰＢＯ系樹脂等の有機樹脂または酸化シリコン等の無機材料によって、３μｍ〜２０μｍの厚さに形成される。 The buffer layer 31 has an inclined surface 31 b that gently descends from the peripheral edge in the vicinity of the opening 31 a, that is, from the corner 16 c of the sealing film 16 to the peripheral edge of the upper surface 20 a of the external connection electrode 20. That is, the angle formed by the inclined surface of the buffer layer 31 and the upper surface 20a of the external connection electrode 20 is an acute angle. In FIG. 1, the inclined surface 31b is illustrated as a circular arc shape in cross section. However, the present invention is not limited to this, and the inclined surface 31b may be a substantially linear inclined surface.
The buffer layer 31 is formed with a thickness of 3 μm to 20 μm by an organic resin such as polyimide resin, epoxy resin, PBO resin, or an inorganic material such as silicon oxide.

外部接続用電極２０の上面２０ａの中央部には半田ボール３５が接合されている。半田ボール３５は、外部接続用電極２０の外形(直径)より大きい外形(直径)を有し、緩衝層３１の開口部３１ａの周縁部、すなわち、緩衝層３１の傾斜面３１ｂに密着している。 A solder ball 35 is joined to the central portion of the upper surface 20a of the external connection electrode 20. The solder ball 35 has an outer shape (diameter) larger than the outer shape (diameter) of the external connection electrode 20 and is in close contact with the peripheral edge of the opening 31a of the buffer layer 31, that is, the inclined surface 31b of the buffer layer 31. .

このように、外部接続用電極２０の上面２０ａとの境界の段差部に形成された封止膜１６の角部１６ｃは緩衝層３１の傾斜面３１ｂにより覆われている。また、外部接続用電極２０の上面２０ａの中央部に接合された半田ボール３５は緩衝層３１の傾斜面３１ｂに密着している。このため、半田ボール３５が封止膜１６の角部１６ｃが当接することに起因する集中応力が半田ボール３５に生じることはない、あるいは、集中応力を大幅に低減することができる。それゆえ、半田ボール３５に亀裂または破断が生じることを防止することができる。 As described above, the corner 16 c of the sealing film 16 formed at the step portion at the boundary with the upper surface 20 a of the external connection electrode 20 is covered with the inclined surface 31 b of the buffer layer 31. In addition, the solder ball 35 bonded to the central portion of the upper surface 20 a of the external connection electrode 20 is in close contact with the inclined surface 31 b of the buffer layer 31. For this reason, the concentrated stress resulting from the contact of the corner 16c of the sealing film 16 with the solder ball 35 does not occur in the solder ball 35, or the concentrated stress can be greatly reduced. Therefore, it is possible to prevent the solder ball 35 from being cracked or broken.

次に、図４〜図１４を参照して図１に図示される本発明の実施形態１に関する半導体装置１０の製造方法の一例を説明する。
先ず、図４に図示されるように、半導体ウエハ１の各半導体装置形成領域Ａ内に、集積回路１１ａと、この集積回路１１ａに接続された接続パッド３と、接続パッド３の中央部を露出する開口部４ａを有し、半導体上ウエハ１の主面を覆う第１の絶縁膜４を形成する。接続パッド３は、例えば、アルミニウム系金属により形成される。第１の絶縁膜４を、半導体上ウエハ１の全面に、ＣＶＤ（Chemical Vapor Deposition）法により酸化シリコンまたは窒化シリコン等の無機材料を成膜した後、第１の開口部４ａを形成する。また、同時に、第１の絶縁膜４の側面がダイシングライン２より少し引っ込んだ位置となるように周囲を除去する。第１の絶縁膜４第１の開口部４ａおよび周囲のパターニングは、一般に知られたフォトリソグラフィ技術を用いて形成することができる。 Next, an example of a method for manufacturing the semiconductor device 10 according to the first embodiment of the present invention illustrated in FIG. 1 will be described with reference to FIGS.
First, as shown in FIG. 4, in each semiconductor device formation region A of the semiconductor wafer 1, an integrated circuit 11a, a connection pad 3 connected to the integrated circuit 11a, and a central portion of the connection pad 3 are exposed. A first insulating film 4 having an opening 4a to cover the main surface of the upper semiconductor wafer 1 is formed. The connection pad 3 is made of, for example, an aluminum metal. After the first insulating film 4 is formed on the entire surface of the semiconductor-on-wafer 1 with an inorganic material such as silicon oxide or silicon nitride by the CVD (Chemical Vapor Deposition) method, the first opening 4a is formed. At the same time, the periphery is removed so that the side surface of the first insulating film 4 is slightly recessed from the dicing line 2. The first insulating film 4 and the first opening 4a and the surrounding patterning can be formed by using a generally known photolithography technique.

次に、図５に図示されるように、第１の絶縁膜４上に第２の絶縁膜１２を形成する。ポリイミド系樹脂またはＰＢＯ系樹脂等の有機樹脂を、第１の絶縁膜４上および接続パッド３上にべた状に塗布する。塗布の方法は、スピンコーティング法、スクリーン印刷法、スキャン塗布法等、適宜な方法を用いることができる。有機樹脂をべた状に塗布した後、フォトリソグラフィ技術によって、接続パッド２の中央部を露出する開口部１２ａを形成すると共に、第２の絶縁膜１２の側面がダイシングライン２より少し引っ込んだ位置となるように周囲を除去する。この場合、第２の絶縁膜１２の開口部１２ａは、第１の絶縁膜４の開口部４ａよりも小さいサイズに形成する。 Next, as illustrated in FIG. 5, a second insulating film 12 is formed on the first insulating film 4. An organic resin such as polyimide resin or PBO resin is applied in a solid form on the first insulating film 4 and the connection pads 3. As a coating method, an appropriate method such as a spin coating method, a screen printing method, or a scan coating method can be used. After the organic resin is applied in a solid form, an opening 12a that exposes the central portion of the connection pad 2 is formed by photolithography, and the side surface of the second insulating film 12 is slightly retracted from the dicing line 2. Remove the surroundings. In this case, the opening 12 a of the second insulating film 12 is formed in a size smaller than the opening 4 a of the first insulating film 4.

次に、図６に図示されるように第１の配線１３および第２の配線１４を形成する。第２の絶縁膜１２上全面および第２の絶縁膜１２の開口部１２ａから露出する接続パッド３上にスパッタ法または無電解めっき法により、例えば、銅系金属からなる金属膜１３Ａを形成する。金属膜１３Ａは、ダイシングライン２およびその近傍に対応する半導体ウエハ１上にも形成される。この金属膜１３Ａ上に、フォトレジスト膜４１を塗布し、フォトリソグラフィ技術により、形成しようとする第２の配線１４の形状にパターニングする。そして、金属膜１３Ａを電流路として電解めっきを行い、第２の配線１４を形成する。この状態を図６に図示する。この後、フォトレジスト膜４１を剥離する。 Next, as shown in FIG. 6, the first wiring 13 and the second wiring 14 are formed. For example, a metal film 13A made of a copper-based metal is formed on the entire surface of the second insulating film 12 and on the connection pad 3 exposed from the opening 12a of the second insulating film 12 by sputtering or electroless plating. The metal film 13A is also formed on the semiconductor wafer 1 corresponding to the dicing line 2 and the vicinity thereof. A photoresist film 41 is applied on the metal film 13A and patterned into the shape of the second wiring 14 to be formed by photolithography. Then, the second wiring 14 is formed by performing electrolytic plating using the metal film 13A as a current path. This state is illustrated in FIG. Thereafter, the photoresist film 41 is peeled off.

次に、金属膜１３Ａ上および第２の配線１４上にフォトレジスト膜４２をべた状に塗布する。このフォトレジスト膜４２は、その上面が、形成する外部接続用電極５０の上面より高い位置となるように、外部接続用電極２０の高さより大きい厚さに形成する。そして、フォトレジスト膜４２を、フォトリソグラフィ技術により、形成しようとする外部接続用電極２０の形状にパターニングする。図７には、フォトレジスト膜４２に外部接続用電極２０の開口部４２ａが形成された状態が図示されている。 Next, a photoresist film 42 is applied onto the metal film 13A and the second wiring 14 in a solid form. The photoresist film 42 is formed to a thickness larger than the height of the external connection electrode 20 so that the upper surface thereof is positioned higher than the upper surface of the external connection electrode 50 to be formed. Then, the photoresist film 42 is patterned by the photolithography technique into the shape of the external connection electrode 20 to be formed. FIG. 7 shows a state in which the opening 42 a of the external connection electrode 20 is formed in the photoresist film 42.

次に、金属膜１３Ａを電流路として電解めっきを行い、フォトレジスト膜４２の開口部４２ａ内に外部接続用電極２０を形成する。この状態を図８に図示する。 Next, electrolytic plating is performed using the metal film 13 </ b> A as a current path to form the external connection electrode 20 in the opening 42 a of the photoresist film 42. This state is illustrated in FIG.

次に、フォトレジスト膜４２を剥離し、第２の配線１４をマスクとして、金属膜１３Ａをエッチングする。これにより第２の配線１４と同一パターンを有する第１の配線１３が形成される。つまり、第１の配線１３上に第２の配線１４が積層された配線１５が形成される。この状態を図９に図示する。 Next, the photoresist film 42 is peeled off, and the metal film 13A is etched using the second wiring 14 as a mask. Thereby, the first wiring 13 having the same pattern as the second wiring 14 is formed. That is, the wiring 15 in which the second wiring 14 is stacked on the first wiring 13 is formed. This state is illustrated in FIG.

次に、封止膜１６を形成する。封止膜１６は、図１０に図示するように、第２の絶縁膜１２上に外部接続用電極２０の上面２０ａを覆うように厚く形成する。封止膜１６は、第２の絶縁膜１２の周囲における半導体ウエハ１上にも形成される。そして、図１１に図示するように封止膜１６の上部を研削して、外部接続用電極２０の上面２０ａを露出させる。 Next, the sealing film 16 is formed. As illustrated in FIG. 10, the sealing film 16 is formed thick on the second insulating film 12 so as to cover the upper surface 20 a of the external connection electrode 20. The sealing film 16 is also formed on the semiconductor wafer 1 around the second insulating film 12. Then, as shown in FIG. 11, the upper portion of the sealing film 16 is ground to expose the upper surface 20 a of the external connection electrode 20.

外部接続用電極２０は、電解めっきにより形成するため、外部接続用電極２０は、１つ１つ高さが異なり、また、各外部接続用電極２０の上面２０ａにはかなり大きな凹凸が形成されている。従って、外部接続用電極２０を露出する工程では、封止膜１６と共に外部接続用電極２０の上部側を研削する。外部接続用電極２０は銅系金属などの軟質の金属で形成されているので、外部接続用電極２０の上面２０ａを研削する工程において、図１１には図示されていないが、外部接続用電極２０の上面２０ａの周囲にバリのようなダレができる。このダレを有する外部接続用電極２０の上面２０ａ上に半田ボールを搭載してリフロー処理をすると、半田ボールが異形となり、外部端子に半田付けした場合、十分な接合強度を得ることができない。 Since the external connection electrodes 20 are formed by electrolytic plating, the heights of the external connection electrodes 20 are different from one another, and a considerably large unevenness is formed on the upper surface 20a of each external connection electrode 20. Yes. Therefore, in the step of exposing the external connection electrode 20, the upper side of the external connection electrode 20 is ground together with the sealing film 16. Since the external connection electrode 20 is formed of a soft metal such as a copper-based metal, the external connection electrode 20 is not shown in FIG. 11 in the step of grinding the upper surface 20a of the external connection electrode 20. A sagging sagging can be formed around the upper surface 20a of the substrate. When a solder ball is mounted on the upper surface 20a of the external connection electrode 20 having the sagging and the reflow process is performed, the solder ball becomes deformed, and sufficient soldering strength cannot be obtained when soldered to an external terminal.

このため、次に、外部接続用電極２０の上面２０ａをエッチングしてダレと共に外部接続用電極２０の上部側を除去する。この工程により、外部接続用電極２０の上面２０ａが封止膜１６の上面１６ａより低くなり、封止膜１６と外部接続用電極２０との境界に段差部ができる。つまり、封止膜１６の外部接続用電極２０との境界に角部１６ｃが形成される。封止膜１６の上面１６ａと外部接続用電極２０の上面２０ａとの段差部の大きさは、１μｍ〜数μｍである。この状態を図１２に図示する。 Therefore, next, the upper surface 20a of the external connection electrode 20 is etched, and the upper side of the external connection electrode 20 is removed together with the sagging. By this step, the upper surface 20a of the external connection electrode 20 becomes lower than the upper surface 16a of the sealing film 16, and a step portion is formed at the boundary between the sealing film 16 and the external connection electrode 20. That is, the corner 16 c is formed at the boundary between the sealing film 16 and the external connection electrode 20. The size of the step portion between the upper surface 16a of the sealing film 16 and the upper surface 20a of the external connection electrode 20 is 1 μm to several μm. This state is illustrated in FIG.

図１２では、半導体ウエハ１上に、第２の絶縁膜１２上に形成された配線１５と、この配線１５上に形成された外部接続用電極２０と、外部接続用電極２０の外周側面の周囲における第２の絶縁膜１２上に形成され、外部接続用電極２０の上面２０ａよりも高い位置に上面１６ａを有し、外部接続用電極２０の上面２０ａを露出する開口部１６ｂを有する封止膜１６が形成された半導体基板組立体１０Ａが構成されている。 In FIG. 12, the wiring 15 formed on the second insulating film 12 on the semiconductor wafer 1, the external connection electrode 20 formed on the wiring 15, and the periphery of the outer peripheral side surface of the external connection electrode 20 And a sealing film having an upper surface 16a at a position higher than the upper surface 20a of the external connection electrode 20 and an opening 16b exposing the upper surface 20a of the external connection electrode 20. A semiconductor substrate assembly 10A in which 16 is formed is configured.

次に、半導体基板組立体１０Ａにおける封止膜１６の上面１６ａ上および外部接続用電極２０上面２０ａ上に緩衝層３１を形成する。緩衝層３１は、ポリイミド系樹脂、エポキシ刑樹脂、ＰＢＯ系樹脂等の有機樹脂材料または酸化シリコン等の無機材料により形成することができる。形成方法としては、スピンコーティング、スキャン塗布法、インクジェット塗布法等適宜な方法を採用することができる。無機材料により形成する場合は、酸化シリコン等の樹脂を用いて形成する。緩衝層３１の厚さは、限定することを意味するものではないが、３μｍ〜２０μｍ程度とすることが推奨される。また、緩衝層３１は感光性を有する材料を適用することが望ましいが、これもこれに限られるものではない。この状態を図１３に図示する。 Next, the buffer layer 31 is formed on the upper surface 16a of the sealing film 16 and the upper surface 20a of the external connection electrode 20 in the semiconductor substrate assembly 10A. The buffer layer 31 can be formed of an organic resin material such as polyimide resin, epoxy resin, PBO resin, or inorganic material such as silicon oxide. As a forming method, an appropriate method such as spin coating, scan coating, or ink jet coating can be employed. In the case of using an inorganic material, it is formed using a resin such as silicon oxide. The thickness of the buffer layer 31 is not meant to be limited, but is recommended to be about 3 μm to 20 μm. Moreover, although it is desirable to apply the photosensitive material to the buffer layer 31, this is not limited to this. This state is illustrated in FIG.

次に、フォトリソグラフィ技術により、緩衝層３１に外部接続用電極２０の上面２０ａの中央部を露出する開口部３１ａを形成する。そして、熱処理炉あるいはオーブンなどに収容して熱硬化処理を行う。この熱硬化処理により、緩衝層３１の開口部３１ａ近傍の周縁部、換言すれば、封止膜１６の角部１６ｃから外部接続用電極２０の上面２０ａの周縁部に対応する領域に、緩やかに下降する傾斜面３１ｂが形成される。この状態を図１４に図示する。 Next, an opening 31 a that exposes the central portion of the upper surface 20 a of the external connection electrode 20 is formed in the buffer layer 31 by photolithography. Then, it is housed in a heat treatment furnace or oven, and a heat curing process is performed. By this thermosetting treatment, the peripheral portion of the buffer layer 31 in the vicinity of the opening 31a, in other words, gently from the corner portion 16c of the sealing film 16 to the region corresponding to the peripheral portion of the upper surface 20a of the external connection electrode 20 A descending inclined surface 31b is formed. This state is illustrated in FIG.

次に、緩衝層３１の開口部３１ａから露出された外部接続用電極２０の上面２０ａ上にフラックス層を印刷法等により形成する（図示せず)。そして、このフラックス層上に半田ボール３５を搭載し、リフロー炉に収容してリフロー処理を行う。このリフロー処理により、半田ボール３５が外部接続用電極２０の上面２０ａに接合される。また、これと共に、半田ボール３５が緩衝層３１の傾斜面３１ｂに密着する。
上記におけるフラックス層の形成に替えて、金またはニッケルなどの半田にぬれ性を示す金属層を形成する表面処理を行うようにしてもよい。 Next, a flux layer is formed on the upper surface 20a of the external connection electrode 20 exposed from the opening 31a of the buffer layer 31 by a printing method or the like (not shown). Then, the solder balls 35 are mounted on the flux layer and accommodated in a reflow furnace to perform a reflow process. By this reflow process, the solder ball 35 is joined to the upper surface 20 a of the external connection electrode 20. At the same time, the solder ball 35 comes into close contact with the inclined surface 31 b of the buffer layer 31.
Instead of forming the flux layer in the above, a surface treatment for forming a metal layer showing wettability to solder such as gold or nickel may be performed.

この後は、図１４に二点鎖線で示すダイシングライン２で緩衝層３１、封止膜１６、第２の絶縁膜１２、第１の絶縁膜４および半導体ウエハ１を切断することにより、図１に図示されるような、半導体基板１１上に、外部接続用電極２０と、この外部接続用電極の周囲に形成された封止膜１６と、封止膜１６上および外部接続用電極２０の上面２０ａの周縁部に形成された緩衝層３１と、外部接続用電極２０の上面２０ａの中央部に接合され、緩衝層３１の傾斜面３１ｂに密着された半田ボール３５を有する半導体装置１０を、同時に多数個得ることができる。 Thereafter, the buffer layer 31, the sealing film 16, the second insulating film 12, the first insulating film 4, and the semiconductor wafer 1 are cut by the dicing line 2 shown by a two-dot chain line in FIG. The external connection electrode 20, the sealing film 16 formed around the external connection electrode, the upper surface of the sealing film 16 and the external connection electrode 20, as illustrated in FIG. The semiconductor device 10 having the buffer layer 31 formed on the peripheral portion of the external connection electrode 20a and the solder ball 35 bonded to the central portion of the upper surface 20a of the external connection electrode 20 and in close contact with the inclined surface 31b of the buffer layer 31 Many can be obtained.

なお、上記実施形態では、半導体ウエハ１を切断して個々の半導体装置を得る前に各半導体装置形成領域Ａ上の外部接続用電極２０上に半田ボール３５を形成する場合で説明した。しかし、半田ボール３５は、接合される外部電子機器の端子側に形成してもよい、この場合には、図１４に図示された状態で半導体ウエハをダイシングすればよい。
実施形態１においては、封止膜１６と半田ボール３５との間に緩衝層３１のみが介在されている構成であった。しかし、封止膜１６との接着力および密着力を増強するための層を介入させるようにしてもよい。以下に、そのような実施形態について記載する。 In the above embodiment, the case where the solder balls 35 are formed on the external connection electrodes 20 on each semiconductor device formation region A before the semiconductor wafer 1 is cut to obtain individual semiconductor devices has been described. However, the solder ball 35 may be formed on the terminal side of the external electronic device to be joined. In this case, the semiconductor wafer may be diced in the state shown in FIG.
In the first embodiment, only the buffer layer 31 is interposed between the sealing film 16 and the solder ball 35. However, a layer for enhancing the adhesive force and the adhesive force with the sealing film 16 may be interposed. Such an embodiment is described below.

（実施形態２)
図１５は本発明の半導体装置の実施形態２に関する拡大断面図である。
図１５に図示された半導体装置５０が、図１に図示された半導体装置１０と相違する点は、緩衝層３１と封止膜１６との間に接着剤層３６が形成されている点である。
その他の構成は実施形態１と同様であるので、同一部材に同一の図面参照番号を付してその説明を省略する。
接着剤層３６は、封止膜１６の上面１６ａおよび封止膜１６の角部１６ｃを含む外部接続用電極２０との段差部における側面に形成されている。緩衝層３１は、その接着剤層３６の上面全体を覆って形成されている。
接着剤材料としては、熱硬化性樹脂系、熱可塑性樹脂系の他、２液常温硬化樹脂系、エマルジョン系等がある。また、ホットメルト系やエラストマ系がある。これらのいずれを用いてもよい。 (Embodiment 2)
FIG. 15 is an enlarged sectional view of the semiconductor device according to the second embodiment of the present invention.
The semiconductor device 50 illustrated in FIG. 15 is different from the semiconductor device 10 illustrated in FIG. 1 in that an adhesive layer 36 is formed between the buffer layer 31 and the sealing film 16. .
Since other configurations are the same as those of the first embodiment, the same reference numerals are assigned to the same members, and descriptions thereof are omitted.
The adhesive layer 36 is formed on the side surface of the step portion between the upper surface 16 a of the sealing film 16 and the external connection electrode 20 including the corner portion 16 c of the sealing film 16. The buffer layer 31 is formed so as to cover the entire upper surface of the adhesive layer 36.
Examples of the adhesive material include a thermosetting resin system, a thermoplastic resin system, a two-component room temperature curing resin system, and an emulsion system. There are also hot melt systems and elastomer systems. Any of these may be used.

接着剤層３６を形成するには、液状あるいはシート状の接着剤を封止膜１６上および外部接続用電極２０の上面２０ａ上の全面に設け、外部接続用電極２０の上面２０ａの中央部に対応する領域をＩＣＰ−ＲＩＥ（Inductively Coupled Plasma-Reactive Ion Etching）法またはレーザビームの照射により除去する。
この後、実施形態１と同様な方法で、接着剤層３６上に緩衝層３１を形成すればよい。 In order to form the adhesive layer 36, a liquid or sheet-like adhesive is provided on the entire surface of the sealing film 16 and the upper surface 20 a of the external connection electrode 20, and is formed at the center of the upper surface 20 a of the external connection electrode 20. The corresponding region is removed by ICP-RIE (Inductively Coupled Plasma-Reactive Ion Etching) method or laser beam irradiation.
Thereafter, the buffer layer 31 may be formed on the adhesive layer 36 by the same method as in the first embodiment.

実施形態２の構成においても実施形態１と同様な効果を奏することができる。加えて、実施形態２では、接着剤層３６を介入することにより緩衝層３１と封止膜１６の接着強度を強化することができる。また、接着剤層３６をＩＣＰ−ＲＩＥ法またはレーザビームの照射により除去する際、外部接続用電極２０の上面２０ａに微細な凹凸が形成され、半田がこの微細な凹凸に食い込むので、外部接続用電極２０と半田ボール３５との接合強度を向上することができる。 In the configuration of the second embodiment, the same effect as that of the first embodiment can be obtained. In addition, in the second embodiment, the adhesive strength between the buffer layer 31 and the sealing film 16 can be enhanced by intervening the adhesive layer 36. Further, when the adhesive layer 36 is removed by ICP-RIE method or laser beam irradiation, fine irregularities are formed on the upper surface 20a of the external connection electrode 20, and the solder bites into the fine irregularities. The bonding strength between the electrode 20 and the solder ball 35 can be improved.

(実施形態３)
次に、図１６に図示する本発明の半導体装置の実施形態３について説明する。
実施形態３における半導体装置６０は、実施形態２における半導体装置５０の接着剤層に替えて密着力向上膜を用いた点を特徴とする。他の構成は、実施形態１および実施形態２と同様であり、同一部材に同一の図面参照番号を付してその説明を省略する。
半導体装置６０の密着力向上膜３７は、封止膜１６の上面１６ａのみに形成されており、封止膜１６における外部接続用電極２０の段差部の側面には形成されていない。この密着力向上膜３７の上面および封止膜１６の外部接続用電極２０の段差部における側面を覆って緩衝層３１が形成されている。 (Embodiment 3)
Next, a semiconductor device according to a third embodiment of the present invention shown in FIG. 16 will be described.
The semiconductor device 60 in the third embodiment is characterized in that an adhesion improving film is used instead of the adhesive layer of the semiconductor device 50 in the second embodiment. Other configurations are the same as those of the first embodiment and the second embodiment, and the same members are denoted by the same reference numerals and description thereof is omitted.
The adhesion improving film 37 of the semiconductor device 60 is formed only on the upper surface 16 a of the sealing film 16, and is not formed on the side surface of the step portion of the external connection electrode 20 in the sealing film 16. A buffer layer 31 is formed so as to cover the upper surface of the adhesion improving film 37 and the side surface of the sealing film 16 at the step portion of the external connection electrode 20.

密着力向上膜３７の材料の一例として、シランカップリング剤がある。シランカップリング剤は原液でもよく、また、アルコール等の有機溶剤あるいは水などで希釈した溶液でもよい。
密着力向上膜３７を形成するには、スクリーン印刷法、グラビア印刷法、凸版印刷法、インクジェット印刷法、スピンコート法、ダイコート法またはＣＶＤ法などを用いる。印刷法による場合は、１つの工程で外部接続用電極２０の上面２０ａを除外したパターンを形成することができる。封止膜１６の上面１６ａおよび外部接続用電極２０の上面２０ａの全面に密着力向上膜３７を設け、フォトリソグラフィ法により外部接続用電極２０の上面２０ａ上の部分を除去するようにしてもよい。除去する方法は、エッチング液によるウエットエッチング法あるいは実施形態２に記載したドライエッチング法のいずれでもよい。 An example of a material for the adhesion improving film 37 is a silane coupling agent. The silane coupling agent may be a stock solution or a solution diluted with an organic solvent such as alcohol or water.
In order to form the adhesion improving film 37, a screen printing method, a gravure printing method, a relief printing method, an ink jet printing method, a spin coating method, a die coating method, a CVD method, or the like is used. In the case of the printing method, a pattern excluding the upper surface 20a of the external connection electrode 20 can be formed in one process. An adhesion improving film 37 may be provided on the entire upper surface 16a of the sealing film 16 and the upper surface 20a of the external connection electrode 20, and a portion on the upper surface 20a of the external connection electrode 20 may be removed by photolithography. . The removal method may be either a wet etching method using an etching solution or the dry etching method described in the second embodiment.

シランカップリング剤としては、分子中に一般式（ＣｎＨ２ｎ＋１Ｏ）ｍ−Ｓｉ−（ただし、ｎ、ｍ＝１、２、３）を有する材料であればよい。一例をあげれば、γ−（２−アミノエチル）アミノプロピルメトキシシラン、γ−（２−アミノエチル）アミノプロピルエトキシシラン、γ−（２−アミノエチル）アミノプロピルメチルジメトキシシラン、アミノシラン、γ−メタクリロキシプロピルトリメトキシシラン、γ−メタクリロキシプロピルメチルジメトキシシラン、γ−メタクリロキシプロピルトリエトキシシラン、γ−グリシドキシプロピルトリメトキシシラン、γ−グリシドキシプロピルメチルジエトキシシラン、γ−メタクリロキシプロピルメチルジエトキシシラン、γ−グリシドキシプロピルトリエトキシシラン、γ−メルカプトプロピルトリメトキシシラン、メチルトリメトキシシラン、メチルトリエトキシシラン、ビニルトリアセトキシシラン、ヘキサメチルジシラザン、γ−アニリノプロピルトリメトキシシラン、ビニルトリメトキシシラン、ビニルトリエトキシシラン、γ−メルカプトプロピルメチルジメトキシシラン、メチルトリクロロシラン、ジメチルジクロロシラン、トリメチルクロロシラン、ビニルトリクロルシラン、ビニルトリエトキシシラン、ビニルトリス(βメトキシエトキシ)シラン、β−(３、４エポキシシクロヘキシル)エチルトリメトキシシラン、ｐ−スチリルトリメトキシシラン、γ−アクリロキシプルピルトリメトキシシラン、γ−アミノプロピルトリメトキシシラン、γ−アミノプロピルトリエトキシシラン、γ−トリエトキシシリル−Ｎ−（１，３−ジメチル−ブチリデン）プロピルアミン、Ｎ−フェニル−３−アミノプロピルトリメトキシシラン、γ−ウレイドプロピルトリエトキシシラン、γ−クロロプロピルトリメトキシシラン、γ−メルカプトプロピルトリメトキシシラン、ビス（トリエトキシシリルプロピル）テトラスルフィド、γ−イソシアナートプロピルトリエトキシシランなどがある。 The silane coupling agent may be a material having a general formula (CnH2n + 1O) m-Si- (where n, m = 1, 2, 3) in the molecule. For example, γ- (2-aminoethyl) aminopropylmethoxysilane, γ- (2-aminoethyl) aminopropylethoxysilane, γ- (2-aminoethyl) aminopropylmethyldimethoxysilane, aminosilane, γ-methacrylic. Roxypropyltrimethoxysilane, γ-methacryloxypropylmethyldimethoxysilane, γ-methacryloxypropyltriethoxysilane, γ-glycidoxypropyltrimethoxysilane, γ-glycidoxypropylmethyldiethoxysilane, γ-methacryloxypropyl Methyldiethoxysilane, γ-glycidoxypropyltriethoxysilane, γ-mercaptopropyltrimethoxysilane, methyltrimethoxysilane, methyltriethoxysilane, vinyltriacetoxysilane, hexamethyldisilazane, γ-anilinopropyltrimethoxysilane, vinyltrimethoxysilane, vinyltriethoxysilane, γ-mercaptopropylmethyldimethoxysilane, methyltrichlorosilane, dimethyldichlorosilane, trimethylchlorosilane, vinyltrichlorosilane, vinyltriethoxysilane, vinyltris (β Methoxyethoxy) silane, β- (3,4, epoxycyclohexyl) ethyltrimethoxysilane, p-styryltrimethoxysilane, γ-acryloxypropylpyrmethoxysilane, γ-aminopropyltrimethoxysilane, γ-aminopropyltriethoxy Silane, γ-triethoxysilyl-N- (1,3-dimethyl-butylidene) propylamine, N-phenyl-3-aminopropyltrimethoxysilane, γ-ureidopropyltriethoxysilane There are lanthanum, γ-chloropropyltrimethoxysilane, γ-mercaptopropyltrimethoxysilane, bis (triethoxysilylpropyl) tetrasulfide, γ-isocyanatopropyltriethoxysilane and the like.

実施形態３において、密着力向上膜３７を、実施形態２の接着剤層３６と同様、封止膜１６の角部１６ｃを含む外部接続用電極２０との段差部における側面に形成するようにしてもよい。
実施形態３においても実施形態２と同様な効果を奏することができる。 In the third embodiment, the adhesion improving film 37 is formed on the side surface of the stepped portion with the external connection electrode 20 including the corner portion 16c of the sealing film 16 like the adhesive layer 36 of the second embodiment. Also good.
In the third embodiment, the same effect as that of the second embodiment can be obtained.

なお、上記各実施形態では、外部接続用電極２０は、接続パッド３に接続された配線１５上に形成する構造として説明をした。しかし、外部接続用電極２０を、直接、接続パッド３上に形成するようにしてもよい。 In each of the above embodiments, the external connection electrode 20 has been described as a structure formed on the wiring 15 connected to the connection pad 3. However, the external connection electrode 20 may be formed directly on the connection pad 3.

第１の絶縁膜４および第２の絶縁膜１２を単層とすることもできる。単層とする場合、酸化シリコン等の無機材料からなる樹脂、またはポリイミド系樹脂、ＰＢＯ樹脂などの有機樹脂を用いて、スピンコート法、スクリーン印刷法などにより形成する。 The first insulating film 4 and the second insulating film 12 may be a single layer. In the case of a single layer, it is formed by spin coating, screen printing, or the like using a resin made of an inorganic material such as silicon oxide, or an organic resin such as a polyimide resin or a PBO resin.

配線１５は第１の配線１３および第２の配線１４の二層積層構造の他、三層積層構造とすることができることは記載したが、スパッタ法あるいは無電解めっき法で形成する単層とすることもできる。 Although it has been described that the wiring 15 can have a three-layer laminated structure in addition to the two-layer laminated structure of the first wiring 13 and the second wiring 14, it is a single layer formed by a sputtering method or an electroless plating method. You can also.

その他、本発明の半導体装置は発明の趣旨の範囲内において、種々、変形して構成することが可能であり、要は、接続パッドを有する半導体基板と、半導体基板上に形成され、接続パッドの一部を露出する開口部を有する絶縁膜と、接続パッドに電気的に接続された外部接続用電極と、外部接続用電極の外周側面の周囲における絶縁膜上に形成され、外部接続用電極の上面よりも高い位置に上面を有し、外部接続用電極の上面を露出する開口部を有する封止膜と、外部接続用電極の上面の中央部を露出する開口部を有し、少なくとも外部接続用電極の上面の周縁部およびその周囲の前記封止膜を覆う緩衝層と、を具備するものであればよい。 In addition, the semiconductor device of the present invention can be variously modified within the scope of the invention. In short, a semiconductor substrate having a connection pad, a semiconductor substrate formed on the semiconductor substrate, An insulating film having an opening exposing a part thereof, an external connection electrode electrically connected to the connection pad, and an insulating film around the outer peripheral side surface of the external connection electrode. A sealing film having an upper surface at a position higher than the upper surface and having an opening that exposes the upper surface of the external connection electrode, and an opening that exposes the central portion of the upper surface of the external connection electrode. And a buffer layer that covers the peripheral edge of the upper surface of the electrode for use and the sealing film around it.

本発明の半導体装置の製造方法は、半導体基板上に、外部接続用電極と、外部接続用電極の外周側面の周囲における半導体基板上に形成され、外部接続用電極の上面よりも高い位置に上面を有し、外部接続用電極の上面を露出する開口部を有する封止膜が形成された半導体基板組立体を準備する工程と、少なくとも外部接続用電極の上面の周縁部およびその周囲の封止膜上に形成され、外部接続用電極の上面の中央部を露出する開口部を有する緩衝層を形成する工程と、を具備するものであればよい。 The method of manufacturing a semiconductor device according to the present invention is formed on a semiconductor substrate on the semiconductor substrate around the outer peripheral side surface of the external connection electrode and the external connection electrode, and the upper surface of the semiconductor device is higher than the upper surface of the external connection electrode. And a step of preparing a semiconductor substrate assembly in which a sealing film having an opening that exposes the upper surface of the external connection electrode is formed, and sealing at least a peripheral portion of the upper surface of the external connection electrode and its periphery And a step of forming a buffer layer having an opening formed on the film and exposing the central portion of the upper surface of the external connection electrode.

また、本発明の半導体装置の製造方法は、接続パッドを有する半導体基板を準備する工程と、半導体基板上に接続パッドを露出する開口部を有する絶縁膜を形成する工程と、絶縁膜上に、接続パッドに接続された配線を形成する工程と、配線に接続された外部接続用電極を形成する工程と、外部接続用電極の外周側面の周囲における絶縁膜上および外部接続用電極の上面上に封止膜を形成する工程と、
少なくとも封止膜を研磨して外部接続用電極の上面を露出する工程と、外部接続用電極の上面を除去して外部接続用電極の上面を前記封止膜の上面より低くする工程と、封止膜上および外部接続用電極の上面上に緩衝層を形成する工程と、緩衝層における外部接続用電極の上面の中央部に対応する領域を除去する工程と、を具備するものであればよい。 The method for manufacturing a semiconductor device of the present invention includes a step of preparing a semiconductor substrate having connection pads, a step of forming an insulating film having an opening exposing the connection pads on the semiconductor substrate, A step of forming a wiring connected to the connection pad, a step of forming an external connection electrode connected to the wiring, and an insulating film around the outer peripheral side surface of the external connection electrode and an upper surface of the external connection electrode. Forming a sealing film;
Polishing at least the sealing film to expose the upper surface of the external connection electrode; removing the upper surface of the external connection electrode to make the upper surface of the external connection electrode lower than the upper surface of the sealing film; What is necessary is just to comprise the process of forming a buffer layer on the stopper film and the upper surface of the electrode for external connection, and the process of removing the region corresponding to the central portion of the upper surface of the electrode for external connection in the buffer layer .

１半導体ウエハ
２ダイシングライン
３接続パッド
４第１の絶縁膜
４ａ開口部
１０、５０、６０半導体装置
１０Ａ半導体基板組立体
１１半導体基板
１２第２の絶縁膜
１２ａ開口部
１３第１の配線
１４第２の配線
１５配線
１６封止膜
１６ａ上面
１６ｂ角部
１６ｃ角部
２０外部接続用電極
２０ａ上面
３１緩衝層
３１ａ開口部
３１ｂ傾斜面
３５半田ボール
３６接着剤層
３７密着力向上膜 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Dicing line 3 Connection pad 4 1st insulating film 4a Opening part 10, 50, 60 Semiconductor device 10A Semiconductor substrate assembly 11 Semiconductor substrate 12 2nd insulating film 12a Opening part 13 1st wiring 14 2nd Wiring 15 Wiring 16 Sealing film 16a Upper surface 16b Corner portion 16c Corner portion 20 External connection electrode 20a Upper surface 31 Buffer layer 31a Opening portion 31b Inclined surface 35 Solder ball 36 Adhesive layer 37 Adhesion layer 37

Claims

A semiconductor substrate having connection pads;
An insulating film formed on the semiconductor substrate and having an opening exposing a part of the connection pad;
An external connection electrode electrically connected to the connection pad;
Formed on the insulating film around the outer peripheral side surface of the external connection electrode, has an upper surface at a position higher than the upper surface of the external connection electrode, and has an opening that exposes the upper surface of the external connection electrode A sealing film;
A buffer layer that has an opening that exposes a central portion of the upper surface of the external connection electrode, covers at least a peripheral portion of the upper surface of the external connection electrode and the surrounding sealing film;
A semiconductor device comprising:

2. The semiconductor device according to claim 1, wherein a solder ball is joined to a central portion of the upper surface of the external connection electrode exposed from the opening of the buffer layer.

3. The semiconductor device according to claim 2, wherein the solder ball is on the buffer layer in a region outside a boundary surface between an outer periphery of the external connection electrode and the sealing film from a central portion of the external connection electrode. A semiconductor device characterized by being formed over the entire area.

4. The semiconductor device according to claim 1, wherein the buffer layer has an inclined surface that descends from a corner portion of the sealing film to a peripheral portion of the upper surface of the external connection electrode, An angle formed by the inclined surface of the buffer tank and the upper surface of the external connection electrode is an acute angle.

5. The semiconductor device according to claim 1, wherein a wiring connected to the connection pad is formed on the insulating film, and the external connection electrode is formed on the wiring. A featured semiconductor device.

6. The semiconductor device according to claim 1, wherein a flux layer or a surface treatment layer is formed on a central portion of the upper surface of the external connection electrode exposed from the opening of the buffer layer. A semiconductor device.

7. The semiconductor device according to claim 1, wherein the buffer layer is formed of any one of a polyimide-based resin, an epoxy-based resin, and a PBO-based resin.

8. The semiconductor device according to claim 1, wherein an adhesive layer is provided between the buffer layer and the sealing film. 9.

8. The semiconductor device according to claim 1, wherein an adhesion improving film is provided between the buffer layer and the sealing film. 9.

10. The semiconductor device according to claim 1, wherein the sealing film is formed of either an epoxy resin or a polyimide-based resin containing a silica filler. A featured semiconductor device.

An external connection electrode and an external connection electrode formed on the semiconductor substrate around the outer peripheral side surface of the external connection electrode on the semiconductor substrate, and having an upper surface at a position higher than the upper surface of the external connection electrode, the external connection Preparing a semiconductor substrate assembly in which a sealing film having an opening exposing the upper surface of the electrode for forming is formed;
Forming a buffer layer having an opening that is formed on at least a peripheral portion of the upper surface of the external connection electrode and the surrounding sealing film and exposes a central portion of the upper surface of the external connection electrode;
A method for manufacturing a semiconductor device, comprising:

12. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming a solder ball bonded to the upper surface of the external connection electrode and in close contact with at least an outer peripheral portion of the upper surface of the external connection electrode of the buffer layer. A method for manufacturing a semiconductor device, comprising:

13. The method of manufacturing a semiconductor device according to claim 12, wherein the solder ball is formed on the sealing film around the outer peripheral side surface of the external connection electrode so as to be in close contact with the insulating film. A method of manufacturing a semiconductor device.

14. The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the buffer layer includes an upper surface of the sealing film by a spin coating method, a scan coating method, or an inject coating method. Forming the buffer layer on the entire upper surface of the external connection electrode, and then forming an opening in the buffer layer to expose a central portion of the upper surface of the external connection electrode. A method for manufacturing a semiconductor device.

15. The method of manufacturing a semiconductor device according to claim 11, wherein the buffer layer has an inclined surface that descends from a corner portion of the sealing film to a peripheral portion of the upper surface of the external connection electrode. And an angle formed by the inclined surface of the buffer tank and the upper surface of the external connection electrode is an acute angle.

16. The method of manufacturing a semiconductor device according to claim 11, wherein after the step of forming the buffer layer and before the step of forming the solder ball, the central portion of the external connection electrode is formed. A method of manufacturing a semiconductor device, comprising a step of forming a flux layer or a surface treatment layer.

17. The method of manufacturing a semiconductor device according to claim 16, wherein the step of forming the solder ball is performed on the flux layer or the surface treatment layer formed on a central portion of the upper surface of the external connection electrode. And a step of reflowing the semiconductor substrate assembly on which the solder balls are mounted to closely adhere the solder balls to the periphery of the opening of the buffer layer. Method.

18. The semiconductor device according to claim 12, further comprising a step of forming an adhesive layer between the buffer layer and the sealing film.

18. The semiconductor device according to claim 12, further comprising a step of forming an adhesion improving film between the buffer layer and the sealing film.

Preparing a semiconductor substrate having connection pads;
Forming an insulating film having an opening exposing the connection pad on the semiconductor substrate; forming a wiring connected to the connection pad on the insulating film;
Forming an external connection electrode connected to the wiring;
Forming a sealing film such that the upper surface thereof is higher than the upper surface of the external connection electrode;
Forming a buffer layer on the upper surface of the sealing film and the upper surface of the external connection electrode;
Removing a region corresponding to a central portion of the upper surface of the external connection electrode in the buffer layer;
A method for manufacturing a semiconductor device, comprising:

21. The method of manufacturing a semiconductor device according to claim 20, further comprising a step of depositing a flux on a central portion of an upper surface of the external connection electrode, a step of mounting a solder ball on the flux, and the external connection A semiconductor substrate having a solder ball mounted on the center of the upper surface of the electrode is subjected to a reflow process, and the solder ball is brought into close contact with at least the portion of the buffer layer formed on the peripheral edge of the upper surface of the external connection electrode. A method for manufacturing a semiconductor device, comprising: a step.