JP5876893B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device package for image sensors such as a CMOS sensor and a CCD sensor, a semiconductor device package for various sensors such as an illuminance sensor and a UV sensor, a semiconductor device such as a semiconductor chip stacked (memory, memory + logic) package, and its manufacture. Regarding the method.

  In recent years, it is called CSP (chip size package), a through via (through hole) is formed from the back side of a semiconductor substrate, a pad electrode formed on the surface of the semiconductor substrate is exposed, and the pad electrode exposed by the via hole is exposed. A semiconductor device has been proposed in which a wiring is formed from an electrical connection to provide electrical continuity and an external terminal is provided on the back side of the semiconductor substrate (for example, Patent Document 1).

  In such a semiconductor device, the surface of the semiconductor substrate is generally covered with a passivation film (insulating layer). The passivation film is also formed so as to cover the pad electrode, but is removed so as to expose a part of the electrode layer for electrical characteristic inspection and other electrical connection formation, and an opening is formed.

JP 2006-128171 A

  However, in the above conventional semiconductor device, since the pad electrode is very thin (for example, 1 to 3 μm), it is weak against stress, and when a force such as a physical impact is applied to the semiconductor device, the through via There was a problem that the pad electrode cracked around and the electrical characteristics could not be obtained.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that suppresses the occurrence of cracks in a conductive layer provided on a first main surface of a semiconductor substrate exposed by a through hole provided in the semiconductor substrate, and a method for manufacturing the same. .

The above problem is solved by the following means. That is,
A method for manufacturing a semiconductor device according to a first aspect of the present invention includes:
An insulating layer having a first opening that covers the first main surface of the semiconductor substrate and the conductive layer formed on the first main surface and exposes a part of the conductive layer is provided. Preparing the semiconductor substrate in contact with the exposed conductive layer and subjected to a characteristic inspection of a semiconductor circuit formed on the first main surface of the semiconductor substrate;
A second opening that exposes a second main surface of the semiconductor substrate and a region that penetrates the semiconductor substrate in a thickness direction from the second main surface of the semiconductor substrate without contacting a region corresponding to the first opening. A wiring layer forming step of forming a wiring layer formed on the inner wall of the through-hole having a portion and electrically connected to the conductive layer through the second opening;
It is characterized by including.

A method for manufacturing a semiconductor device according to a second aspect of the present invention includes:
An insulating layer having a first opening covering a first main surface of a semiconductor substrate and one pad conductive layer formed on the first main surface and exposing a part of the one pad conductive layer; Preparing the semiconductor substrate that is in contact with the one pad conductive layer exposed by the first opening and subjected to a characteristic inspection of a semiconductor circuit formed on the first main surface of the semiconductor substrate;
A second opening is formed in the second main surface of the semiconductor substrate and a second region penetrating the semiconductor substrate in a thickness direction and spaced apart from a first region corresponding to the first opening of the second main surface of the semiconductor substrate. A wiring layer forming step of forming a wiring layer formed on the inner wall of the through-hole including a portion and electrically connected to the one pad conductive layer through the second opening;
It is characterized by including.

The semiconductor device of the first aspect of the present invention is
A semiconductor circuit formed on the first main surface of the semiconductor substrate;
For evaluating the characteristics of the semiconductor circuit, covering a first main surface of a semiconductor substrate and one pad conductive layer formed on the first main surface of the semiconductor substrate and exposing a part of the one pad conductive layer An insulating layer having a first opening of
A through-hole provided with a second opening in a second region that penetrates the semiconductor substrate in a thickness direction and is spaced apart from a first region corresponding to the first opening of the second main surface of the semiconductor substrate;
A wiring layer formed on the inner wall of the through-hole and the second main surface of the semiconductor substrate and electrically connected to the one pad conductive layer through the second opening;
It is characterized by providing.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which suppressed the crack generation of the conductive layer provided in the 1st main surface of the semiconductor substrate exposed by the through-hole provided in the semiconductor substrate, and its manufacturing method can be provided.

1 is a schematic plan view of a semiconductor device according to a first embodiment. It is an AA schematic sectional drawing of FIG. It is process drawing which shows the manufacturing process of the semiconductor device which concerns on 1st Embodiment. In the manufacturing process of the semiconductor device concerning a 1st embodiment, it is a schematic perspective view showing signs that a pad electrode was arranged on a silicon wafer (silicon substrate). In the manufacturing process of the semiconductor device concerning a 1st embodiment, it is a schematic perspective view showing signs that a passivation film which has an opening is arranged on a silicon wafer (silicon substrate). In the manufacturing process of the semiconductor device concerning a 1st embodiment, it is a schematic perspective view showing signs that a penetration via was arranged in a silicon wafer (silicon substrate). 1 is a schematic plan view of a semiconductor device according to a first embodiment. It is an AA schematic sectional drawing of FIG. It is process drawing which shows the manufacturing process of the semiconductor device which concerns on 1st Embodiment. In the manufacturing process of the semiconductor device concerning a 1st embodiment, it is a schematic perspective view showing signs that a passivation film which has an opening is arranged on a silicon wafer (silicon substrate). In the manufacturing process of the semiconductor device concerning a 1st embodiment, it is a schematic perspective view showing signs that a penetration via was arranged in a silicon wafer (silicon substrate).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, what has the substantially same function is attached | subjected and demonstrated through the whole figure, and the description may be abbreviate | omitted depending on the case.

(First embodiment)
FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional view taken along line AA of FIG. FIG. 3 is a process diagram showing the manufacturing process of the semiconductor device according to the first embodiment.

  The semiconductor device 100 according to the first embodiment is, for example, a CSP (chip size package) semiconductor device.

  The semiconductor device 100 according to the first embodiment includes a silicon substrate 10 (semiconductor substrate) as shown in FIGS. A semiconductor circuit 12 (semiconductor element) is disposed at the center of the first main surface of the silicon substrate 10. The semiconductor circuit 12 is a semiconductor circuit such as a sensor element circuit (image sensor (for example, CMOS sensor, CCD sensor, etc.), other sensor (illuminance sensor, UV sensor, etc.)), memory circuit, and logic circuit.

  A pad electrode 14 (electrode layer) is disposed at the end of the first main surface of the silicon substrate 10. The pad electrode 14 is, for example, an aluminum electrode, and is electrically connected to the semiconductor circuit 12 (not shown), for example. In the present embodiment, for example, five pad electrodes 14 are arranged along each of two opposing sides of the first main surface of the silicon substrate 10. In the present embodiment, the pad electrode 14 is disposed directly on the first main surface of the silicon substrate 10 in the drawing. Usually, the pad electrode 14 is interposed via an insulating film such as a silicon oxide film. It is disposed on the first main surface of the silicon substrate 10.

  A passivation film 16 (insulating layer) is disposed on the entire first main surface of the silicon substrate 10 so as to cover the semiconductor circuit 12 and the pad electrode 14. For example, a silicon nitride film is applied to the passivation film 16. The passivation film 16 is provided with an opening 16A that exposes a part of the pad electrode 14 (in this embodiment, the central portion). The opening 16A is for exposing a part of the pad electrode 14 for electrical characteristic inspection or other electrical connection formation. In the present embodiment, the opening 16A is provided for electrical characteristic inspection. is there.

  A glass substrate 18 (protective substrate) for protecting the semiconductor device 100 is disposed on the first main surface of the silicon substrate 10. The glass substrate 18 is disposed on the passivation film 16 with the adhesive film 20 interposed therebetween.

  On the other hand, a through via 22 (through hole) penetrating in the thickness direction is disposed on the second main surface of the silicon substrate. The through via 22 is formed so as to expose a part of the pad electrode 14 (a central portion in the present embodiment) to the second main surface side of the silicon substrate. In the present embodiment, five through vias 22 are arranged along each of two opposing sides of the second main surface of the silicon substrate 10 according to the arrangement position of the pad electrode 14, for example. .

  The through-via 22 has an opening diameter (opening diameter at a position in contact with the pad electrode 14) larger than an opening diameter of the opening 16A of the passivation film 16 (opening diameter at a position in contact with the pad electrode 14). The edge (opening edge at a position in contact with the pad electrode 14) is disposed outside the opening edge of the opening 16A of the passivation film 16 (opening edge at the position in contact with the pad electrode 14). In other words, the opening 16A of the passivation film 16 has an opening diameter (opening diameter at a position in contact with the pad electrode 14) smaller than an opening diameter of the through via 22 (opening diameter at a position in contact with the pad electrode 14). The opening edge (opening edge at a position in contact with the pad electrode 14) is disposed inside the opening edge (opening edge at the position in contact with the pad electrode 14) of the through via 22.

  Here, the opening diameter means the maximum diameter. The difference between the opening diameter of the through via (the opening diameter at the position in contact with the pad electrode 14) and the opening diameter of the opening 16A of the passivation film 16 (the opening diameter at the position in contact with the pad electrode 14) is, for example, 10 μm or more. There should be.

  Further, the second main surface of the silicon substrate 10 is electrically connected to the pad electrode 14 embedded and exposed in the through via 22, and the wiring 24 (for example, a copper wire) routed on the second main surface. Etc.) are arranged. An external terminal 26 (for example, a solder ball) is disposed on a part of the wiring 24. Although not shown, the sidewalls of the through vias 22 and the silicon substrate 10 are formed on the sidewalls of the through vias 22 and the second main surface of the silicon substrate 10 via an insulating film (for example, a silicon oxide film) and a barrier metal film (for example, a Ti film). 2 is disposed on the main surface.

  In the present embodiment, the wiring 24 is embedded in the through via 22 so as to be electrically connected to the pad electrode 14. However, the wiring 24 does not need to be embedded in the through via 22 and the surface of the pad electrode 14 exposed by the through via 22 is used. To the second main surface of the silicon substrate 10 through the side wall of the through via 22.

  A protective film 28 (for example, a solder resist film) is disposed on the entire second main surface of the silicon substrate so as to cover the surface of the wiring 24 except for a connection portion with the external terminal 26.

  Hereinafter, a method for manufacturing the semiconductor device 100 according to the present embodiment having the above-described configuration will be described.

  First, as shown in FIG. 3A, a first main surface of a silicon wafer 10A (silicon substrate 10) is divided into a plurality of element regions, and a semiconductor circuit 12 is formed in each region by a semiconductor process. . Then, after a mask is formed by resist application, exposure, and etching, a pad electrode 14 made of aluminum is formed by sputtering, plating, or the like (see FIG. 4).

Next, as shown in FIG. 3B, a passivation film 16 made of a silicon nitride film is formed on the first main surface of the silicon wafer 10 </ b> A (silicon substrate 10) so as to cover the semiconductor circuit 12 and the pad electrode 14. At the same time, an opening 16A exposing a part of the pad electrode 14 is formed in the passivation film 16 (see FIG. 5). The passivation film 16 is formed using, for example, a silicon nitride film by plasma-assisted chemical vapor deposition (P-CVD) using SiH ₄ , NH _3, and N ₂ as a source gas. The opening 16A of the passivation film 16 is formed by, for example, forming a mask on the passivation film 16 by applying, exposing, and etching a resist, and then etching the passivation film 16.

  Here, the silicon wafer 10A on which the passivation film 16 is formed is called, for example, a sensor wafer, a memory wafer or the like, and is often shipped or transported to another line in order to perform a packaging process in this state. For this reason, before shipping, transporting to another line, or before performing a post-process (packaging process) on another line, electrical characteristic inspection is performed through the pad electrode 14 exposed through the opening 16A provided in the passivation film 16. Is done. Therefore, the opening 16A for exposing the pad electrode 14 is important in the manufacturing process.

  Next, as shown in FIG. 3C, an adhesive film 20 is applied on the passivation film 16 disposed on the silicon wafer 10A using a spin coating method or the like, and then a glass substrate 18 is attached. The step of attaching the glass substrate 18 may be performed at any time after the formation of the passivation film 16 and before the individualization described later.

  Next, as shown in FIG. 3D, the second main surface of the silicon wafer 10A (silicon substrate 10) is cut (a bite, a grindstone, a buff, etc.) and, for example, the silicon wafer 10A ( The silicon substrate 10) is thinned.

  Next, as shown in FIG. 3E, the pad electrode 14 is formed on the second main surface of the silicon wafer 10A (silicon substrate 10) by using dry etching processing, wet etching processing, or laser processing. Cutting is performed until it is exposed, and a through via 22 penetrating in the thickness direction of the silicon wafer 10A (silicon substrate 10) is formed (see FIG. 6). The pad electrode 14 is exposed by the through via 22.

  Next, as shown in FIG. 3F, after a mask is formed by resist application, exposure, and etching, a wiring 24 made of copper wiring is embedded in the through via 22 by sputtering, plating, etc., and the silicon wafer 10A. It is formed by drawing around the second main surface of (silicon substrate 10). Thereafter, a protective film 28 such as a solder resist film is formed by using a spin coating method or the like, an opening for exposing a part of the wiring 24 is formed, and the wiring 24 exposed in the opening is formed. External terminals 26 such as solder balls are formed.

  Then, as shown in FIG. 3G, CSP (chip size package) semiconductor device 100 is obtained by dividing into pieces by dicing or the like.

  In the semiconductor device 100 according to the present embodiment described above, the opening diameter of the through via 22 (opening diameter at a position in contact with the pad electrode 14) is the opening diameter of the opening 16A in the passivation film 16 (at the position in contact with the pad electrode 14). Larger than the opening diameter), and the opening edge of the through via 22 (the opening edge in contact with the pad electrode 14) is outside the opening edge of the opening 16A in the passivation film 16 (the opening edge in contact with the pad electrode 14). It is located and located.

  For this reason, since the pad electrode 14 is exposed by the through via 22 while the inner periphery of the opening edge of the through via 22 is held or supported by the passivation film 16, the pad electrode 14 is generated in the manufacturing process thereof, for example. The occurrence of cracks is suppressed by stress resulting from impact or the like.

(Second Embodiment)
FIG. 7 is a schematic plan view of the semiconductor device according to the second embodiment. FIG. 8 is a schematic cross-sectional view taken along line AA of FIG. FIG. 9 is a process diagram showing a manufacturing process of the semiconductor device according to the second embodiment.

  In the semiconductor device 101 according to the second embodiment, the through-via 22 has an opening edge (an opening edge in contact with the pad electrode 14) of the opening 16A of the passivation film 16 (an opening in contact with the pad electrode 14). It is disposed at a position that does not overlap with the edge. In other words, the opening 16A of the passivation film 16 is located at a position where the opening edge (the opening edge in contact with the pad electrode 14) does not overlap the opening edge of the through via 22 (the opening edge in contact with the pad electrode 14). It is arranged.

  Specifically, for example, the through vias 22 are arranged so as to be unevenly distributed so that one end of the pad electrode 14 is exposed. On the other hand, the opening portion 16A of the passivation film 16 is arranged to be unevenly distributed so that the other end portion side of the pad electrode 14 is exposed. Here, the opening edge of the through via 22 and the opening edge of the opening 16A of the passivation film 16 do not overlap when projected onto the same plane in the thickness direction of the pad electrode 14. The distance between the opening edge of the through via 22 and the opening edge of the opening 16A of the passivation film 16 (the shortest distance when both are projected on the same plane in the thickness direction of the pad electrode 14) is, for example, 10 μm or more. Is good.

  Except for these, the configuration is the same as in the first embodiment, and a description thereof will be omitted.

Hereinafter, a method for manufacturing the semiconductor device 101 according to the present embodiment will be described.
First, in FIG. 9B, the opening 16A of the passivation film 16 is arranged unevenly so that the other end side of the pad electrode 14 is exposed (see FIG. 10). In FIG. 9E, the through via 22 is padded so that the opening edge thereof does not overlap the opening edge of the opening 16A of the passivation film 16 (the opening edge in contact with the pad electrode 14). The electrode 14 is arranged so as to be unevenly distributed so that one end portion side is exposed (see FIG. 11).

  Since the other steps are the same as those in the first embodiment, description thereof is omitted.

  In the semiconductor device 101 according to the present embodiment described above, the opening edge of the through via 22 (the opening edge in contact with the pad electrode 14) is the opening edge of the opening 16A in the passivation film 16 (the portion in contact with the pad electrode 14). (Opening edge) is arranged at a position that does not overlap.

  For this reason, since the pad electrode 14 is exposed by the through via 22 while all the inner side of the opening edge of the through via 22 is held or supported by the passivation film 16, the pad electrode 14 is generated in the manufacturing process, for example. The occurrence of cracks is suppressed by stress resulting from impact or the like.

  In the semiconductor device according to any of the above embodiments, the occurrence of cracks is suppressed by devising the shape and positional relationship between the through via 22 and the opening 16A of the passivation film 16. Accordingly, there is no need to perform additional operations (processes) or special processes, and a semiconductor device can be easily manufactured without increasing the number of manufacturing processes, and cost reduction can be realized. On the other hand, in the related art (for example, Japanese Patent Application Laid-Open No. 2006-128171), the pad electrode exposed to the through via is held or supported by the wiring layer connected thereto in the region exposed to the through via 22. However, the wiring layer must be formed separately, and it is difficult to reduce the number of manufacturing steps and reduce the cost. In this regard, in the semiconductor device according to any of the above embodiments, as described above, the occurrence of cracks in the pad electrode is suppressed at a low cost without increasing the number of manufacturing steps.

  The semiconductor device according to any of the above embodiments includes a semiconductor device package for image sensors such as a CMOS sensor and a CCD sensor, a semiconductor device package for various sensors such as an illuminance sensor and a UV sensor, and a semiconductor chip stacked (memory, memory + logic) package. Applicable to etc.

  In any of the above-described embodiments, it is needless to say that the present invention is not construed in a limited manner and can be realized within the range satisfying the requirements of the present invention.

DESCRIPTION OF SYMBOLS 10 Silicon substrate 10A Silicon wafer 12 Semiconductor circuit 14 Pad electrode 16 Passivation film 16A Opening part 18 Glass substrate 20 Adhesive film 22 Through-via 24 Wiring 26 External terminal 28 Protective film 100, 101 Semiconductor device

Claims (7)

An insulating layer having a first opening that covers the first main surface of the semiconductor substrate and the conductive layer formed on the first main surface and exposes a part of the conductive layer is provided. Preparing the semiconductor substrate in contact with the exposed conductive layer and subjected to a characteristic inspection of a semiconductor circuit formed on the first main surface of the semiconductor substrate;
A second opening that exposes a second main surface of the semiconductor substrate and a region that penetrates the semiconductor substrate in a thickness direction from the second main surface of the semiconductor substrate without contacting a region corresponding to the first opening. A wiring layer forming step of forming a wiring layer formed on the inner wall of the through-hole having a portion and electrically connected to the conductive layer through the second opening;
A method for manufacturing a semiconductor device, comprising: An insulating layer having a first opening covering a first main surface of a semiconductor substrate and one pad conductive layer formed on the first main surface and exposing a part of the one pad conductive layer; Preparing the semiconductor substrate that is in contact with the one pad conductive layer exposed by the first opening and subjected to a characteristic inspection of a semiconductor circuit formed on the first main surface of the semiconductor substrate;
A second opening is formed in the second main surface of the semiconductor substrate and a second region penetrating the semiconductor substrate in a thickness direction and spaced apart from a first region corresponding to the first opening of the second main surface of the semiconductor substrate. A wiring layer forming step of forming a wiring layer formed on the inner wall of the through-hole including a portion and electrically connected to the one pad conductive layer through the second opening;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating layer is a passivation film.   The method of manufacturing a semiconductor device according to claim 2, wherein the first region and the second region are separated from each other by 10 μm or more. A semiconductor circuit formed on the first main surface of the semiconductor substrate;
For evaluating the characteristics of the semiconductor circuit, covering a first main surface of a semiconductor substrate and one pad conductive layer formed on the first main surface of the semiconductor substrate and exposing a part of the one pad conductive layer An insulating layer having a first opening of
A through-hole provided with a second opening in a second region that penetrates the semiconductor substrate in a thickness direction and is spaced apart from a first region corresponding to the first opening of the second main surface of the semiconductor substrate;
A wiring layer formed on the inner wall of the through-hole and the second main surface of the semiconductor substrate and electrically connected to the one pad conductive layer through the second opening;
A semiconductor device comprising:   The semiconductor device according to claim 5, wherein the insulating layer is a passivation film.   The semiconductor device according to claim 5, wherein the first region and the second region are separated by 10 μm or more.

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