JP2011076685A - Nonvolatile semiconductor memory device and writing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device and a writing method thereof, for achieving further miniaturization without causing a reduction in writing speed, a writing error, etc. <P>SOLUTION: The nonvolatile semiconductor memory device includes: a plurality of memory cells having selection transistors and memory cell transistors; a bit line connected to a drain of the selection transistor; a first word line connected to a control gate of the memory cell transistor; a second word line connected to a select gate of the selection transistor; and a source line connected to a source of the memory cell transistor. Information is written into the memory cells by at least performing a first step to apply a second voltage V<SB>pulse(1)</SB>in a pulsed manner to the source line while applying a first voltage V<SB>step(1)</SB>to the first word line, and a second step to apply a fourth voltage V<SB>pulse(2)</SB>lower than the second voltage in a pulsed manner to the source line while applying a third voltage V<SB>step(2)</SB>higher than the first voltage to the first word line. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a writing method thereof.

  Recently, a nonvolatile semiconductor memory device in which a memory cell is formed by a selection transistor and a memory cell transistor has been proposed.

  In such a nonvolatile semiconductor memory device, a bit line, a word line, a source line, etc. are appropriately selected by a column decoder or a row decoder, whereby a memory cell is selected, information is read from the selected memory cell, Writing, erasing, etc. are performed.

JP-A-10-188586

  However, when further miniaturization is attempted, it is conceivable that a writing speed delay, a writing failure, or the like occurs.

  An object of the present invention is to provide a nonvolatile semiconductor memory device and a writing method thereof that can realize further miniaturization without causing a delay in writing speed or a writing failure.

  According to one aspect of the embodiment, a plurality of memory cells having a selection transistor and a memory cell transistor connected to the selection transistor, a bit line connected to a drain of the selection transistor, and the memory cell transistor A first word line connected to the control gate, a second word line connected to the select gate of the select transistor, and a source line connected to the source of the memory cell transistor, A first step of applying a second voltage to the source line while applying a voltage to the first word line; and a third step higher than the first voltage after the first step. The second voltage is applied to the source line in a pulsed manner by applying a fourth voltage lower than the second voltage to the first word line. By performing at least a-up, non-volatile semiconductor memory device and writes the information into said memory cells is provided.

  According to another aspect of the embodiment, a plurality of memory cells having a selection transistor and a memory cell transistor connected to the selection transistor; a bit line connected to a drain of the selection transistor; and the memory cell transistor A non-volatile semiconductor memory having a first word line connected to the control gate of the memory cell; a second word line connected to the select gate of the select transistor; and a source line connected to the source of the memory cell transistor A writing method of a device, comprising: a first step of applying a second voltage to the source line in a pulsed manner while applying a first voltage to the first word line; and Later, while applying a third voltage higher than the first voltage to the first word line, the second voltage is applied to the source line. By performing at least a second step of applying a lower fourth voltage pulsed, writing method for a nonvolatile semiconductor memory device and writes the information into said memory cells is provided.

  According to the disclosed nonvolatile semiconductor memory device and the writing method thereof, the magnitude of the pulse voltage applied to the source line SL in the first step is equal to the pulse voltage applied to the source line SL in the second step and thereafter. It is set higher than the size. In the first step of writing, it is necessary to rapidly increase the threshold voltage of the memory cell transistor having a significantly low threshold voltage to a predetermined determination level. On the other hand, in the first step of writing, since the potential of the first word line is relatively low, even if the pulse voltage applied to the source line is set to be relatively high, an error occurs in the unselected memory cells. No writing occurs. Since the threshold voltage of the memory cell transistor exceeds a predetermined determination level in the first step writing, it is not necessary to set the pulse voltage applied to the source line to be relatively high in the second step after writing. In the second and subsequent steps of writing, since the pulse voltage applied to the source line is not set to be relatively high, erroneous writing to non-selected memory cells does not occur. Therefore, it is possible to miniaturize the nonvolatile semiconductor memory device without causing a writing speed delay or a writing failure.

It is a circuit diagram which shows the non-volatile semiconductor memory device by a reference example. FIG. 2 is a schematic view showing a cross section of a memory cell of the nonvolatile semiconductor memory device shown in FIG. 1. 3 is a flowchart showing a writing method of the nonvolatile semiconductor memory device shown in FIGS. 1 and 2. 6 is a graph showing a relationship between a difference V _OD between a control gate voltage and a threshold voltage and a threshold voltage shift amount ΔV _th . It is a graph (the 1) which shows the dispersion | variation in the threshold voltage of a memory cell transistor. It is a graph (the 2) which shows the dispersion | variation in the threshold voltage of a memory cell transistor. 4 is a flowchart showing a writing method of the nonvolatile semiconductor memory device. 1 is a circuit diagram illustrating a nonvolatile semiconductor memory device according to one embodiment. FIG. 1 is a plan view showing a memory cell array of a nonvolatile semiconductor memory device according to one embodiment. FIG. 10 is a cross-sectional view taken along line AA ′ of FIG. 9. It is BB 'sectional drawing of FIG. FIG. 10 is a sectional view taken along the line CC ′ of FIG. 9. It is a figure which shows the reading method of the non-volatile semiconductor memory device by one Embodiment, the writing method, and the erasing method. 3 is a time chart showing a method for writing to a nonvolatile semiconductor memory device according to one embodiment. It is process sectional drawing (the 1) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 2) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 3) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 4) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 5) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 6) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 7) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 8) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 9) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 10) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 11) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 12) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 13) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 14) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 15) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. It is process sectional drawing (the 16) which shows the manufacturing method of the non-volatile semiconductor memory device by one Embodiment. 10 is a time chart showing a modification (No. 1) of the writing method of the nonvolatile semiconductor memory device according to the embodiment. 12 is a time chart showing a modification (No. 2) of the writing method of the nonvolatile semiconductor memory device according to the embodiment.

  FIG. 1 is a circuit diagram showing a nonvolatile semiconductor memory device according to a reference example.

  As shown in FIG. 1, a memory cell MC is formed by a select transistor ST and a memory cell transistor MT connected to the select transistor ST. The source of the selection transistor ST is connected to the drain of the memory cell transistor MT.

  The plurality of memory cells MC are arranged in a matrix. A memory cell array 110 is formed by a plurality of memory cells MC arranged in a matrix.

  The drains of the plurality of select transistors ST present in the same column are commonly connected by a bit line BL. Control gates of a plurality of memory cell transistors MT existing in the same row are commonly connected by a first word line WL1. Select gates of a plurality of select transistors ST present in the same row are commonly connected by a second word line WL2. The sources of the plurality of memory cell transistors MT in the same row are commonly connected by a source line SL. The sources of the memory cell transistors MT present in adjacent rows are connected by a common source line SL.

  A plurality of bit lines BL that commonly connect the drains of the selection transistors ST are connected to the column decoder 112. The column decoder 112 is connected to a sense amplifier 113 for detecting a current flowing through the bit line BL.

  The plurality of first word lines WL1 that commonly connect the control gates of the memory cell transistors MT are connected to the first row decoder 114. A plurality of second word lines WL2 that commonly connect the select gates of the select transistors ST are connected to the second row decoder 116. A plurality of source lines SL that commonly connect the sources of the memory cell transistors MT are connected to the third row decoder 118.

  FIG. 2 is a schematic diagram showing a cross section of the memory cell of the nonvolatile semiconductor memory device shown in FIG.

  As shown in FIG. 2, a floating gate (FG) 130a of the memory cell transistor MT is formed on the semiconductor substrate 120 via a tunnel insulating film 28a. A control gate (CG) 134a of the memory cell transistor MT is formed on the floating gate 130a via an insulating film 132a. The control gates 134a of the memory cell transistors MT existing in the same row are commonly connected. In other words, the first word line WL1 that commonly connects the control gates 134a is formed on the floating gate 130a via the insulating film 132a.

  A select gate (SG) 130b of the select transistor ST is formed on the semiconductor substrate 120 in parallel with the floating gate 130a of the memory cell transistor MT. The select gates 130b of the select transistors ST present in the same row are commonly connected. In other words, the second word line WL2 that commonly connects the select gates 130b is formed on the semiconductor substrate 120 via the gate insulating film 128b. A polysilicon layer 134b is formed on the select gate 130b via an insulating film 132b.

  N-type impurity diffusion layers 136a, 136b, and 136c are formed in the semiconductor substrate 120 on both sides of the floating gate 130a and in the semiconductor substrate 120 on both sides of the select gate 130b. The impurity diffusion layer 136b serving as the drain of the memory cell transistor MT and the impurity diffusion layer 136b serving as the source of the selection transistor ST are formed by the same impurity diffusion layer 136b.

  Thus, the memory cell transistor MT having the floating gate 130a, the control gate 134a, and the source / drain diffusion layers 136a and 136b is formed. In addition, a select transistor ST having a select gate 130b and source / drain diffusion layers 136b and 136c is formed.

  The source diffusion layer 136a of the memory cell transistor MT is connected to the source line SL. The drain diffusion layer 136c of the selection transistor ST is connected to the bit line BL. In the nonvolatile semiconductor memory device shown in FIG. 1 and FIG. 2, information is written in the memory cell transistor MT by generating hot carriers and injecting the generated hot carriers into the floating gate 130a of the memory cell transistor MT.

  FIG. 3 is a flowchart showing a writing method of the nonvolatile semiconductor memory device shown in FIGS.

When writing information to the memory cell transistor MT, the potential of the bit line BL connected to the memory cell MC to be selected is set to 0V. On the other hand, the potentials of the bit lines BL other than the selected bit line BL are set to _VCC .

Further, the potential of the second word line WL2 is connected to the memory cell to be selected and V _CC. On the other hand, the potentials of the second word lines WL2 other than the selected second word line WL2 are set to 0 V (ground).

  Further, the voltage applied to the first word line WL1 connected to the memory cell MC to be selected is gradually increased. The voltage applied to the first word line WL1 is gradually increased, for example, in three stages. The voltage applied to the first word line WL1 in the first step is 3V, for example. In the second step, the voltage applied to the first word line WL1 is, for example, 4.5V. The voltage applied to the first word line WL1 in the third step is, for example, 6V. On the other hand, the potential of the first word line WL1 other than the selected first word line WL1 is set to 0 V or floating.

  Further, a voltage is applied in a pulse form to the source line SL connected to the memory cell MC to be selected. The pulse voltage applied to the source line SL is, for example, 5.5V. On the other hand, the potentials of the source lines SL other than the selected source line SL are set to 0 V or floating.

  As described above, the voltage applied to the first word line WL1 connected to the memory cell MC to be selected is gradually increased, and the voltage is pulsed to the source line SL connected to the memory cell MC to be selected. By applying the voltage, information is written in the memory cell transistor MT.

  The reason why the voltage is applied in pulses to the source line SL in the selected row while gradually increasing the voltage applied to the first word line WL1 in the selected row is as follows. That is, when a relatively high voltage is applied to the control gate 134b of the memory cell transistor MT, the electrical resistance between the source / drain of the memory cell transistor MT is reduced. As a result, the electrical resistance between the source and the drain of the memory cell transistor MT becomes smaller than the electrical resistance between the source and the drain of the selection transistor ST. As a result, a relatively large lateral electric field is applied between the source / drain of the selection transistor ST, whereas a sufficient lateral electric field is not applied between the source / drain of the memory cell transistor MT. If a sufficient lateral electric field is not applied between the source / drain of the memory cell transistor MT, electrons are not accelerated between the source / drain of the memory cell transistor MT, and the writing speed is reduced.

  On the other hand, if a relatively low voltage is applied to the first word line WL1 in the selected row in the initial stage of writing, the electrical resistance between the source and drain of the memory cell transistor MT becomes excessively small. There is no end to it. Then, when a voltage is applied to the source line SL of the selected row in a pulse shape, charges are injected into the floating gate 130a of the memory cell transistor MT.

  If the voltage is applied to the source line SL of the selected row in a pulsed manner while gradually increasing the voltage of the first word line WL1 of the selected row, charges are gradually injected into the floating gate 130a of the memory cell transistor MT. Go. Although the voltage applied to the first word line WL1 in the selected row gradually increases, the charge accumulated in the floating gate 130a also gradually increases. Therefore, the voltage between the source and drain of the memory cell transistor MT is increased. The electrical resistance does not become excessively small.

  As described above, when the voltage applied to the source line SL in the selected row is applied in a pulsed manner while gradually increasing the voltage applied to the first word line WL1 in the selected row, information is written to the memory cell transistor MT. It is possible to increase the speed.

FIG. 4 is a graph showing the relationship between the difference V _OD between the control gate voltage and the threshold voltage and the threshold voltage shift amount ΔV _th . The horizontal axes in FIGS. 4A and 4B indicate the difference V _OD between the control gate voltage and the threshold voltage. The vertical axes in FIGS. 4A and 4B indicate the threshold voltage shift amount ΔV _th .

FIG. 4A shows a case where the gate voltage V _SG of the selection transistor is changed. In FIG. 4A, the ▪ marks indicate the case where the gate voltage V _SG of the selection transistor ST is 1.7V. In FIG. 4A, the ♦ mark indicates the case where the gate voltage V _SG of the selection transistor ST is 2V. A plot with a circle in FIG. 4A shows a case where the gate voltage V _SG of the selection transistor ST is 2.3V. In FIG. 4A, the plots indicated by the triangles indicate the case where the gate voltage V _SG of the selection transistor ST is 2.6V.

In addition, when acquiring the electrical characteristic shown to Fig.4 (a), it set to the following conditions. The source voltage V _S was set to 5.5V. The drain current _ID was 1 μA. The pulse width of the voltage applied to the source line SL was 5 μsec. The time for erasing information written in the memory cell transistor MT in advance was 400 ms.

FIG. 4B shows a case where the source voltage V _S is changed. In FIG. 4B, the ▪ marks indicate the case where the pulse voltage applied to the source voltage SL is 4.75V. The plot with ◆ in FIG. 4B shows the case where the voltage applied to the source voltage SL in a pulsed manner is 5V. In FIG. 4B, the plots with squares indicate the case where the voltage applied in a pulsed manner to the source voltage SL is 5.25V. In FIG. 4B, the circled plots indicate a case where the voltage applied in a pulsed manner to the source voltage SL is 5.5V. In FIG. 4B, the plots indicated by the triangles indicate the case where the voltage applied to the source voltage SL in a pulsed manner is 5.75V.

In addition, when acquiring the characteristic shown in FIG.4 (b), it set to the following conditions. The gate voltage V _SG of the selection transistor ST is set to V _CC , that is, 2.3V. The drain current _ID was 1 μA. The pulse width of the voltage _{V S} applied to the source line SL is set to 5 .mu.sec. The time for erasing information written in the memory cell transistor MT in advance was 400 ms.

As can be seen from FIGS. 4A and 4B, the threshold voltage shift amount ΔV _{th at} the time of writing includes the control gate voltage of the memory cell transistor MT, the gate voltage V _SG of the selection transistor ST, and the source line SL. It depends on the voltage V _S applied to the.

FIG. 5 is a graph (part 1) showing variation in the threshold voltage of the memory cell transistor. The horizontal axis in FIG. 5 indicates the threshold voltage _Vth of the memory cell transistor. The vertical axis in FIG. 5 represents the inverse function of the standard normal cumulative distribution.

  The plot with ◇ in FIG. 5 shows the distribution of the threshold voltage of the memory cell transistor after erasing, that is, before writing. In FIG. 5, the ◯ marks indicate the threshold voltage distribution of the memory cell transistor MT when the first step writing is completed. That is, the distribution of the threshold voltage of the memory cell transistor MT when the voltage of the first word line WL1 is raised to 3V and a pulse voltage of 5.5V is applied to the source line SL is shown.

  A plot indicated by Δ in FIG. 5 shows the threshold voltage distribution of the memory cell transistor MT when the writing in the second step is completed. That is, the threshold voltage distribution of the memory cell transistor MT when the voltage of the first word line WL1 is raised to 4.5 V and a pulse voltage of 5.5 V is applied to the source line SL is shown.

  The plots indicated by □ in FIG. 5 indicate the threshold voltage distribution of the memory cell transistor MT when the write in the third step is completed. That is, the distribution of the threshold voltage of the memory cell transistor MT when the voltage of the first word line WL1 is raised to 6V and a pulse voltage of 5.5V is applied to the source line SL is shown.

  Note that the pulse width of the voltage applied to the source line SL was 5 μsec. In each of the first step, the second step, and the third step, the number of pulses applied to the source line SL is set to one each.

  In each step, it is necessary that the threshold voltage of the memory cell transistor MT exceeds each determination level. In the first step, the threshold voltage of the memory cell transistor MT needs to exceed the first determination level. In the second step, the threshold voltage of the memory cell transistor MT needs to exceed the second determination level. In the third step, it is necessary that the threshold voltage of the memory cell transistor MT exceeds the third determination level. The first determination level is, for example, −0.5V. The second determination level is, for example, 1V. The third determination level is, for example, 2.5V. Whether or not the threshold voltage of the memory cell transistor MT exceeds a predetermined determination level is determined by detecting a current flowing through the bit line BL when a voltage of a predetermined determination level is applied to the first word line WL1. Is possible.

  When information is written to the memory cell transistor MT, a pulsed voltage is repeatedly applied to the source line SL until the threshold voltage of the memory cell transistor MT exceeds each determination level. If the threshold voltage of the memory cell transistor MT does not exceed a predetermined determination level only by applying the pulse voltage to the source line SL once, the pulse voltage is applied to the source line SL within one step. It may be applied multiple times. FIG. 3 shows an example in which a pulsed voltage is applied to the source line SL once in each step.

  In the case of FIG. 5, the variation in the threshold voltage of the memory cell transistor MT before writing is relatively small, and there is no memory cell transistor MT with a very low threshold voltage.

  Accordingly, in the first step of writing, the threshold voltage of any memory cell transistor MT exceeds the first determination level only by applying the pulse voltage to the source line SL once. Also in the second step of writing, the threshold voltage of any memory cell transistor MT exceeds the second determination level only by applying the pulse voltage to the source line SL once. Also in the third step of writing, the threshold voltage of any memory cell transistor MT exceeds the third determination level only by applying the pulse voltage to the source line SL once.

  However, if the nonvolatile semiconductor memory device is further miniaturized, the variation in the erase characteristic of the memory cell transistor MT increases, and the variation in the threshold voltage of the memory cell transistor MT before writing may increase. Then, when various conditions such as a change in applied voltage applied to each part of the memory cell MC are taken into consideration, it is considered that variations as shown in FIG. 6 occur.

FIG. 6 is a graph (part 2) showing variation in the threshold voltage of the memory cell transistor. The horizontal axis in FIG. 6 shows the threshold voltage _Vth of the memory cell transistor MT. The vertical axis in FIG. 6 represents the inverse function of the standard normal cumulative distribution.

  The plot with ◇ in FIG. 6 shows the threshold voltage distribution of the memory cell transistor MT after erasing, that is, before writing.

  The large ● mark plot, large ○ mark plot, small ● mark plot, and small ○ mark plot in FIG. 6 indicate the threshold voltage distribution of the memory cell transistor MT when writing in the first step. Yes. In FIG. 6, a large mark ● indicates that the threshold of the memory cell transistor MT when the potential of the first word line WL1 is raised to the potential of the first step and a pulse voltage is applied to the source line SL once. The voltage distribution is shown.

  In FIG. 6, the large circled plots indicate that the threshold of the memory cell transistor MT when the potential of the first word line WL1 is raised to the potential of the first step and a pulse voltage is applied to the source line SL six times. The voltage distribution is shown.

  In FIG. 6, the small ● mark plots the threshold of the memory cell transistor MT when the potential of the first word line WL1 is raised to the potential of the first step and a pulse voltage is applied 12 times to the source line SL. The voltage distribution is shown.

  In FIG. 6, the small circled plots indicate that the threshold of the memory cell transistor MT when the potential of the first word line WL1 is raised to the potential of the first step and a pulsed voltage is applied 19 times to the source line SL. The voltage distribution is shown.

  Note that the potential of the first word line WL1 in the first step was set to 3.0V. In consideration of the case where the voltage applied to the source line SL varies, the voltage applied to the source line SL is set to a value 5% lower than the rated value. Further, considering the case where the gate voltage of the selection transistor ST varies, the gate voltage of the selection transistor ST is set to 2.07 V which is 10% lower than the rated value 2.3V.

  In FIG. 6, the plots indicated by ▲ and △ indicate the threshold voltage distribution of the memory cell transistor when the second step writing is performed. In FIG. 6, a plot indicated by a triangle mark shows that the threshold voltage of the memory cell transistor MT when the potential of the first word line WL1 is raised to the potential of the second step and a pulse voltage is applied to the source line SL once. The distribution of is shown.

  The plot of Δ in FIG. 6 shows the threshold voltage of the memory cell transistor MT when the potential of the first word line WL1 is raised to the potential of the second step and a pulse voltage is applied twice to the source line SL. The distribution of is shown.

  Note that the potential of the first word line WL1 in the second step was set to 4.5V. In consideration of the case where the voltage applied to the source line SL varies, the voltage applied to the source line SL is set to a value 5% lower than the rated value. Further, considering the case where the gate voltage of the selection transistor ST varies, the gate voltage of the selection transistor ST is set to 2.07 V which is 10% lower than the rated value 2.3V.

  In FIG. 6, the ▪ marks indicate the threshold voltage distribution of the memory cell transistor MT when the third step writing is performed. In FIG. 6, the ■ mark plots the threshold voltage of the memory cell transistor MT when the potential of the first word line WL1 is raised to the potential of the third step and a pulse voltage is applied to the source line SL once. The distribution of is shown.

  Note that the potential of the first word line WL1 in the third step was 6.0V. In consideration of the case where the voltage applied to the source line SL varies, the voltage applied to the source line SL is set to a value 5% lower than the rated value. Further, considering the case where the gate voltage of the selection transistor ST varies, the gate voltage of the selection transistor ST is set to 2.07 V which is 10% lower than the rated value 2.3V.

  Note that the pulse width of the voltage applied to the source line SL was 5 μsec.

  When the nonvolatile semiconductor memory device is further miniaturized, as can be seen from FIG. 6, the variation in threshold voltage of the memory cell transistor MT after erasure, that is, before writing becomes relatively large. Further, a memory cell transistor MT whose threshold voltage before writing is as low as about −4.5 V, for example, may occur.

  As can be seen from FIG. 6, in the case of the memory cell transistor MT having a remarkably low threshold voltage before writing, the threshold voltage of the memory cell transistor MT is the same even when a pulse voltage is applied to the source line SL, for example, 19 times. The determination level of 1 may not be exceeded. As described above, when the voltage applied to the first word line WL1 in the second step increases in the memory cell transistor MT having a remarkably low threshold voltage, the writing becomes more difficult to proceed, and finally a writing failure occurs.

As a technique for preventing the writing failure, it is conceivable to increase the gate voltage V _SG of the selection transistor ST. This is because the threshold voltage shift amount ΔV _{th of} the memory cell transistor MT tends to increase as the gate voltage V _SG of the selection transistor ST is set higher (see FIG. 4A).

However, when the gate voltage V _SG of the select transistor ST is increased, the leakage current of the bit line BL may increase.

Further, by increasing the voltage V _S applied to the source line SL, and it is conceivable to prevent the write failure. The higher set voltage V _S applied to the source line SL, and because the shift amount [Delta] V _th of the threshold voltage of the memory cell transistor MT tends to increase (see Figure 4 (b)).

However, when simply increasing the voltage V _S applied to the source line SL, there is a possibility that erroneous writing with respect to the non-selected memory cell MC is caused.

That is, as described above with reference to FIG. 1, the sources of the plurality of memory cell transistors MT in the same row are commonly connected by the source line SL. For this reason, the same voltage as the source voltage of the memory cell transistor MT of the selected memory cell MC is applied to the source of the memory cell transistor MT of the non-selected memory cell MC existing in the same row as the selected memory cell MC. Is done. Therefore, as the voltage V _S applied to the source line SL is high, erroneous writing is likely to occur with respect to the non-selected memory cell MC.

  Note that, as the voltage of the first word line WL1 is higher, erroneous writing to the non-selected memory cell MC is more likely to occur. The higher the voltage of the first word line WL1, the more likely that erroneous writing to unselected memory cells MC occurs. The higher the voltage of the first word line WL1, the more hot carriers are injected into the floating gate 130a. This is because it becomes easier.

  As a result of intensive studies, the inventors of the present application have made the magnitude of the pulse voltage applied to the source line SL in the first step higher than the magnitude of the pulse voltage applied to the source line SL in the second step and thereafter. (See FIG. 7). FIG. 7 is a flowchart showing a writing method of the nonvolatile semiconductor memory device.

In the first writing step, the voltage of the first word line WL1 is 3 V, for example (see FIG. 3). When writing in the first step to the memory cell transistor MT having a threshold voltage of −4V, for example, the difference V _OD between the control gate voltage and the threshold voltage is 7V. When the voltage V _S applied to the source line SL is 5.75 V (see FIG. 7) and the difference V _OD between the control gate voltage and the threshold voltage is 7 V, it can be seen from FIG. 4B. In addition, the threshold voltage shift amount ΔV _th is about 4V. Therefore, in this case, the threshold voltage of the memory cell transistor MT can be raised to 0 V by simply applying a pulse voltage to the source line SL once in the first step writing. When the first determination level is −0.5 V, for example, the threshold voltage of the memory cell transistor MT is set to the first determination level only by applying a pulse voltage of 5.75 V to the source line SL once. Over.

  If the threshold voltage of the memory cell transistor MT before writing is as low as about −4.5 V, for example, the first determination is made only by applying a pulse voltage of 5.75 V to the source line SL once. It may not exceed the level.

  However, if a pulse voltage of 5.75 V is applied to the source line SL, for example, twice, the threshold voltage of the memory cell transistor MT exceeds the first determination level.

  Therefore, even if the threshold voltage of the memory cell transistor MT is as low as about −4.5 V, for example, no particular problem occurs.

  Note that in the first step of writing, the voltage applied to the first word line WL1 is relatively low at 3V, so the pulse voltage applied to the source line SL is relatively high at 5.75V. In other words, no erroneous writing occurs in the non-selected memory cells MC.

In the second step of writing, the voltage applied to the source line SL is set to 5.5 V, for example. In the second writing step, for example, a voltage of 4.5 V is applied to the first word line WL1 (see FIG. 3). When writing in the second step to the memory cell transistor MT whose threshold voltage has increased to 0V, the difference V _OD between the control gate voltage and the threshold voltage is 4.5V. When the voltage V _S applied to the source line SL is 5.5 V and the difference V _OD between the control gate voltage and the threshold voltage is 4.5 V, as can be seen from FIG. The voltage shift amount ΔV _th is about 2V. Therefore, in this case, the threshold voltage _Vth of the memory cell transistor MT rises to 2V just by applying a pulse voltage once to the source line SL in the second step writing. When the second determination level is 1 V, for example, the threshold voltage of the memory cell transistor MT exceeds the second determination level only by applying a pulse voltage once to the source line SL.

  Note that in the second step of writing, the voltage applied to the source line SL is relatively low, for example, 5.5 V, so that erroneous writing does not occur in the non-selected memory cells MC.

Also in the third step of writing, the voltage applied to the source line SL is set to 5.5 V, for example. In the third step of writing, for example, a voltage of 6 V is applied to the first word line WL1 (see FIG. 3). When writing in the third step for the memory cell transistor MT whose threshold voltage has risen to 2V, the difference V _OD between the control gate voltage and the threshold voltage is 4V. When the voltage applied to the source line SL is 5.5V and the difference V _OD between the control gate voltage and the threshold voltage is 4V, as can be seen from FIG. 4B, the threshold voltage shift amount. ΔV _th is about 1.7V. In this case, in the third step writing, the threshold voltage _Vth of the memory cell transistor MT rises to 3.7 V, for example, by applying a pulse voltage once to the source line SL. When the third determination level is 2.5 V, for example, the threshold voltage of the memory cell transistor MT exceeds the third determination level only by applying a pulse voltage once to the source line SL.

In the third step of the writing, the voltage V _S applied to the source line SL is relatively low and 5.5V, does not write error occurs for unselected memory cell MC.

  Thus, the inventor of the present application makes the magnitude of the pulse voltage applied to the source line SL in the first step higher than the magnitude of the pulse voltage applied to the source line SL in the second step and thereafter. I came up with it. In the first step of writing, it is necessary to rapidly increase the threshold voltage of the memory cell transistor MT having a significantly low threshold voltage to the first determination level. On the other hand, in the first writing step, since the potential of the first word line WL1 is relatively low, even if the pulse voltage applied to the source line SL is set relatively high, the non-selected memory cell MC On the other hand, no erroneous writing occurs. Since the threshold voltage of the memory cell transistor MT exceeds the first determination level in the first step writing, it is necessary to set the pulse voltage applied to the source line SL relatively high after the second step of writing. Absent. In the second and subsequent steps of writing, since the pulse voltage applied to the source line SL is not set to be relatively high, erroneous writing to non-selected memory cells MC does not occur. Therefore, according to the method conceived by the inventor of the present application, it is possible to miniaturize the nonvolatile semiconductor memory device without causing a delay in writing speed or a writing failure.

[One Embodiment]
A nonvolatile semiconductor memory device according to the first embodiment, a writing method, a reading method, an erasing method, and a manufacturing method of the nonvolatile semiconductor memory device will be described with reference to FIGS.

(Nonvolatile semiconductor memory device)
First, the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIGS. FIG. 8 is a circuit diagram showing the nonvolatile semiconductor memory device according to the present embodiment.

  As shown in FIG. 8, in the nonvolatile semiconductor memory device according to the present embodiment, a memory cell MC is formed by a select transistor ST and a memory cell transistor MT connected to the select transistor ST. The source of the selection transistor ST is connected to the drain of the memory cell transistor MT. More specifically, the source of the selection transistor ST and the drain of the memory cell transistor MT are integrally formed by one impurity diffusion layer.

  The plurality of memory cells MC are arranged in a matrix. A memory cell array 10 is formed by a plurality of memory cells MC arranged in a matrix.

  The drains of the plurality of select transistors ST present in the same column are commonly connected by a bit line BL. Control gates of a plurality of memory cell transistors MT existing in the same row are commonly connected by a first word line WL1. Select gates of a plurality of select transistors ST present in the same row are commonly connected by a second word line WL2.

  The sources of the plurality of memory cell transistors MT in the same row are commonly connected by a source line SL. The sources of the memory cell transistors MT present in adjacent rows are connected by a common source line SL.

  A plurality of bit lines BL that commonly connect the drains of the select transistors ST are connected to the column decoder 12. The column decoder 12 is for controlling the potentials of a plurality of bit lines BL that commonly connect the drains of the selection transistors ST. The column decoder 12 is connected to a sense amplifier 13 for detecting a current flowing through the bit line BL. The column decoder 12 is formed by a low voltage circuit that operates at a relatively low voltage.

  The plurality of first word lines WL1 that commonly connect the control gates of the memory cell transistors MT are connected to the first row decoder 14. The first row decoder 14 is for controlling the potentials of the plurality of first word lines WL1 that commonly connect the control gates of the memory cell transistors MT. The first row decoder 14 is formed by a high voltage circuit (high voltage circuit).

  The first row decoder 14 is connected to first voltage application means (not shown). The first voltage applying means can change the output voltage as appropriate. Therefore, in this embodiment, the voltage applied to the first word line WL1 can be changed as appropriate.

  A plurality of second word lines WL2 that commonly connect the select gates of the select transistors ST are connected to the second row decoder 16. The second row decoder 16 is for controlling the potentials of the plurality of second word lines WL2 that commonly connect the select gates of the select transistors ST. The second row decoder 16 is formed by a low voltage circuit (low withstand voltage circuit).

  A plurality of source lines SL that commonly connect the sources of the memory cell transistors MT are connected to the third row decoder 18. The third row decoder 18 is for controlling the potentials of a plurality of source lines SL that commonly connect the sources of the memory cell transistors MT. The third row decoder 18 is formed by a high voltage circuit (high voltage circuit).

  The third row decoder 18 is connected to a second voltage application unit (not shown). The second voltage applying means can change the output voltage as appropriate. Therefore, in this embodiment, the magnitude of the voltage applied to the source line SL can be changed as appropriate.

  Next, the structure of the memory cell array of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIGS. FIG. 9 is a plan view of the memory cell array of the nonvolatile semiconductor memory device according to the present embodiment. FIG. 10 is a cross-sectional view taken along the line AA ′ of FIG. 11 is a cross-sectional view taken along the line BB ′ of FIG. 12 is a cross-sectional view taken along the line CC ′ of FIG.

  In the semiconductor substrate 20, an element isolation region 22 that defines an element region 21 is formed. As the semiconductor substrate 20, for example, a P-type silicon substrate is used. The element isolation region 22 is formed by, for example, an STI (Shallow Trench Isolation) method.

  An N-type buried diffusion layer 24 is formed in the semiconductor substrate 20 in which the element isolation region 22 is formed. The upper portion of the N type buried diffusion layer 24 is a P type well 26.

  A floating gate 30a is formed on the semiconductor substrate 20 via a tunnel insulating film 28a. The floating gate 30 a is electrically isolated for each element region 21.

  A control gate 34a is formed on the floating gate 30a via an insulating film 32a. The control gates 34a of the memory cell transistors MT existing in the same row are commonly connected. In other words, the first word line WL1 that commonly connects the control gate 34a is formed on the floating gate 30 via the insulating film 32a.

  A select gate 30b of the select transistor ST is formed on the semiconductor substrate 20 in parallel with the floating gate 30a. The select gates 30b of the select transistors ST existing in the same row are connected in common. In other words, the second word line WL2 that commonly connects the select gates 30b is formed on the semiconductor substrate 20 via the gate insulating film 28b. The thickness of the gate insulating film 28b of the selection transistor ST is equal to the thickness of the tunnel insulating film 28a of the memory cell transistor MT.

  A polysilicon layer 34b is formed on the select gate 30b via an insulating film 32b.

  N-type impurity diffusion layers 36a, 36b, and 36c are formed in the semiconductor substrate 20 on both sides of the floating gate 30a and in the semiconductor substrate 20 on both sides of the select gate 30b.

  The impurity diffusion layer 36b serving as the drain of the memory cell transistor MT and the impurity diffusion layer 36b serving as the source of the selection transistor ST are formed by the same impurity diffusion layer 36b.

  A sidewall insulating film 37 is formed on the side wall portion of the stacked body having the floating gate 30a and the control gate 34a.

  A sidewall insulating film 37 is formed on the side wall portion of the stacked body having the select gate 30b and the polysilicon layer 34b.

  Silicide layers 38a to 38d made of, for example, cobalt silicide are formed on the source region 36a of the memory cell transistor MT, the drain region 36c of the selection transistor ST, the upper portion of the control gate 34a, and the upper portion of the polysilicon layer 34b, respectively. ing. The silicide layer 38a on the source electrode 36a functions as a source electrode. The silicide layer 38c on the drain electrode 36c functions as a drain electrode.

  Thus, the memory cell transistor MT having the floating gate 30a, the control gate 34a, and the source / drain diffusion layers 36a and 36b is formed.

  Further, a selection transistor ST having a select gate 30b and source / drain diffusion layers 36b and 36c is formed.

  On the semiconductor substrate 20 on which the memory cell transistor MT and the select transistor ST are formed, an interlayer insulating film 40 made of a silicon nitride film (not shown) and a silicon oxide film (not shown) is formed.

  In the interlayer insulating film 40, contact holes 42 reaching the source electrode 38a and the drain electrode 38b are formed.

  A conductor plug 44 made of, for example, tungsten is embedded in the contact hole 42.

  A wiring (first metal wiring layer) 46 is formed on the interlayer insulating film 40 in which the conductor plugs 44 are embedded.

  An interlayer insulating film 48 is formed on the interlayer insulating film 40 on which the wiring 46 is formed.

  A contact hole 50 reaching the wiring 46 is formed in the interlayer insulating film 48.

  A conductor plug 52 made of, for example, tungsten is embedded in the contact hole 50.

  A wiring (second metal wiring layer) 54 is formed on the interlayer insulating film 48 in which the conductor plug 52 is embedded.

  An interlayer insulating film 56 is formed on the interlayer insulating film 48 on which the wiring 54 is formed.

  A contact hole 58 reaching the wiring 54 is formed in the interlayer insulating film 56.

  A conductor plug 60 made of, for example, tungsten is embedded in the contact hole 58.

  A wiring (third metal wiring layer) 62 is formed on the interlayer insulating film 56 in which the conductor plug 60 is embedded.

  Thus, the memory cell array 10 (see FIG. 8) of the nonvolatile semiconductor memory device according to the present embodiment is formed.

(Operation of nonvolatile semiconductor memory device)
Next, the operation method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIGS. FIG. 13 is a diagram illustrating a read method, a write method, and an erase method of the nonvolatile semiconductor memory device according to the present embodiment. In FIG. 13, the parentheses indicate the potential of the non-selected line. In FIG. 13, F indicates floating. FIG. 14 is a time chart showing the writing method of the nonvolatile semiconductor memory device according to the present embodiment.

(Writing method)
Next, the writing method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIGS.

  When writing information to the memory cell transistor MT, the potential of each part is set as follows.

That is, when writing information to the memory cell transistor MT, the potential of the bit line BL connected to the memory cell MC to be selected is set to 0V. On the other hand, the potentials of the bit lines BL other than the selected bit line BL are set to _VCC .

Further, the potential of the second word line WL2 is connected to the memory cell to be selected and V _CC. On the other hand, the potentials of the second word lines WL2 other than the selected second word line WL2 are set to 0 V (ground).

Further, the voltage V _step applied to the first word line WL1 connected to the memory cell MC to be selected is gradually increased. The voltage applied to the first word line WL1 is gradually increased, for example, in three stages.

The voltage V _{step (1)} applied to the first word line WL1 in the first step of writing is, for example, 3V. Note that the voltage _{Vstep (1)} applied to the first word line WL1 in the first step is not limited to 3V. The voltage V _{step (1)} applied to the first word line WL1 may be set as appropriate so that the writing proceeds efficiently without causing erroneous writing to the non-selected memory cells MC.

In the second writing step, a voltage V _{step (2)} higher than the voltage V _{step (1)} applied to the first word line WL1 in the first writing step is applied to the first word line WL1. The voltage V _{step (2)} applied to the first word line WL1 in the second step of writing is, for example, 4.5V. Note that the voltage _{Vstep (2)} applied to the first word line WL1 in the second step of writing is not limited to 4.5V. The voltage V _{step (2)} applied to the first word line WL1 may be set as appropriate so that the writing proceeds efficiently without causing erroneous writing to the non-selected memory cells MC.

In the third step of writing, a voltage V _{step (3)} higher than the voltage applied to the first word line WL1 in the second step of writing is applied to the first word line WL1. The voltage V _{step (3)} applied to the first word line WL1 in the third step of writing is, for example, 6V. Note that the voltage V _{step (3)} applied to the first word line WL1 in the third step of writing is not limited to 6V. The voltage V _{step (3)} to be applied to the first word line WL1 may be set as appropriate so that writing proceeds efficiently without causing erroneous writing to the non-selected memory cells MC.

  Note that the potentials of the first word lines WL1 other than the selected first word line WL1 are set to 0 V or floating.

Further, the voltage V _pulse is applied in a pulse form to the source line SL connected to the memory cell MC to be selected. In the first writing step, the voltage V _{pulse (1)} applied in a pulsed manner to the source line SL is set to, for example, 5.8V. In the second writing step, the voltage V _{pulse (2)} applied in a pulsed manner to the source line SL is set to 5.5 V, for example. In the third step of writing, the voltage V _{pulse (3)} applied in a pulsed manner to the source line SL is set to, for example, 5.5V. The pulse width of the voltage V _pulse applied to the source line SL is, for example, 5 μsec.

In the present embodiment, the reason why the voltage V _{pulse (1)} applied to the source line SL in the first step of writing is set to 5.8 V, for example, is as follows. That is, in FIG. 7, the voltage applied to the source line SL in the first step of writing is set to 5.75V. However, when the voltage applied to the source line SL is set to 5.8V, substantially the same characteristics are obtained. can get. Further, if the voltage applied to the source line SL is increased, it can contribute to the improvement of the shift amount of the threshold voltage of the memory cell transistor MT. Therefore, in the present embodiment, the voltage V _{pulse (1)} applied to the source line SL in the first writing step is set to, for example, 5.8V.

Note that the voltage V _{pulse (1)} applied to the source line SL in the first step of writing is not limited to 5.8V. The voltage V _{pulse (1)} applied to the source line SL in the first step of writing may be set higher than 5.8V or lower than 5.8V. For example, the voltage V _{pulse (1)} applied to the source line SL in the first writing step may be 5.75 V as in FIG. If the voltage V _{pulse (1)} applied to the source line SL in the first step is set at least higher than the voltage applied to the source line SL in the second step, the progress of writing in the first step can be promoted. Is possible.

When writing information to the memory cell transistor MT, the pulsed voltage V _{pulse (1)} is repeatedly applied to the source line SL until the threshold voltage of the memory cell transistor MT exceeds each determination level. If the threshold voltage of the memory cell transistor MT does not exceed a predetermined determination level only by applying the _pulse voltage V _{pulse (1)} once to the source line SL, the source line SL is applied to the source line SL within one step. The pulsed voltage V _{pulse (1)} is applied a plurality of times. FIG. 14 shows an example in which a _pulsed voltage V _{pulse (1)} is applied to the source line SL once in each step.

The voltages V _{pulse (2)} and V _{pulse (3)} applied to the source line SL after the second step of writing are not limited to 5.5V. The voltages V _{pulse (2)} and V _{pulse (3)} to be applied to the source line SL may be set as appropriate so that the writing proceeds efficiently without causing erroneous writing to the unselected memory cells MC.

Further, the voltage V _{pulse (3)} applied to the source line SL in the third step of writing may be equal to the voltage V _{pulse (2)} applied to the source line SL in the second step of writing. It may be different from V _{pulse (2)} . However, the voltage V _{pulse (3)} applied to the source line SL in the third step of writing is preferably set lower than the voltage V _{pulse (1)} applied to the source line SL in the first step of writing.

The magnitude of the _pulse voltage V _{pulse (1)} applied to the source line SL in the first step is equal to the pulse voltage V _{pulse (2)} , V _{pulse ( 2)} applied to the source line SL in the second step and thereafter. It is set larger than the size of ₃₎ .

  The potential of the well 26 is always 0 V (ground).

Thus, in the present embodiment, the magnitude of the pulse voltage _{V pulse} applied to the source line SL ₍₁₎ in a first step, a pulsed voltage _{V pulse} applied to the source line SL in the second and subsequent step ₍₂₎ It is made larger than the size of V _{pulse (3)} .

In the first writing step, the voltage V _{step (1)} of the first word line WL1 is, for example, 3 V (see FIG. 14). When writing in the first step to the memory cell transistor MT having a threshold voltage of −4V, for example, the difference V _OD between the control gate voltage and the threshold voltage is 7V. When the voltage V _{pulse (1)} applied to the source line SL is 5.8 V, and the difference V _OD between the control gate voltage and the threshold voltage is 7 V, the threshold voltage shift amount ΔV _th is about 4 V. (See FIG. 4B). When the voltage V _{pulse (1)} applied to the source line SL is 5.8 V, the threshold voltage shift amount of the memory cell transistor MT is set to 5.75 V for the voltage V _{pulse (1)} applied to the source line SL. This is because the threshold voltage shift amount of the memory cell transistor MT in this case is almost the same. Therefore, in this case, the threshold voltage of the memory cell transistor MT can be raised to 0 V by applying the _pulse voltage V _{pulse (1)} once to the source line SL in the first step writing. it can. When the first determination level is −0.5 V, for example, the threshold voltage of the memory cell transistor MT can be obtained by applying the _pulse voltage V _{pulse (1)} of 5.8 V once to the source line SL. The first determination level is exceeded.

In addition, when the threshold voltage of the memory cell transistor MT before writing is remarkably low, for example, about −4.5 V, the _pulse voltage V _{pulse (1)} of 5.75 V is simply applied once to the source line SL. The first determination level may not be exceeded.

However, if the pulse voltage V _{pulse (1)} of 5.8 V is applied to the source line SL, for example, twice, the threshold voltage of the memory cell transistor MT exceeds the first determination level.

  Therefore, even if the threshold voltage of the memory cell transistor MT is as low as about −4.5 V, for example, no particular problem occurs.

In the first step, since the voltage V _{step (1)} applied to the first word line WL1 is relatively low, the pulsed voltage V _{pulse (1)} applied to the source line SL is relatively high. Nevertheless, no erroneous writing occurs in the non-selected memory cell MC.

In the second step of writing, the voltage V _{pulse (2)} applied to the source line SL is set to, for example, 5.5V. In the second step of writing, for example, a voltage V _{step (2) of} 4.5 V is applied to the first word line WL1 (see FIG. 14). When writing in the second step to the memory cell transistor MT whose threshold voltage has increased to 0V, the difference V _OD between the control gate voltage and the threshold voltage is 4.5V. When the voltage V _{pulse (2)} applied to the source line SL is 5.5 V and the difference V _OD between the control gate voltage and the threshold voltage is 4.5 V, it can be seen from FIG. In addition, the threshold voltage shift amount ΔV _th is about 2V. Therefore, in this case, the threshold voltage _Vth of the memory cell transistor MT rises to 2V just by applying the _pulsed voltage _{Vpulse (2)} once to the source line SL in the second step writing. . When the second determination level is 1 V, for example, the threshold voltage of the memory cell transistor MT exceeds the second determination level just by applying the _pulse voltage V _{pulse (2)} once to the source line SL. .

In the second step of writing, the voltage V _{pulse (2)} applied to the source line SL is relatively low, for example, 5.5 V, so that no erroneous writing occurs in the non-selected memory cells MC.

Also in the third step of writing, the voltage V _{pulse (3)} applied to the source line SL is set to 5.5 V, for example. In the third step of writing, for example, a voltage V _{step (3) of} 6 V is applied to the first word line WL1 (see FIG. 14). When writing in the third step for the memory cell transistor MT whose threshold voltage has risen to 2V, the difference V _OD between the control gate voltage and the threshold voltage is 4V. When the voltage V _{pulse (3)} applied to the source line SL is 5.5 V and the difference V _OD between the control gate voltage and the threshold voltage is 4 V, as can be seen from FIG. The threshold voltage shift amount ΔV _th is about 1.7V. In this case, the threshold voltage _Vth of the memory cell transistor MT rises to 3.7 V, for example, by applying the _pulse voltage V _{pulse (3)} once to the source line SL in the third step writing. To do. When the third determination level is 2.5 V, for example, the threshold voltage of the memory cell transistor MT is set to the third determination level only by applying the _pulsed voltage V _{pulse (3)} once to the source line SL. Over.

Even in the third step of writing, since the voltage V _{pulse (3)} applied to the source line SL is relatively low, no erroneous writing occurs in the non-selected memory cells MC.

Thus, in the present embodiment, the magnitude of the pulse voltage _{V pulse} applied to the source line SL ₍₁₎ in a first step, a pulsed voltage _{V pulse} applied to the source line SL in the second and subsequent step ₍₂₎ Set higher than the magnitude of V _{pulse (3)} . That is, in the present embodiment, in the first step of writing, the second voltage V _{pulse (1)} is applied to the source line SL while applying the first voltage V _{step (1)} to the first word line WL1. Is applied in pulses. In the second step of writing, the third voltage V _{step (2)} higher than the first voltage V _{step (1)} is selectively applied to the first word line WL1, while being applied to the source line SL. A fourth voltage V _{pulse (2)} lower than the second voltage V _{pulse (1)} is applied in a pulse shape. In the third step of writing, the fifth voltage V _{step (3)} higher than the third voltage V _{step (2)} is selectively applied to the first word line WL1, and the source line SL is applied. A sixth voltage V _{pulse (3)} lower than the second voltage V _{pulse (1 )} is applied. In the first step of writing, it is necessary to rapidly increase the threshold voltage of the memory cell transistor MT having a significantly low threshold voltage to the first determination level. On the other hand, in the first step of writing, since the potential V _{step (1) of} the first word line WL1 is relatively low, the pulse voltage V _{pulse (1)} applied to the source line SL is set to be relatively high. However, no erroneous writing occurs in the non-selected memory cells MC. Since the threshold voltage of the memory cell transistor MT exceeds the first determination level in the first step writing, the pulsed voltages V _{pulse (2)} and V _pulse applied to the source line SL in the second and subsequent steps of the writing. ₍₃₎ need not be set higher. In the second and subsequent steps of writing, since the pulse voltages V _{pulse (2)} and V _{pulse (3)} applied to the source line SL are relatively low, erroneous writing to the non-selected memory cells MC does not occur. . Therefore, according to the present embodiment, it is possible to miniaturize the nonvolatile semiconductor memory device without causing a write speed delay or a write failure.

(Reading method)
First, the read method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG.

  When reading the information written in the memory cell array 10, the potential of each part is set as follows.

That is, the potential of the bit line BL connected to the memory cell MC to be selected is set to _VCC . On the other hand, the potentials of the bit lines BL other than the selected bit line are set to 0V. The potentials of the source lines SL are all 0V. Potential of the first word line WL1 is in a read operation standby, both of which always _{V CC.} The potential of the second word line WL2 is connected to the memory cell MC to be selected to V _CC. On the other hand, the potentials of the second word lines WL2 other than the selected second word line WL2 are set to 0V. The potentials of the wells 26 are all 0V.

Since the potential of the source line SL is set to 0V during the read standby and the potential of the first word line WL1 is always set to _VCC during the read standby, the potential of the bit line BL and the second word Information can be read only by controlling the potential of the line WL2.

  In this embodiment, since the column decoder 12 that controls the potential of the bit line BL is formed by a low voltage circuit, the bit line BL is controlled at high speed. In addition, since the second row decoder 16 that controls the potential of the second word line WL2 is formed by a low voltage circuit, the second word line WL2 is controlled at high speed. Therefore, according to the present embodiment, information written in the memory cell transistor MT can be read at high speed.

  When information is written in the memory cell transistor MT, that is, when the information in the memory cell transistor MT is 0 ″, charges are accumulated in the floating gate 30a of the memory cell transistor MT. No current flows between the source diffusion layer 36a of the memory cell transistor MT and the drain diffusion layer 36c of the selection transistor ST, and no current flows through the selected bit line BL. It is determined that the MT information is “0”.

  On the other hand, when the information written in the memory cell transistor MT is erased, that is, when the information of the memory cell is “1”, no charge is accumulated in the floating gate 30a of the memory cell transistor MT. In this case, a current flows between the source diffusion layer 36a of the memory cell transistor MT and the drain diffusion layer 36c of the selection transistor ST, and a current flows through one selected bit line BL. The current flowing through the selected bit line BL is detected by the sense amplifier 13. In this case, it is determined that the information of the memory cell transistor MT is “1”.

(Erase method)
Next, the erasing method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG.

  When erasing information written in the memory cell array 10, the potential of each part is set as follows.

  That is, the potentials of the bit lines BL are all floating. The potentials of the source lines SL are all floating. The potential of the first word line WL1 is set to −9 V, for example. The potential of the second word line WL2 is all floating. The potential of the well 26 is, for example, + 9V.

  When the potential of each part is set as described above, charges are extracted from the floating gate 30a of the memory cell transistor MT. As a result, no charge is accumulated in the floating gate 30a of the memory cell transistor MT, and information in the memory cell transistor MT is erased.

(Method for manufacturing nonvolatile semiconductor memory device)
Next, the method for fabricating the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIGS. 15 to 30 are process cross-sectional views illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the present embodiment.

  15 (a), 16 (a), 17 (a), 18 (a), 19 (a), 20 (a), 21 (a), 22 (a), and 23. FIGS. 24A, 24A, 25, 27, and 29 show the memory cell array region (core region) 2. FIG. 15 (a), 16 (a), 17 (a), 18 (a), 19 (a), 20 (a), 21 (a), 22 (a), and 23. FIGS. 24A, 24 </ b> A, 25, 27, and 29 correspond to the CC ′ cross section of FIG. 9. 15 (a), 16 (a), 17 (a), 18 (a), 19 (a), 20 (a), 21 (a), 22 (a), and 23. FIGS. 24A, 24A, 25, 27 and 29 on the right side of the drawing correspond to the AA ′ cross section of FIG.

  15 (b), FIG. 16 (b), FIG. 17 (b), FIG. 18 (b), FIG. 19 (b), FIG. 20 (b), FIG. 21 (b), FIG. 22 (b), FIG. FIGS. 24B, 24 </ b> B, 26, 28, and 30 illustrate the peripheral circuit region 4. 15 (b), FIG. 16 (b), FIG. 17 (b), FIG. 18 (b), FIG. 19 (b), FIG. 20 (b), FIG. 21 (b), FIG. 22 (b), FIG. The left side of FIG. 24B, FIG. 24B, FIG. 26, FIG. 28, and FIG. 30 shows the region 6 where the high voltage transistor is formed. The left side of the drawing in the region 6 where the high breakdown voltage transistor is formed shows a region 6N where the high breakdown voltage N-channel transistor is formed. The right side of the region 6N where the high breakdown voltage N-channel transistor is formed shows the region 6P where the high breakdown voltage P-channel transistor is formed. The right side of the region 6P where the high breakdown voltage P-channel transistor is formed shows a region 6N where the high breakdown voltage N-channel transistor is formed.

  15 (b), FIG. 16 (b), FIG. 17 (b), FIG. 18 (b), FIG. 19 (b), FIG. 20 (b), FIG. 21 (b), FIG. 22 (b), FIG. The right side of FIG. 24B, FIG. 24B, FIG. 26, FIG. 28, and FIG. 30 shows the region 8 where the low voltage transistor is formed. The left side of the paper 8 in the region 8 where the low voltage transistor is formed shows the region 8N where the low voltage N channel transistor is formed, and the right side of the paper 8 in the region 8 where the low voltage transistor is formed is the low voltage P channel. A region 8P where a transistor is formed is shown.

  First, the semiconductor substrate 20 is prepared. For example, a P-type silicon substrate is prepared as the semiconductor substrate 20.

  Next, a 15 nm-thickness thermal oxide film 64 is formed on the entire surface by, eg, thermal oxidation.

  Next, a silicon nitride film 66 having a thickness of 150 nm is formed on the entire surface by, eg, CVD.

  Next, a photoresist film (not shown) is formed on the entire surface by, eg, spin coating.

  Next, an opening (not shown) is formed in the photoresist film using a photolithography technique. The opening is for patterning the silicon nitride film 66.

  Next, the silicon nitride film 66 is patterned using the photoresist film as a mask. Thereby, a hard mask 66 made of a silicon nitride film is formed.

  Next, the semiconductor substrate 20 is etched by dry etching using the hard mask 66 as a mask. As a result, a groove 68 is formed in the semiconductor substrate 20 (see FIG. 15). The depth of the groove 68 formed in the semiconductor substrate 20 is, for example, 400 nm from the surface of the semiconductor substrate 20.

  Next, the exposed portion of the semiconductor substrate 20 is oxidized by a thermal oxidation method. As a result, a silicon oxide film (not shown) is formed on the exposed portion of the semiconductor substrate 20.

  Next, as shown in FIG. 16, a 700 nm-thickness silicon oxide film 22 is formed on the entire surface by high-density plasma CVD.

  Next, as shown in FIG. 17, the silicon oxide film 22 is polished by CMP (Chemical Mechanical Polishing) until the surface of the silicon nitride film 66 is exposed. Thus, an element isolation region 22 made of a silicon oxide film is formed.

  Next, a heat treatment for curing the element isolation region 22 is performed. The heat treatment conditions are, for example, 900 ° C. and 30 minutes in a nitrogen atmosphere.

  Next, the silicon nitride film 66 is removed by wet etching.

  Next, as shown in FIG. 18, a sacrificial oxide film 69 is grown on the surface of the semiconductor substrate 20 by thermal oxidation.

  Next, as shown in FIG. 19, an N type buried diffusion layer 24 is formed by deeply implanting an N type dopant impurity into the memory cell array region 2. At this time, an N-type buried diffusion layer 24 is formed also by deeply implanting an N-type dopant impurity in the region 6N where the high breakdown voltage N-channel transistor is formed. Also, a P-type well 26 is formed by implanting a P-type dopant impurity shallower than the buried diffusion layer 24 into the memory cell array region 2. Also, a P-type well 72P is formed by implanting a P-type dopant impurity shallower than the buried diffusion layer 24 into the region 6N where the high breakdown voltage N-channel transistor is to be formed.

  Next, an N-type diffusion layer 70 is formed in a frame shape in the region 6N where the high breakdown voltage N-channel transistor is formed. The frame-shaped diffusion layer 70 is formed so as to extend from the surface of the semiconductor substrate 20 to the peripheral portion of the buried diffusion layer 24. The P-type well 72P is surrounded by the buried diffusion layer 24 and the diffusion layer 70. Although not shown, the P-type well 26 in the memory cell array region 2 is also surrounded by the buried diffusion layer 24 and the frame-like diffusion layer 70.

  Next, an N-type well 72N is formed by introducing an N-type dopant impurity into the region 6P where the high breakdown voltage P-channel transistor is formed.

  Next, channel doping is performed on the memory cell array region 2 (not shown).

  Next, channel doping is performed on the region 6N where the high breakdown voltage N-channel transistor is formed and the region 6P where the high breakdown voltage P-channel transistor is formed (not shown).

  Next, the sacrificial oxide film 69 present on the surface of the semiconductor substrate 20 is removed by etching.

  Next, a tunnel insulating film 28 having a thickness of 10 nm is formed on the entire surface by thermal oxidation.

  Next, a polysilicon film 30 having a thickness of 90 nm is formed on the entire surface by, eg, CVD. As the polysilicon film 30, a polysilicon film doped with impurities is formed.

  Next, the polysilicon film 30 existing in the peripheral circuit region 4 is removed by etching.

  Next, an insulating film (ONO film) 32 formed by sequentially laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film is formed on the entire surface. The insulating film 32 is for insulating the floating gate 30a and the control gate 34a.

  Next, as shown in FIG. 20, a P-type well 74P is formed by introducing a P-type dopant impurity into a region 8N where a low-voltage N-channel transistor is to be formed.

  Next, an N-type well 74N is formed by introducing an N-type dopant impurity into the region 8P where the low-voltage P-channel transistor is to be formed.

  Next, channel doping is performed on the region 8N where the low-voltage N-channel transistor is formed and the region 8P where the low-voltage P-channel transistor is formed (not shown).

  Next, the insulating film (ONO film) 32 present in the peripheral circuit region 4 is removed by etching.

  Next, a gate insulating film 76 of, eg, a 15 nm-thickness is formed on the entire surface by thermal oxidation.

  Next, the gate insulating film 76 present in the region 8 where the low voltage transistor is formed is removed by wet etching.

  Next, a gate insulating film 78 of, eg, a 3 nm-thickness is formed on the entire surface by thermal oxidation. Thereby, in the region 8 where the low voltage transistor is formed, for example, a gate insulating film having a film thickness of 3 nm is formed. On the other hand, in the region 6 where the high breakdown voltage transistor is formed, the thickness of the gate insulating film 76 is, for example, about 16 nm.

  Next, a polysilicon film 34 of, eg, a 180 nm-thickness is formed on the entire surface by, eg, CVD.

  Next, an antireflection film 80 is formed on the entire surface.

  Next, as shown in FIG. 21, the antireflection film 80, the polysilicon film 34, the insulating film 32, and the polysilicon film 30 are dry-etched using photolithography. As a result, a stacked body including the floating gate 30a made of polysilicon and the control gate 34a made of polysilicon is formed in the memory cell array region 2. A stacked body including a select gate 30b made of polysilicon and a polysilicon film 34b is formed in the memory cell array region 2.

  Next, the polysilicon film 34b is removed by etching (not shown) in a region where the wiring (first metal wiring) 46 and the select gate 30b are to be connected.

  Next, as shown in FIG. 22, a silicon oxide film (FIG. 22) is formed on the sidewall portion of the floating gate 30a, the sidewall portion of the control gate 34a, the sidewall portion of the select gate 30b, and the sidewall portion of the polysilicon film 34b by thermal oxidation. (Not shown).

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, an opening (not shown) that exposes the memory cell array region 2 is formed in the photoresist film using a photolithography technique.

  Next, N-type dopant impurities are introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thus, impurity diffusion layers 36a to 36c are formed in the semiconductor substrate 20 on both sides of the floating gate 30a and in the semiconductor substrate 20 on both sides of the select gate 30b. Thereafter, the photoresist film is peeled off.

  Thus, the memory cell transistor MT having the floating gate 30a, the control gate 34a, and the source / drain diffusion layers 36a and 36b is formed. Further, the selection transistor ST having the control gate 30b and the source / drain diffusion layers 36b and 36c is formed.

  Next, a silicon oxide film 82 is formed on the sidewall portion of the floating gate 30a, the sidewall portion of the control gate 34b, the sidewall portion of the select gate 30b, and the sidewall portion of the polysilicon film 34b by thermal oxidation.

  Next, a 50 nm-thickness silicon nitride film 84 is formed by, eg, CVD.

  Next, by performing anisotropic etching on the silicon nitride film 84 by dry etching, a sidewall insulating film 84 made of a silicon nitride film is formed. At this time, the antireflection film 80 is removed by etching.

  Next, the photolithography technique is used to pattern the polysilicon film 34 in the region 6 where the high voltage transistor is formed and the region 8 where the low voltage transistor is formed. Thereby, the gate electrode 34c of the high breakdown voltage transistor made of the polysilicon film 34 is formed. Further, a gate electrode 34d of a low voltage transistor made of polysilicon 34 is formed.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, using a photolithography technique, an opening (not shown) exposing the region 6N where the high voltage N-channel transistor is to be formed is formed in the photoresist film.

  Next, N-type dopant impurities are introduced into the semiconductor substrate 20 using the photoresist film as a mask. As a result, an N-type low-concentration diffusion layer 86 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high breakdown voltage N-channel transistor. Thereafter, the photoresist film is peeled off.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, using a photolithography technique, an opening (not shown) exposing the region 6P where the high voltage P-channel transistor is to be formed is formed in the photoresist film.

  Next, a P-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. As a result, a P-type low-concentration diffusion layer 88 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high breakdown voltage P-channel transistor. Thereafter, the photoresist film is peeled off.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, using a photolithography technique, an opening (not shown) exposing the region 8N where the low voltage N-channel transistor is to be formed is formed in the photoresist film.

  Next, N-type dopant impurities are introduced into the semiconductor substrate 20 using the photoresist film as a mask. As a result, an N-type low-concentration diffusion layer 90 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low-voltage N-channel transistor. Thereafter, the photoresist film is peeled off.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, an opening (not shown) exposing the region 8P where the low-voltage P-channel transistor is to be formed is formed in the photoresist film by using a photolithography technique.

  Next, a P-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. As a result, a P-type low-concentration diffusion layer 92 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low-voltage P-channel transistor. Thereafter, the photoresist film is peeled off.

  Next, a 100 nm-thickness silicon oxide film 93 is formed by, eg, CVD.

  Next, the silicon oxide film 93 is anisotropically etched by dry etching. As a result, a sidewall insulating film 93 made of a silicon oxide film is formed on the side wall portion of the stacked body having the floating gate 30a and the control gate 34a (see FIG. 23). A sidewall insulating film 93 made of a silicon oxide film is formed on the side wall portion of the stacked body having the select gate 30b and the polysilicon film 34b. A sidewall insulating film 93 made of a silicon oxide film is formed on the side wall portion of the gate electrode 34c. A sidewall insulating film 93 made of a silicon oxide film is formed on the side wall portion of the gate electrode 34d.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, using a photolithography technique, an opening (not shown) exposing the region 6N where the high voltage N-channel transistor is to be formed is formed in the photoresist film.

  Next, N-type dopant impurities are introduced into the semiconductor substrate 20 using the photoresist film as a mask. Thereby, an N-type high concentration diffusion layer 94 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high breakdown voltage N-channel transistor. The N-type low-concentration diffusion layer 86 and the N-type high-concentration diffusion layer 94 form an N-type source / drain diffusion layer 96 having an LDD structure. Thus, a high breakdown voltage N-channel transistor 110N having the gate electrode 34c and the source / drain diffusion layer 96 is formed. The high breakdown voltage N-channel transistor 110N is used in a high voltage circuit (high breakdown voltage circuit). Thereafter, the photoresist film is peeled off.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, using a photolithography technique, an opening (not shown) exposing the region 6P where the high voltage P-channel transistor is to be formed is formed in the photoresist film.

  Next, a P-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. As a result, a P-type high concentration diffusion layer 98 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34c of the high breakdown voltage P-channel transistor. The P-type low-concentration diffusion layer 88 and the P-type high-concentration diffusion layer 98 form a P-type source / drain diffusion layer 100 having an LDD structure. Thus, a high breakdown voltage P-channel transistor 110P having the gate electrode 34c and the source / drain diffusion layer 100 is formed. The high breakdown voltage P-channel transistor 110P is used in a high voltage circuit (high breakdown voltage circuit). Thereafter, the photoresist film is peeled off.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, using a photolithography technique, an opening (not shown) exposing the region 8N where the low voltage N-channel transistor is to be formed is formed in the photoresist film.

  Next, N-type dopant impurities are introduced into the semiconductor substrate 20 using the photoresist film as a mask. As a result, an N-type high concentration diffusion layer 102 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low-voltage N-channel transistor. An N-type source / drain diffusion layer 104 having an LDD structure is formed by the N-type low-concentration diffusion layer 90 and the N-type high-concentration diffusion layer 102. Thus, the low voltage N-channel transistor 112N having the gate electrode 34d and the source / drain diffusion layer 104 is formed. The low voltage N-channel transistor 112N is used in a low voltage circuit. Thereafter, the photoresist film is peeled off.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, an opening (not shown) exposing the region 8P where the low-voltage P-channel transistor is to be formed is formed in the photoresist film by using a photolithography technique.

  Next, a P-type dopant impurity is introduced into the semiconductor substrate 20 using the photoresist film as a mask. As a result, a P-type high concentration diffusion layer 106 is formed in the semiconductor substrate 20 on both sides of the gate electrode 34d of the low voltage P-channel transistor. The P-type low-concentration diffusion layer 92 and the P-type high-concentration diffusion layer 106 form a P-type source / drain diffusion layer 108 having an LDD structure. Thus, the low voltage P-channel transistor 112P having the gate electrode 34d and the source / drain diffusion layer 108 is formed. The low voltage P-channel transistor 112P is used in a low voltage circuit. Thereafter, the photoresist film is peeled off.

  Next, a cobalt film having a thickness of 10 nm is formed on the entire surface by, eg, sputtering.

  Next, heat treatment is performed to react silicon atoms on the surface of the semiconductor substrate 20 with cobalt atoms in the cobalt film. Also, silicon atoms on the surface of the control gate 34c are reacted with cobalt atoms in the cobalt film. Further, silicon atoms on the surface of the polysilicon film 34d are reacted with cobalt atoms in the cobalt film. Further, silicon atoms on the surfaces of the gate electrodes 34c and 34d are reacted with cobalt atoms in the cobalt film. Thus, cobalt silicide films 38a and 38b are formed on the source / drain diffusion layers 36a and 36c (see FIG. 24). A cobalt silicide film 38c is formed on the control gate 34a. A cobalt silicide film 38d is formed on the polysilicon film 34b. A cobalt silicide film 38e is formed on the source / drain diffusion layers 96, 100, 104, and 108. A cobalt silicide film 38f is formed on the gate electrodes 34c and 34d.

  Next, the unreacted cobalt film is removed by etching.

  The cobalt silicide film 38b formed on the drain diffusion layer 36c of the selection transistor ST functions as a drain electrode.

  The cobalt silicide film 38a formed on the source diffusion layer 36a of the memory cell transistor MT functions as a source electrode.

  The cobalt silicide film 38e formed on the source / drain diffusion layers 96, 100 of the high breakdown voltage transistors 110N, 110P functions as a source / drain electrode.

  The cobalt silicide film 38e formed on the source / drain diffusion layers 104 and 108 of the low voltage transistors 112N and 112P functions as a source / drain electrode.

  Next, as shown in FIGS. 25 and 26, a 100 nm-thickness silicon nitride film 114 is formed on the entire surface by, eg, CVD. The silicon nitride film 114 functions as an etching stopper.

  Next, a 1.6 μm-thickness silicon oxide film 116 is formed on the entire surface by CVD. Thus, the interlayer insulating film 40 composed of the silicon nitride film 114 and the silicon oxide film 116 is formed.

  Next, the surface of the interlayer insulating film 40 is planarized by CMP.

  Next, a contact hole 42 reaching the source / drain electrodes 38a, 38b, a contact hole 42 reaching the cobalt silicide film 38e, and a contact hole 42 reaching the cobalt silicide film 38f are formed by using a photolithography technique (FIG. 27, FIG. 27). (See FIG. 28).

  Next, a barrier layer (not shown) composed of a Ti film and a TiN film is formed on the entire surface by sputtering.

  Next, a 300 nm-thickness tungsten film 44 is formed on the entire surface by, eg, CVD.

  Next, the tungsten film 44 and the barrier film are polished by CMP until the surface of the interlayer insulating film 40 is exposed. Thus, the conductor plug 44 made of, for example, tungsten is embedded in the contact hole 42.

  Next, a laminated film 46 formed by sequentially laminating a Ti film, a TiN film, an Al film, a Ti film, and a TiN film is formed on the interlayer insulating film 40 in which the conductor plugs 44 are embedded, for example, by sputtering.

  Next, the laminated film 46 is patterned using a photolithography technique. As a result, a wiring (first metal wiring layer) 46 made of a laminated film is formed.

  Next, as shown in FIGS. 29 and 30, a 700 nm-thickness silicon oxide film 118 is formed by, for example, high-density plasma CVD.

  Next, a silicon oxide film 120 is formed by TEOSCVD. The silicon oxide film 118 and the silicon oxide film 120 form an interlayer insulating film 48.

  Next, a contact hole 50 reaching the wiring 46 is formed in the interlayer insulating film 48 using a photolithography technique.

  Next, a barrier layer (not shown) composed of a Ti film and a TiN film is formed on the entire surface by sputtering.

  Next, a 300 nm-thickness tungsten film 52 is formed on the entire surface by, eg, CVD.

  Next, the tungsten film 52 and the barrier film are polished by CMP until the surface of the interlayer insulating film 48 is exposed. Thus, the conductor plug 52 made of, for example, tungsten is embedded in the contact hole 50.

  Next, a laminated film 54 formed by sequentially laminating a Ti film, a TiN film, an Al film, a Ti film, and a TiN film is formed on the interlayer insulating film 48 in which the conductor plugs 52 are embedded, for example, by sputtering.

  Next, the laminated film 54 is patterned using a photolithography technique. As a result, a wiring (second metal wiring layer) 54 made of a laminated film is formed.

  Next, a silicon oxide film 122 is formed by, for example, a high density plasma CVD method.

  Next, a silicon oxide film 124 is formed by TEOSCVD. An interlayer insulating film 56 is formed by the silicon oxide film 122 and the silicon oxide film 124.

  Next, a contact hole 58 reaching the wiring 54 is formed in the interlayer insulating film 56 using a photolithography technique.

  Next, a barrier layer (not shown) composed of a Ti film and a TiN film is formed on the entire surface by sputtering.

  Next, a 300 nm-thickness tungsten film 60 is formed on the entire surface by, eg, CVD.

  Next, the tungsten film 60 and the barrier film are polished by CMP until the surface of the interlayer insulating film 56 is exposed. Thus, a conductor plug 60 (see FIG. 30) made of, for example, tungsten is buried in the contact hole 58.

  Next, the laminated film 62 is formed on the interlayer insulating film 56 in which the conductor plug 60 is embedded, for example, by sputtering.

  Next, the laminated film 62 is patterned using a photolithography technique. Thereby, a wiring (third metal wiring layer) 62 made of a laminated film is formed.

  Next, a silicon oxide film 126 is formed by, for example, a high density plasma CVD method.

  Next, a silicon oxide film 128 is formed by TEOSCVD. An interlayer insulating film 130 is formed by the silicon oxide film 126 and the silicon oxide film 128.

  Next, a contact hole 132 reaching the wiring 62 is formed in the interlayer insulating film 130 using a photolithography technique.

  Next, a barrier layer (not shown) composed of a Ti film and a TiN film is formed on the entire surface by sputtering.

  Next, a 300 nm-thickness tungsten film 134 is formed on the entire surface by, eg, CVD.

  Next, the tungsten film 134 and the barrier film are polished by CMP until the surface of the interlayer insulating film 130 is exposed. Thus, a conductor plug (not shown) 134 made of, for example, tungsten is buried in the contact hole 132.

  Next, a laminated film 136 is formed on the interlayer insulating film 130 in which the conductor plugs 134 are embedded, for example, by sputtering.

  Next, the laminated film 136 is patterned using a photolithography technique. Thereby, a wiring (fourth metal wiring layer) 136 made of a laminated film is formed.

  Next, a silicon oxide film 138 is formed by, for example, high density plasma CVD.

  Next, a silicon oxide film 140 is formed by TEOSCVD. The silicon oxide film 138 and the silicon oxide film 140 form an interlayer insulating film 142.

  Next, a contact hole 143 reaching the wiring 136 is formed in the interlayer insulating film 142 by using a photolithography technique.

  Next, a barrier layer (not shown) composed of a Ti film and a TiN film is formed on the entire surface by sputtering.

  Next, a 300 nm-thickness tungsten film 146 is formed on the entire surface by, eg, CVD.

  Next, the tungsten film 146 and the barrier film are polished by CMP until the surface of the interlayer insulating film 142 is exposed. Thus, the conductor plug 144 made of, for example, tungsten is buried in the contact hole 143.

  Next, the laminated film 145 is formed on the interlayer insulating film 142 in which the conductor plugs 144 are embedded, for example, by sputtering.

  Next, the laminated film 145 is patterned using a photolithography technique. As a result, a wiring (fifth metal wiring layer) 145 made of a laminated film is formed.

  Next, a silicon oxide film 146 is formed by, for example, a high density plasma CVD method.

  Next, a silicon nitride film 148 having a thickness of 1 μm is formed by plasma CVD.

  Thus, the nonvolatile semiconductor memory device according to the present embodiment is manufactured.

  As described above, in this embodiment, the magnitude of the pulse voltage applied to the source line SL in the first step is set higher than the magnitude of the pulse voltage applied to the source line SL in the second step and thereafter. . In the first step of writing, it is necessary to rapidly increase the threshold voltage of the memory cell transistor MT having a significantly low threshold voltage to the first determination level. On the other hand, in the first writing step, since the potential of the first word line WL1 is relatively low, even if the pulse voltage applied to the source line SL is set relatively high, the non-selected memory cell MC On the other hand, no erroneous writing occurs. Since the threshold voltage of the memory cell transistor MT exceeds the first determination level in the first step writing, it is necessary to set the pulse voltage applied to the source line SL relatively high after the second step of writing. Absent. In the second and subsequent steps of writing, since the pulse voltage applied to the source line SL is not set to be relatively high, erroneous writing to non-selected memory cells MC does not occur. Therefore, according to the present embodiment, the nonvolatile semiconductor memory device can be miniaturized without causing a delay in writing speed or a writing failure.

(Modification (Part 1))
Next, a modification (No. 1) of the writing method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG. FIG. 31 is a time chart showing a writing method of the nonvolatile semiconductor memory device according to this modification.

  When writing information to the memory cell transistor MT, the potential of each part is set as follows.

That is, when writing information to the memory cell transistor MT, the potential of the bit line BL connected to the memory cell MC to be selected is set to 0V. On the other hand, the potentials of the bit lines BL other than the selected bit line BL are set to _VCC .

Further, the potential of the second word line WL2 is connected to the memory cell to be selected and V _CC. On the other hand, the potentials of the second word lines WL2 other than the selected second word line WL2 are set to 0 V (ground).

Further, the voltage V _step applied to the first word line WL1 connected to the memory cell MC to be selected is gradually increased. Here, the voltage V _step applied to the first word line WL1 is gradually increased, for example, in four stages.

The voltage V _{step (1)} applied to the first word line WL1 in the first writing _step is set to 1.0 V, for example. Note that the voltage _{Vstep (1)} applied to the first word line WL1 in the first step is not limited to 1.0V. The voltage V _{step (1)} applied to the first word line WL1 may be set as appropriate so that the writing proceeds efficiently without causing erroneous writing to the non-selected memory cells MC.

In the second writing step, a voltage V _{step (2)} higher than the voltage V _{step (1)} applied to the first word line WL1 in the first writing step is applied to the first word line WL1. The voltage V _{step (2)} applied to the first word line WL1 in the second step of writing is, for example, 3.0V. Note that the voltage _{Vstep (2)} applied to the first word line WL1 in the second step of writing is not limited to 3.0V. The voltage V _{step (2)} applied to the first word line WL1 may be set as appropriate so that the writing proceeds efficiently without causing erroneous writing to the non-selected memory cells MC.

In the third step of writing, a voltage V _{step (3)} higher than the voltage applied to the first word line WL1 in the second step of writing is applied to the first word line WL1. The voltage V _{step (3)} applied to the first word line WL1 in the third step of writing is, for example, 4.5V. Note that the voltage V _{step (3)} applied to the first word line WL1 in the third step of writing is not limited to 4.5V. The voltage V _{step (3)} to be applied to the first word line WL1 may be set as appropriate so that writing proceeds efficiently without causing erroneous writing to the non-selected memory cells MC.

In the fourth step of writing, a voltage V _{step (4)} higher than the voltage applied to the first word line WL1 in the second step of writing is applied to the first word line WL1. The voltage V _{step (4)} applied to the first word line WL1 in the fourth step of writing is set to 6.0 V, for example. Note that the voltage _{Vstep (4)} applied to the first word line WL1 in the fourth step of writing is not limited to 6.0V. The voltage V _{step (4)} applied to the first word line WL1 may be set as appropriate so that the writing proceeds efficiently without causing erroneous writing to the unselected memory cells MC.

  Note that the potentials of the first word lines WL1 other than the selected first word line WL1 are set to 0 V or floating.

Further, the voltage V _pulse is applied in a pulse form to the source line SL connected to the memory cell MC to be selected. In the first writing step, the voltage V _{pulse (1)} applied in a pulsed manner to the source line SL is set to, for example, 5.8V. In the second writing step, the voltage V _{pulse (2)} applied in a pulsed manner to the source line SL is set to 5.5 V, for example. In the third step of writing, the voltage V _{pulse (3)} applied in a pulsed manner to the source line SL is set to, for example, 5.5V. In the fourth step of writing, the voltage V _{pulse (4)} applied to the source line SL in a pulsed manner is set to 5.5 V, for example. The pulse width of the voltage V _pulse applied to the source line SL is, for example, 5 μsec.

Note that the voltage V _{pulse (1)} applied to the source line SL in the first step of writing is not limited to 5.8V. The voltage V _{pulse (1)} applied to the source line SL in the first step of writing may be set higher than 5.8V or lower than 5.8V. For example, the voltage V _{pulse (1)} applied to the source line SL in the first writing step may be 5.75 V as in FIG. If the voltage V _{pulse (1)} applied to the source line SL in the first step is set at least higher than the voltage applied to the source line SL in the second step, the progress of writing in the first step can be promoted. Is possible.

When writing information to the memory cell transistor MT, the pulsed voltage V _{pulse (1)} is repeatedly applied to the source line SL until the threshold voltage of the memory cell transistor MT exceeds each determination level. If the threshold voltage of the memory cell transistor MT does not exceed a predetermined determination level only by applying the _pulse voltage V _{pulse (1)} once to the source line SL, the source line SL is applied to the source line SL within one step. The pulsed voltage V _{pulse (1)} is applied a plurality of times. FIG. 31 shows an example in which a _pulsed voltage V _{pulse (1)} is applied once to the source line SL in each step.

The voltages V _{pulse (2)} , V _{pulse (3)} , and V _{pulse (4)} applied to the source line SL after the second step of writing are not limited to 5.5V. The voltages V _{pulse (2)} , V _{pulse (3)} , and V _{pulse (4)} applied to the source line SL are appropriately set so that writing proceeds efficiently without causing erroneous writing to the non-selected memory cells MC. You only have to set it.

Further, the voltage V _{pulse (3)} applied to the source line SL in the third step of writing may be equal to the voltage V _{pulse (2)} applied to the source line SL in the second step of writing. It may be different from V _{pulse (2)} . However, the voltage V _{pulse (3)} applied to the source line SL in the third step of writing is preferably set lower than the voltage V _{pulse (1)} applied to the source line SL in the first step of writing.

In addition, the voltage V _{pulse (4)} applied to the source line SL in the fourth step is equal to the voltages V _{pulse (2)} and V _{pulse (3)} applied to the source line SL in the second step and the third step. They may be equal or different from the voltages V _{pulse (2)} and V _{pulse (3)} . However, the voltage V _{pulse (4)} applied to the source line SL in the fourth step of writing is preferably set lower than the voltage V _{pulse (1)} applied to the source line SL in the first step of writing.

As described above, the magnitude of the pulse voltage _{V pulse} applied to the source line SL in the first step _(1), the pulse shaped voltage _{V pulse} applied to the source line SL in the subsequent second step _{(2 )} , V _{pulse (3)} , and V _{pulse (4)} .

  The potential of the well 26 is always 0 V (ground).

In this way, the voltage V _step applied to the first word line WL1 may be gradually increased in four steps. Also in this case, the magnitude of the pulse-like voltage V _{pulse (1)} applied to the source line SL in the first step is set to be equal to the pulse-like voltage V _{pulse (2)} applied to the source line SL in the second step and thereafter. It is set larger than the magnitudes of V _{pulse (3)} and V _{pulse (4)} . Also according to the present modification, the nonvolatile semiconductor memory device can be miniaturized without causing a delay in writing speed or a writing failure.

(Modification (Part 2))
Next, a modification (No. 2) of the writing method of the nonvolatile semiconductor memory device according to the present embodiment will be explained with reference to FIG. FIG. 32 is a time chart showing a writing method of the nonvolatile semiconductor memory device according to the present modification.

  When writing information to the memory cell transistor MT, the potential of each part is set as follows.

That is, when writing information to the memory cell transistor MT, the potential of the bit line BL connected to the memory cell MC to be selected is set to 0V. On the other hand, the potentials of the bit lines BL other than the selected bit line BL are set to _VCC .

Further, the potential of the second word line WL2 is connected to the memory cell to be selected and V _CC. On the other hand, the potentials of the second word lines WL2 other than the selected second word line WL2 are set to 0 V (ground).

Further, the voltage V _step applied to the first word line WL1 connected to the memory cell MC to be selected is gradually increased. Here, the voltage V _step applied to the first word line WL1 is gradually increased, for example, in two stages.

The voltage V _{step (1)} applied to the first word line WL1 in the first writing _step is set to 3.0 V, for example. Note that the voltage _{Vstep (1)} applied to the first word line WL1 in the first step is not limited to 3.0V. The voltage V _{step (1)} applied to the first word line WL1 may be set as appropriate so that the writing proceeds efficiently without causing erroneous writing to the non-selected memory cells MC.

In the second writing step, a voltage V _{step (2)} higher than the voltage V _{step (1)} applied to the first word line WL1 in the first writing step is applied to the first word line WL1. The voltage V _{step (2)} applied to the first word line WL1 in the second step of writing is set to 6.0 V, for example. Note that the voltage V _{step (2)} applied to the first word line WL1 in the second writing _step is not limited to 6.0V. The voltage V _{step (2)} applied to the first word line WL1 may be set as appropriate so that the writing proceeds efficiently without causing erroneous writing to the non-selected memory cells MC.

  Note that the potentials of the first word lines WL1 other than the selected first word line WL1 are set to 0 V or floating.

Further, the voltage V _pulse is applied in a pulse form to the source line SL connected to the memory cell MC to be selected. In the first writing step, the voltage V _{pulse (1)} applied in a pulsed manner to the source line SL is set to, for example, 5.8V. In the second writing step, the voltage V _{pulse (2)} applied in a pulsed manner to the source line SL is set to 5.5 V, for example. The pulse width of the voltage V _pulse applied to the source line SL is, for example, 5 μsec.

Note that the voltage V _{pulse (1)} applied to the source line SL in the first step of writing is not limited to 5.8V. The voltage V _{pulse (1)} applied to the source line SL in the first step of writing may be set higher than 5.8V or lower than 5.8V. For example, the voltage V _{pulse (1)} applied to the source line SL in the first writing step may be 5.75 V as in FIG. If the voltage V _{pulse (1)} applied to the source line SL in the first step is set at least higher than the voltage applied to the source line SL in the second step, the progress of writing in the first step can be promoted. Is possible.

When writing information to the memory cell transistor MT, the pulsed voltage V _{pulse (1)} is repeatedly applied to the source line SL until the threshold voltage of the memory cell transistor MT exceeds each determination level. If the threshold voltage of the memory cell transistor MT does not exceed a predetermined determination level only by applying the _pulse voltage V _{pulse (1)} once to the source line SL, the source line SL is applied to the source line SL within one step. The pulsed voltage V _{pulse (1)} is applied a plurality of times. FIG. 32 shows an example in which a _pulsed voltage V _{pulse (1)} is applied to the source line SL once in each step.

The voltage V _{pulse (2)} applied to the source line SL in the second step of writing is not limited to 5.5V. The voltage V _{pulse (2)} to be applied to the source line SL may be set as appropriate so that the writing proceeds efficiently without causing erroneous writing to the non-selected memory cells MC.

As described above, the magnitude of the _pulse voltage V _{pulse (1)} applied to the source line SL in the first step is equal to the pulse voltage V _{pulse (2)} applied to the source line SL in the second step. It is set larger than the size of.

  The potential of the well 26 is always 0 V (ground).

As described above, the voltage V _step applied to the first word line WL1 may be gradually increased in two stages. Also in this case, the magnitude of the _pulsed voltage V _{pulse (1)} applied to the source line SL in the first step is equal to the magnitude of the pulsed voltage V _{pulse (2)} applied to the source line SL in the second step. Set larger than this. Also according to the present modification, the nonvolatile semiconductor memory device can be miniaturized without causing a delay in writing speed or a writing failure.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

For example, in the above embodiment, the case where the voltage V _step applied to the first word line WL1 is gradually increased in two steps, steps, or four steps has been described as an example. However, the voltage applied to the first word line WL1 is described as an example. V _step may be gradually increased in five steps or more. Also in this case, the magnitude of the pulse voltage applied to the source line SL in the first step may be set larger than the magnitude of the pulse voltage applied to the source line SL in the second step and thereafter.

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1)
A plurality of memory cells having a selection transistor and a memory cell transistor connected to the selection transistor;
A bit line connected to the drain of the select transistor;
A first word line connected to a control gate of the memory cell transistor;
A second word line connected to the select gate of the select transistor;
A source line connected to the source of the memory cell transistor,
A first step of applying a second voltage to the source line in a pulsed manner while applying a first voltage to the first word line; and after the first step, from the first voltage Performing at least a second step of applying a fourth voltage lower than the second voltage to the source line in a pulsed manner while applying a high third voltage to the first word line, A nonvolatile semiconductor memory device, wherein information is written into the memory cell.
(Appendix 2)
In the nonvolatile semiconductor memory device according to attachment 1,
After the second step, while applying a fifth voltage higher than the third voltage to the first word line, a sixth voltage lower than the second voltage is pulsed to the source line. A nonvolatile semiconductor memory device, wherein information is written to the memory cell by further executing a third step of applying.
(Appendix 3)
In the nonvolatile semiconductor memory device according to attachment 2,
The nonvolatile semiconductor memory device, wherein the sixth voltage is equal to the fourth voltage.
(Appendix 4)
In the nonvolatile semiconductor memory device according to any one of appendices 1 to 3,
A nonvolatile semiconductor memory device, wherein when writing information to the memory cell, a seventh voltage is applied to the second word line and the bit line is grounded.
(Appendix 5)
In the nonvolatile semiconductor memory device according to any one of appendices 1 to 4,
The memory cell transistor includes a floating gate formed on a semiconductor substrate through a tunnel insulating film, the gate electrode formed on the floating gate through an insulating film, and the floating gate on one side of the floating gate. A non-volatile semiconductor device, comprising: a first impurity diffusion layer that is formed in a semiconductor substrate and serves as the source; and a second impurity diffusion layer formed in the semiconductor substrate on the other side of the floating gate. Semiconductor memory device.
(Appendix 6)
A plurality of memory cells having a selection transistor and a memory cell transistor connected to the selection transistor; a bit line connected to a drain of the selection transistor; a first connected to a control gate of the memory cell transistor; A writing method for a nonvolatile semiconductor memory device, comprising: a word line; a second word line connected to a select gate of the selection transistor; and a source line connected to a source of the memory cell transistor,
A first step of applying a second voltage to the source line in a pulsed manner while applying a first voltage to the first word line; and after the first step, from the first voltage Performing at least a second step of applying a fourth voltage lower than the second voltage to the source line in a pulsed manner while applying a high third voltage to the first word line, Information is written in the memory cell. A writing method of a nonvolatile semiconductor memory device.
(Appendix 7)
In the writing method of the nonvolatile semiconductor memory device according to appendix 6,
After the second step, while applying a fifth voltage higher than the third voltage to the first word line, a sixth voltage lower than the second voltage is pulsed to the source line. A method for writing into a nonvolatile semiconductor memory device, wherein information is written into the memory cell by further executing a third step of applying.
(Appendix 8)
In the nonvolatile semiconductor memory device writing method according to appendix 7,
The sixth voltage is equal to the fourth voltage. A writing method of a nonvolatile semiconductor memory device, wherein:
(Appendix 9)
In the writing method of the nonvolatile semiconductor memory device according to any one of appendices 6 to 8,
When writing information to the memory cell, a seventh voltage is applied to the second word line, and the bit line is grounded. A writing method of a nonvolatile semiconductor memory device,

2 ... Memory cell array region 4 ... Peripheral circuit region 6 ... Region 6N where high breakdown voltage transistors are formed ... Region 6P where high breakdown voltage N-channel transistors are formed ... Region 8 where high breakdown voltage P-channel transistors are formed ... Low voltage transistors Formed region 8N ... Low voltage N-channel transistor formed region 8P ... Low voltage P-channel transistor formed region 10 ... Memory cell array 12 ... Column decoder 13 ... Sense amplifier 14 ... First row decoder 16 ... first 2 row decoders 18 ... third row decoder 20 ... semiconductor substrate 21 ... element region 22 ... element isolation region 24 ... buried diffusion layer 26 ... well 28 ... tunnel insulation film 28a ... tunnel insulation film 28b ... gate insulation film 30a ... floating Gate 30b ... select gates 32a, 32b ... insulating film 34a ... control Gate gate 34b ... polysilicon films 34c, 34d ... gate electrode 36a ... impurity diffusion layer, source diffusion layer 36b ... impurity diffusion layer, source / drain diffusion layer 36c ... impurity diffusion layer, drain diffusion layer 37 ... sidewall insulating film 38a ... silicide Layer, source electrode 38b ... silicide layer, drain electrodes 38c-38f ... silicide layer 39 ... sidewall insulating film 40 ... interlayer insulating film 42 ... contact hole 44 ... conductor plug 46 ... wiring (first metal wiring layer)
48 ... Interlayer insulating film 50 ... Contact hole 52 ... Conductor plug 54 ... Wiring (second metal wiring layer)
56 ... Interlayer insulating film 58 ... Contact hole 60 ... Conductor plug 62 ... Wiring (third metal wiring layer)
64 ... thermal oxide film 66 ... silicon nitride film 68 ... trench 69 ... sacrificial oxide film 70 ... buried diffusion layer 72P ... P type well 72N ... N type well 74P ... P type well 74N ... N type well 76 ... gate insulating film 78 ... Gate insulating film 80 ... antireflection film 82 ... silicon oxide film 84 ... silicon nitride film, sidewall insulating film 86 ... low concentration diffusion layer 88 ... low concentration diffusion layer 90 ... low concentration diffusion layer 92 ... low concentration diffusion layer 93 ... silicon Oxide film, sidewall insulating film 94 ... high concentration diffusion layer 96 ... source / drain diffusion layer 98 ... high concentration diffusion layer 100 ... source / drain diffusion layer 102 ... high concentration diffusion layer 104 ... source / drain diffusion layer 106 ... high concentration Diffusion layer 108 ... Source / drain diffusion layer 110N ... High breakdown voltage N-channel transistor 110P ... High breakdown voltage P-channel transistor 112N ... Low voltage N Channel transistor 112P ... Low-voltage P-channel transistor 114 ... Silicon nitride film 116 ... Silicon oxide film 118 ... Silicon oxide film 120 ... Silicon oxide film 122 ... Silicon oxide film 124 ... Silicon oxide film 126 ... Silicon oxide film 128 ... Silicon oxide film 130 ... Interlayer insulating film 132 ... Contact hole 134 ... Conductor plug 136 ... Wiring (fourth metal wiring layer)
138 ... Silicon oxide film 140 ... Silicon oxide film 142 ... Interlayer insulating film 143 ... Contact hole 144 ... Conductor plug 145 ... Wiring 146 ... Silicon oxide film 148 ... Silicon nitride film ST ... Select transistor MT ... Memory cell transistor MC ... Memory cell BL ... bit line WL1 ... first word line WL2 ... second word line SL ... source line 210 ... memory cell array 212 ... column decoder 213 ... sense amplifier 214 ... first row decoder 216 ... second row decoder 218 ... first 3 row decoder 220 ... semiconductor substrate 228a ... tunnel insulating film 228b ... gate insulating film 230a ... floating gate 230b ... select gate 232a, 232b ... insulating film 234a ... control gate 234b ... polysilicon film 236a ... impurity diffusion layer, source diffusion layer 2 6b ... impurity diffusion layer, source / drain diffusion layer 236c ... impurity diffusion layer, a drain diffusion layer

Claims (5)

A plurality of memory cells having a selection transistor and a memory cell transistor connected to the selection transistor;
A bit line connected to the drain of the select transistor;
A first word line connected to a control gate of the memory cell transistor;
A second word line connected to the select gate of the select transistor;
A source line connected to the source of the memory cell transistor,
A first step of applying a second voltage to the source line in a pulsed manner while applying a first voltage to the first word line; and after the first step, from the first voltage Performing at least a second step of applying a fourth voltage lower than the second voltage to the source line in a pulsed manner while applying a high third voltage to the first word line, A nonvolatile semiconductor memory device, wherein information is written into the memory cell. The nonvolatile semiconductor memory device according to claim 1,
After the second step, while applying a fifth voltage higher than the third voltage to the first word line, a sixth voltage lower than the second voltage is pulsed to the source line. A nonvolatile semiconductor memory device, wherein information is written to the memory cell by further executing a third step of applying. The nonvolatile semiconductor memory device according to claim 2.
The nonvolatile semiconductor memory device, wherein the sixth voltage is equal to the fourth voltage. A plurality of memory cells having a selection transistor and a memory cell transistor connected to the selection transistor; a bit line connected to a drain of the selection transistor; a first connected to a control gate of the memory cell transistor; A writing method for a nonvolatile semiconductor memory device, comprising: a word line; a second word line connected to a select gate of the selection transistor; and a source line connected to a source of the memory cell transistor,
A first step of applying a second voltage to the source line in a pulsed manner while applying a first voltage to the first word line; and after the first step, from the first voltage Performing at least a second step of applying a fourth voltage lower than the second voltage to the source line in a pulsed manner while applying a high third voltage to the first word line, A method for writing into a nonvolatile semiconductor memory device, wherein information is written into the memory cell. 5. The writing method of the nonvolatile semiconductor memory device according to claim 4,
After the second step, while applying a fifth voltage higher than the third voltage to the first word line, a sixth voltage lower than the second voltage is pulsed to the source line. A method for writing into a nonvolatile semiconductor memory device, wherein information is written into the memory cell by further executing a third step of applying.

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