JP2001284554A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the influence of an electronic trap inside an insulating film concerning a cell current. SOLUTION: On a substrate (or well) 12, a NAND cell unit is formed. Diffusion layers 13, 13b and 13c of memory cells and select gate transistors inside the NAND cell unit are buried in the substrate 12 and do not touch the surface of the substrate 12. The peak of a concentration profile on impurities comprising the diffusion layers 13, 13b and 13c exists in the depth of >=0.04 μm from the surface of the substrate 12. On the terminal diffusion layers 13b and 13c inside the NAND cell unit, diffusion layers 13b' and 13c' are formed. The diffusion layers 13b' and 13c' electrically connect the diffusion layers 13b and 13c and contact plugs 16b and 16c with low resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory comprising a memory cell having a charge storage layer (for example, a floating gate electrode, a nitride film, etc.) and a control gate electrode. This is used for a binary NAND flash memory in which binary data is stored in a memory cell, a multi-level NAND flash memory in which multi-level data of three or more values are stored in one memory cell, and the like.

[0002]

2. Description of the Related Art A NAND flash memory is an EEPROM (Electrically Erase) having a cell structure capable of electrically changing cell data and having a cell structure suitable for high integration of elements.
It is well known as one of asable and programmable read only memories.

FIG. 50 shows a memory cell array of a NAND flash memory. FIG. 51 shows a part of the memory cell array of FIG.

A memory cell array of a NAND flash memory includes a plurality of NANDs arranged in a matrix.
It is composed of cell units. A plurality of NAND cell units (for example, 4, 8, 16, 32, and
Such. In this example, it is 16. ) NAND cell consisting of memory cells, and two (plural) select gate transistors connected one by one (or a plurality of) to both ends.

[0005] Each memory cell constituting the NAND cell has
For example, it has a stacked gate structure, that is, a floating gate electrode, and a control gate electrode stacked thereover via an insulating film. Each select gate transistor also has a structure similar to a memory cell for reasons such as cost reduction due to simplification of the manufacturing process. In the NAND cell unit, two transistors (memory cell and select gate transistor) adjacent to each other share one diffusion layer (source or drain).

The select gate transistor connected to the drain side node of the NAND cell is connected to bit lines (data lines) BL0, BL1,...
The select gate transistor connected to the source node of the D cell is connected to a source line (common source line as a reference potential line) SL.

The control gate electrodes of a plurality of memory cells arranged in the row direction, that is, in one row, are electrically connected to each other to form control gate lines (word lines) CG0,... CG14, CG15. ing.
The gate electrodes of the plurality of select gate transistors arranged in the row direction are connected to select gate lines SGD, SGD.
They are electrically connected to each other by GS.

Hereinafter, a read (READ) operation, a write (PROGRAM) operation and an erase (ERASE) operation of the NAND type flash memory, and problems inherent in each operation will be described.

(1) Read (READ) For example, in the case of a binary memory, when "1" data is stored in a memory cell, the threshold voltage is negative,
When “0” is stored in the memory cell, the threshold voltage is positive.

Therefore, in a read operation, for example, after setting a bit line to a precharge potential, a ground potential is applied to one selected word line, and a positive potential (for example, 3. 5V). At this time, the select gate line in the selected block is set to a positive potential, so that all the select gate transistors in the selected block are on.

On the other hand, the drain side select gate line in the unselected block is set to the ground potential. For this reason,
The drain-side select gate transistor in the unselected block is off, and the NA in the unselected block is
The ND cell unit is electrically disconnected from the bit line.

The potential of the bit line varies depending on the value of data stored in the memory cell. That is,
When the data of the memory cell connected to the selected word line is “1”, the memory cell is turned on, so that the potential of the bit line decreases toward 0V. Conversely, when the data of the memory cell connected to the selected word line is "0", the memory cell is turned off, so that the bit line maintains the precharge potential.

The read operation is performed simultaneously on, for example, one page of memory cells connected to the selected word line (control gate line). The read data for one page is sensed by a sense amplifier having a latch function, and is further latched. Thereafter, the read data of the latch circuit is serially output outside the chip. Note that in data reading, a so-called shield bit line reading method may be adopted.

One of the problems in the read operation is that the conductance Gm of the memory cell is degraded by hot carriers generated during the read operation. It is generally known that the deterioration of the conductance Gm due to the hot carriers increases when a nitride film exists near the gate. As shown in FIGS. 52 and 53, variations in the conductance Gm cause variations in the read speed. Therefore, it is very important to prevent the conductance Gm from deteriorating in a memory that repeats a read operation.

Conventionally, this problem has been avoided by increasing the impurity concentration of the diffusion layer. However, as memory cells become finer in the future, in order to prevent the short channel effect, In addition, the impurity concentration of the diffusion layer must be set low. That is, with the miniaturization of memory cells, a problem arises in that deterioration of hot carrier resistance cannot be avoided.

Another problem in the read operation is that the NA
The on-current (cell current) flowing through the memory cell fluctuates due to the charge trapped in the gate insulating film of the transistor (memory cell and select gate transistor) in the ND cell unit.

In a memory cell having a charge storage layer (for example, a floating gate electrode), the data value is determined by the amount of charge in the charge storage layer. In the read operation, the cell current of the memory cell is set as large as possible in order to detect the on / off of the memory cell when the read potential is applied to the control gate electrode, that is, the change in the potential of the bit line accompanying the read / write. Is preferred. However, the electric charge trapped at the interface between the gate insulating film and the silicon substrate may make it impossible to sufficiently increase the cell current.

FIG. 54 shows the structure of a conventional memory cell.

This memory cell has a surface channel type MOS.
It is composed of transistors. On a P-type silicon substrate (may be a well) 101, a gate insulating film (tunnel insulating film) 103, a floating gate electrode 104, an insulating film (for example, ONO film) 105, and a control gate electrode 106 are formed. Inside, N
Diffusion layers (source or drain) 107 and 108 are formed.

In the surface channel type MOS transistor,
The floating gate electrode 104, the control gate electrode 106, and the diffusion layers 107 and 108 have the same conductivity type, and the diffusion layers 107 and 108 and the silicon substrate 10
1 have mutually different conductivity types. When a read potential is applied to the control gate electrode 106, the silicon substrate 101 between the diffusion layers 107 and 108
When the conductivity type of the surface portion of is inverted and a channel is formed,
Cell current flows. Thus, the cell current of the memory cell flows on the surface of the silicon substrate 101.

However, when phenomena such as scattering of impurities at the interface between the silicon substrate 101 and the gate insulating film 103 and electron traps in the gate insulating film 103 occur,
Cell current flowing on the surface of the silicon substrate 101 decreases,
There is a problem that the reading operation cannot be performed accurately. In particular,
Charges are easily trapped in the gate insulating film (tunnel insulating film) 103 due to damage due to a manufacturing process or repeated writing / erasing operations. In particular, charges are trapped at the interface between the gate insulating film 103 and the silicon substrate 101. When trapped, this charge has a significant effect on the data read operation.

(2) Write (PROGRAM) The write operation is, for example, a self-boost write (se
lf-boost programming). The advantage of adopting the self-boost writing method is that the flash memory can operate at a low voltage. That is, according to this method, all the transistors constituting the circuit such as the column decoder are replaced with the external power supply potential Vcc.
(Lower operating voltage), the size of these transistors, that is, the area of a circuit such as a column decoder can be reduced, and the chip size can be reduced.

Before describing a write operation by the self-boost write method, preconditions are defined as follows.

It is assumed that binary data is stored in a memory cell. The memory cell has binary data (“1”,
"0") and multi-valued data ("0", "1",... "N
(N is a natural number of 3 or more) "), but in this example, in order to simplify the description, binary data is stored in the memory cell as described above. Shall be.

First, an erasing operation is performed, for example, all the memory cells in the selected block are set to an erasing state ("1" state). Thereafter, a write operation (self-boost write operation) is performed on all memory cells in the selected block in page units or byte units.

In the case of normal writing, in the NAND cell unit, from the memory cell farthest from the bit line (source line side memory cell) to the bit line side memory cell, 1
Writing is performed sequentially for each cell. In the case of random writing, writing is performed on an arbitrary one of a plurality of memory cells connected between a bit line and a source line.

As shown in FIG. 51, in the self-boost write method, first, the potential Vsgs of the gate electrode (select gate line) SGS of the source line side select gate transistors S21 and S22 is set to 0 V, and these select gate transistors S21 , S22 are cut off.

Next, "0" -write ("0" -program
mming) the potential VB of the bit line (selected bit line) BL1 to which the memory cell A (M11) to be connected is connected.
L1 is set to 0V (data "0"), and the memory cell B to be "1" -written ("1" -programming)
(M12), that is, a write-inhibited cell (program inhib
The potential VBL2 of the bit line (non-selected bit line) BL2 to which the transition cell is connected is set to a positive potential (data "1").

At this time, the drain-side select gate transistor S11 connected to the bit line BL1 is turned on, and the potential (0 V) of the bit line BL1 changes to the memory cell A.
It is transmitted to the channel of (M11). In addition, bit line B
The drain-side select gate transistor S12 connected to L2 is initially turned on, and has an initial potential (ini
tial potential) is transmitted to the channel of the memory cell B (M12). Thereafter, the drain-side select gate transistor S12 is cut off.

The potential VBL applied to the bit line BL2
2 is a drain side select gate transistor S11,
The potential may be lower than the potential Vsgd applied to the gate electrode (select gate line) SGD of S12, but in this case, the drain-side select gate transistor S12 needs to be cut off.

In this state, the selected word line (control gate line) CG1 in the selected block is set.
Is set to the write potential Vpp, and the unselected word lines (control gate lines) CG in the selected block are set.
0, CG2,... CG15 are transfer potentials Vpass (Vpp>
(Vpass> Vcc).

The specific timing for applying these potentials Vpp and Vpass is as follows.

First, the gate electrodes of all the drain-side select gate transistors S11 and S12 in the selected block, that is, the potential Vsg of the select gate line SGD.
d is set to power supply potential Vcc. When the potentials Vcg0, Vcg1,... Vcg15 of the word lines CG0, CG1,... CG15 in the selected block are set to the power supply potential Vcc, N connected to the bit line BL1
The memory cells M01, M11,... In the AND cell unit
..M151 and select gate transistor S11
Is turned on, the potential VBL of the bit line BL1 is
1 (= 0V) are the memory cells M01, M11,.
151 channel.

The NAN connected to the bit line BL2
Memory cells M02, M12,... In the D cell unit
Since M152 and select gate transistor S12 are also turned on, memory cells M02, M12,.
Charge is transferred from the bit line BL2 to the channel of M152 via the select gate transistor S12.

Therefore, the NA connected to the bit line BL2
Memory cells M02, M12,... In the ND cell unit
The channel potential of M152 gradually increases and reaches the initial potential Vini obtained by subtracting the threshold Vth of the select gate transistor S12 from the potential VBL2 of the bit line BL2.

The memory cells M02, M12,... M15
When the channel potential of No. 2 becomes the initial potential, the select gate transistor S12 enters the cutoff state, and the channels of the memory cells M02, M12,... At this time, the source line SL
Is set to the ground potential (0 V) or a positive potential for sufficiently cutting off the source side select gate transistor S22.

Thereafter, a pulse-like write potential Vp is applied to the selected word line (control gate line) CG1.
The transfer potential Vpass is applied to the unselected word lines (control gate lines) CG0, CG2,.

Therefore, the channel potential of the memory cell A (M11) to be "0" -written is 0 V, and the potential of the control gate electrode (word line CG1) is Vpp.
Then, “0” -writing (operation of injecting electrons into the floating gate electrode) is performed on the memory cell A (M11).

On the other hand, the initial potential Vini of the channel of the memory cell B (M12) to be "1" -written is
VBL2-Vth. Further, the memory cell B (M1
The channel 2) is in a floating state.
Therefore, the write potential V is applied to the selected word line CG1.
pp, unselected word lines CG0, CG2,... CG1
5, the transfer potential Vpass is applied to the memory cell B
Due to the capacitive coupling between the channel of (M12) and the control gate electrode (word line CG1), the channel potential of the memory cell B (M12) increases.

Therefore, in the memory cell B (M12) to be "1" -written, since a high voltage is not applied between the channel and the control gate electrode, no electrons are injected into the floating gate electrode. . That is, "1" -write operation (operation for maintaining the erased state) is performed on the memory cell B (M12), that is, the write-inhibited cell.

Here, in order to maintain the erased state of the memory cell B (M12), the channel potential of the memory cell B (M12) is sufficiently increased, and the channel of the memory cell B (M12) and the control gate electrode are connected. What is necessary is just to prevent high voltage from being applied in between. That is, the memory cell B (M1
Regarding 2), the value of the channel potential is set so that the amount of change in the threshold value due to the pulsed write potential Vpp falls within an allowable range.

The operation procedure of the self-boost writing method has been described above. In this writing method, a so-called erroneous writing (progr.
am error) is known to occur.

More specifically, as shown in FIG. 51, for a memory cell A (M11) connected between a word line (control gate line) CG1 and a bit line BL1,
When “0” -write (write to make the threshold value positive) is performed, the memory cell B (M
12) and unselected memory cell C (M21)
The problem of erroneous writing occurs.

It should be noted that there are naturally memory cells other than B and C in FIG. 51 in which erroneous writing may occur. That is, for example, the problem that occurs in the memory cell B (M12) is that “1” -write target connected between bit lines (unselected bit lines) other than the selected word line CG1 and bit line BL2. The problem that occurs in the memory cell C (M21) also occurs in the memory cell A (M21).
.. M151 in all non-selected memory cells M01, M31,... M151 in the NAND cell unit including (M11).

First, the problem of erroneous writing of the memory cell B (M12) will be described.

The selected word line (control gate line) CG1 is set to the write potential Vpp. On the other hand, the initial potential Vi of the channel of the memory cell B (M12)
ni is VBL2-Vth. That is, the write potential Vpp is applied to the selected word line CG1, and the transfer potential Vpass is not selected.
G2,... CG15, the memory cell B
The channel potential of (M12) rises to a value higher than the initial potential Vini due to capacitive coupling.

At this time, if the channel potential of memory cell B (M12) does not rise sufficiently, memory cell B (M12)
Electrons are injected into the floating gate electrode, and erroneous writing occurs.

Therefore, in order not to cause erroneous writing to the memory cell B (M12), the transfer potential Vpas
s is set to a value as large as possible, and at the time of writing (when the write pulse Vpp is supplied), the memory cell B (M1
It is necessary to make the channel potential of 2) sufficiently high. This is because if the channel potential of the memory cell B (M12) is sufficiently increased, the voltage between the channel of the memory cell B (M12) and the control gate electrode (word line CG1) can be relaxed.

Next, the problem of erroneous writing of the memory cell C (M21) will be described.

In writing data, unselected word lines (control gate lines) CG0, CG2,.
Is set to Vpass (Vpp>Vpass> Vcc). On the other hand, the channel potential of the memory cell C (M21) is maintained at 0V. At this time, if the value of Vpass is too large, a high voltage is applied between the channel of the memory cell C (M21) and the control gate electrode (word line CG2), and erroneous writing occurs.

Therefore, in order to prevent erroneous writing to the memory cell C (M21), the transfer potential Vpas
s is set to a value as small as possible, and at the time of writing (when the write pulse Vpp is supplied), the memory cell C (M2
1) Channel and control gate electrode (word line C
It is necessary to relax the voltage during G2).

As described above, in the “0” -write operation to the memory cell A (M11), the change amount of the threshold voltage of the memory cell B (M12) to be written “1” and the unselected memory cell The amount of change in the threshold voltage of C (M21) needs to be reduced. However, Vp
As the value of ass increases, the amount of change in the threshold voltage of the memory cell B (M12) decreases, but the memory cell C (M12)
The fluctuation amount of the threshold voltage of 21) becomes large. Conversely, Vp
When the value of ass is reduced, the amount of change in the threshold voltage of the memory cell C (M21) decreases, but the amount of change in the memory cell B (M
The fluctuation amount of the threshold voltage of 12) becomes large.

For this reason, the value of Vpass is set to an optimum value such that the variation of the threshold voltage of each of the memory cells B and C falls within an allowable range.

The problem of erroneous writing in the self-boost writing method and the problem of determining the optimum value of Vpass will be described later in detail.

FIGS. 55A and 55B show the capacitance generated in the memory cell.

The capacitance generated in the memory cell comprises the total value of the capacitance C1 generated between the channel and the control gate electrode CG, the capacitance generated between the channel and the well 12, and the capacitance generated between the diffusion layer 13 and the well 12. Junction capacitance C
And 2. Further, the capacitance C1 includes a capacitance generated between the channel and the floating gate electrode (charge storage layer) FG and a capacitance generated between the floating gate electrode FG and the control gate electrode CG.

Here, for example, when the potential Vcg is applied to the control gate electrode CG, as shown in FIG. 55B, the channel potential Vch of the memory cell becomes {C1 /
(C1 + C2)｝ × Vcg. That is, the potential Vcg of the control gate electrode CG and the channel potential Vch of the memory cell have a relationship of Vch = α × Vcg. This constant α (= C1 / (C1 + C2))
Is called the channel's boost ratio.

At the time of data writing, the potential Vcg of the selected word line (control gate line) in the selected block is set to the high potential Vpp for programming, and the unselected word line (control) in the selected block is set. The potential Vcg of the control gate line) is Vpass (Vpp> Vp
ass> Vcc).

"1" -NAN including a memory cell to be written (write-inhibited cell maintaining the erased state)
In the D cell unit, the channel potential Vc of each memory cell
h rises based on the potential Vcg of the control gate electrode CG and the boost ratio α. Ultimately, this NA
Channel potential Vc of each memory cell in the ND cell unit
h becomes uniform and rises to a predetermined value.

Therefore, Vpp or Vpas as Vcg
If s is set to a predetermined positive value, the channel potential Vch
Rises enough to connect to the selected word line "1"-
Erroneous writing of the writing cell can be prevented.

Normally, the values of Vpass and Vpp are defined as an initial potential, a step potential, and a final potential, respectively.
Step up gradually, and Vpass and Vp
The pulse width of p is also optimized. Such step-up writing reduces the width of the threshold voltage distribution after the “0” -writing of the memory cell to be “0” -written (the cell for which the threshold is raised from negative to positive), and , "1" -write is effective in preventing "0" -write (erroneous write) to a memory cell (write-inhibited cell) to be written or a non-selected memory cell.

(3) Erasing (ERASE) In a NAND flash memory, usually, a memory cell array is composed of a plurality of blocks. The data is erased in block units (block erase) or simultaneously for all blocks (chip erase). In the case of block erasing, it is possible to erase the data of the memory cells in one predetermined block or to erase the data of the memory cells in arbitrary plural blocks. In the case of chip erasure, data of memory cells in all blocks are simultaneously erased.

In chip erasing, 0 V is applied to all word lines (control gate lines) in the memory cell array, and the potential of all select gate lines is set to Vpp (for example, 18 V).
, The bit line and the source line are set in a floating state, and the potential of the well in which the memory cell is formed is set to the erasing potential (for example, 20 V). At this time, electrons in the floating gate electrode are emitted to the well by the tunnel effect, and the threshold value of the memory cell changes in the negative direction.

It is to be noted that all select gate lines at the time of chip erasing may be set not to Vpp but to a predetermined potential exceeding 0 V and equal to or lower than an erasing potential (for example, 20 V).
Further, the floating state may be set.

In block erasing, all word lines (control gate lines) in the selected block are set to 0 V, all word lines (control gate lines) in unselected blocks, and all select lines in all blocks are selected. The gate line is set to Vpp (for example, 18 V), the bit line and the source line are set to the floating state, and the potential of the well in which the memory cell is formed is set to
This is executed by setting to an erasing potential (for example, 20 V). At this time, in the memory cells in the selected block, electrons in the floating gate electrode are emitted to the well by the tunnel effect, and the threshold value of the memory cell changes in the negative direction.

Note that all word lines (control gate lines) in unselected blocks and all select gate lines in all blocks at the time of block erasing are Vp.
Instead of p, it exceeds 0 V and is at the erase potential (for example, 20 V)
The potential may be set to the following predetermined potential or may be in a floating state.

After data is erased, a verify operation is usually performed to verify whether all memory cells to be erased are within a predetermined threshold range determined to be in an erased state. . In the verify operation, first, data of a memory cell to be erased is read by a verify read, and based on the read data, whether erase OK (sufficient) or erase NG (insufficient) is performed. Judge. Then, if it is determined that the erasure is NG, the data is erased again.

Next, the device structure of a conventional NAND flash memory will be described.

FIG. 56 is a plan view showing an example of a device structure of a conventional NAND flash memory. Fig. 57
FIG. 5 is a sectional view taken along line LVII-LVII in FIG.
8 is a cross-sectional view along the line LVIII-LVIII in FIG.

The memory cell array of the NAND type flash memory includes a plurality of NANDs arranged in a matrix.
It is composed of cell units. The NAND cell unit includes, for example, a NAND cell composed of 16 memory cells connected in series, and two select gate transistors connected one by one to both ends thereof.

The memory cell and select gate transistor in the NAND cell unit are, for example, a P-type well 12 in an N-type well 11 formed in a P-type semiconductor substrate 10.
Inside, that is, in a double well. Each memory cell in the NAND cell has a floating gate electrode 5 (F
G) has a so-called stack gate structure in which control gate electrodes 7 (CG0, CG1,... CG15) are stacked via an interpoly insulating film 6. The gate insulating film 4 functions as a tunnel insulating film. In order to simplify the manufacturing process, the select gate transistor has a structure similar to a memory cell.

Word line (control gate line) 7 (C
G0, CG1,... CG15) extend in the row direction of the memory cell array, and are commonly connected to a plurality of memory cells in the row direction. Similarly, select gate line 7
(SGD, SGS) also extends in the row direction of the memory cell array, and is commonly connected to a plurality of select gate transistors in the row direction.

In the NAND cell unit, two transistors (memory cells or select gate transistors) adjacent to each other share one diffusion layer (source or drain) 13. Further, two NAND cell units adjacent in the column direction include a drain diffusion layer 13b.
Alternatively, they share the source diffusion layer 13c.

The drain-side select gate transistor arranged at one end of the NAND cell is connected to a bit line (data line) 9 (BL) via a bit line contact portion 14. The bit line contact portion 14 includes a contact plug 16a, and an intermediate layer 17a is arranged between the bit line 9 (BL) and the contact plug 16a. The source side select gate transistor arranged at the other end of the NAND cell is connected to the source line contact portion 1.
5, and is connected to a source line (reference potential line) SL. The source line contact portion 15 is provided with the contact plug 1
6b. The source line SL is, for example, commonly connected to all NAND cell units constituting the memory cell array.

In the NAND flash memories of FIGS. 56 to 58, the element isolation region 3a surrounding the element region 2 is a field oxide film formed by the LOCOS method. And FIG.
As shown in FIG. 3, the element isolation region 3a is formed by STI (Shallow T
(Rench Isolation) It may be composed of a silicon oxide film having a structure.

Conventionally, in a NAND flash memory adopting the self-boost write method, the following structure, process, operation (for example, “1” at the time of writing—the channel potential of the write cell) of the memory cell are as follows. Such a problem has arisen.

FIG. 61 shows a timing waveform of a potential applied to a memory cell in a self-boost write operation.

First, the potential VBL1 of the bit line BL1 to which the memory cell to be "0" -written is connected is set to
The potential is set to 0 V, and the potential VBL2 of the bit line BL2 to which the memory cell to be "1" -written is connected is set to the power supply potential (for example, 2.5 V) Vcc. Also, the potential Vsgs of the source side select gate line SGS is set to 0
V, and the potential Vsgd of the drain-side select gate line SGD is set to the power supply potential Vcc.

At this time, the two select gate transistors in the NAND cell unit including the memory cell to be "1" -written are both turned off, and the channel and the channel of the memory cell in this NAND cell unit are turned off. The diffusion layer is in an electrically floating state.

Thereafter, the potential Vcg1 of the selected word line (control gate line) CG1 is changed to the writing potential Vcg.
pp, and the potentials Vcg0, CG15 of the unselected word lines (control gate lines) CG0, CG2,.
Vcg2,..., Vcg15 to transfer potential Vpass
(Vpp>Vpass> Vcc), “1”
-The potential Vch of the channel (in a floating state) of the memory cell to be written is boosted (boosted) to a predetermined value.

Here, the relationship between "1" -the channel potential Vch of the memory cell to be written and the potential applied to each electrode of the memory cell can be expressed by the following equation (1). Vch = Vsg−Vsgth (Vchinit) + Cr1 (Vpass−Vpassth−Vchinit) + Cr2 · Vpp− (Tpw / 16 (Cins + Cch)) × I (1) where Vsg is the bit line side (drain side). This corresponds to the potential Vsgd of the select gate line SGD, and is set to, for example, the power supply potential Vcc. Vchinit is the initial potential transmitted from the bit line to the channel of the memory cell, Vsgth (Vchinit) is the threshold value of the select gate transistor on the bit line side when the channel potential is Vchinit, and Cr1 is The transfer ratio Vpass is the boost ratio of the channel of the memory cell to which the write potential is applied, and Cr2 is the boost ratio of the channel of the memory cell to which the write potential Vpp is applied.

Vpassth is a potential required to turn on a memory cell to which Vpass is applied when the channel potential is Vch, and Tpw
Is the pulse width of the write pulse Vpp, and Cins
Is the capacitance per memory cell, Cch is the sum of the depletion layer capacitance extending below the channel and the junction capacitance between the diffusion layer and the well, and I escapes from the channel to the well and bit line. It is the total value of the current.

That is, the write potential Vpp is applied to the selected word line CG1, and the unselected word lines CG0, CG
By applying the transfer potential Vpass to the CG15, the potential of the channel (floating state) of the memory cell to be "1" -written is boosted to Vch. For this reason, in the memory cell targeted for “1” -writing, electrons are hardly injected into the floating gate electrode, the erased state is maintained, and erroneous writing (“0” -writing) is prevented.

However, the channel potential of the memory cell to be "1" -written may not sufficiently rise, and erroneous writing may occur.

For example, impurities (for example, impurities) in a P-type well in which a select gate transistor and a memory cell are formed
The variation in the concentration profile of boron (boron), the concentration profile of the impurity introduced into the channel portion of the select gate transistor and the memory cell, and the variation in the concentration profile of the impurity in the diffusion layer (source / drain) of the select gate transistor and the memory cell are as follows. , The initial potential Vchinit transferred to the channel may decrease.

Further, the increase in capacitance generated in the depletion layer below the channel lowers the channel boost efficiency (Cr1, Cr2). In this case, at the time of the write operation, the channel potential of the memory cell to be "1" -written does not rise sufficiently, and as a result, the threshold value of this memory cell rises,
Erroneous writing ("0" -writing) occurs.

FIG. 62 shows that "0" in the write operation.
The graph shows the relationship between the threshold value fluctuation of the memory cell not to be written and the value of the transfer potential Vpass applied to the unselected word line.

Here, cells B and C refer to cells B and C shown in FIG. 51, and cells A, B and C shown in FIG.
It is assumed that C is initially in the erased state (“1” state). FIG. 62 shows a case where “0” -writing is performed on the cell A of FIG.
(“1” -write cell) and cell C (unselected cell)
Shows the amount of change in the threshold value.

First, when Vpass is set to a low value,
At the time of “0” -writing to the cell A, the channel potential of the cell (write-inhibited cell) B to be subjected to “1” -writing does not sufficiently rise, and electrons are injected into the floating gate electrode of the cell B. Therefore, as shown by the solid line in FIG. 62, the threshold value of the cell B to be written “1” -increases gradually from the initial value Vth1, and the threshold value of the cell B changes to the “1” state indicated by the dashed line. And the boundary line of the “0” state. As a result, erroneous writing (“0” -writing) is performed on the cell B to be subjected to “1” -writing.
Occurs.

When Vpass is set to a sufficiently high value, when “0” -write is performed on cell A, “1”-
The channel potential of the cell to be written (write-inhibited cell) B sufficiently rises. Therefore, as shown by the solid line in FIG. 62, the threshold value of the cell B to be "1" -written remains the initial value (erased state) Vth1, and the erroneous write ("0" -write) ) Is prevented (that is, “1” -writing is performed).

On the other hand, regarding the unselected cell C, the cell A
0V is transferred from the bit line to the channel, and the channel potential is fixed at 0V. Therefore, Vpa
If the value of ss is too high, a high voltage is applied between the control gate electrode of the cell C and the channel at the time of “0” -writing to the cell A, and electrons are injected into the floating gate electrode of the cell C. Therefore, as shown by the broken line in FIG. 62, the threshold value of the cell C is the initial value (erased state) V
The threshold value of the cell C gradually increases from th1, and exceeds the boundary between the “1” state and the “0” state indicated by the dashed line. As a result, erroneous writing (“0” -writing) occurs in the unselected cell C.

When "0" -write is performed on the cell A, if the value of Vpass is set sufficiently low, the voltage applied between the control gate electrode of the cell C and the channel is relaxed. Therefore, as indicated by the broken line in FIG. 62, the threshold value of the cell C is maintained at Vth1 (erased state), and erroneous writing (“0” -writing) is prevented.

As described above, in order to prevent erroneous writing to the cell B targeted for "1" -writing, Vp
While it is necessary to make the value of ass sufficiently high, it is necessary to make the value of Vpass sufficiently low in order to prevent erroneous writing to unselected cells C.

Therefore, in order to prevent erroneous writing for all cells which are not targeted for “0” -writing,
The threshold value (solid line and broken line) after the write operation is always
The range of the transfer potential Vpass is selected so as to be below the boundary line between the “1” state and the “0” state (dotted line) (“0” state), and the value of Vpass must be determined from the range. No.

However, as memory cells are miniaturized,
In particular, the surface breakdown voltage of the diffusion layer of the source-side select gate transistor decreases. The surface breakdown voltage refers to the PN junction breakdown voltage at the edge of the diffusion layer (the surface portion of the silicon substrate). As the miniaturization progresses, the surface breakdown voltage becomes a serious problem. When the surface withstand voltage is lowered, the
Leakage current (surface leakage current) occurs at the edge of the diffusion layer, and the channel potential of the write-inhibited cell does not rise sufficiently, which may cause erroneous writing.

For example, as shown in FIG. 63, as the number of times of programming (or the number of times of rewriting) increases, the threshold voltage Vth1 of the memory cell ("1" state) gradually increases in the positive direction due to factors such as electron traps. fluctuate. That is,
Threshold voltage Vth of memory cell in erased state (“1” state)
Since 1 shifts in the positive direction, Vth1 in FIG. 62 becomes close to the dashed line (the boundary between “1” and “0”).

In particular, in a device in which the surface breakdown voltage of the diffusion layer of a transistor is low and a surface leakage current may occur, as shown in FIG. 63, the amount of change in the threshold value with respect to the number of times of programming is large (a large slope). As a result, erroneous writing is likely to occur in cells B and C that are not targeted for “0” writing.

As described above, in the conventional NAND type flash memory, the channel potential of the "1" -write cell cannot be sufficiently increased due to the decrease in the surface breakdown voltage of the diffusion layer during the write operation due to the miniaturization of the memory cell. Erroneous writing may occur. This problem is particularly noticeable when arsenic (As) is used as the ions constituting the diffusion layer.

The above-mentioned problem becomes particularly noticeable when a write operation is performed by a local self-boost (LSB) method.

FIG. 64 shows the potential applied to each electrode in the write operation by the LSB method.

In the LSB operation, 0 V is applied to the word lines (control gate lines) CG0, CG2 on both sides of the selected word line (control gate line) CG1, and the remaining unselected word lines (control gate lines) CG3,・
.. Apply transfer potential Vpass to CG15. "1"-
The write cell (write-inhibited cell) M12 is cut off due to the back gate bias effect because its channel is boosted by Vpass.

Thereafter, the write potential Vpp changes to the word line C.
When given to G1 (“0” —the control gate electrode of the write cell M11), “1” —the write cell M12
Are boosted by capacitive coupling. At this time, for example, if Vpp is 18 V and the channel boost ratio is 0.5, the channel potential of the cell M12 is 8 to 9
It rises to about V. This value is a sufficiently large value as the write inhibit potential.

However, as described above, if the surface breakdown voltage of the diffusion layer of the source-side select gate transistor is reduced due to the miniaturization of the memory cell, the surface breakdown of the diffusion layer (junction breakdown) occurs when the LSB operation is performed. ) Occurs, causing a leak, which is very problematic from the viewpoint of reliability and the like.

Such a problem can be avoided by separately forming the diffusion layer of the select gate transistor and the diffusion layer of the memory cell. However, in this case, the manufacturing process becomes complicated and causes an increase in cost. In recent years,
With the miniaturization of memory cells, it is desired that a diffusion layer of a select gate transistor and a diffusion layer of a memory cell be formed simultaneously in the same step.

Therefore, it is necessary to develop a new device structure for preventing a leak current at the time of writing and sufficiently improving the cutoff characteristics of the select gate transistor without complicating the manufacturing process.

[0106]

As described above, the conventional N
First, the AND flash memory has a problem that the conductance Gm of the memory cell is deteriorated due to an electron trap or the like in reading. Secondly,
Regarding writing, there is a problem of erroneous writing when a method of boosting a channel such as a self-boost method or an LSB method is employed. This problem has become more remarkable when the surface breakdown voltage of the diffusion layer of the source-side select gate transistor is reduced due to the miniaturization of the memory cell.

The present invention has been made in order to solve the above-mentioned drawbacks, and an object of the present invention is to provide a high reliability device having a structure capable of accurately performing a read operation and a write operation even when a memory cell is miniaturized. To provide a novel nonvolatile semiconductor memory.

[0108]

According to the present invention, there is provided a nonvolatile semiconductor memory comprising a plurality of memory cells arranged in series on a surface region of a semiconductor substrate of a first conductivity type and connected in series.
An AND cell, disposed in a surface region of the semiconductor substrate,
A select gate transistor connected to the NAND cell, wherein a peak of a concentration profile of a first impurity forming a source / drain diffusion layer of a second conductivity type of the plurality of memory cells and the select gate transistor is the peak of the semiconductor It is set at a position of 0.04 μm or more from the surface of the substrate.

A nitride film is disposed on the source / drain diffusion layers of the plurality of memory cells and the select gate transistor. The peak of the concentration profile of the first impurity forming the source / drain diffusion layers of the plurality of memory cells and the select gate transistor is set at a position of 0.2 μm or less from the surface of the semiconductor substrate.

The peak value of the concentration profile of the first impurity is twice or more larger than the concentration value of the concentration profile of the first impurity on the surface of the semiconductor substrate. The concentration of the second impurity of the first conductivity type between the plurality of memory cells and the channel portion of the select gate transistor is higher than the concentration of the second impurity in the channel portion. The concentration of the concentration profile of the first impurity at the surface of the semiconductor substrate is lower than the surface concentration of the second impurity of the first conductivity type between the plurality of memory cells and the channel portion of the select gate transistor.

A first conductivity type diffusion layer is disposed on the source / drain diffusion layers of the plurality of memory cells and the select gate transistor. The peak of the concentration profile of the second impurity forming the first conductivity type diffusion layer is set at a position less than 0.04 μm from the surface of the semiconductor substrate. The width of the first conductivity type diffusion layer in the channel length direction is smaller than the width of the source / drain diffusion layer in the channel length direction.

On the source / drain diffusion layers of the plurality of memory cells and the select gate transistor, a second conductivity type low concentration diffusion layer having a concentration lower than that of the source / drain diffusion layers is disposed. I have. The peak of the concentration profile of the second impurity forming the low-concentration diffusion layer is set at a position less than 0.04 μm from the surface of the semiconductor substrate. The concentration of the concentration profile of the second impurity at the surface of the semiconductor substrate is higher than the concentration of the third impurity of the first conductivity type between the plurality of memory cells and the channel portion of the select gate transistor. The width of the low concentration diffusion layer in the channel length direction is smaller than the width of the source / drain diffusion layer in the channel length direction.

Each of the plurality of memory cells has a charge storage layer and a control gate electrode on the charge storage layer, and two memory cells adjacent to each other share one source / drain diffusion layer. ing. A second conductivity type auxiliary diffusion layer is disposed in the semiconductor substrate on the source / drain diffusion layer on the contact portion side of the select gate transistor, and a peak of a concentration profile of an impurity forming the auxiliary diffusion layer is: It is set at a position less than 0.04 μm from the surface of the semiconductor substrate.

The first impurity is arsenic, and the second impurity is
The impurity is boron. The first and second impurities are:
Both are arsenic. Further, the first impurity may be arsenic, and the second impurity may be phosphorus.

For the plurality of memory cells, a self-boost writing method is applied in which at least the channel potential of one selected memory cell is boosted to inhibit writing to the selected one memory cell. .

A nonvolatile semiconductor memory according to the present invention is arranged in a surface region of a semiconductor substrate of a first conductivity type, and comprises a NAND cell composed of a plurality of memory cells connected in series, and is arranged in a surface region of the semiconductor substrate. A select gate transistor connected to both ends of the NAND cell one by one; and a nitride film disposed on a source / drain diffusion layer of a second conductivity type of the plurality of memory cells and the select gate transistor. The source / drain diffusion layers of the plurality of memory cells and the select gate transistor are embedded in the semiconductor substrate, and a surface portion of the semiconductor substrate on the source / drain diffusion layer includes:
A first conductivity type diffusion layer is disposed.

The non-volatile semiconductor memory according to the present invention includes a source / drain of a second conductivity type disposed in a semiconductor substrate of a first conductivity type.
A drain diffusion layer; a buried layer of a second conductivity type disposed in the semiconductor substrate between the source / drain diffusion layers; a charge storage layer disposed on the buried layer; And a memory cell having a buried channel structure including a control gate electrode arranged.

The charge storage layer is a floating gate electrode, and a gate insulating film having a function of a tunnel insulating film is disposed between the semiconductor substrate and the floating gate electrode. The floating gate electrode includes a first or second conductivity type impurity. When the floating gate electrode contains impurities of the second conductivity type, for example, when the first conductivity type is P-type and the second conductivity type is N-type, the potential of the floating gate electrode becomes negative. A read operation is performed based on the potential.
Further, when the first conductivity type is N-type and the second conductivity type is P-type, the read operation is performed with a potential relationship in which the potential of the floating gate electrode is positive.

The control gate electrode is of the first or second conductivity type. During a read operation, data stored in the memory cell is read by detecting a current flowing inside the buried layer. The memory cell comprises:
It is applied to a memory cell of a NAND flash memory.

In the nonvolatile semiconductor memory according to the present invention, in the nonvolatile semiconductor memory having the buried source / drain diffusion layers, each of the plurality of memory cells constituting the NAND cell is replaced with a memory cell having a buried channel structure. Is replaced by

The charge storage layer may be a floating gate electrode or an insulating film (for example, a nitride film) having a charge trapping function.

[0122]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor memory according to the present invention will be described in detail with reference to the drawings.

The present invention can be applied to a nonvolatile semiconductor memory having a charge storage layer (for example, a floating gate electrode) and a control gate electrode. In particular, a self-boost write system and a local self-boost (LSB) write system This is a very significant effect for a NAND flash memory to which a write method for boosting the channel potential of a write-inhibited cell is applied.

The present invention can be applied to all of the above nonvolatile semiconductor memories.
Number of data stored in the cell (binary or multi-valued), element isolation structure (LOCOS, STI, etc.), memory cell array structure (NAND type, NOR type, etc.), manufacturing process, N
In the case of an AND flash memory, the present invention can be applied regardless of the number of cells in the NAND cell unit, the number of select gate transistors, and the like.

However, in the following, in order to simplify the description,
A case where the present invention is applied to a NAND flash memory having a stack gate structure (a floating gate electrode and a control gate electrode) will be described.

[A] First, a NAND flash memory according to the first embodiment of the present invention will be described.

FIG. 1 schematically shows the device structure of a NAND flash memory according to the first embodiment of the present invention.

P-type silicon substrate (may be a well) 12
On the top, a NAND cell composed of a plurality of (16 in this example) memory cells M01,..., M151 connected in series, and two NAND cells connected one at each end of the NAND cell
Two select gate transistors S11 and S21 are formed.

Each of the memory cells M01,..., M151 has a floating gate electrode FG and control gate electrodes CG0,. The select gate transistors S11, S21 are connected to the gate electrodes SGS, S
GD.

The feature of the memory of the present invention resides in a diffusion layer (source / drain).

Usually, the diffusion layer of the memory cell is in contact with the surface of the silicon substrate as shown in FIG. 54, for example. That is, the peak of the profile of the impurity concentration of the diffusion layer substantially coincides with the surface of the silicon substrate (in fact, the peak is slightly
Since it enters the silicon substrate, it is called “substantially”. ).

On the other hand, in the present invention, the peak of the concentration profile of the N-type impurity of the N-type diffusion layers (source / drain) 13, 13b, 13c is intentionally set in the silicon substrate 12. That is, in the present invention, the diffusion layer 1
The parts having the lowest resistances of 3, 13b, and 13c are not provided on the surface of the silicon substrate 12, but are provided at positions deeper by a certain distance from the surface of the silicon substrate 12.

Specifically, the N-type diffusion layers 13, 13b, 1
The peak of the concentration profile of the N-type impurity 3c is set at a position deeper than the surface of the silicon substrate 12 by 0.04 μm or more (for example, at a position of about 0.1 μm). In this example,
The peak of the concentration profile was set at a position deeper than the surface of the silicon substrate 12 by 0.04 μm or more. This condition is determined from the viewpoint of hot carrier resistance. If the peak of the profile is set to a position deeper than the surface of the silicon substrate 12 by 0.04 μm or more as in this example, it seems that most devices can be handled.

It is preferable that the peak of the concentration profile of the N-type impurity in the N-type diffusion layers 13, 13b and 13c is set at a position of 0.2 μm or less from the surface of the silicon substrate 12.

As a result of setting the peak of the concentration profile of the N-type impurity in the N-type diffusion layers 13, 13b and 13c in the silicon substrate 12, in this example, the N-type diffusion layers 13, 13b and 13c
13c is separated from the surface of the silicon substrate 12 by a certain distance. That is, for example, a region between the surface of the silicon substrate 12 and the N-type diffusion layer 13 is a P-type region (at the surface of the silicon substrate 12, the concentration of the P-type impurity is higher than the concentration of the N-type impurity. high.).

However, in the present invention, the N-type diffusion layers 13
If the peak of the concentration profile of the N-type impurity of b, 13c is set in the silicon substrate, the N-type diffusion layer 13,
13b and 13c may be in contact with the surface of the silicon substrate 12.

Diffusion layers 13 and 1 in NAND cell unit
Among the diffusion layers 13b and 13c, the contact portions (plugs) 16b and 16c and the diffusion layers 13b are disposed on the diffusion layer 13b disposed closest to the drain (bit line) and the diffusion layer 13b disposed closest to the source (source line). 13b and 13c are connected to each other with a low resistance and reliably.
b ′ and 13c ′ are arranged.

FIG. 2 shows one of the memory cells of FIG. FIG. 3 shows a concentration profile of a cross section perpendicular to the diffusion layer of the memory cell of FIG.

N-type impurity (arsenic (As)) in N-type diffusion layer
The peak of the concentration profile at a position between 0.04 μm and 0.2 μm from the surface of the silicon substrate (for example,
(At a position of about 0.1 μm). At the surface of the silicon substrate, the concentration of the P-type impurity (boron (B)) is higher than the concentration of the N-type impurity (As). That is, the N-type diffusion layer is apart from the surface of the silicon substrate.

According to such a memory cell structure, for example, as shown in FIG. 4, the current path in the NAND cell unit is formed on the surface of the silicon substrate 12 in the channel portion of the transistor (memory cell and select gate transistor). Thus, the diffusion layer 13 disposed between the channels of the transistors is inside the silicon substrate 12. Therefore, the resistance value of the diffusion layer 13 (the part that determines the resistance value is inside the silicon substrate 12) is hardly affected by the electric charge trapped at the interface between the insulating film on the diffusion layer 13 and the silicon substrate 12. Even if the memory cell is miniaturized, it is possible to suppress the occurrence of the variation in the conductance Gm or the variation in the reading speed.

In the above-described example, the memory cell and the select gate transistor are constituted by N-channel MOS transistors. However, the present invention is naturally applicable to the case constituted by P-channel MOS transistors. It is.

Next, N according to the first embodiment of the present invention will be described.
A method for manufacturing an AND flash memory will be described.

In the manufacturing method described below, the case where each of the memory cell and the select gate transistor is an N-channel type is taken as an example, but the type of impurities and ion implantation conditions (dose amount, acceleration voltage, etc.) are changed. Thereby, it can be easily applied to the case of the P-channel type. A so-called peripheral circuit formed around the memory cell array portion is also formed in parallel with the manufacturing method described below, but the description thereof will be omitted.

First, as shown in FIG. 5, a silicon oxide film 41a having a thickness of about 10 nm is formed on a P-type silicon substrate 40 by, for example, thermal oxidation.

Next, as shown in FIG. 6, an N-type impurity (for example, phosphorus (P)) is ion-implanted into the silicon substrate 40 using a mask for forming an N-type well to form an N-type well region 42. To form Here, the N-type well region 42 has, for example, an acceleration energy of 1.5 [MeV], 4.0 × 1.
At a dose of 0 ¹³ cm ^-2, the silicon phosphorus substrate 40
It is formed by ion implantation.

The formation of the N-type well region 42 is performed, for example,
For example, it may be realized by three-stage ion implantation. That is,
In the first stage, for example, an acceleration energy of 1.5 [MeV]
Geek, 4.0 × 10¹²cm^-2With a dose of
Ion implantation into the silicon substrate, in the second stage, for example,
For example, acceleration energy of 750 [KeV], 8.0 × 10
¹²cm^-2Phosphorus into the silicon substrate at a dose of
In the third stage, for example, 150 [KeV]
Acceleration energy of 1.0 × 10¹²cm^-2The dose of
In a quantity, phosphorus is ion-implanted into a silicon substrate.

Next, a P-type impurity (for example, boron (B)) is ion-implanted into the silicon substrate 40 using a mask for forming a P-type well to form a P-type well region 43. Here, the P-type well region 43 is, for example, 300
[KeV] acceleration energy, 3.0 × 10 ¹³ cm
It is formed by ion-implanting boron into the silicon substrate 40 at a dose of ^-2 .

The formation of the P-type well region 43 may be realized by, for example, two-stage ion implantation. That is,
In the first stage, for example, boron is ion-implanted into the silicon substrate at an acceleration energy of 400 [KeV] and a dose of 4.0 × 10 ¹³ cm ⁻² , and in the second stage, for example, 200 [KeV] Acceleration energy of 1.0 × 10
Boron is ion-implanted into the silicon substrate at a dose of ¹² cm ^-2 .

The acceleration energy of, for example, 10 [KeV] with respect to the surface of the P-type well region 43, 3.0,
A dose of × ¹⁰ 13 ^{cm -2,} to boron ion implantation (so-called channel implantation). Thereafter, the silicon oxide film 41a is removed.

It is to be noted that a so-called channel implant (chann) is used.
El ion-implantation may be performed after removing the silicon oxide film 41a. That is, the silicon oxide film 41a
Is removed, a silicon oxide film having a thickness of about 10 nm is formed again on the P-type silicon substrate 40 by thermal oxidation,
Patterning for channel implantation is performed. Then, for example, acceleration energy of 10 [KeV], 3.0
At a dose of × 10 ¹³ cm ⁻² , boron ion implantation (channel implantation) is performed, and then the silicon oxide film is peeled off.

Next, as shown in FIG.
Thermal oxidation in an oxygen atmosphere of silicon substrate 4
Then, a silicon oxide film 41 having a thickness of about 8 nm is formed on zero.
Further, for example, the silicon oxide film 41 is formed by using the CVD method.
On top, an N-type impurity (eg, phosphorus) is added to about 2 × 10 ²⁰ c
An N-type polysilicon film 45 having a thickness of about 50 nm containing m- ³ is formed.

Thereafter, a silicon nitride film 46 having a thickness of about 100 nm is further formed on the polysilicon film 45 by using, for example, a CVD method. Subsequently, a silicon oxide film (TEOS film) 47 having a thickness of about 150 nm is formed on the silicon nitride film 46 by using, for example, a CVD method.

Further, a resist pattern is formed on the silicon oxide film 47 by PEP (photo etching process). Using this resist pattern as a mask, the silicon oxide film 47 is etched by RIE (reactive ion etching). After the silicon nitride film 46 is etched by RIE using the silicon oxide film 47 as a mask, the silicon oxide film 47 is removed.

Next, as shown in FIG. 8, using the silicon nitride film 46 as a mask, the polysilicon film 45 and the silicon oxide film 41 are sequentially etched by RIE. The silicon substrate 4 is formed using the silicon nitride film 46 as a mask.
0 is etched to form a trench 48 in the silicon substrate 40. The depth of the trench 48 is, for example,
It is about 0.3 μm.

Next, as shown in FIG.
The TEOS film 49 having a thickness of about 800 nm is formed on the silicon nitride film 46 so as to completely fill the trench 48 by using the method.
To form Thereafter, the TEOS film 49 is polished using a CMP (Chemical Mechanical Polishing) method, and the TEOS film 49 is left only in the trench 48, thereby forming an STI (Shallow Trench).
Isolation) Complete the structure.

Since the silicon nitride film 46 functions as an etching stopper during CMP, the TEOS film 4
9 substantially coincides with the surface of the silicon nitride film 46 (generally, the surface of the TEOS film 49 is slightly lower than the surface of the silicon nitride film 46). Thereafter, the silicon nitride film 46 is removed.

Next, as shown in FIG.
Using method D, a thickness of about 100
A polysilicon film 50 of nm is formed. Thereafter, an N-type impurity (for example, phosphorus) is introduced into the polysilicon film 50 by about 2 × 10 ²⁰ cm ⁻³ by, for example, a thermal diffusion method to lower the resistance of the polysilicon film 50.

Next, as shown in FIG.
By the method D, a thickness of about 200 nm is formed on the polysilicon film 50.
Is formed. The silicon nitride film 51 is patterned to form slits extending in the column direction in the silicon nitride film 51 except for the regions where the source-side and drain-side select gate transistors are formed. The width of the slit (width in the row direction)
Is 200 to 300 nm.

Further, a silicon nitride film 52 having a thickness of about 80 nm is formed on the silicon nitride film 51 by the CVD method. When the silicon nitride film 52 is etched by RIE, the silicon nitride film 52 remains only on the side wall of the slit of the silicon nitride film 51.

Thereafter, when the polysilicon film 50 is etched by RIE using the silicon nitride films 51 and 52 as a mask, a slit-like opening 53 is formed in the polysilicon film 50 as shown in FIG. . Here, the width of the opening 53 (the width in the row direction) is equal to T to realize the STI structure.
Since the width (width in the row direction) of the EOS film 49 is narrower, the polysilicon film 4 serving as a floating gate
5, 50 are wing-shaped.

After that, the silicon nitride films 51 and 52
(FIG. 11) is removed.

Next, as shown in FIG. 13, an insulating film 54 is formed on the polysilicon film 50. This insulating film 54
For example, a silicon oxide film having a thickness of about 5 nm and a thickness of about 8 nm
And a silicon oxide film having a thickness of about 5 nm (a so-called ONO film). Also, for example, CV
A polysilicon film 55 having a thickness of about 150 nm is formed on the insulating film 54 by the method D. In addition, approximately 3.6 × 10 ²⁰ cm ⁻³ N is ^{deposited in} the polysilicon film 55 by a thermal diffusion method.
Type impurity (for example, phosphorus) is introduced, and the polysilicon film 5 is formed.
5 is reduced in resistance.

Next, as shown in FIG.
Using a D method, a polysilicon film 56 having a thickness of about 100 nm containing an N-type impurity is formed on the polysilicon film 55. In addition, for example, a tungsten silicide (WSi) film 57 having a thickness of about 200 nm is formed on the polysilicon film 56 by using the CVD method. Then, a thickness of about 100 n is formed on the tungsten silicide film 57 by the CVD method.
An m-th silicon nitride film 58 is formed. Further, a silicon oxide film (TEOS film) 59 having a thickness of about 100 nm is formed on the silicon nitride film 58 by the CVD method.

Thereafter, by PEP (photo etching step),
A resist pattern is formed on the silicon oxide film 59, and the silicon oxide film 59 is etched by RIE using the resist pattern as a mask. Using the silicon oxide film 59 as a mask, the silicon nitride film 58 is formed by RIE.
Is etched, silicon oxide film 59 is removed.

Next, as shown in FIG. 15, using the patterned silicon nitride film 58 as a mask, the tungsten silicide film 57 and the polysilicon film 5 are formed by RIE.
6, 55 are sequentially etched. Thus, control gate electrodes CG0 to CG15 and select gate electrodes SGS (upper) and SGD (upper) extending in the row direction are completed. Control gate electrodes CG0,... CG15
Are set, for example, to 0.2 μm, respectively.

Next, as shown in FIG. 16, using the silicon nitride film 58 as a mask, the insulating film 54 and the polysilicon films 50 and 45 are sequentially etched by RIE. As a result, the floating gate electrode FG extending in the row direction
Then, the select gate electrodes SGS (lower) and SGD (lower) are completed.

Next, as shown in FIG. 17, a silicon nitride film 58 (control gate electrode and select gate)
Using a mask as a mask, an N-type impurity (for example, arsenic) is ion-implanted into the P-type well region 43 by self-alignment.
N-type diffusion layers 61, 61a and 61b are formed. The diffusion layer 61a serves as a source of the NAND cell unit,
The diffusion layer 61b becomes a drain of the NAND cell unit.

Here, the N-type diffusion layers 61, 61a, 61b
Is such that the peak of the concentration profile of the N-type impurity (As) is located inside the silicon substrate (P-type well region 43) 40, specifically, at a position deeper than the surface of the silicon substrate 40 by 0.04 μm or more. It is formed. For example, the peak of the concentration profile of the N-type impurity (As) is about 0.1
It is set at a position deeper by μm.

For this purpose, for example, the conditions for arsenic (As) ion implantation are set as follows: acceleration energy of 120 [KeV],
The dose may be set to 5.0 × 10 ¹³ cm ⁻² .
Under these conditions, an arsenic concentration profile (see FIG. 3) having a peak at a depth of about 0.1 μm from the surface of the silicon substrate 40 can be easily obtained. The diffusion layers 61, 61a, 61b are separated from the surface of the silicon substrate 40, but may be in contact with the surface of the silicon substrate 40, for example.

Regarding the concentration profile of arsenic constituting the diffusion layers 61, 61a and 61b, for example, the peak value (peak concentration value) is at least twice the concentration value of the surface portion of the silicon substrate 40. It is desirable to be large. Usually, a silicon substrate (P-type well region 43)
For example, boron (B) has a dose of about 3.0 × 10 ¹³ cm on the surface portion of the transistor 40 for controlling the threshold value of the transistor (memory cell and select gate transistor).
It is injected under the condition of ^-2 .

Therefore, the surface portion of the silicon substrate 40 between the channels of the respective transistors has a very high resistance P
As shown in FIG. 4, the electron path from the source line to the bit line (current path; however, the direction of the current is opposite to the moving direction of the electrons) is the type region. In the channel portion, it becomes the surface of the silicon substrate 40, and in the diffusion layer between the channel portions of the respective transistors, it becomes the inside of the silicon substrate 40.

Before forming the diffusion layers 61, 61a and 61b (before arsenic ion implantation), for example, at a temperature of about 10 ° C.
Thermal oxidation at 00 ° C. is performed, and the control gate electrode CG0
CG15, the surfaces of the select gate electrodes SGS, SGD and the floating gate electrode FG, and the surface of the silicon substrate (P-type well region 43) 40 may be formed with silicon oxide films.

Incidentally, the concentration profile of the impurity (arsenic) constituting the diffusion layers 61, 61a, 61b is adjusted by the conditions of ion implantation, that is, the acceleration energy and dose of the impurity (ion). In the present example, the peak of the arsenic concentration profile is set at 0.
In order to set the position of 1 μm, the conditions of arsenic ion implantation
Acceleration energy 150 [KeV], dose amount 5.0 × 1
It was set to 0 ¹³ cm ^-2 .

However, the peak of the impurity concentration profile of the diffusion layers 61, 61a and 61b only needs to be at a position of 0.04 μm or more from the surface of the silicon substrate 40. In this case, for example, the acceleration energy is 30 ~ 15
The range of 0 [KeV] and the dose amount are 1.0 × 10 ¹³ c.
It can be selected from the range of m ^{−2 to} 1.0 × 10 ¹⁴ cm ⁻² .

Next, as shown in FIG. 18, the diffusion layer 61a on the most source side (source line side) of the NAND cell unit.
N-type diffusion layers 61 a ′ and 61 b ′ are formed on the upper side and on the diffusion layer 61 b closest to the drain side (bit line side).

The N-type diffusion layers 61 a ′ and 61 b ′ have a peak of a concentration profile of an N-type impurity (for example, arsenic) on the surface of the silicon substrate 40. N-type diffusion layer 6
1a 'and 61b' are arranged to reduce the contact resistance in the bit line contact portion and the source line contact portion. Therefore, the N-type diffusion layers 61a 'and 61b'
Is formed by ion implantation of arsenic under normal conditions for forming a diffusion layer (source / drain), for example, under the conditions of an acceleration energy of 25 [KeV] and a dose of 3.0 × 10 ¹³ cm ⁻² .

The N-type diffusion layers 61, 61a, 61b,
After the formation of 61a 'and 61b', defect recovery annealing at, for example, a temperature of about 950 ° C. and a time of about 30 seconds is performed in order to recover damage to the silicon substrate 40 due to ion implantation.

The N-type diffusion layers 61a 'and 61b'
May be formed by ion implantation of arsenic after forming a contact hole (bit line contact portion, source line contact portion) with the silicon substrate (P-type well region 43) 40. In this case, the conditions for ion implantation are also ordinary conditions, for example, acceleration energy 25 [Ke
V] and a dose of 3.0 × 10 ¹³ cm ⁻² .

Next, as shown in FIG.
Using method D, control gate electrodes CG0-CG1
5. A silicon nitride film 60 having a thickness of about 20 nm covering the select gate electrodes SGS, SGD and the floating gate electrode FG is formed. The silicon nitride film 60 functions as an etching stopper when forming a contact hole (bit line contact portion, source line contact portion) with the silicon substrate (P-type well region 43) 40 (this will be described later). .

The film quality of the silicon nitride film 60 is as follows:
This affects the resistance value of the surface of the silicon substrate (P-type well region 43) 40. That is, when an electron trap is generated in the silicon nitride film 60, the resistance of the surface of the silicon substrate 40 is increased. However, in the present invention, the diffusion layer 6
1, 61a and 61b are formed inside the silicon substrate 40, so that they are less affected by the silicon nitride film 60.

Thereafter, a BPSG film 62 having a thickness of about 1.45 μm is formed on silicon nitride film 60. Also, CM
Using the P method, the BPSG film 62 is polished by about 0.4 μm,
The surface of the BPSG film 62 is made flat.

Next, as shown in FIG.
2 a silicon nitride film 91 as an etching stopper
To form Subsequently, TEOS is formed on the silicon nitride film 91.
A film 64 is formed.

Further, a resist pattern is formed by PEP. Using this resist pattern as a mask, RIE
The TEOS film 64 is etched by
A wiring groove is formed on the substrate. At this time, the silicon nitride film 91 becomes
Functions as an etching stopper in RIE. Thereafter, the resist pattern is removed.

[0184] Again, a resist pattern is formed by PEP. Using this resist pattern as a mask, RIE
Thereby, contact holes reaching the diffusion layer (source) 61a 'and the diffusion layer (drain) 61b' are formed in the BPSG film 62, the silicon nitride film 60, and the silicon oxide film 41. At the same time, a contact hole (not shown) reaching the contact region of the first-layer select gate electrodes SGS (lower) and SGD (lower) is formed by this RIE.
Thereafter, the resist pattern is removed.

Here, regarding the formation of the contact holes reaching the diffusion layer (source) 61a 'and the diffusion layer (drain) 61b', first, the BPSG film 62 is etched using the silicon nitride film 60 as an etching stopper. Then, the silicon nitride film 60 and the silicon oxide film 41 are simultaneously etched.

Note that, as described above, the diffusion layers 61a ',
61b 'may be formed by, for example, ion implantation of arsenic (As) after forming a contact hole reaching the silicon substrate (P-type well region 43) 40 on the diffusion layers 61a and 61b.

Thereafter, barrier metals 65A and 65B made of, for example, a laminate of titanium and titanium nitride are formed on the inner surface of the wiring groove and the inner surface of the contact hole. Also, TE
On the OS film 64, tungsten films 66A and 66B that completely fill the wiring groove and the contact hole are formed. When the tungsten films 66A and 66B are polished by the CMP method and left only in the wiring groove and the contact hole, the NA
Source line SL connected to the source of ND cell unit
And wirings 65B and 66B connected to the drains of the NAND cell units.

Next, as shown in FIG.
4 is formed with a TEOS film 92. A silicon nitride film 93 as an etching stopper is formed on the TEOS film 92. Subsequently, a TEOS film 94 is formed on the silicon nitride film 93.
To form

Further, a resist pattern is formed by PEP. Using this resist pattern as a mask, RIE
The TEOS film 94 is etched by
Then, wiring grooves for bit lines, dummy bit lines, and the like are formed. At this time, the silicon nitride film 93 functions as an etching stopper in RIE. Thereafter, the resist pattern is removed.

[0190] Again, a resist pattern is formed by PEP. Using this resist pattern as a mask, RIE
Thereby, contact holes reaching the wirings 65B and 66B are formed in the silicon nitride film 93 and the TEOS film 92. Thereafter, the resist pattern is removed.

Thereafter, a barrier metal 68 made of, for example, a laminate of titanium and titanium nitride is formed on the inner surface of the wiring groove and the inner surface of the contact hole. Also, the TEOS film 94
A metal film (for example, an aluminum film) 69 that completely fills the wiring groove and the contact hole is formed thereon. When the metal film 69 is polished by the CMP method and left only in the wiring groove and the contact hole, a plurality of bit lines BL are formed.

Note that a passivation film made of a silicon nitride film is formed on these wirings.

Through the above manufacturing steps, a NAND flash memory having the memory cell and select gate transistor of the present invention is completed.

As described above, according to the NAND flash memory and the method of manufacturing the same according to the first embodiment of the present invention, the transistors (memory cells and select gate transistors) in the NAND cell unit have respective diffusions. The position where the peak of the impurity concentration profile of the layer is deeper than the surface of the silicon substrate (specifically,
(A position deeper than 0.04 μm). in this case,
For example, each diffusion layer is separated from the surface of the silicon substrate, and the surface portion (excluding the channel portion) of the silicon substrate becomes a high-resistance region.

Therefore, in the NAND flash memory of this example, for example, due to the influence of the manufacturing process and the like, FIG.
Even if a large amount of damage occurs in the silicon nitride film 60 and charges (electrons) are trapped by this damage, the influence of the deterioration of the conductance Gm is hardly affected. On the other hand, when the peak of the impurity concentration profile of the diffusion layer substantially coincides with the surface of the silicon substrate, the electron trap causes variations in the resistance of the diffusion layer and the silicon substrate at the gate edge. And the ON current fluctuates, which affects the reading speed.

In particular, the surface breakdown voltage of the source-side select gate transistor becomes very problematic when boosting the channel potential in the write-inhibited cell (“1” -write cell). That is, the write inhibit potential (“1”)
Since the (cell potential of the write cell) is generated by the self-boost operation, if the surface withstand voltage is low, a surface leak current occurs and the channel potential cannot be sufficiently increased.

However, in recent years, memory cells have been miniaturized, and the surface breakdown voltage of the diffusion layer of the select gate transistor has tended to decrease. Therefore, with the progress of miniaturization, the problem of erroneous writing has rapidly emerged.

In the present invention, the peaks of the concentration profiles of the diffusion layers of the memory cell and the select gate transistor are both provided inside the silicon substrate, and the surface portion (excluding the channel portion) of the silicon substrate corresponds to the high resistance region. In particular, the surface breakdown voltage of the select gate transistor is improved, and the channel potential of the write-inhibited cell can be sufficiently increased. That is, according to the present invention,
Since the write inhibit potential can be generated stably, erroneous write can be prevented.

FIG. 22 shows the reading speed when the present invention is applied. It can be seen that in the device employing the present invention, the reading speed is improved and uniformized. FIG. 23 shows the relationship between the number of times of programming and the change in the threshold voltage of the memory cell. Since the device employing the present invention has almost no surface leakage current, the amount of change in the threshold voltage with respect to the number of times of programming is smaller than that of a conventional device in which surface leakage current occurs. In other words, it can be seen that when the present invention is employed, erroneous writing hardly occurs.

As described above, according to the present invention, the influence of hot carriers generated near the surface of the semiconductor substrate, that is, NAN
It is hardly affected by the deterioration of the conductance Gm due to the read operation of the D cell.

[B] Next, a NAND flash memory according to a second embodiment of the present invention will be described.

In the NAND flash memory according to the first embodiment, the N-type diffusion layers (the diffusion layers below the bit line contact portions and the source line contact portions) of the transistors (memory cells and select gate transistors) in the NAND cell unit are provided. The concentration of the P-type impurity (B) in the P-type high-resistance region (except for the diffusion layer of) is a so-called channel implantation (cha) for controlling the threshold of the transistor.
It is determined by the dose of the P-type impurities in the n-ion ion-implantation process.

Therefore, the N-type impurity (As) in the N-type diffusion layer
Concentration peak of the silicon substrate (P-type well region)
However, depending on the conditions of the channel implantation, the region on the N-type diffusion layer (the surface region of the silicon substrate) does not have a sufficiently high resistance and functions as a diffusion layer, even if the position is set sufficiently deeper than the surface of the substrate. May be.

In this case, the purpose of setting the main path (excluding the channel portion) of the current (charge) flowing through the NAND cell unit inside the silicon substrate cannot be sufficiently achieved. Therefore, in this example, for example, the main path of the current flowing through the NAND cell unit (excluding the channel portion)
Is proposed to be able to be surely set inside the silicon substrate.

It should be noted here that, in the present invention, it is important to set the main path of the current flowing through the transistor (excluding the channel portion) inside the silicon substrate. Even if the part is caused to flow on the surface of the silicon substrate as in the related art, there is no problem at all (see fourth and fifth embodiments described later).

FIG. 24 schematically shows the device structure of a NAND flash memory according to the second embodiment of the present invention.

P-type silicon substrate (may be a well) 12
On the top, a NAND cell composed of a plurality of (16 in this example) memory cells M01,..., M151 connected in series, and two NAND cells connected one at each end of the NAND cell
Two select gate transistors S11 and S21 are formed.

The memory cells M01,..., M151 have a floating gate electrode FG and control gate electrodes CG0,. The select gate transistors S11, S21 are connected to the gate electrodes SGS, S
GD.

The memory cells M01,..., M151 and the N-type diffusion layers (source / drain) 13, 13b, 13c of the select gate transistors S11, S21 are similar to the devices according to the above-described first embodiment. The peak of the concentration profile of the type impurity is set inside silicon substrate 12. That is, the lowest resistance portions of the diffusion layers 13, 13 b, and 13 c are not provided on the surface of the silicon substrate 12 but are provided at positions deeper by a certain distance from the surface of the silicon substrate 12.

The specific position of the peak of the concentration profile of the N-type impurity in the N-type diffusion layers 13, 13b, and 13c is zero from the surface of the silicon substrate 12 as in the device according to the above-described first embodiment. It is a position deeper than .04 μm (for example, a position of about 0.1 μm). In this example, the peak of the concentration profile is set at a position deeper than the surface of the silicon substrate 12 by 0.04 μm or more.
Determined from the viewpoint of hot carrier resistance. However, as in this example, the peak of the profile is
If it is set at a position of 0.04 μm or more and 0.2 μm or less from the surface, most devices can be handled.

The feature of the device of this example is that the N-type diffusion layer 1
The point is that the P-type diffusion layers 30, 30b, and 30c are arranged on the surface of the silicon substrate (may be a well) 12 on the layers 3, 13b, and 13c. P-type diffusion layers 30, 30b, 3
Oc is formed by, for example, a unique ion implantation process different from channel implantation.

As described above, in this example, the N-type diffusion layers 13 and
Since the P-type diffusion layers 30, 30b, and 30c are formed on the surface of the silicon substrate 12 on the layers 13b and 13c, the surface of the silicon substrate 12 on the N-type diffusion layers 13, 13b and 13c is always high. It is a resistance region. Therefore, N
The main path of the current flowing through the transistor (excluding the channel portion) in the AND cell unit is at a sufficiently deep position (at a position of 0.04 μm or more) with respect to the surface of the silicon substrate 12, and the reading speed (diffusion layers 13 and 13b) , 13c) are not affected by the film quality of the insulating film (for example, a nitride film) on the N-type diffusion layers 13, 13b, 13c.

Diffusion layers 13, 1 in NAND cell unit
Among the diffusion layers 13b and 13c, the contact portions (plugs) 16b and 16c and the diffusion layers 13b are disposed on the diffusion layer 13b disposed closest to the drain (bit line) and the diffusion layer 13b disposed closest to the source (source line). N-type auxiliary diffusion layers 13b and 13c are electrically connected to each other with low resistance and reliably.
b ′ and 13c ′ are arranged.

In this example, as described above, the P-type diffusion layers 30, 30b, and 30b are formed on the N-type diffusion layers 13, 13b, and 13c.
30c, the N-type auxiliary diffusion layers 13b ', 1
3c 'is to be formed in the P-type diffusion layers 30b and 30c.

FIG. 25 shows one of the memory cells of FIG. FIG. 26 shows a concentration profile of a cross section perpendicular to the diffusion layer of the memory cell of FIG.

N-type impurity (arsenic (As)) in N-type diffusion layer
Is set at a position deeper than the surface of the silicon substrate by 0.04 μm or more (for example, at a position of about 0.1 μm). In this example, P on the N-type diffusion layer
Since the type diffusion layer is formed, the concentration of the P-type impurity (boron (B)) is sufficiently higher than the concentration of the N-type impurity (As) at the surface of the silicon substrate.

According to such a memory cell structure, NA
The current path in the ND cell unit is on the surface of the silicon substrate 12 in the channel portion of the transistor (memory cell and select gate transistor), and is inside the silicon substrate 12 in the diffusion layer 13 disposed between the channels of the transistors. Becomes

Therefore, the resistance value of the diffusion layer 13 (the part that determines the resistance value is inside the silicon substrate 12) is almost free from the influence of the charges trapped at the interface between the insulating film on the diffusion layer 13 and the silicon substrate 12. I will not receive it. Further, even if the memory cell is miniaturized, the conductance Gm does not deteriorate due to the hot carrier, and the reading speed does not vary.

Further, in this example, since the P-type diffusion layer is formed on the N-type diffusion layer, the surface of the silicon substrate 12 on the N-type diffusion layer (current main path) has a P-type high resistance region. Has become. That is, the P-type diffusion layer (high-resistance region) does not function as a diffusion layer (source / drain) of the transistor, and can contribute to stabilization of the on-current (read speed) of the memory cell.

In the above-described example, the memory cell and the select gate transistor are composed of N-channel MOS transistors. However, the present invention is naturally applicable to the case where the memory cells and select gate transistors are composed of P-channel MOS transistors. It is.

Next, N according to the second embodiment of the present invention will be described.
A method for manufacturing an AND flash memory will be described.

First, the control gate electrodes CG0 to CG15 and the select gate electrode SGS are manufactured by using the same manufacturing method as that of the first embodiment.
(Top), SGD (top), floating gate electrode FG
Then, the select gate electrodes SGS (lower) and SGD (lower) are completed (see the description of FIGS. 5 to 16).

Next, as shown in FIG. 27, using the silicon nitride film 58 (control gate electrode and select gate electrode) as a mask, a P-type impurity (for example, boron) is formed in the P-type well region 43 by self-alignment. Ion implantation is performed to form P-type diffusion layers 70, 70a, 70b. The ion implantation conditions at this time include the P-type diffusion layers 70, 70a,
The condition is such that 70b is formed on the surface of the silicon substrate (P-type well region 43) 40. For example, the condition of ion implantation of boron (B) is that the acceleration energy is 10 [K
eV], and the dose is set to 1.0 × 10 ¹³ cm ⁻² .

Thereafter, using the silicon nitride film 58 (control gate electrode and select gate electrode) as a mask, an N-type impurity (for example, arsenic) is ion-implanted into the P-type well region 43 by self-alignment, and the N-type diffusion is performed. Layer 6
1, 61a and 61b are formed. The diffusion layer 61a
Is the source of the NAND cell unit, and the diffusion layer 61
b becomes the drain of the NAND cell unit.

Here, the N-type diffusion layers 61, 61a, 61b
Is such that the peak of the concentration profile of the N-type impurity (As) is located inside the silicon substrate (P-type well region 43) 40, specifically, at a position deeper than the surface of the silicon substrate 40 by 0.04 μm or more. It is formed. For example, the peak of the concentration profile of the N-type impurity (As) is about 0.1
It is set at a position deeper by μm.

For this purpose, for example, the conditions for arsenic (As) ion implantation may be set to an acceleration energy of 30 [KeV] and a dose of 5.0 × 10 ¹³ cm ⁻² . By setting such conditions, an arsenic concentration profile (see FIG. 26) having a peak at a position deeper than 0.04 μm from the surface of the silicon substrate 40 can be easily obtained.

In the present example, the surface of the silicon substrate 40 between the channels of the transistors in the NAND cell unit is provided with very high-resistance P-type diffusion layers 70, 70a, 7
0b. Therefore, the path of the electrons from the source line to the bit line (current path; however, the direction of the current is opposite to the moving direction of the electrons) is the surface of the silicon substrate 40 in the channel portion of each transistor. Between the channel portions of the transistors, a silicon substrate 4
0.

Thus, the N-type diffusion layers 61, 61a, 6
The resistance value of 1b is not affected by the charges trapped in the insulating film (especially, the silicon nitride film) formed on the silicon substrate 40, and the variation in the conductance Gm is eliminated. As a result, according to the present invention, a stable read operation can be ensured, and a highly reliable device can be provided.

In the above example, the P-type diffusion layers 70, 7
0a, 70b are formed, and then N-type diffusion layers 61, 61 are formed.
a and 61b are formed. For example, the N-type diffusion layers 61 and 6 are formed.
After forming 1a, 61b, P-type diffusion layers 70, 70
a, 70b may be formed.

Before forming the P-type diffusion layers 70, 70a, 70b and the N-type diffusion layers 61, 61a, 61b (before ion implantation), thermal oxidation at, for example, a temperature of about 1000 ° C. is performed to form a control gate electrode. A silicon oxide film may be formed on each of CG0 to CG15, the surfaces of the select gate electrodes SGS and SGD, the floating gate electrode FG, and the surface of the silicon substrate (P-type well region 43) 40.

Thereafter, a NAND flash memory as shown in FIG. 28 is completed by using the same manufacturing method as that of the first embodiment described above (see the description of FIGS. 19 to 21). .

In this example, the N-type diffusion layer 61a 'is also provided on the diffusion layer 61a on the most source side (source line side) and the most diffusion side (bit line side) of the NAND cell unit. , 61b 'are formed.

The N-type diffusion layers 61 a ′ and 61 b ′ are formed when the diffusion layers 61, 61 a, 61 b, 70, 70 a, and 70 b are formed or when the silicon substrate (P-type well region 43) 40 has a contact hole (bit line contact). , Source line contact portion).

As described above, according to the NAND flash memory and the method of manufacturing the same according to the second embodiment of the present invention, each transistor (memory cell and select gate transistor) in the NAND cell unit is The peak of the impurity concentration profile of the diffusion layer is set at a position deeper than the surface of the silicon substrate (specifically, at a position deeper than 0.04 μm). Also,
On the surface of the silicon substrate on the diffusion layer of each transistor, a high resistance region of a conductivity type opposite to that of the diffusion layer of each transistor is formed.

Therefore, for example, a lot of damage occurs in the silicon nitride film 60 in FIG. 28 due to the influence of the manufacturing process and the like, and even if charges (electrons) are trapped by this damage, the problem ( Conductance G
variation in read speed due to deterioration of m)
Rarely occurs.

In particular, the surface breakdown voltage of the source-side select gate transistor becomes very problematic when boosting the channel potential in the write-inhibited cell (“1” -write cell). That is, the write inhibit potential (“1”)
Since the channel potential of the write cell is generated by the self-boost operation, if the surface withstand voltage is low, a surface leak current occurs, and the channel potential cannot be sufficiently increased.

In the present invention, the peaks of the concentration profiles of the diffusion layers of the memory cell and the select gate transistor are both provided inside the silicon substrate, and the surface portion (excluding the channel portion) of the silicon substrate has the diffusion profile of each transistor. Since the high-resistance region has a conductivity type opposite to that of the layer, the surface breakdown voltage of the select gate transistor is particularly improved, and the channel potential of the write-inhibited cell can be sufficiently increased. That is, according to the present invention, a write inhibit potential can be stably generated, so that erroneous write can be prevented.

In addition, according to the present invention, the influence of hot carriers generated near the surface of the semiconductor substrate is reduced,
The deterioration of the conductance Gm due to the read operation of the NAND cell is also eliminated.

[C] Next, a NAND flash memory according to a third embodiment of the present invention will be described.

FIG. 29 schematically shows the device structure of a NAND flash memory according to the third embodiment of the present invention.

The device of this example is a modification of the second embodiment described above, and includes control gate electrodes CG0 to CG
15. The feature is that so-called sidewall spacers 80 are formed on the side walls of the select gate electrodes SGS, SGD and the floating gate electrode FG. The side wall spacer 80 is made of, for example, a silicon nitride film (SiN), a silicon oxide film (SiO ₂ ), TEOS
It can be composed of a film or a laminated film of these.

The side wall spacer 80 functions as a mask at the time of ion implantation (boron ion implantation) for forming the P-type diffusion layers 70, 70a, 70b. In this case, the width of the P-type diffusion layers 70, 70a, 70b is smaller than the width of the N-type diffusion layers 61, 61a, 61b.

In the device according to the present embodiment, the same effect as in the device according to the above-described second embodiment can be obtained.

Hereinafter, the diffusion layers 61, 61a, 61b, 70, 70 in the case where the sidewall spacers 80 are employed.
The procedure for forming a and 70b will be described with reference to FIG.
A brief description will be given.

First, control gate electrodes CG0-CG
After forming G15, select gate electrodes SGS and SGD, and floating gate electrode FG, thermal oxidation is performed at a temperature of 1000 ° C. in, for example, an oxygen atmosphere. Further, arsenic (As) is converted into, for example, an acceleration energy of about 30 [Ke
V] and a dose amount of about 5 × 10 ¹³ [cm ⁻² ].
Implanted into a silicon substrate (P-type well region 43) 40,
N-type diffusion layers 61, 61a and 61b are formed.

Next, a silicon nitride film (SiN) is formed to a thickness of about 30 nm by using, for example, the LPCVD method. Thereafter, heat treatment is performed. However, this heat treatment may be omitted. Then, the silicon nitride film is etched by RIE to form a sidewall spacer 80. Here, the sidewall spacer 80 may be formed of an insulating film such as a TEOS film instead of the silicon nitride film.

Thereafter, boron (B) is added, for example, at an acceleration energy of about 10 [KeV] and a dose of about 1 × 10
^Under the condition of ¹³ [cm ⁻² ], it is implanted into the silicon substrate (P-type well region 43) 40 and the P-type diffusion layers 70, 70 a,
70b is formed.

Incidentally, the diffusion layers 61, 61a, 61b, 7
Except for the method of forming 0, 70a, and 70b, the method is the same as the manufacturing method according to the above-described second embodiment, and a detailed description thereof will be omitted.

[D] Next, a NAND flash memory according to a fourth embodiment of the present invention will be described.

The N according to the second and third embodiments described above
In the AND flash memory, a P-type diffusion layer is formed on an N-type diffusion layer of an N-channel MOS transistor (memory cell and select gate transistor) in a NAND cell unit. Therefore, the path of the current flowing through the N-channel MOS transistor (excluding the channel portion) is set at a position sufficiently deeper than the surface of the silicon substrate (P-type well region), and the current flows through the surface of the silicon substrate excluding the channel portion. It does not flow.

On the other hand, in the NAND-type flash memory of this example, a high-concentration N-type diffusion layer is formed inside the silicon substrate, and the main path (excluding the channel portion) of the current (charge) flowing through the N-channel MOS transistor is formed. ) Is set inside the silicon substrate and a low-concentration N-type diffusion layer is formed on the surface of the silicon substrate to increase the value of the ON current of the N-channel MOS transistor. The current also flows.

FIG. 30 schematically shows the device structure of a NAND flash memory according to the fourth embodiment of the present invention.

P-type silicon substrate (may be a well) 12
On the top, a NAND cell composed of a plurality of (16 in this example) memory cells M01,..., M151 connected in series, and two NAND cells connected one at each end of the NAND cell
Two select gate transistors S11 and S21 are formed.

Each of the memory cells M01,..., M151 has a floating gate electrode FG and control gate electrodes CG0,. The select gate transistors S11, S21 are connected to the gate electrodes SGS, S
GD.

The memory cells M01,..., M151 and the N-type diffusion layers (source / drain) 13, 13b, 13c of the select gate transistors S11, S21 are similar to the devices according to the above-described first embodiment. The peak of the concentration profile of the type impurity is set inside silicon substrate 12. That is, the lowest resistance portions of the diffusion layers 13, 13 b, and 13 c are not provided on the surface of the silicon substrate 12 but are provided at positions deeper by a certain distance from the surface of the silicon substrate 12.

The specific position of the peak of the concentration profile of the N-type impurity in the N-type diffusion layers 13, 13b, and 13c is zero from the surface of the silicon substrate 12 as in the device according to the above-described first embodiment. It is a position deeper than .04 μm (for example, a position of about 0.1 μm). In this example, the peak of the concentration profile is set at a position deeper than the surface of the silicon substrate 12 by 0.04 μm or more.
Determined from the viewpoint of hot carrier resistance. However, as in this example, the peak of the profile is
If it is set at a position of 0.04 μm or more and 0.2 μm or less from the surface, most devices can be handled.

A feature of the device of this example is that the N-type diffusion layer 1
N-type diffusion layers 13, 13b, 13c are provided on the surface of silicon substrate (or wells) 12 on 3, 13, b, 13c.
Is that N-type diffusion layers 31, 31b, and 31c formed of an N-type impurity having a lower concentration than the concentration of the N-type impurity constituting are formed.

In this example, the N-type diffusion layers 13, 13b, 13
n-type diffusion layers 31 and 3
1b and 31c are formed, the N-type diffusion layer 13,
The current also flows on the surface of the silicon substrate 12 on 13b and 13c. However, the N-type diffusion layers 31, 31b, 31c
Is of low concentration, the main path of the current flowing through the N-channel MOS transistor (memory cell and select gate transistor) is inside the silicon substrate 12, ie, N
The mold diffusion layers 13, 13b and 13c are formed.

That is, according to this example, the main path of the current flowing through the transistors (excluding the channel portion) in the NAND cell unit is located at a position sufficiently deep with respect to the surface of the silicon substrate 12 (at a position of 0.04 μm or more). ), And the reading speed (resistance value of the diffusion layers 13, 13b, 13c) is not affected by the film quality of the insulating film (for example, nitride film) on the N-type diffusion layers 13, 13b, 13c.

Further, in this example, since the current also flows through the surface of the silicon substrate 12, that is, the N-type diffusion layers 31, 31b and 31c, the ON current of the MOS transistor can be increased.

Diffusion layers 13, 1 in NAND cell unit
Among the diffusion layers 13b and 13c, the contact portions (plugs) 16b and 16c and the diffusion layers 13b are disposed on the diffusion layer 13b disposed closest to the drain (bit line) and the diffusion layer 13b disposed closest to the source (source line). N-type auxiliary diffusion layers 1b and 13c are electrically connected to each other with a low resistance and reliably.
3 'and 13c' are arranged.

In this example, as described above, the N-type diffusion layers 31, 13b, 13c are provided on the N-type diffusion layers 31, 13b, 13c.
31c, the N-type auxiliary diffusion layers 13 ', 13'
c ′ is formed in the N-type diffusion layers 31b and 31c.

FIG. 31 shows one of the memory cells of FIG. FIGS. 32A and 32B show the concentration profiles of the cross sections perpendicular to the diffusion layers of the memory cell of FIG.

FIG. 32A shows that the high-concentration N-type diffusion layer serving as a main current path is made of arsenic (As), and the low-concentration N-type diffusion layer on the high-concentration N-type diffusion layer is also arsenic (As). 6 shows a density profile in the case of the configuration of As). In this example, the peak of the concentration profile of the N-type impurity of the high-concentration N-type diffusion layer is set at a position deeper than the surface of the silicon substrate by 0.04 μm or more (for example, at a position of about 0.1 μm). Further, the peak of the concentration profile of the N-type impurity in the low-concentration N-type diffusion layer is set substantially at the surface of the silicon substrate, specifically, at a position less than 0.04 μm from the surface of the silicon substrate.

FIG. 32B shows that the high-concentration N-type diffusion layer serving as a main current path is made of arsenic (As), and the low-concentration N-type diffusion layer on the high-concentration N-type diffusion layer is phosphorus ( 3 shows a density profile in the case of constituting from FIG. Also in this example, the peak of the concentration profile of the N-type impurity of the high-concentration N-type diffusion layer is set at a position deeper than the surface of the silicon substrate by 0.04 μm or more (for example, a position at about 0.1 μm). The peak of the concentration profile of the N-type impurity in the low-concentration N-type diffusion layer is set substantially at the surface of the silicon substrate, that is, at a position less than 0.04 μm from the surface of the silicon substrate.

According to such a memory cell structure, NA
The main path of the current in the ND cell unit is the surface of the silicon substrate 12 in the channel portion of the transistor (memory cell and select gate transistor),
Diffusion layer 13 arranged between channels of each transistor
Is inside the silicon substrate 12. Therefore, the resistance value of the diffusion layer 13 (the part that determines the resistance value is inside the silicon substrate 12) is hardly affected by the electric charge trapped at the interface between the insulating film on the diffusion layer 13 and the silicon substrate 12. Even if the memory cell is miniaturized, it is possible to suppress the occurrence of the variation in the ON current (cell current) or the variation in the reading speed of the memory cell.

In this example, since the low-concentration N-type diffusion layer is formed on the high-concentration N-type diffusion layer serving as the main current path,
Silicon substrate 1 on high concentration N-type diffusion layer (main path of current)
A current also flows on the surface of No. 2, that is, on the low-concentration N-type diffusion layer. Therefore, the ON current of the MOS transistor can be increased, and data can be read quickly and accurately.

In the above-described example, the memory cell and the select gate transistor are constituted by N-channel MOS transistors. However, the present invention can of course be applied to the case constituted by P-channel MOS transistors. It is.

Next, N according to the fourth embodiment of the present invention will be described.
A method for manufacturing an AND flash memory will be described.

First, the control gate electrodes CG0 to CG15 and the select gate electrode SGS are manufactured by using the same manufacturing method as that of the first embodiment.
(Top), SGD (top), floating gate electrode FG
Then, the select gate electrodes SGS (lower) and SGD (lower) are completed (see the description of FIGS. 5 to 16).

Next, as shown in FIG. 33, using the silicon nitride film 58 (control gate electrode and select gate electrode) as a mask, N-type impurities (for example, phosphorus, arsenic, etc.) , Etc.) to form N-type diffusion layers 71, 71a, 71b. The ion implantation conditions at this time are as follows:
71a and 71b are silicon substrates (P-type well region 43)
The conditions are such that they are formed on the surface of the forty.

For example, when phosphorus (P) is used as an impurity, the condition of ion implantation is that the acceleration energy is 15 [Ke
V], the dose is set to 1.0 × 10 ¹³ cm ⁻² ,
When arsenic (As) is used as an impurity, conditions for ion implantation are set to an acceleration energy of 30 [KeV] and a dose of 1.0 × 10 ¹³ cm ⁻² .

Thereafter, using the silicon nitride film 58 (control gate electrode and select gate electrode) as a mask, an N-type impurity (for example, arsenic) is ion-implanted into the P-type well region 43 by self-alignment, and the N-type diffusion is performed. Layer 6
1, 61a and 61b are formed. The diffusion layer 61a
Is the source of the NAND cell unit, and the diffusion layer 61
b becomes the drain of the NAND cell unit.

Here, the N-type diffusion layers 61, 61a, 61b
Is such that the peak of the concentration profile of the N-type impurity (As) is located inside the silicon substrate (P-type well region 43) 40, specifically, at a position deeper than the surface of the silicon substrate 40 by 0.04 μm or more. It is formed. For example, the peak of the concentration profile of the N-type impurity (As) is about 0.1
It is set at a position deeper by μm.

For this purpose, for example, the conditions for arsenic (As) ion implantation may be set to an acceleration energy of 30 [KeV] and a dose of 5.0 × 10 ¹³ cm ⁻² . By setting such conditions, an arsenic concentration profile (see FIG. 26) having a peak at a position deeper than 0.04 μm from the surface of the silicon substrate 40 can be easily obtained.

In this example, the low concentration N-type diffusion layers 71, 71a, 71b are formed on the surface of the silicon substrate 40 between the channels of the transistors in the NAND cell unit. Therefore, the path of the electrons from the source line to the bit line (current path; however, the direction of the current is opposite to the moving direction of the electrons) is the surface of the silicon substrate 40 in the channel portion of each transistor. The portion between the channel portions of the transistor is the inside (main path) of the silicon substrate 40 and the surface portion.

Thus, the N-type diffusion layers 61, 61a, 6
The resistance value of 1b is hardly affected by the charge trapped in the insulating film (especially, the silicon nitride film) formed on the silicon substrate 40, and the variation in the conductance Gm and the variation in the reading speed are eliminated. as a result,
According to the present invention, a stable read operation can be ensured, and a highly reliable device can be provided.

In the above example, the low-concentration N-type diffusion layer 7
After the formation of the high-concentration N-type diffusion layers 61, 61a and 61b after the formation of
After forming the type diffusion layers 61, 61a and 61b, the low concentration N-type diffusion layers 71, 71a and 71b may be formed.

The low-concentration N-type diffusion layers 71, 71a, 7
Before forming the 1b and the high-concentration N-type diffusion layers 61, 61a, 61b (before ion implantation), for example, at a temperature of about 1000 ° C.
Of the control gate electrodes CG0 to CG
15. A silicon oxide film may be formed on the surfaces of the select gate electrodes SGS, SGD and the floating gate electrode FG, and the surface of the silicon substrate (P-type well region 43) 40, respectively.

Thereafter, a NAND flash memory as shown in FIG. 34 is completed by using the same manufacturing method as that of the first embodiment described above (see the description of FIGS. 19 to 21). .

In this example, the N-type diffusion layer 61a 'is also formed on the diffusion layer 61a on the most source side (source line side) and the diffusion layer 61b on the most drain side (bit line side) of the NAND cell unit. , 61b 'are formed.

The N-type diffusion layers 61 a ′ and 61 b ′ are formed when the diffusion layers 61, 61 a, 61 b, 71, 71 a and 71 b are formed, or when the contact holes (bit line contacts) with the silicon substrate (P-type well region 43) 40 are formed. , Source line contact portion).

As described above, according to the NAND flash memory and the method of manufacturing the same according to the fourth embodiment of the present invention, each transistor (memory cell and select gate transistor) in the NAND cell unit is The peak of the impurity concentration profile of the diffusion layer is set at a position deeper than the surface of the silicon substrate (specifically, at a position deeper than 0.04 μm).

Therefore, for example, a lot of damage occurs in the silicon nitride film 60 of FIG. 34 due to the influence of the manufacturing process and the like, and even if charges (electrons) are trapped in this damage, the influence ( The variation of the ON current of the memory cell) is hardly received.

According to the present invention, the peaks of the concentration profiles of the memory cell and the diffusion layer of the select gate transistor are both provided inside the silicon substrate, and
The surface portion (excluding the channel portion) of the silicon substrate is a low-concentration region of the same conductivity type as that of the diffusion layer of each transistor. In other words, according to the present invention, since a current flows through the buried diffusion layer and also flows on the surface of the silicon substrate on the buried diffusion layer, the value of the on-current can be increased, and the reading speed can be increased. Stable reading can be achieved. In particular, the surface breakdown voltage of the select gate transistor is improved, and the channel potential of the write-inhibited cell can be sufficiently increased. That is, according to the present invention, the write inhibit potential can be stably generated,
Erroneous writing can be prevented.

[E] Next, a NAND flash memory according to a fifth embodiment of the present invention will be described.

FIG. 35 schematically shows a device structure of a NAND flash memory according to the fifth embodiment of the present invention.

The device of this example is a modification of the above-described fourth embodiment, and includes control gate electrodes CG0 to CG
15. The feature is that so-called sidewall spacers 81 are formed on the side walls of the select gate electrodes SGS, SGD and the floating gate electrode FG. The side wall spacer 81 is made of, for example, a silicon nitride film (SiN), a silicon oxide film (SiO ₂ ), TEOS
It can be composed of a film or a laminated film of these.

The sidewall spacer 81 functions as a mask at the time of ion implantation (arsenic ion implantation) for forming the N-type diffusion layers 71, 71a, 71b. In this case, the width of the N-type diffusion layers 71, 71a, 71b is smaller than the width of the N-type diffusion layers 61, 61a, 61b.

In the device according to the present embodiment, the same effect as in the device according to the above-described second embodiment can be obtained.

In this example, the surface of the silicon substrate 40 between the channels of the transistors (memory cells and select gate transistors) in the NAND cell unit has the same conductivity type as the N-type diffusion layers 61, 61a and 61b. N-type diffusion layers 71, 71a, and 71b. That is,
When the sidewall spacer 81 is adopted, the N-type diffusion layers 71, 71a, 71b are
Is separated from the gate edge by the thickness of.

Therefore, the N-type diffusion layers 71, 71a, 71b
Even if the impurity concentration of the N-type impurity in the inside is set to a relatively high value (it is necessary to be lower than the impurity concentration of the diffusion layers 61, 61a, 61b), the diffusion layers 71, 71a, 7
Since the surface withstand voltage of 1b does not deteriorate, a highly reliable device that has a high reading speed and does not cause erroneous writing in a write-inhibited cell can be provided.

Hereinafter, the diffusion layers 61, 61a, 61b, 71, 71 when the sidewall spacers 81 are employed.
The procedure for forming a and 71b will be described with reference to FIG.
A brief description will be given.

First, control gate electrodes CG0-CG
After forming G15, select gate electrodes SGS and SGD, and floating gate electrode FG, thermal oxidation is performed at a temperature of 1000 ° C. in, for example, an oxygen atmosphere. Further, arsenic (As) is converted into, for example, an acceleration energy of about 30 [Ke
V] and a dose amount of about 5 × 10 ¹³ [cm ⁻² ].
Implanted into a silicon substrate (P-type well region 43) 40,
N-type diffusion layers 61, 61a and 61b are formed.

Next, a silicon nitride film (SiN) is formed to a thickness of about 30 nm by using, for example, the LPCVD method. Thereafter, heat treatment is performed. However, this heat treatment may be omitted. Then, the silicon nitride film is etched by RIE to form a sidewall spacer 81. Here, the sidewall spacer 81 may be formed of an insulating film such as a TEOS film instead of the silicon nitride film.

Thereafter, arsenic (As) is again converted to, for example,
Acceleration energy about 30 [KeV], dose about 2 × 10
^Under the condition of ¹³ [cm ⁻² ], it is implanted into a silicon substrate (P-type well region 43) 40 and N-type diffusion layers 71
71b is formed.

Incidentally, the diffusion layers 61, 61a, 61b, 7
Except for the method of forming 1, 71a, 71b, it is the same as the manufacturing method according to the above-described fourth embodiment, and a detailed description thereof will be omitted.

FIG. 36 shows electrons (current) flowing in the NAND cell unit when the device structure of FIG. 35 is adopted.
Is schematically shown.

Most of the electrons are supplied to the source line contact portion 1
6c flows to the bit line contact portion 16b via the buried diffusion layer and the inversion layer (channel) of each MOS transistor. Most of the electrons flow between the channels of the MOS transistors through the buried diffusion layer, but part of the electrons flow through the low concentration diffusion layer formed on the surface of the silicon substrate. The low concentration diffusion layer is separated from the edge portions of the gate electrodes SGS and SGD of the select gate transistor and the edge portion of the floating gate electrode FG of the memory cell by a fixed distance due to the sidewall spacer 81. Of the surface withstand voltage can be prevented.

[F] Next, a nonvolatile semiconductor memory according to a sixth embodiment of the present invention will be described.

In the above-described first to fifth embodiments, the read operation is disturbed (variation in read speed) mainly due to charges trapped in the insulating film on the diffusion layer of the transistor (memory cell, select gate transistor, etc.). In this case, a diffusion layer is formed inside the silicon substrate (buried diffusion layer) so that the current path of the tonlangis except for the channel portion is not inside the silicon substrate but inside the silicon substrate.

On the other hand, this embodiment mainly proposes a device structure which does not hinder read operation (variation in read speed, etc.) even when charges are trapped in the gate insulating film. .

FIG. 37 shows a memory cell of a nonvolatile semiconductor memory according to the sixth embodiment of the present invention.

This memory cell has a so-called buried channel structure.

An N-type buried layer 102 is arranged on a P-type silicon substrate 101. A floating gate electrode 104 is arranged on the N-type buried layer 102 via a gate insulating film (thermal oxide film) 103. The floating gate electrode 104 is made of, for example, polysilicon containing a P-type impurity.

On the floating gate electrode 104,
For example, an insulating film (so-called ONO) having a structure in which silicon oxide, silicon nitride, and silicon oxide are sequentially stacked
A film 105 is disposed. Further, on the insulating film 105,
A control gate electrode 106 is provided. The control gate electrode 106 is made of, for example, polysilicon containing an N-type impurity.

On both sides of the floating gate electrode 104 and the control gate electrode 106, N-type diffusion layers (source / drain) 107 and 108 are arranged. That is, the N-type buried layer 102 is disposed between the N-type diffusion layers 107 and 108, and the N-type buried layer 102 forms a buried channel of the memory cell.

In the above example, the structure of the memory cell has been described. However, for example, in the case of a memory having a select gate transistor (such as a NAND flash memory), the present invention can be applied to a select gate transistor.

However, when the gate insulating film of the memory cell also functions as a so-called tunnel insulating film,
Charges are easily trapped in the gate insulating film of the memory cell,
Therefore, it is most effective to apply the structure of the present invention to a memory cell.

As described above, the present invention is characterized in that a memory cell having a stack gate structure has a buried channel structure. In this case, as shown in FIG.
When reading is performed in a voltage relationship where the cell current is saturated, the depletion layer 10
9a and 109b are generated, and the cell current flows not inside the surface of the N-type buried layer 102 but inside it.

Therefore, even if scattering occurs at the interface between the N-type buried layer 102 and the gate insulating film 103, and trapping of electric charges in the gate insulating film 103, such influences are less likely to occur, and the cell current increases. can do.

In the above embodiment, the case where control gate electrode 106 is made of polysilicon has been described. However, control gate electrode 106 has a structure in which silicide such as WSi and polysilicon are stacked. You may. Further, as shown in FIG. 39, the conductivity type of control gate electrode 106 is not limited to N-type, but may be P-type.

[G] Next, a nonvolatile semiconductor memory according to the seventh embodiment of the present invention will be described.

This embodiment is a modification of the above-described sixth embodiment. That is, the memory cell of the sixth embodiment is an N-channel type, but the memory cell of the present embodiment is a P-channel type.

FIG. 40 shows a memory cell of a nonvolatile semiconductor memory according to the seventh embodiment of the present invention.

This memory cell is a P-channel MOS transistor having a buried channel structure.

On N-type silicon substrate 201, P-type buried layer 202 is arranged. A floating gate electrode 204 is arranged on the P-type buried layer 202 via a gate insulating film (thermal oxide film) 203. The floating gate electrode 204 is made of, for example, polysilicon containing an N-type impurity.

On the floating gate electrode 204,
For example, an insulating film (so-called ONO) having a structure in which silicon oxide, silicon nitride, and silicon oxide are sequentially stacked
A film 205 is disposed. Further, on the insulating film 205,
A control gate electrode 206 is provided. The control gate electrode 206 is made of, for example, polysilicon containing an N-type impurity.

On both sides of floating gate electrode 204 and control gate electrode 206, P-type diffusion layers (source / drain) 207, 208 are arranged. That is, the P-type buried layer 202 is disposed between the P-type diffusion layers 207 and 208, and the P-type buried layer 202 forms a buried channel of the memory cell.

In the above example, the structure of the memory cell has been described. However, for example, in the case of a memory having a select gate transistor (such as a NAND flash memory), the present invention is naturally applicable to a select gate transistor.

However, when the gate insulating film of the memory cell also functions as a so-called tunnel insulating film,
Charges are easily trapped in the gate insulating film of the memory cell,
Therefore, it is most effective to apply the structure of the present invention to a memory cell.

As described above, the present invention is characterized in that a memory cell having a stack gate structure has a buried channel structure. In this case, as shown in FIG.
When reading is performed in a voltage relationship where the cell current becomes saturated, the depletion layer 20
9a and 209b are generated, and the cell current flows not inside the surface of the P-type buried layer 202 but inside it.

Therefore, even if scattering occurs at the interface between the P-type buried layer 202 and the gate insulating film 203 and charge trapping in the gate insulating film 203 occurs, the influence of the scattering becomes less and the cell current increases. can do.

In the above embodiment, the case where control gate electrode 206 is made of polysilicon has been described. However, control gate electrode 206 has a structure in which silicide such as WSi and polysilicon are stacked. You may. Further, as shown in FIG. 42, the conductivity type of control gate electrode 206 is not limited to N-type, but may be P-type.

[H] Next, a nonvolatile semiconductor memory according to an eighth embodiment of the present invention will be described.

This embodiment is a modification of the above-described sixth embodiment. That is, in the memory cell of the sixth embodiment, the conductivity type (N type) of the buried layer and the conductivity type (P type) of the floating gate electrode are opposite to each other. Then, the conductivity type (N type) of the buried layer and the conductivity type (N
Types) are the same as each other.

FIG. 43 shows a memory cell of a nonvolatile semiconductor memory according to the eighth embodiment of the present invention.

This memory cell is an N-channel MOS transistor having a buried channel structure.

On P-type silicon substrate 101, N-type buried layer 102 is arranged. A floating gate electrode 104 is arranged on the N-type buried layer 102 via a gate insulating film (thermal oxide film) 103. The floating gate electrode 104 is made of, for example, polysilicon containing an N-type impurity.

On the floating gate electrode 104,
For example, an insulating film (so-called ONO) having a structure in which silicon oxide, silicon nitride, and silicon oxide are sequentially stacked
A film 105 is disposed. Further, on the insulating film 105,
A control gate electrode 106 is provided. The control gate electrode 106 is made of, for example, polysilicon containing an N-type impurity.

On both sides of floating gate electrode 104 and control gate electrode 106, N-type diffusion layers (source / drain) 107 and 108 are arranged. That is, the N-type buried layer 102 is disposed between the N-type diffusion layers 107 and 108, and the N-type buried layer 102 forms a buried channel of the memory cell.

In the above example, the structure of the memory cell is shown. However, in the case of a memory having a select gate transistor (such as a NAND flash memory), the present invention can be applied to a select gate transistor.

However, when the gate insulating film of the memory cell also functions as a so-called tunnel insulating film,
Charges are easily trapped in the gate insulating film of the memory cell,
Therefore, it is most effective to apply the structure of the present invention to a memory cell.

As described above, the present invention is characterized in that a memory cell having a stack gate structure has a buried channel structure, and both a buried layer and a floating gate electrode are set to N-type. In this case, FIG.
As shown in FIG. 7, when reading is performed with a voltage relationship such that the floating gate electrode 104 is negative with respect to the silicon substrate (ground potential) 101, depletion layers 109a and 109b are generated on the surface and the bottom surface of the N-type buried layer 102. However, the cell current flows not inside the surface of the N-type buried layer 102 but inside it.

Therefore, even if scattering occurs at the interface between the N-type buried layer 102 and the gate insulating film 103 and charge trapping in the gate insulating film 103 occurs, the influence of such scattering is reduced, and the cell current increases. can do.

In the above embodiment, the case where control gate electrode 106 is made of polysilicon has been described. However, control gate electrode 106 has a structure in which silicide such as WSi and polysilicon are stacked. You may. Further, as shown in FIG. 45, the conductivity type of control gate electrode 106 is not limited to N-type, but may be P-type.

[I] Next, a nonvolatile semiconductor memory according to a ninth embodiment of the present invention will be described.

This embodiment is a modification of the above-described seventh embodiment. That is, in the memory cell of the seventh embodiment, the conductivity type (P type) of the buried layer and the conductivity type (N type) of the floating gate electrode are opposite to each other. Then, the conductivity type (P type) of the buried layer and the conductivity type (P type) of the floating gate electrode
Types) are the same as each other.

FIG. 46 shows a memory cell of a nonvolatile semiconductor memory according to the ninth embodiment of the present invention.

This memory cell is a P-channel MOS transistor having a buried channel structure.

On N type silicon substrate 201, P type buried layer 202 is arranged. A floating gate electrode 204 is arranged on the P-type buried layer 202 via a gate insulating film (thermal oxide film) 203. The floating gate electrode 204 is made of, for example, polysilicon containing a P-type impurity.

On the floating gate electrode 204,
For example, an insulating film (so-called ONO) having a structure in which silicon oxide, silicon nitride, and silicon oxide are sequentially stacked
A film 205 is disposed. Further, on the insulating film 205,
A control gate electrode 206 is provided. The control gate electrode 206 is made of, for example, polysilicon containing an N-type impurity.

On both sides of the floating gate electrode 204 and the control gate electrode 206, P-type diffusion layers (source / drain) 207 and 208 are arranged. That is, the P-type buried layer 202 is disposed between the P-type diffusion layers 207 and 208, and the P-type buried layer 202 forms a buried channel of the memory cell.

In the above example, the structure of the memory cell has been described. However, in the case of a memory having a select gate transistor (such as a NAND flash memory), the present invention can be applied to a select gate transistor.

However, when the gate insulating film of the memory cell also functions as a so-called tunnel insulating film,
Charges are easily trapped in the gate insulating film of the memory cell,
Therefore, it is most effective to apply the structure of the present invention to a memory cell.

As described above, the present invention is characterized in that a memory cell having a stack gate structure has a buried channel structure. In this case, as shown in FIG.
When reading is performed with a voltage relationship such that the floating gate electrode 204 becomes positive with respect to the silicon substrate (ground potential) 201, the depletion layers 209a. 209b is generated, and the cell current flows through the inside of the P-type buried layer 202, not the surface.

Therefore, even if scattering at the interface between the P-type buried layer 202 and the gate insulating film 203 and trapping of charges in the gate insulating film 203 occur, they are less affected by them, and the cell current increases. can do.

In the above-described embodiment, the case where control gate electrode 206 is made of polysilicon has been described. However, control gate electrode 206 has a structure in which silicide such as WSi and polysilicon are stacked. You may. Further, as shown in FIG. 48, the conductivity type of control gate electrode 206 is not limited to N-type, but may be P-type.

[J] Next, a nonvolatile semiconductor memory according to the tenth embodiment of the present invention will be described.

FIG. 49 shows a NAND flash memory according to the tenth embodiment of the present invention.

The device of this example is characterized by the features (buried N-type diffusion layer + low-concentration N-type diffusion layer) of the device according to the fourth embodiment and the device according to the sixth or eighth embodiment. (Embedded channel structure).

That is, the low-concentration N-type diffusion layers 71 and 7 shown in FIG.
1a and 71b are all shared and a silicon substrate (P
When the N-type diffusion layer 71 is formed on the entire surface of the mold well region 43) 40, the device shown in FIG. 49 can be obtained.

According to such a structure, the current flowing in the NAND cell unit always takes the inside of the silicon substrate (P-type well region 43) 40 as the main path. It is possible to eliminate adverse effects (such as a decrease in reading speed and erroneous writing due to surface leak) due to charges trapped in a film or an insulating film over a diffusion layer.

[0354]

As described above, according to the present invention, first, with respect to the source / drain diffusion layers of the nonvolatile semiconductor memory, the concentration at the surface of the semiconductor substrate is reduced.
In addition, by setting the peak of the impurity concentration at a position sufficiently deep from the surface of the semiconductor substrate, the main part of the current path can be provided inside the semiconductor substrate. As a result, for example, the influence of hot carriers generated near the surface of the semiconductor substrate is reduced, and the conductance Gm due to the read operation of the NAND cell does not deteriorate.

In a NAND flash memory in which data is written by the self-boost method, the source / drain diffusion layers of the select gate transistor have the above-described structure. The surface withstand voltage of the transistor can be sufficiently ensured, and leakage current at the time of writing or reading can be suppressed.

Second, in particular, with respect to a memory cell having a stack gate structure, embedding of the conductivity type opposite to that of the semiconductor substrate (the same conductivity type as that of the source / drain diffusion layers) in the surface portion of the semiconductor substrate. A layer is formed, and the memory cell is a MOS transistor having a so-called buried channel structure. Thus, at the time of data reading, the cell current of the memory cell flows inside the buried layer, so that it is less susceptible to the scattering of the interface between the semiconductor substrate and the gate insulating film and the charge trapped in the gate insulating film. Become. Therefore, a decrease in the read current can be prevented, and a stable read operation can be performed.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a memory cell in the device of FIG.

FIG. 3 is a view showing a concentration profile in a direction vertically crossing a diffusion layer of the memory cell of FIG. 2;

FIG. 4 is a sectional view showing a state of electrons flowing in the device of FIG. 1;

FIG. 5 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 7 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 9 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 11 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 12 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 13 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 14 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 15 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 16 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 17 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 18 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 19 is a sectional view showing one step of a manufacturing method according to the first embodiment of the present invention.

FIG. 20 is a sectional view showing one step of the manufacturing method according to the first embodiment of the present invention.

FIG. 21 is a sectional view showing one step of the manufacturing method according to the first embodiment of the present invention.

FIG. 22 is a diagram showing variations in cell current for the device of the present invention.

FIG. 23 is a diagram showing a relationship between the number of times of programming and a threshold variation for the device of the present invention.

FIG. 24 is a sectional view schematically showing a device according to a second embodiment of the present invention.

FIG. 25 is a sectional view showing a memory cell in the device of FIG. 24;

FIG. 26 is a diagram showing a concentration profile in a direction vertically crossing a diffusion layer of the memory cell of FIG. 25;

FIG. 27 is a sectional view showing one step of a manufacturing method according to the second embodiment of the present invention.

FIG. 28 is a sectional view showing one step of a manufacturing method according to the second embodiment of the present invention.

FIG. 29 is a sectional view showing a device according to a third embodiment of the present invention.

FIG. 30 is a sectional view schematically showing a device according to a fourth embodiment of the present invention.

FIG. 31 is a sectional view showing a memory cell in the device of FIG. 30;

FIG. 32 is a diagram showing a concentration profile in a direction vertically crossing a diffusion layer of the memory cell of FIG. 31;

FIG. 33 is a sectional view showing one step of a manufacturing method according to the fourth embodiment of the present invention.

FIG. 34 is a sectional view showing one step of a manufacturing method according to the fourth embodiment of the present invention.

FIG. 35 is a sectional view showing a device according to a fifth embodiment of the present invention.

FIG. 36 is a view showing a state of electrons flowing in the device of FIG. 35;

FIG. 37 is a sectional view showing a device according to a sixth embodiment of the present invention.

FIG. 38 is a sectional view showing a state when the device of FIG. 37 is turned on.

FIG. 39 is a sectional view showing a modification of the device of FIG. 37.

FIG. 40 is a sectional view showing a device according to a seventh embodiment of the present invention.

FIG. 41 is a sectional view showing a state when the device of FIG. 40 is turned on.

FIG. 42 is a sectional view showing a modification of the device in FIG. 40;

FIG. 43 is a sectional view showing a device according to an eighth embodiment of the present invention.

FIG. 44 is a sectional view showing a state when the device of FIG. 43 is turned on.

FIG. 45 is a sectional view showing a modification of the device of FIG. 43;

FIG. 46 is a sectional view showing a device according to a ninth embodiment of the present invention.

FIG. 47 is a sectional view showing a state when the device of FIG. 46 is turned on.

FIG. 48 is a sectional view showing a modification of the device in FIG. 46.

FIG. 49 is a sectional view showing a device according to a tenth embodiment of the present invention.

FIG. 50 is a circuit diagram showing a memory cell array of the NAND flash memory.

FIG. 51 is a circuit diagram showing a part of the memory cell array of FIG. 50;

FIG. 52 is a view showing variation in sheet resistance of a diffusion layer of a conventional device.

FIG. 53 is a diagram showing a variation in cell current of a conventional device.

FIG. 54 is a cross-sectional view showing the structure of a conventional memory cell.

FIG. 55 is a diagram showing capacitance generated in a memory cell;

FIG. 56 is a plan view of a conventional NAND flash memory.

FIG. 57 is a sectional view taken along the line LVII-LVII of FIG. 56;

FIG. 58 is a sectional view taken along the line LVIII-LVIII in FIG. 56;

FIG. 59 is a view showing a modification of the device shown in FIGS. 56 to 58;

FIG. 60 is a view showing a modification of the device shown in FIGS. 56 to 58;

FIG. 61 is a diagram showing the timing of a signal applied to a memory cell array at the time of writing.

FIG. 62 is a diagram showing a relationship between a transfer potential and a threshold change at the time of writing.

FIG. 63 is a diagram showing a relationship between the number of times of programming and a threshold variation for a conventional device.

FIG. 64 is a diagram showing a potential relationship during local self-boost.

[Explanation of symbols]

3a: element isolation oxide film, 4: gate insulating film, 5: floating gate electrode, 6, 54: insulating film (ONO)
7): control gate electrode; 8, 62: interlayer insulating film; 9: bit line; 10, 40: P-type silicon substrate; 11, 42: N-type well region; 12, 43: P-type well region; , 13b, 13b ', 13c, 13c': N-type diffusion layer, 14: Bit line contact portion, 15: Source line contact portion, 16a, 16b: Contact plug, 17a: Intermediate layer, 41, 41a, 47, 49, 59, 64: silicon oxide film, 45, 50, 55, 56: polysilicon film, 46, 51, 52, 58, 60: silicon nitride film, 57: tungsten silicide film, 61, 61a, 61a ', 61b, 61b ': Diffusion layer, 65A, 65B, 68: barrier metal, 66A, 66B: tungsten film, 69: metal film, CG0,... CG15: Lead wires (control gate line), SGD, SGS: select gate line, BL1, BL2: the bit line, M01, ··· M151, M02, ··· M152:
Memory cells, S11, S12, S21, S22: select gate transistors.

Continued on the front page F term (reference) 5F001 AA01 AB08 AC02 5F083 EP02 EP23 EP62 EP67 GA15 GA21 JA36 JA39 NA01 PR03 PR09 PR12 PR21 PR36 PR40 5F101 BA01 BB05 BC02

Claims (32)

[Claims] 1. A NAND cell comprising a plurality of memory cells arranged in series in a surface region of a semiconductor substrate of a first conductivity type and connected in series, and connected to the NAND cell arranged in a surface region of the semiconductor substrate. Wherein the peak of the concentration profile of the first impurity forming the plurality of memory cells and the source / drain diffusion layers of the second conductivity type of the select gate transistor is from the surface of the semiconductor substrate. A non-volatile semiconductor memory set at a position of 0.04 μm or more. 2. The method according to claim 1, wherein the plurality of memory cells and the source / drain diffusion layers of the select gate transistor are provided on:
2. The nonvolatile semiconductor memory according to claim 1, wherein a nitride film is disposed. 3. The peak of the concentration profile of the first impurity constituting the source / drain diffusion layers of the plurality of memory cells and the select gate transistor is set at a position of 0.2 μm or less from the surface of the semiconductor substrate. The nonvolatile semiconductor memory according to claim 1, wherein 4. The non-volatile memory according to claim 1, wherein the peak value of the concentration profile of the first impurity is at least twice as large as the concentration value of the concentration profile of the first impurity on the surface of the semiconductor substrate. Semiconductor memory. 5. The method according to claim 1, wherein a concentration of the second impurity of the first conductivity type between the plurality of memory cells and a channel portion of the select gate transistor is higher than a concentration of the second impurity in the channel portion. Claim 1
The nonvolatile semiconductor memory according to any one of the preceding claims. 6. A concentration of the concentration profile of the first impurity at a surface of the semiconductor substrate is higher than a surface concentration of a second impurity of a first conductivity type between the plurality of memory cells and a channel portion of the select gate transistor. 2. The non-volatile semiconductor memory according to claim 1, wherein said non-volatile semiconductor memory is also low. 7. The method according to claim 7, wherein the plurality of memory cells and the source / drain diffusion layers of the select gate transistor are provided
2. The nonvolatile semiconductor memory according to claim 1, wherein a diffusion layer of a first conductivity type is disposed. 8. A second conductive layer comprising the first conductive type diffusion layer.
8. The nonvolatile semiconductor memory according to claim 7, wherein the peak of the impurity concentration profile is set at a position less than 0.04 [mu] m from the surface of the semiconductor substrate. 9. The nonvolatile semiconductor device according to claim 7, wherein the width of the first conductivity type diffusion layer in the channel length direction is smaller than the width of the source / drain diffusion layer in the channel length direction. memory. 10. A low-concentration diffusion layer of a second conductivity type having a lower concentration than that of the source / drain diffusion layer is disposed on the source / drain diffusion layers of the plurality of memory cells and the select gate transistor. The nonvolatile semiconductor memory according to claim 1, wherein: 11. The semiconductor device according to claim 10, wherein the peak of the concentration profile of the second impurity forming the low-concentration diffusion layer is set at a position less than 0.04 μm from the surface of the semiconductor substrate. Non-volatile semiconductor memory. 12. The concentration of the concentration profile of the second impurity at the surface of the semiconductor substrate is higher than the concentration of the third impurity of the first conductivity type between the plurality of memory cells and the channel portion of the select gate transistor. 12. The non-volatile semiconductor memory according to claim 11, which is high. 13. The nonvolatile semiconductor memory according to claim 10, wherein a width of said low concentration diffusion layer in a channel length direction is smaller than a width of said source / drain diffusion layer in said channel length direction. 14. Each of the plurality of memory cells has a charge storage layer and a control gate electrode on the charge storage layer, and two memory cells adjacent to each other have one source / drain diffusion layer. 2. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is shared. 15. An auxiliary diffusion layer of a second conductivity type is disposed in the semiconductor substrate on a source / drain diffusion layer on a contact portion side of the select gate transistor, and a concentration of an impurity forming the auxiliary diffusion layer is provided. 2. The nonvolatile semiconductor memory according to claim 1, wherein a peak of the profile is set at a position less than 0.04 [mu] m from a surface of the semiconductor substrate. 16. The semiconductor device according to claim 5, wherein the first impurity is arsenic, and the second impurity is boron.
Or the nonvolatile semiconductor memory according to 6 or 8. 17. The nonvolatile semiconductor memory according to claim 11, wherein said first and second impurities are both arsenic. 18. The semiconductor device according to claim 11, wherein the first impurity is arsenic, and the second impurity is phosphorus.
Or the nonvolatile semiconductor memory according to 12. 19. A self-boost writing method for boosting a channel potential of at least one selected memory cell and prohibiting writing to the selected one memory cell is applied to the plurality of memory cells. The nonvolatile semiconductor memory according to claim 1, wherein: 20. A NAND cell comprising a plurality of memory cells arranged in series on a surface region of a semiconductor substrate of a first conductivity type and connected in series, and connected to the NAND cell arranged on a surface region of the semiconductor substrate. A plurality of memory cells and a source / drain diffusion layer of the select gate transistor are embedded in the semiconductor substrate, and a surface of the semiconductor substrate on the source / drain diffusion layer is provided. A non-volatile semiconductor memory, wherein a diffusion layer of the first conductivity type is disposed in the portion. 21. A source / drain diffusion layer of a second conductivity type disposed in a semiconductor substrate of a first conductivity type, and a second conductivity type disposed in the semiconductor substrate between the source / drain diffusion layers. A non-volatile semiconductor memory comprising a buried channel structure, a charge storage layer disposed on the buried layer, and a control cell electrode disposed on the charge storage layer. 22. The charge storage layer is a floating gate electrode, and a gate insulating film having a function of a tunnel insulating film is disposed between the semiconductor substrate and the floating gate electrode. Item 22. The nonvolatile semiconductor memory according to item 21. 23. The nonvolatile semiconductor memory according to claim 22, wherein said floating gate electrode contains a first conductivity type impurity. 24. The nonvolatile semiconductor memory according to claim 22, wherein said floating gate electrode contains an impurity of a second conductivity type. 25. When the first conductivity type is P-type and the second conductivity type is N-type, the read operation is performed in a potential relationship where the potential of the floating gate electrode is negative. 25. The nonvolatile semiconductor memory according to claim 24, wherein: 26. When the first conductivity type is N-type and the second conductivity type is P-type, the read operation is performed with a potential relationship in which the potential of the floating gate electrode is positive. 25. The nonvolatile semiconductor memory according to claim 24, wherein: 27. The control gate electrode according to claim 1,
22. The nonvolatile semiconductor memory according to claim 21, which is of a conductivity type. 28. The control gate electrode comprising:
22. The nonvolatile semiconductor memory according to claim 21, which is of a conductivity type. 29. The nonvolatile semiconductor memory according to claim 21, wherein at the time of a read operation, data stored in said memory cell is read by detecting a current flowing inside said buried layer. 30. The nonvolatile semiconductor memory according to claim 21, wherein said memory cell is applied to a memory cell of a NAND flash memory. 31. The nonvolatile semiconductor memory according to claim 1, wherein each of said plurality of memory cells constituting said NAND cell is replaced with a memory cell having a buried channel structure according to claim 21. A nonvolatile semiconductor memory characterized by the above-mentioned. 32. The nonvolatile semiconductor memory according to claim 1, wherein the charge storage layer is a floating gate electrode or a nitride film disposed on the semiconductor substrate.