JP2011070444A - Programmable controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a programmable controller that prevents system activation time from increasing. <P>SOLUTION: The programmable controller includes a plurality of I/O units 3 and a CPU unit controlling the I/O units 3 individually, and is integrally assembled as the I/O units 3 are connected to the CPU unit one by one. Each of the I/O units 3 includes a signal line forming unit 9a that forms a signal line 9 to the CPU unit, and a signal output circuit 35 that outputs an initialization completion signal notifying that self-initialization is complete. The signal line 9 changes in state when the initialization completion signals are output from the signal output circuits 35 of all the I/O units 3. The CPU unit recognizes initialization of all the I/O units 3 upon detecting the change in state of the signal line 9. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a programmable controller.

  Conventionally, a programmable controller to which an I / O unit can be added has been provided. FIG. 7A shows a building block type programmable controller. Each power supply unit 1 and CPU unit 2 and a plurality (six in FIG. 7A) I / O units 3 are backplanes 5. Has been implemented. In this programmable controller, the system power generated by the power supply unit 1 is supplied to the CPU unit 2 and each I / O unit 3 via an internal bus provided in the backplane 5.

  FIG. 7B shows a stacking (stacked) type programmable controller, which includes one power supply unit 1 and one CPU unit 2, and a plurality (six in FIG. 7B) of I / O units 3. Consists of. Since this programmable controller does not include the backplane 5 as in the building block type described above, it is fixed by being connected to an adjacent unit, and the system power generated by the power supply unit 1 is also The power is supplied to the CPU unit 2 and each I / O unit 3 via the stack connector 6.

  In these programmable controllers, when all the I / O units 3 are initialized after the power is turned on, the CPU unit 2 recognizes each I / O unit 3 and each I / O unit 3 The communication program is started to execute the sequence program.

  Here, the apparatus shown in Patent Document 1 is an example of an apparatus that starts communication after all extension units are initialized, and in this apparatus, a plurality of extension units connected to the main unit are connected. Of these, initialization is sequentially performed from the most downstream side extension unit, and the upstream side extension unit is initialized by detecting an initialization completion signal from the downstream side extension unit. Finally, when the main unit detects the initialization completion signal from the most upstream expansion unit, the main unit determines that all the expansion units have been initialized and starts communication with each expansion unit. It is.

JP 2000-105521 A (paragraph [0057] -paragraph [0060] and FIGS. 10 and 11)

  In the apparatus shown in Patent Document 1 described above, when the communication between the main unit and each extension unit is started, the initialization of the extension unit is completed, but the extension unit on the upstream side as described above. Since the initialization is performed after detecting the initialization completion signal from the downstream expansion unit, the startup time increases cumulatively. As a result, the initialization of all the expansion units is completed and the system May take some time to start up. Here, the time until the system is started refers to the time until initialization of all the expansion units is completed and the CPU unit recognizes each expansion unit and starts communication.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a programmable controller that prevents an increase in system startup time.

  The invention of claim 1 is a programmable controller comprising one or more extension units and a CPU unit for controlling the extension units, wherein the one or more extension units are sequentially connected to the CPU unit. A signal line forming unit that forms a signal line to the unit, and a signal output circuit that outputs an initialization completion signal notifying that the initialization has been completed, and the signal line is a signal of all extension units When an initialization completion signal is output from the output circuit, the state changes, and the CPU unit recognizes that all the extension units have been initialized when detecting a change in the state of the signal line.

  In the invention of claim 2, the extension unit has a power supply line forming portion for forming a power supply line from the CPU unit, the signal line is pulled up to a predetermined control voltage, and the signal output circuit is formed of the signal line. The switch element is interposed between the power supply line forming section and the switch element is turned on when the power supplied from the power supply line forming section reaches a predetermined reference value, and the initialization of itself is completed. Then, it is turned off by a predetermined control signal, and the CPU unit recognizes that all the extension units are initialized when the switch elements of all the extension units are turned off and the signal line state changes to the high level. It is characterized by.

  According to the first aspect of the present invention, since each extension unit starts initialization individually when power is supplied, the startup time of the system is determined by the longest initialization time. Therefore, the system startup time can be prevented from increasing, and the signal line status change can be detected to confirm that all the expansion units have been initialized. There is an effect that the CPU unit can be recognized.

  According to the invention of claim 2, the same effect as that of claim 1 can be obtained, and a simple and inexpensive signal output circuit can be realized by using a switch element, and as a result, a programmable controller that suppresses cost increase is provided. There is an effect that can be.

(A) is a block diagram of the I / O unit used for the programmable controller of this embodiment, (b)-(d) is a circuit diagram of the component circuit. It is a schematic system diagram same as the above. It is a block diagram of CPU unit used for the same as the above. It is a connection example of the signal output circuit of the I / O unit used in the same as above. It is a time chart at the time of initialization of the I / O unit used for the same as the above. It is a time chart at the time of operation | movement same as the above. (A) (b) is a disassembled perspective view which shows the programmable controller of a prior art example.

  Embodiments of a programmable controller according to the present invention will be described below with reference to the drawings. The programmable controller according to the present invention is used as a control device such as an industrial machine. In the following description, a stacking (stacked) type programmable controller will be described as an example, and the external appearance is the same as that in FIG. 7B. Therefore, the description will be made with reference to FIG.

  FIG. 2 is a schematic system diagram of the programmable controller according to the present embodiment. The programmable controller includes a power supply unit 1 that supplies power to the entire system and a plurality of (four in FIG. 2) interfaces that are matched to the devices to be controlled. ) I / O unit (extension unit) 3, a CPU unit 2 for individually controlling each I / O unit 3, and a termination unit 4 connected to the termination I / O unit 3. Then, as shown in FIG. 7B, these units are arranged in the order of the power supply unit 1, the CPU unit 2, the I / O unit 3, and the termination unit 4 (not shown in FIG. 7B) from the left. Are connected sequentially. In the following description, when the I / O units 3 need to be distinguished from each other, they are referred to as I / O units 3A, 3B, 3C, 3D in order from the CPU unit 2 side. That is, in this embodiment, the I / O unit 3D is a terminal extension unit. Each unit is electrically connected via a stack connector 6 as shown in FIG.

  The power supply unit 1 receives power supply from an external power supply (not shown), converts it to a voltage required by the system, and supplies the system power supply V + to the CPU unit 2 and each I / O unit 3 via the power supply line 10. In addition, the power supply unit 1 of this embodiment is provided with the capacitor (charging element) C1 as a backup power supply when an external power supply is turned off by a power failure etc., for example (refer FIG. 3), and when a power failure occurs As the capacitor C1 is discharged, power can be supplied to the CPU unit 2 and each I / O unit 3. Details will be described later.

  As shown in FIGS. 2 and 3, the CPU unit 2 includes a power supply circuit 23 that generates a drive power supply (internal power supply) VCC from a system power supply V + supplied via the power supply line 10, and a power supply voltage of the system power supply V +. Voltage detection circuits 24 and 25 that detect and output a predetermined detection signal, a reset synthesis circuit 22 that outputs a start completion signal PSO when the drive power VCC from the power supply circuit 23 is supplied, and a program as a programmable controller And a control circuit 21 to be executed. The reset synthesis circuit 22 needs to be activated first when the system is activated, and in this embodiment, a CMOS logic IC or PLD (programmable logic device) that can ignore the activation time is used.

  The voltage detection circuit 24 detects the power supply voltage of the system power supply V +, and outputs the activation signal PF1 to the reset synthesis circuit 22 when the detected voltage reaches a predetermined reference voltage V1 (see FIG. 6). When the activation signal PF <b> 1 is input, the reset synthesis circuit 22 outputs the reset signal CPU_RESET to the control circuit 21 and activates the control circuit 21. Here, when the control circuit 21 is activated, the reset signal CPU_RESET is set to H level, and when the control circuit 21 is reset, the reset signal CPU_RESET is set to L level.

  The voltage detection circuit 25 detects the power supply voltage of the system power supply V +, and outputs a stop signal PF2 to the reset synthesis circuit 22 when the detected voltage becomes equal to or lower than a predetermined reference voltage V2 (V2 <V1, see FIG. 6). When the stop signal PF <b> 2 is input, the reset synthesis circuit 22 outputs an L level reset signal CPU_RESET to the control circuit 21 to stop the control circuit 21.

  The reset synthesizing circuit 22 starts and stops the control circuit 21 as described above, and outputs a start completion signal PSO to the adjacent I / O unit 3A when the drive power supply VCC is supplied. When the activation completion signal PSO (all unit activation completion signal PSR) input from the I / O unit 3D input via the termination unit 4 is input to the reset synthesis circuit 22 via the signal line 7, the reset synthesis circuit In 22, it recognizes that the power has been distributed to all the I / O units 3, outputs a reset signal ERESET to each I / O unit 3 via the signal line 8, and resets each I / O unit 3. Is released. Here, when each I / O unit 3 is activated, the reset signal ERESET is set to H level, and when each I / O unit 3 is reset, the reset signal ERESET is set to L level. Become. Further, when starting the power supply circuit 33 described later, the start completion signal PSO is set to H level. Conversely, when stopping the power supply circuit 33, the start completion signal PSO is set to L level.

  As shown in FIGS. 1A and 2, the I / O unit 3 includes a power supply circuit 33 that generates a drive power supply (internal power supply) VCC from a system power supply V + supplied via a power supply line 10, and a power supply circuit. From the voltage detection circuit 34 that detects the output voltage 33 and outputs a start completion signal PSO when the output voltage reaches a predetermined reference voltage V3 (see FIG. 6), and the reset synthesis circuit 22 or the voltage detection circuit 34 described above. When the activation completion signal PSO is input, the activation trigger circuit 32 that activates the power supply circuit 33, the control circuit 31 that executes the program as the I / O unit, and the completion of initialization of the control circuit 31 are notified. And a signal output circuit 35 for outputting an initialization completion signal.

  FIG. 1B is a circuit diagram of the start trigger circuit 32 described above, and includes two transistors Tr1 and Tr2 as main components. The base of the transistor Tr1 is connected to the reset synthesis circuit 22 of the CPU unit 2 or the voltage detection circuit 34 of the adjacent I / O unit 3 via the resistor R1. When an H-level activation completion signal PSO is input, the transistor Tr1 Becomes ON, and the collector-emitter becomes conductive. The collector of the transistor Tr1 is connected to the base of the transistor Tr2 and is connected to the system power supply V + via the resistor R6. When the transistor Tr1 is turned on, that is, when the collector-emitter of the transistor Tr1 is conductive, the transistor Tr2 is turned off. It is comprised so that it may become. Then, when the transistor Tr2 is turned off, the power supply circuit (power supply IC) 33 is activated, and the drive power supply VCC is supplied to each circuit.

  FIG. 1C is a circuit diagram of the voltage detection circuit 34 described above, and the comparator CP1 is the main component. A drive power supply VCC is connected to the input terminal Vin of the comparator CP1 via a resistor R2. The power supply voltage of the drive power supply VCC is compared with a predetermined reference voltage, and when it becomes higher than the reference voltage, a start completion signal is output from the output terminal. PSO is output.

  FIG. 1D is a circuit diagram of the signal output circuit 35 described above, and includes transistors Tr3 and Tr4 as main components. The base of the transistor Tr3 is connected to the control circuit 31 via the resistor R3. When an H level BOOT signal (a signal notifying that the initialization is completed) output from the control circuit 31 is input, the transistor Tr3 Turns ON and conducts between collector and emitter. The collector of the transistor Tr3 is connected to the base of the transistor Tr4, and is connected to the power supply line 10 (actually a signal line forming unit 10a described later) via the resistor R4. Further, the collector of the transistor Tr4 is a signal line 9 for transmitting an all unit initialization completion signal DONE notifying that the initialization of all the I / O units 3 has been completed (in practice, a signal line forming unit described later). 9a). In this signal output circuit 35, the transistor Tr4 is turned on when the system power supply V + is supplied, but when the H level BOOT signal is outputted from the control circuit 31, the transistor Tr3 is turned on. As a result, the transistor Tr4 is turned on. Turns off. Here, in this embodiment, the transistor Tr4 is a switch element, and the BOOT signal is a predetermined control signal.

  4 is an example of the signal line 9 in a state where the CPU unit 2 and the I / O units 3A to 3D are connected, and the transistor Tr4 of each signal output circuit 35 is connected in parallel to the signal line 9, respectively. The signal line 9 is pulled up to the drive power supply VCC through a resistor R5. Therefore, in a state where any of the transistors Tr4 is ON, the all unit initialization completion signal DONE is set to the L level, so that the CPU unit 2 has the I / O unit 3 that has not been initialized yet. Recognizing that there is, all unit initialization signal DONE is set to H level when all transistors Tr4 are OFF, so CPU unit 2 has completed initialization of all I / O units 3 Recognize that.

  In addition, as shown in FIG. 1A, the I / O unit 3 is similar to the power supply line forming unit 10a that forms one power supply line 10 together with the adjacent CPU unit 2 and other I / O units 3. And signal line forming portions 7 a to 9 a for forming one signal line 7 to 9 together with the CPU unit 2 and the other I / O unit 3 adjacent to each other. In the I / O unit 3, the system power V + is supplied through the power line forming unit 10a, and the reset signal ERESET is transmitted from the CPU unit 2 through the signal line forming unit 8a. Further, in the I / O unit 3, an initialization completion signal DONE is transmitted to the CPU unit 2 via the signal line forming unit 9a, and an all unit activation completion signal PSR is transmitted to the CPU unit 2 via the signal line forming unit 7a. It is transmitted.

  FIG. 5 is a time chart when the I / O unit 3 is initialized. When a power switch (not shown) is turned on at time t1, the system power V + is not yet supplied. The unit initialization completion signal DONE is at the L level, and the reset signal ERESET and the BOOT signal are at the H level. When system power supply V + reaches 10 V at time t2, reset signal ERESET and BOOT signal become L level, and control circuit 31 is reset. At this time, since the transistor Tr3 of the output signal circuit 35 is OFF and the transistor Tr4 is ON, the all unit initialization completion signal DONE remains at the L level.

  After that, when the system power supply V + becomes 24 V at time t3, the reset signal ERESET and the BOOT signal become H level. When there is one I / O unit 3, all unit initialization completion signals DONE are at H level. Therefore, the CPU unit 2 recognizes that the initialization of all (one) I / O units 3 has been completed. On the other hand, when there are a plurality of I / O units 3, the all unit initialization completion signal DONE remains at the L level. When the all unit initialization completion signal DONE becomes the H level at time t4, the CPU unit 2 recognizes that the initialization of all the I / O units 3 has been completed.

  As shown in FIG. 2, the termination unit 4 is a unit for short-circuiting the signal output terminal of the voltage detection circuit 34 of the termination I / O unit 3D and the signal line forming unit 7a. The activation completion signal PSO (all unit activation completion signal PSR) output from the I / O unit 3D is input to the CPU unit 2 via the signal line 7. When the activation completion signal PSO is input to the CPU unit 2, the CPU unit 2 recognizes that power has been distributed to all the I / O units 3.

  Here, since the programmable controller of the present embodiment includes the capacitor C1 as described above, even when the power supply is stopped due to a power failure or the like, the CPU unit 2 is terminated by the power supplied from the capacitor C1. (For example, data backup) can be executed. However, since the capacity of the capacitor C1 is limited, the power supply may be turned off before the termination process is completed when there are many connected I / O units 3. Therefore, in the present embodiment, in order to allow time for the termination process of the CPU unit 2, when the output voltage from the capacitor C1 becomes equal to or lower than a predetermined reference voltage V1 (see FIG. 6), the activation completion signal PSO is set to the L level. And the power supply circuit 33 of each I / O unit 3 is stopped.

  Next, the operation of the programmable controller will be described with reference to the time chart of FIG. When the system power supply V + supplied from the power supply unit 1 reaches the reference voltage V1 at time t1, in the CPU unit 2, the activation signal PF1 is output from the voltage detection circuit 24 to the reset synthesis circuit 22, and the reset synthesis circuit 22 An H level reset signal CPU_RESET is output to the control circuit 21. Further, the reset synthesis circuit 22 outputs an H level start completion signal PSO to the adjacent I / O unit 3A at time t2 by the built-in delay timer, and the I / O unit 3A starts the start trigger circuit 32. When the completion signal PSO is input, the power supply circuit 33 is activated. When the output voltage of the power supply circuit 33 reaches the reference voltage V3 at time t3, the H detection start signal PSO is output from the voltage detection circuit 34 to the adjacent I / O unit 3B.

  Similarly, the H-level start completion signal PSO is sequentially transmitted in the order of the I / O units 3C and 3D, and the output voltage of the power supply circuit 33 of the terminal I / O unit 3D at the time t6 becomes the reference voltage V3. When it reaches, the voltage detection circuit 34 outputs an H-level start completion signal PSO. The activation completion signal PSO is transmitted to the signal line 7 via the termination unit 4 and input to the reset synthesis circuit 22 of the CPU unit 2. That is, the CPU unit 2 recognizes that the power has been distributed to all the I / O units 3 at this time. Thereafter, the reset synthesizing circuit 22 of the CPU unit 2 outputs the reset signal ERESET at H level to the signal line 8 at the time t7 by the delay timer, and the reset signal ERESET is input to each I / O unit 3. Then, the reset state of the control circuit 31 is released. As a result, the initialization of the control circuit 31 is executed in each I / O unit 3 whose reset state is released, and when the initialization of the control circuits 31 of all the I / O units 3 is completed at time t8, The H-level all unit initialization completion signal DONE is input to the CPU unit 2. Then, the CPU unit 2 recognizes that all the I / O units 3 have been initialized. The CPU unit 2 recognizes each I / O unit 3 and starts communication with each I / O unit 3 to execute a sequence program.

  Next, the operation when power supply from the external power supply is stopped due to a power failure or the like will be described with reference to the time chart of FIG. As described above, in the event of a power failure, the capacitor C1 included in the power supply unit 1 is discharged, so that the system power supply V + is supplied to the CPU unit 2 and each I / O unit 3, but at time t9, the capacitor When the output voltage of C1 becomes equal to or lower than the reference voltage V1, the CPU unit 2 outputs an L level activation signal PF1 (voltage drop signal) from the voltage detection circuit 24 to the reset synthesis circuit 22. Then, the reset synthesis circuit 22 outputs an L level reset signal ERESET to each I / O unit 3, and as a result, the control circuit 31 of each I / O unit 3 is reset. In addition, the reset synthesis circuit 22 outputs the L level activation completion signal PSO to the adjacent I / O unit 3A at time t10 by the delay timer, and the I / O unit 3A sets the activation completion signal PSO to L level. As a result, the power supply circuit 33 is stopped. When the output voltage of the power supply circuit 33 becomes 0 V at time t11, the activation completion signal PSO output from the voltage detection circuit 34 becomes L level, and this activation completion signal PSO is sent to the adjacent I / O unit 3B. Is output.

  Similarly, the L level activation completion signal PSO is sequentially transmitted in the order of the I / O units 3C and 3D, so that the power supply circuit 33 included in the I / O unit 3 is sequentially stopped. When the output voltage of the power supply circuit 33 of the / O unit 3D becomes 0 V and the activation completion signal PSO output from the voltage detection circuit 34 becomes L level, the CPU unit 2 receives the L level input via the signal line 7 It is recognized that all the I / O units 3 have been powered off by the all unit activation completion signal PSR. Finally, when the output voltage of the capacitor C1 becomes equal to or lower than the reference voltage V2 at time t15, the voltage detection circuit 25 outputs a stop signal PF2 to the reset synthesis circuit 22, and the reset synthesis circuit 22 outputs the reset signal CPU_RESET at the L level. Is output to the control circuit 21. As a result, the control circuit 21 is reset by the reset signal CPU_RESET, and then the system power supply V + and the drive power supply VCC become 0V. A broken line a in FIG. 6 indicates a voltage change of the system power supply V + when the I / O unit 3 is not turned off. According to the present embodiment, the CPU unit 2 is (t15−t14). Can be delayed. As a result, the CPU unit 2 can have a sufficient time for the end processing such as data backup.

  Thus, according to the present embodiment, since each I / O unit 3 starts initialization individually when power is supplied, the system startup time is determined by the longest initialization time. Since the startup time does not increase cumulatively as described above, it is possible to prevent the system startup time from becoming long, and all I / O units can be detected by detecting the state change of the signal line 9. 3 can be recognized by the CPU unit 2. Furthermore, as in the present embodiment, a simple and inexpensive signal output circuit 35 can be realized by using the transistor Tr4, and as a result, a programmable controller that suppresses cost increase can be provided.

  In the present embodiment, a stacking type programmable controller has been described as an example. However, a building block type programmable controller as shown in FIG. 7A may be used. In this embodiment, the case where the extension unit is the I / O unit 3 has been described as an example. However, the extension unit is not limited to this embodiment. For example, the extension unit is for a communication network unit or serial data. It may be a control unit or the like. Furthermore, although the case where the number of I / O units 3 is four has been described as an example in the present embodiment, the number of I / O units 3 is not limited to the present embodiment, and may be one. Two, three, or five or more may be used. In the present embodiment, the power supply unit 1 is provided. However, for example, a power supply function may be provided in the CPU unit 2.

2 CPU units 3A to 3D I / O unit (extension unit)
9 signal line 9a signal line forming part 35 signal output circuit

Claims (2)

  A programmable controller comprising one or more extension units and a CPU unit for controlling the extension units, wherein the one or more extension units are sequentially connected to the CPU unit, wherein the extension units are connected to the CPU unit. A signal line forming unit that forms a signal line; and a signal output circuit that outputs an initialization completion signal notifying that the self-initialization has been completed, and the signal line outputs the signal output of all extension units. The state changes when the initialization completion signal is output from the circuit, and the CPU unit recognizes that all the extension units are initialized when detecting the state change of the signal line. controller.   The extension unit includes a power supply line forming unit that forms a power supply line from the CPU unit, the signal line is pulled up to a predetermined control voltage, and the signal output circuit includes the signal line forming unit and the signal line forming unit. The switch element is interposed between the ground and the switch element is turned on when the power supplied from the power line forming unit reaches a predetermined reference value, and the initialization of the switch element is completed. The CPU unit is turned off by a predetermined control signal, and the CPU unit recognizes that all the extension units are initialized when the switch elements of all the extension units are turned off and the state of the signal line changes to a high level. The programmable controller according to claim 1.

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