JP2011066244A - Semiconductor device for electrostatic protection - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a protection circuit that protects a semiconductor integrated circuit from the eddy current noise of an ESD and eddy current noise in a latch-up test and can enhance the degree of flexibility in the arrangement of wiring from a power terminal to a protective element, and to prevent a chip area from increasing. <P>SOLUTION: With a structure for setting a base ground current amplification factor of a bipolar transistor 12 to be protected from overcurrent noise in a latch-up test to 0.5 to 1.0, the overcurrent noise in the latch-up test entering from an I/O terminal 10 flows into a ground terminal 11 through the bipolar transistor 12, thus the wiring from the power terminal 9 to the base of the bipolar transistor 12 is made to be thin and the degree of flexibility in the wiring arrangement is enhanced. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device for electrostatic protection of a high voltage semiconductor integrated circuit.

  Semiconductor integrated circuits are usually connected to external terminals in order to prevent internal circuits from being destroyed by overcurrent noise applied from external terminals (for example, pulse currents such as ESD (Electrostatic Discharge) simulator and latch-up simulator test pulses). And an electrostatic protection circuit provided between the internal circuits. For example, when overcurrent noise is applied to the I / O terminal, this electrostatic protection circuit operates at a voltage (hereinafter referred to as a trigger voltage) that is several volts higher than the maximum operating voltage of the elements constituting the internal circuit. Designed to allow overcurrent noise to flow through the ground terminal or power supply terminal. The simplest way to meet this goal is to prevent current from flowing below a certain voltage, such as a diode (reverse connection), off-transistor, thyristor, etc. This can be realized by connecting the element as an electrostatic protection element between the I / O terminal and the ground terminal. The resistance to noise of the semiconductor integrated circuit including the electrostatic protection element as described above is evaluated using a simulator such as an ESD simulator, a CDM (Charged Device Model) simulator, and a latch-up simulator.

  When creating a semiconductor integrated circuit with higher withstand voltage, the electrostatic protection element used to protect against overcurrent noise must be able to pass overcurrent noise to the ground terminal or power supply terminal with a higher trigger voltage. I must. A protective element for protecting such an internal circuit with a high withstand voltage must be able to withstand more severe conditions regarding destruction due to Joule heat than a protective element for protecting an internal circuit with a low withstand voltage. Regarding the pulse width of overcurrent noise, a longer pulse width is a more severe condition with respect to destruction due to Joule heat. In particular, since the pulse width of the current pulse used for simulating latch-up is on the order of several ms, which is longer than other noises, special attention must be paid to the destruction of the electrostatic protection element itself.

  In order to prevent the electrostatic protection element itself from being destroyed by Joule heat, it is necessary to reduce the current density per unit area of the cross section through which the current flows to suppress heat generation, but this leads to an increase in the element size. Therefore, it cannot be increased without limit from the viewpoint of cost. Also, the protection method varies depending on the state of each terminal when overcurrent noise is applied. For example, in the case of ESD, since the noise is applied while the terminals to which noise is applied and the terminals other than the ground terminal are open, there is only a ground terminal to release the noise, but in the case of a current pulse in the latch-up test In the state where the power supply terminal and the ground terminal are connected to each other, overcurrent noise is applied to the remaining terminals, so that there are two terminals, the power supply terminal and the ground terminal, through which the overcurrent noise can be released.

Japanese Patent Laid-Open No. 11-26695

  When protecting internal circuits with high breakdown voltage as described above, protection from ESD overcurrent noise and overcurrent noise with a pulse width on the order of several ms, such as the test pulse of the latch-up simulator, without increasing the chip size. In order to achieve this, a protection circuit as shown in FIG. 3 or FIG. 4 has been conventionally considered.

  The first conventional example (FIG. 3) is a protection circuit in which a diode 17 is connected between the I / O terminal 15 and the power supply terminal 14 and a diode 18 is connected between the I / O terminal 15 and the ground terminal 16. It is. When overcurrent noise such as ESD is applied to the I / O terminal 15, the power supply terminal 14 is not connected, so that the diode 18 connected between the I / O terminal 15 and the ground terminal 16 breaks down and overcurrent noise is generated. Is released to the ground terminal 16. In the case of the latch-up test, a power supply is connected to the power supply terminal 14 and the potential is maintained at the maximum operating voltage. When overcurrent noise is applied to the I / O terminal 15 in this state, when the potential of the I / O terminal 15 becomes equal to or higher than (the potential of the power supply terminal 14 + the diffusion potential of the diode 17), the overcurrent noise is generated. The current flows through the diode 17 connected between the I / O terminal 15 and the power supply terminal 14 in the forward direction to the power supply terminal 14.

  In the second conventional example (FIG. 4), a diode 22 is connected between the I / O terminal 20 and the power supply terminal 19, and an off-MOS field effect transistor 23 is connected between the I / O terminal 20 and the ground terminal 21. It has become. Similar to the first conventional example (FIG. 3), when an overcurrent noise such as ESD is applied to the I / O terminal 20, the off-MOS type field effect transistor 23 operates and the I / O terminal 20 Overcurrent noise is passed through the ground terminal 21. Also in the case of the latch-up test, as in the first conventional example (FIG. 3), the overcurrent noise passes through the diode 22 connected between the I / O terminal 20 and the power supply terminal 19 in the forward direction. Will be shed.

  With the configuration described above, the diode 18 between the I / O terminal 15 and the ground terminal 16 or the off-MOS field effect transistor 23 between the I / O terminal 20 and the ground terminal 21 can be an ESD type. The element size can be reduced so that only the overcurrent noise of the order of several tens of ns can flow, so that the element size can be reduced. Further, a large-energy overcurrent noise having a pulse width on the order of several ms, such as a test pulse of a latch-up simulator, is generated by the diode 17 between the I / O terminal 15 and the power supply terminal 14 or the I / O terminal 20 and the power supply. Since the overcurrent noise flows in the forward direction through the diode 22 between the terminals 19, the resistance is lower than that in the case of flowing the overcurrent noise in the reverse direction, and the element size can be reduced.

  What is cited as a problem in the case of adopting the above configuration is that a thick wiring capable of flowing overcurrent noise must be drawn from the power supply terminal 14 to the diode 17 or from the power supply terminal 19 to the diode 22. The degree of freedom of arrangement is limited, and depending on the arrangement of the I / O terminals, there is a possibility of increasing the chip area corresponding to the wiring width.

  The present invention has been made in view of the above problems. In an electrostatic protection circuit that protects internal circuits with high withstand voltage, for protecting electrostatic circuits that protects internal circuits from ESD overcurrent noise and latch-up test overcurrent noise, and suppresses increase in chip area due to wiring An object is to provide a semiconductor device.

In order to solve the above problems, an electrostatic protection semiconductor device according to the present invention includes an ESD protection element connected between an I / O terminal and a ground terminal, a power supply terminal as a base, an I / O terminal as an emitter, and a ground. In an electrostatic protection circuit having a bipolar transistor whose terminal is connected to the collector, the structure of the bipolar transistor is such that the base ground current gain factor α ₀ is 0.5 to 1.0, and the ESD Overcurrent noise or latch-up test overcurrent noise was allowed to flow to the ground terminal side.

  With the above configuration, the width of the wiring from the power supply terminal to the base of the bipolar transistor can be reduced, and an electrostatic protection circuit with improved wiring layout freedom and reduced chip area for wiring is provided. A semiconductor integrated circuit can be manufactured.

1 is a cross-sectional view illustrating a part of a semiconductor device for electrostatic protection according to an embodiment of the present invention. The circuit diagram concerning the embodiment of the present invention. The circuit diagram concerning the 1st conventional example. The circuit diagram which concerns on a 2nd prior art example.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In the following description, the term “I / O terminal” or “input / output terminal” is used to include not only an input / output terminal but also an input-only terminal and an output-only terminal.

FIG. 2 is a circuit diagram according to an embodiment of the present invention. In the embodiment, for example, an N-channel off-MOS field effect transistor 13 is arranged between the ground terminal 11 and the I / O terminal 10 (also referred to as input / output terminal) as an ESD protection element for protecting ESD overcurrent noise. The drain is connected to the I / O terminal 10, and the source, gate, and back gate are connected to the ground terminal 11. Further, as a latch-up protection element for protecting against overcurrent noise in the latch-up test, for example, a pnp bipolar transistor 12 having a base ground current gain factor α ₀ of 0.5 to 1.0 is arranged, and the emitter is an I / O terminal. The collector is connected to the ground terminal 11 and the base is connected to the power supply terminal 9.

A cross-sectional view of an embodiment of the pnp bipolar transistor 12 is shown in FIG. The pnp bipolar transistor 100 has the following configuration. For example, in a P-type silicon substrate 1 having a resistance of 20 to 30 Ωcm, a P-type buried collector region 7 is formed to a thickness of about 8 μm from a depth of about 5 to 6 μm from the surface, and the impurity is 1 × 10 ¹⁶ as boron, for example. ^Forms about cm ^-3 . Next, a low-concentration N-type well base region 4 is formed on the P-type buried collector region 7 with a thickness of about 6 μm, the impurity is, for example, phosphorus, and a concentration of about 1 × 10 ¹⁶ cm ^−3. A low-concentration P-type well collector region 3 is formed so as to be in contact with the well base region 4 and surround the N-type well base region 4 with a thickness of about 10 μm and impurities as boron, for example, with a concentration of about 1 × 10 ¹⁶ cm ^−3. . Next, by ion implantation using the resist pattern as a mask in the low-concentration N-type well base region 4, the P-type high-concentration emitter region 2 has a depth of 0.4 μm, and the impurity is, for example, about 1 × 10 ²⁰ cm ⁻³ as boron. The N-type high-concentration base region 6 has a depth of 0.4 μm and the impurity is, for example, phosphorus as 1 × 10 ²⁰ cm by ion implantation using the resist pattern as a mask in the low-concentration N-type well base region 4. ^-3 and further implanted into the low concentration P-type well collector region 3 by ion implantation using the resist pattern as a mask. Form 10 ²⁰ cm ^-3 or so.

By providing the P-type buried collector region 7 and setting the emitter-collector distance 8 to, for example, about 5 μm, among the holes injected from the P-type high-concentration emitter region 2, the N-type well base region 4 The proportion of holes passing through and reaching the P-type buried collector region 7 and reaching the P-type high-concentration collector region 5 through the P-type well collector region 3 is increased, resulting in a base ground current gain factor α ₀ of 0.5. A pnp bipolar transistor 100 of ˜1.0 can be obtained. In FIG. 2, if a pnp bipolar transistor 12 having a base ground current gain factor α ₀ of 0.5 to 1.0 having the above-described structure is used, the current flowing from the I / O terminal 10 to the power supply terminal 9 is reduced. The thickness of the wiring connected to the emitter of the pnp bipolar transistor 12 can be reduced, so that the degree of freedom of wiring arrangement can be improved and the chip area can be reduced.

  In the above description, a MOS field effect transistor is provided between the I / O terminal and the ground terminal, and a bipolar transistor is provided between the I / O terminal and the power supply terminal. A semiconductor element other than the MOS field effect transistor may be disposed as an ESD protection element between them. When the ESD protection element is a diode or thyristor, the anode of the diode is connected to the I / O terminal, the cathode is connected to the ground terminal, and a bipolar transistor is provided between the I / O terminal and the power supply terminal. An effect can be obtained.

1 P-type silicon substrate 2 P-type high-concentration emitter region 3 P-type well collector region 4 N-type well base region 5 P-type high-concentration collector region 6 N-type high-concentration base region 7 P-type buried collector region 8 Emitter-collector distance 9 Power supply terminal 10 I / O terminal 11 Ground terminal 12 pnp bipolar transistor 13 N channel off MOS field effect transistor 100 pnp bipolar transistor

Claims (5)

A semiconductor substrate;
An ESD protection element disposed on a surface of the semiconductor substrate and connected between an input / output terminal and a ground terminal;
A bipolar transistor disposed on the surface of the semiconductor substrate, having an emitter connected to the input / output terminal, a base connected to a power supply terminal, and a collector connected to the ground terminal;
A semiconductor device for electrostatic protection, wherein a base ground current gain factor of the bipolar transistor is 0.5 to 1.0. The bipolar transistor is:
A first conductivity type first low-concentration well region provided on the first conductivity type semiconductor substrate;
A buried region of a first conductivity type provided under the first low-concentration well region;
A first first conductivity type high concentration region provided on a surface of the first low concentration well region;
A second conductivity type high concentration region provided on the surface of the first low concentration well region so as to be separated from the first first conductivity type high concentration region and to surround the first first conductivity type high concentration region When,
A second low-concentration well region of a first conductivity type provided in contact with and surrounding the first low-concentration well region;
A second first conductivity type high concentration region provided on the surface of the second low concentration well region;
The semiconductor device for electrostatic protection according to claim 1, comprising:   3. The semiconductor device for electrostatic protection according to claim 1, wherein the ESD protection element is a protection diode having an anode connected to the input / output terminal and a cathode connected to the ground terminal.   3. The semiconductor device for electrostatic protection according to claim 1, wherein the ESD protection element is a MOS transistor having a drain connected to the input / output terminal and a source, a gate, and a back gate connected to the ground terminal.   3. The semiconductor device for electrostatic protection according to claim 1, wherein the ESD protection element is a thyristor having an anode connected to the input / output terminal and a cathode connected to the ground terminal.

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