JP2011066171A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element for achieving a stable withstand voltage without performing neutron emission. <P>SOLUTION: This semiconductor device includes: a first conductivity type first semiconductor region; a second conductivity type second semiconductor region formed from one-side surface of the first semiconductor region; a second conductivity type third semiconductor region formed to surround the second semiconductor region and extending from the one-side surface of the first semiconductor region; a first conductivity type fourth semiconductor region formed to surround the third semiconductor region and extending from the one-side surface of the first semiconductor region; a first conductivity type fifth semiconductor region extending to one-side main surface of the first semiconductor region without affecting the second, third and fourth semiconductor regions extending to the one-side main surface of the first conductivity type first semiconductor region; and a first conductivity type sixth semiconductor region extending from the other-side surface of the first semiconductor region. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for electric power requiring a high breakdown voltage of 1.7 kV or higher.

  As the power semiconductor device, one having a withstand voltage class which varies depending on the application is used. It is the length of the depletion layer that spreads depending on the impurity concentration in the drift region that determines the breakdown voltage of the power semiconductor device. For example, when a voltage is applied between the emitter and collector electrodes in the off state of the semiconductor device, a depletion layer spreads from the pn junction between the p-type base region and the n-type drift region into the drift region. When the impurity concentration in the drift region increases, the spread of the depletion layer can be suppressed and the breakdown voltage can be increased.

  In high-voltage power semiconductor devices, a wafer that has been grown by the FZ method and whose resistivity is determined by neutron irradiation is mainly used for the drift region. That is, first, a high-resistance silicon single crystal ingot is grown by the FZ method. During the growth, nitrogen is added in order to suppress the occurrence of ingot dislocations and crystal defects. Next, the resistivity of the entire ingot is reduced by neutron irradiation.

The resistivity of the entire ingot can be highly controlled by neutron irradiation. That is, the silicon single crystal is composed of 28Si (92.1%) and its isotopes 29Si (4.7%) and 30Si (3.0%). When a silicon single crystal is irradiated with neutrons, 30Si captures and absorbs neutrons, emits γ-rays, shifts to the unstable isotope 31Si, and becomes stable by β ⁻ decay with a half-life of 2.62 hours. It is converted into a body 31P. This 31P functions as an n-type dopant in the silicon single crystal and becomes a dopant in the drift region. At this time, the impurity concentration of the drift region, that is, the resistivity can be controlled by controlling the neutron irradiation amount.

  FIG. 6 is an example of an IGBT which is a conventional power semiconductor device.

In the IGBT shown in the figure, the resistivity of the n ⁻ layer 31 serving as the drift region is controlled by neutron irradiation. On one main surface of n ⁻ layer 31, p layer 32 is formed by diffusion. P layers 321, 322, 323, 324, 325, 326 and 327 are formed by diffusion so as to surround the p layer 32. Further, an n ⁺ layer 33 is formed on the outermost periphery of the IGBT.

A semiconductor region made of n ⁺ layer 34 is formed on the other surface of n ⁻ layer 31, and a semiconductor region made of p ⁺ layer 35 is formed on one surface of n ⁺ layer 34. An emitter electrode 36 having a field plate is formed on the p layer 32, and a collector electrode 37 is formed on the main surface with which the semiconductor region made of the p ⁺ layer 35 is in contact with the low resistance. Auxiliary electrodes 331, 332, 333, 334, 335, 336, 337 and 38 are placed on the p layers 321, 322, 323, 324, 325, 326, 327 and the n ⁺ layer 33 so as to make low resistance contact with the respective layers. Is formed. Auxiliary electrodes 331, 332, 333, 334, 335, 336, 337 and 38 have field plates that cover n ⁻ layer 31 through insulating films 341, 342, 343, 344, 345, 346, 347, and 39. is doing. In the figure, the region indicated by (a) is referred to as an active region, and the region indicated by (b) is referred to as a termination region.

When a voltage is applied between the emitter electrode 36 and the collector electrode 37 in the off state of the IGBT, a depletion layer spreads from the pn junction between the n ⁻ layer 31 and the p layer 32 in the active region. The depletion layer extends through the termination region to the outermost periphery of the chip and through the n ⁺ layer 34 toward the collector electrode 37. When the impurity concentration of the n ⁻ layer 31 and the n ⁺ layer 34 increases, the spread of the depletion layer can be suppressed and the breakdown voltage can be increased. In IGBTs with different breakdown voltage classes, the target breakdown voltage can be ensured by controlling the impurity concentration of the n ⁻ layer 31, that is, the resistivity by neutron irradiation during the wafer manufacturing process.

JP 2007-176725 A

  However, in recent years, a long time has passed since the construction of the neutron irradiation furnace, and there is a concern over aging. Therefore, it is expected that it will be difficult to manufacture a power semiconductor device in which a drift region is formed by neutron irradiation.

  In order to manufacture a power semiconductor element without performing neutron irradiation, it is necessary to ensure a high breakdown voltage by an element structure suitable for it.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor element that realizes a stable breakdown voltage without performing neutron irradiation.

  In order to achieve the above object, a semiconductor device of the present invention has a first semiconductor region of the first conductivity type and a second semiconductor of the second conductivity type formed from one surface of the first semiconductor region. A second conductive type third semiconductor region that extends from one surface of the first semiconductor region, and a third semiconductor region that surrounds the third semiconductor region. A first conductive type fourth semiconductor region formed and extending from one surface of the first semiconductor region; and the second semiconductor extending to one main surface of the first conductive type first semiconductor region. A first conductivity type fifth semiconductor region extending to one main surface of the first semiconductor region without affecting the region, the third semiconductor region, and the fourth semiconductor region, and the first semiconductor A sixth semiconductor region of the first conductivity type extending from the other surface of the region A first main electrode formed on the surface of the sixth semiconductor region, a second main electrode formed through an insulating film in low resistance contact with the second semiconductor region, and a third The semiconductor device includes a plurality of auxiliary electrodes that are in low-resistance contact with the semiconductor region and formed on the side of the second semiconductor region and the opposite side thereof through an insulating film.

  According to the semiconductor device of the present invention, the length of the depletion layer spreads between the fifth semiconductor region of the first conductivity type provided on one surface of the first semiconductor region, and the first semiconductor region. Since it is controlled by the depth and concentration of the sixth semiconductor region of the first conductivity type provided on the other surface and the breakdown voltage can be controlled by the fifth semiconductor region and the sixth semiconductor region, it has a high resistance without neutron irradiation. A stable withstand voltage semiconductor device can be obtained using a silicon wafer.

It is sectional drawing which shows Example 1 of the semiconductor device of this invention. It is sectional drawing which shows Example 2 of the semiconductor device of this invention. It is sectional drawing which shows Example 3 of the semiconductor device of this invention. It is sectional drawing which shows Example 4 of the semiconductor device of this invention. It is sectional drawing which shows Example 5 of the semiconductor device of this invention. It is sectional drawing which shows IGBT which is the conventional semiconductor device.

  Hereinafter, the details of the semiconductor device of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

In the semiconductor device shown in the figure, the n ⁻ layer 11 is a high-resistance silicon wafer whose resistivity is not controlled by neutron irradiation. A p layer 12 is formed on one main surface of the n ⁻ layer 11 by diffusion. P layers 121, 122, 123, 124, 125, 126, and 127 are formed by diffusion so as to surround the p layer 12. Further, an n ⁺ layer 13 is formed on the outermost periphery of the semiconductor device. Furthermore, each p layer 12, 121, 122, 123, 124, 125, 126, 127, and n layer 14 is formed between n ⁺ layer 13 and n ⁻ layer 11 by diffusion or epitaxial growth. An n ⁺ layer 15 is formed on the other surface of the n ⁻ layer 11 by diffusion or epitaxial growth. A semiconductor region 16 is formed on one surface of the n ⁺ layer 15 by diffusion or epitaxial growth. Here, the conductivity type of the semiconductor region 16 is a p ⁺ type in the case of a semiconductor device having a p emitter layer such as an IGBT, a thyristor, or a GTO, and an n ⁺ type in the case of a MOSFET or a diode. A main electrode 17 having a field plate is formed on the p layer 12, and a main electrode 18 is formed on the main surface where the semiconductor region 16 is in contact with each other so as to make a low resistance contact. Auxiliary electrodes 131, 132, 133, 134, 135, 136, 137, and 19 are in low resistance contact with the p layers 121, 122, 123, 124, 125, 126, 127 and the n ⁺ layer 13, respectively. It is formed as follows. The auxiliary electrodes 131, 132, 133, 134, 135, 136, 137, and 19 have a field plate that covers the n ⁻ layer 11 through the insulating films 141, 142, 143, 144, 145, 146, 147, and 20. is doing.

Since the resistivity of the n ⁻ layer 11 is high, that is, the impurity concentration is low, the breakdown voltage is secured by the n layer 14 and the n ⁺ layer 15. At this time, under the condition that the n layer 14 is deeper than the p layer 12 and the p layers 121, 122, 123, 124, 125, 126, 127, the depth and impurity concentration of the n layer 14 and the n ⁺ layer 15 are Depends on the pressure class. Since the breakdown voltage is secured by the n layer 14 and the n ⁺ layer 15, a stable breakdown voltage can be secured even when a high-resistance silicon wafer is used.

Further, since the breakdown voltage of the semiconductor device is controlled by the depth and concentration of the n layer 14 and the n ⁺ layer 15, the silicon wafer used as the n ⁻ layer 11 uses a wafer having the same resistance value regardless of a plurality of breakdown voltage classes. can do. For this reason, the wafer cost can be reduced.

  FIG. 2 is a cross-sectional view of a semiconductor device which is an embodiment in which the n layer 41 is disposed so as to cover only the p layers 121, 122, 123, 124, 125, 126, 127.

In the semiconductor device shown in the figure, the n ⁻ layer 11 is a high-resistance silicon wafer whose resistivity is not controlled by neutron irradiation. A p layer 12 is formed on one main surface of the n ⁻ layer 11 by diffusion. P layers 121, 122, 123, 124, 125, 126, and 127 are formed by diffusion so as to surround the p layer 12. Further, an n ⁺ layer 13 is formed on the outermost periphery of the semiconductor device. Further and n each p layer 121,122,123,124,125,126,127 ^- n layer 41 is formed by diffusion or epitaxial growth between the layer 11. An n ⁺ layer 15 is formed on the other surface of the n ⁻ layer 11 by diffusion or epitaxial growth. A semiconductor region 16 is formed on one surface of the n ⁺ layer 15 by diffusion or epitaxial growth. Here, the conductivity type of the semiconductor region 16 is a p ⁺ type in the case of a semiconductor device having a p emitter layer such as an IGBT, a thyristor, or a GTO, and an n ⁺ type in the case of a MOSFET or a diode. A main electrode 17 having a field plate is formed on the p layer 12, and a main electrode 18 is formed on the main surface where the semiconductor region 16 is in contact with each other so as to make a low resistance contact. Auxiliary electrodes 131, 132, 133, 134, 135, 136, 137, and 19 are in low resistance contact with the p layers 121, 122, 123, 124, 125, 126, 127 and the n ⁺ layer 13, respectively. It is formed as follows. The auxiliary electrodes 131, 132, 133, 134, 135, 136, 137, and 19 have a field plate that covers the n ⁻ layer 11 through the insulating films 141, 142, 143, 144, 145, 146, 147, and 20. is doing.

In the semiconductor device of FIG. 2, the breakdown voltage is controlled by the depth and concentration of the n layer 41 and the n ⁺ layer 15 even when the n layer 41 covers only the p layers 121, 122, 123, 124, 125, 126, 127. Therefore, a stable breakdown voltage can be secured.

The position where the n layer 41 is arranged is the same when the p layers 12, 121, 122, 123, 124, 125, 126, 127 and any part between the n ⁺ layer 13 and the n ⁻ layer 11 are covered. effective.

  FIG. 3 is a cross-sectional view of a semiconductor device which is an embodiment in which n layers 42 and 43 are arranged so as to cover only the p layers 121 and 122 and the p layers 124, 125 and 126, respectively.

In the semiconductor device shown in the figure, the n ⁻ layer 11 is a high-resistance silicon wafer whose resistivity is not controlled by neutron irradiation. A p layer 12 is formed on one main surface of the n ⁻ layer 11 by diffusion. P layers 121, 122, 123, 124, 125, 126, and 127 are formed by diffusion so as to surround the p layer 12. Further, an n ⁺ layer 13 is formed on the outermost periphery of the semiconductor device. Further, an n layer 42 is formed between the p layers 121 and 122 and the n ⁻ layer 11, and an n layer 43 is formed between the p layers 124, 125 and 126 and the n ⁻ layer 11 by diffusion or epitaxial growth. . An n ⁺ layer 15 is formed on the other surface of the n ⁻ layer 11 by diffusion or epitaxial growth. A semiconductor region 16 is formed on one surface of the n ⁺ layer 15 by diffusion or epitaxial growth. Here, the conductivity type of the semiconductor region 16 is a p ⁺ type in the case of a semiconductor device having a p emitter layer such as an IGBT, a thyristor, or a GTO, and an n ⁺ type in the case of a MOSFET or a diode. A main electrode 17 having a field plate is formed on the p layer 12, and a main electrode 18 is formed on the main surface where the semiconductor region 16 is in contact with each other so as to make a low resistance contact. Auxiliary electrodes 131, 132, 133, 134, 135, 136, 137, and 19 are in low resistance contact with the p layers 121, 122, 123, 124, 125, 126, 127 and the n ⁺ layer 13, respectively. It is formed as follows. The auxiliary electrodes 131, 132, 133, 134, 135, 136, 137, and 19 have a field plate that covers the n ⁻ layer 11 through the insulating films 141, 142, 143, 144, 145, 146, 147, and 20. is doing.

In the semiconductor device of FIG. 2, even in a structure in which the n layers 42 and 43 cover only the p layers 121 and 122 and the p layers 124, 125 and 126, the breakdown voltage is the same as the depth of the n layers 42 and 43 and the n ⁺ layer 15. Since the concentration is controlled, a stable breakdown voltage can be secured.

The positions where the n layers 42 and 43 are arranged cover the p layers 12, 121, 122, 123, 124, 125, 126, 127 and any part between the n ⁺ layer 13 and the n ⁻ layer 11. Has the same effect.

Even when an arbitrary number of n layers similar to the n layers 42 and 43 are added, each p layer 12, 121, 122, 123, 124, 125, 126, 127 and between the n ⁺ layer 13 and the n ⁻ layer 11 If any part is covered, it has the same effect.

FIG. 4 is a cross-sectional view of a semiconductor device which is an embodiment in which an n ⁻ layer 21 is disposed between the n ⁻ layer 11 and the n layer 14.

In the semiconductor device shown in the figure, the n ⁻ layer 11 is a high-resistance silicon wafer whose resistivity is not controlled by neutron irradiation. A p layer 12 is formed on one main surface of the n ⁻ layer 11 by diffusion. P layers 121, 122, 123, 124, 125, 126, and 127 are formed by diffusion so as to surround the p layer 12. Further, an n ⁺ layer 13 is formed on the outermost periphery of the semiconductor device. Furthermore, each p layer 12, 121, 122, 123, 124, 125, 126, 127, and n layer 14 is formed between n ⁺ layer 13 and n ⁻ layer 11 by diffusion or epitaxial growth. Further, an n ⁻ layer 21 is formed between the n ⁻ layer 11 and the n layer 14 by diffusion or epitaxial growth. An n ⁺ layer 15 is formed on the other surface of the n ⁻ layer 11 by diffusion or epitaxial growth. A semiconductor region 16 is formed on one surface of the n ⁺ layer 15 by diffusion or epitaxial growth. Here, the conductivity type of the semiconductor region 16 is a p ⁺ type in the case of a semiconductor device having a p emitter layer such as an IGBT, a thyristor, or a GTO, and an n ⁺ type in the case of a MOSFET or a diode. A main electrode 17 having a field plate is formed on the p layer 12, and a main electrode 18 is formed on the main surface where the semiconductor region 16 is in contact with each other so as to make a low resistance contact. Auxiliary electrodes 131, 132, 133, 134, 135, 136, 137, and 19 are in low resistance contact with the p layers 121, 122, 123, 124, 125, 126, 127 and the n ⁺ layer 14, respectively. It is formed as follows. The auxiliary electrodes 131, 132, 133, 134, 135, 136, 137, and 19 have a field plate that covers the n ⁻ layer 11 through the insulating films 141, 142, 143, 144, 145, 146, 147, and 20. is doing.

In the semiconductor device of FIG. 1, when the n layer 14 is formed by diffusion or epitaxial growth and the impurity concentration difference between the n layer 14 and the n ⁻ layer is large, an electric field is concentrated on the boundary between the n ⁻ layer and the n layer 14. In addition, the breakdown voltage is reduced. In the semiconductor device of FIG. 4, n ^- to form a layer 21, n ^{- -} n between layers and the n-layer 14 to reduce the electric field concentration layer and n layer 14, a stable withstand voltage can be secured.

  FIG. 5 is a cross-sectional view of the semiconductor device 3 which is an embodiment where the semiconductor region 16 is not provided in the semiconductor device of the first embodiment.

In the semiconductor device shown in the figure, the n ⁻ layer 11 is a silicon wafer whose resistivity is not controlled by neutron irradiation. A p layer 12 is formed on one main surface of the n ⁻ layer 11 by diffusion. P layers 121, 122, 123, 124, 125, 126, and 127 are formed by diffusion so as to surround the p layer 12. Further, an n ⁺ layer 13 is formed on the outermost periphery of the IGBT. Furthermore, each p layer 12, 121, 122, 123, 124, 125, 126, 127, and n layer 14 is formed between n ⁺ layer 13 and n ⁻ layer 11 by diffusion or epitaxial growth. An n ⁺ layer 15 is formed on the other surface of the n ⁻ layer 11 by diffusion or epitaxial growth. A main electrode 17 having a field plate is formed on the p layer 12, and a main electrode 18 is formed on the main surface where the n ⁺ layer 15 is in contact with each other so as to make a low resistance contact. Auxiliary electrodes 131, 132, 133, 134, 135, 136, 137, and 19 are in low resistance contact with the p layers 121, 122, 123, 124, 125, 126, 127 and the n ⁺ layer 13, respectively. It is formed as follows. The auxiliary electrodes 131, 132, 133, 134, 135, 136, 137, and 19 have a field plate that covers the n ⁻ layer 11 through the insulating films 141, 142, 143, 144, 145, 146, 147, and 20. is doing.

In the semiconductor device of FIG. 5, even in the structure in which the n ⁺ layer 15 is in contact with the main electrode 18, the breakdown voltage is controlled by the depth and concentration of the n layer 14 and the n ⁺ layer 15, so that a stable breakdown voltage can be secured.

11 n ^- layer 12, 32, 121, 122, 123, 124, 125, 126, 127, 321, 322, 323, 324, 325, 326, 327 p layer 13, 15, 33, 34 n ⁺ layer 19, 38, 131, 132, 133, 134, 135, 136, 137, 331, 332, 333, 334, 335, 336, 337 Auxiliary electrodes 14, 41, 43, 44 n layer 20, 39, 141, 142, 143 144, 145, 146, 147, 341, 342, 343, 344, 345, 346, 347 Insulating film 16 Semiconductor region 17, 18 Main electrode 21, 31 n ⁻ layer 35 p ⁺ layer 36 emitter electrode 37 collector electrode

Claims (9)

  The first conductive type first semiconductor region, the second conductive type second semiconductor region formed from one surface of the first semiconductor region, and the second semiconductor region are formed. A third semiconductor region of a second conductivity type extending from one surface of the first semiconductor region, and surrounding the third semiconductor region and extending from one surface of the first semiconductor region A fourth semiconductor region of the first conductivity type; the second semiconductor region extending to one main surface of the first semiconductor region of the first conductivity type; the third semiconductor region; and the fourth semiconductor A fifth semiconductor region of a first conductivity type that extends to one main surface of the first semiconductor region without damaging the region, and a sixth of a first conductivity type that extends from the other surface of the first semiconductor region. And the first semiconductor region formed on the surface of the sixth semiconductor region. A low resistance contact with the electrode, the second semiconductor region, a second main electrode formed through an insulating film, and a low resistance contact with the third semiconductor region, the second semiconductor region side and A semiconductor device comprising a plurality of auxiliary electrodes formed on the opposite side with an insulating film interposed therebetween. The semiconductor device according to claim 1,
The semiconductor device, wherein the first semiconductor region is formed by a silicon wafer which is grown by an FZ method and is not irradiated with neutrons. The semiconductor device according to claim 1, wherein:
The first conductive type fifth semiconductor region has a diffusion depth deeper than that of the second conductive type second semiconductor region and the second conductive type third semiconductor region. . The semiconductor device according to claim 1, claim 2, or claim 3,
The fifth semiconductor region of the first conductivity type includes a second semiconductor region of the second conductivity type, a plurality of third semiconductor regions of the second conductivity type, and a fourth semiconductor region of the first conductivity type. A semiconductor device characterized by covering all parts of the semiconductor device. The semiconductor device according to claim 1, claim 2, or claim 3,
The fifth semiconductor region of the first conductivity type includes a second semiconductor region of the second conductivity type, a plurality of third semiconductor regions of the second conductivity type, and a fourth semiconductor region of the first conductivity type. Part of the semiconductor device. The semiconductor device according to claim 1, claim 2, or claim 3,
The fifth semiconductor region of the first conductivity type includes a second semiconductor region of the second conductivity type, a plurality of third semiconductor regions of the second conductivity type, and a fourth semiconductor region of the first conductivity type. A plurality of portions of the semiconductor device. The semiconductor device according to claim 1, claim 2, claim 3, claim 4, claim 5, and claim 6,
One main surface of the first semiconductor region without damaging the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region of the first conductivity type A semiconductor device having a seventh semiconductor region of a first conductivity type extending in the direction. In the semiconductor device according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7,
An eighth semiconductor region of the second conductivity type formed on the main surface of the first conductivity type sixth semiconductor region on the side in contact with the first main electrode and in contact with the first main electrode. A semiconductor device comprising: In the semiconductor device according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7,
A ninth semiconductor region of the first conductivity type formed on a main surface of the sixth semiconductor region of the first conductivity type on the side in contact with the first main electrode and in contact with the first main electrode A semiconductor device comprising:

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