JP2011066040A - Structure for mounting semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the connection reliability of a semiconductor device which is mounted on a circuit board by solder terminals. <P>SOLUTION: A structure for mounting semiconductor device has a columnar electrode 10 which is provided, on the surface thereof, with a solder terminal for external connection. The circuit board on which the semiconductor device is mounted includes a connection pad provided at the end of wiring, and a protective insulation layer 16 which covers the wiring. The protective insulation layer is provided with an opening which exposes the connection pad, and the following relationship is satisfied between the diameter R of the opening, and the diameter D of the columnar electrode, 0.9D≤R≤0.98D. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a mounting structure of a semiconductor device.

  Some semiconductor devices are generally called CSP (chip size package). In the CSP, an insulating film is provided on the surface of the semiconductor substrate on which the connection pad is provided, and the insulating film is provided with an opening at a portion corresponding to the central portion of the connection pad. A rewiring is formed on the surface of the insulating film, and the rewiring is connected to the connection pad through the opening of the insulating film. A columnar electrode is provided at the end of the rewiring, and the rewiring and the insulating film are sealed with a sealing film. The columnar electrode is exposed from the sealing layer, and a solder terminal is provided on the surface of the columnar electrode. The semiconductor device is connected to a circuit board via a solder terminal (see, for example, Patent Document 1).

  A circuit board to which the semiconductor device is connected is provided with wiring having a connection pad at an end. Also, a solder resist layer that covers the wiring is provided, and an opening that exposes the connection pad is provided in the solder resist layer. The soldering is performed by the reflow method in a state where the solder terminals are arranged at the positions of the openings, so that the semiconductor device is mounted on the circuit board.

JP 2007-287048 A

  By the way, when a semiconductor device is mounted on a circuit board with solder terminals, damage may occur at the portions of the solder terminals, resulting in poor connection.

  The subject of this invention is improving the connection reliability of the semiconductor device mounted in a circuit board by a solder terminal.

  In order to solve the above problems, the invention according to claim 1 is a semiconductor device having a columnar electrode having a diameter D, a solder terminal connected to the columnar electrode, and a connection pad connected to the solder terminal. A protective insulating layer in which an opening for opening the connection pad is formed, and the diameter R of the opening in a state where the connection pad is connected to the solder terminal satisfies 0.9D ≦ R ≦ 0.98D And a connected medium.

  The columnar electrode preferably has a higher Young's modulus than the solder terminal. The connection pad preferably has a higher Young's modulus than the solder terminal.

  According to the present invention, the connection reliability of a semiconductor device mounted on a circuit board with solder terminals can be improved.

1 is a cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. 2 is a cross-sectional view showing a connection portion between a semiconductor device 1 and a circuit board 13. FIG. 2 is a cross-sectional view showing a connection portion between a semiconductor device 1 and a circuit board 13. FIG. 2 is a cross-sectional view showing a connection portion between a semiconductor device 1 and a circuit board 13. FIG. 2 is a cross-sectional view showing a connection portion between a semiconductor device 1 and a circuit board 13. FIG. 6 is a histogram showing a variation distribution of opening diameters of openings in Example 1. 10 is a histogram showing variation distribution of opening diameters of openings in a solder resist layer of Comparative Example 2. 10 is a histogram showing a variation distribution of opening diameters of openings in a solder resist layer of Comparative Example 3. It is a Weibull plot in which the number of cycles and the failure rate are plotted.

  FIG. 1 is a cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. The semiconductor device 1 is generally called a CSP and includes a semiconductor substrate 2 made of silicon or the like. The semiconductor substrate 2 has a substantially quadrilateral shape.

  A plurality of connection pads 3 made of metal or the like are provided on the surface of the semiconductor substrate 2 along the periphery of the semiconductor substrate 2. An insulating film 4 made of silicon oxide or the like is provided on the surface of the semiconductor substrate 2. A protective film 6 made of epoxy resin, polyimide resin, or the like is provided on the surface of the insulating film 4.

The insulating film 4 and the protective film 6 are respectively provided with openings 5 and 7 that expose the central portion of the connection pad 3. The openings 5 and 7 can be formed by wet etching, laser etching, or the like.
A base metal layer 8 made of copper or the like is provided on the surface of the protective film 6. The underlying metal layer 8 may be a single metal layer or a plurality of layers in which different metals are laminated. The base metal layer 8 preferably has a thickness of 200 nm to 2000 nm. A rewiring 9 made of copper is provided on the surface of the base metal layer 8. The rewiring 9 preferably has a thickness of 1 μm to 10 μm. One end portions of the base metal layer 8 and the rewiring 9 are connected to the connection pads 3 through the openings 5 and 7, respectively.

Columnar electrodes 10 made of copper (Young's modulus 110 GPa, thermal expansion coefficient 1.62 × 10 ⁻⁵ / K) are provided at the other end portions of the base metal layer 8 and the rewiring 9, respectively. The columnar electrodes 10 are arranged in a lattice pattern in the central region surrounded by the connection pads 3 in the substantially quadrilateral semiconductor substrate 2. Each of the base metal layers 8 and the redistribution layer 9 is connected to the connection pads 3 and the columnar electrodes 10 that are different from each other, and each of the base metal layers 8 and the redistribution layer 9 is a stack of other base metal layers 8 and rewirings 9. Arranged so as to be electrically insulated. On the surfaces of the rewiring 9 and the protective film 6, a sealing film 11 made of an epoxy resin, a polyimide resin, or the like is provided so that the surface of the sealing film 11 is substantially flush with the surface of the columnar electrode 10. It is provided to be exposed. The sealing film 11 protects the columnar electrode 10 from its side surface, and protects the base metal layer 8 and the rewiring 9 from their upper surface. A substantially spherical solder terminal 12 (Young's modulus 20 to 30 GPa, thermal expansion coefficient 2 to 3 × 10 ⁻⁵ / K) is provided on the surface of each columnar electrode 10 for connection to the connection pad 14 of the circuit board 13. It has been. The solder terminals 12 are electrically connected to each other by contacting the circular upper surface of the columnar electrode 10. The circuit board 13 is a printed circuit board (PCB) board, and a plurality of circuits and wirings are provided on a base board 15 which is a resist having a thickness of 600 μm to 1000 μm.

FIG. 2 is a cross-sectional view showing a connection portion between the semiconductor device 1 and the circuit board 13. In the semiconductor device 1, illustration of the semiconductor substrate 2 and the like is omitted. A plurality of wirings (not shown) are provided on the upper surface of the circuit board 13, and connection pads 14 having copper (Young's modulus 110 GPa, thermal expansion coefficient 1.62 × 10 ⁻⁵ / K) are provided at the ends of each wiring. ing. Further, a protective insulating layer 16 such as a solder resist formed by curing a photocurable resin or a thermosetting resin is provided on the surface of the circuit board 13 on which the wiring and the connection pads 14 are provided. The thickness of the protective insulating layer 16 is 30 to 50 μm. The protective insulating layer 16 is provided with an opening 17 through which the connection pad 14 is exposed. The shape of the opening 17 is circular in plan view. The opening 17 can be formed by wet etching, laser etching, or the like. In the opening 17, the diameter R on the upper surface 16 </ b> A side (upper side) of the protective insulating layer 16 is longer than the diameter on the connection pad 14 side (lower side) in accordance with the shape of the spherical solder terminal 12. Both the columnar electrode 10 and the connection pad 14 need not be copper as long as the Young's modulus (rigidity) is higher than that of the solder terminal 12 and the difference in thermal expansion coefficient from the solder terminal 12 is sufficient.

  The semiconductor device 1 is electrically connected to the circuit board 13 by bonding the solder terminals 12 to the connection pads 14 by a bonding device (not shown). As described above, the connection pad 3 of the semiconductor device 1 and the connection pad 14 of the circuit board 13 are electrically connected via the base metal layer 8, the rewiring 9, the columnar electrode 10, and the solder terminal 12.

  The semiconductor device 1 is mounted on the circuit board 13 by a face-down method and a reflow method. That is, first, the circuit board 13 is placed on a stage (not shown). The semiconductor device 1 moves above the circuit board 13 with the surface on which the solder terminals 12 are formed facing downward. Next, alignment adjustment is performed so that each solder terminal 12 is aligned with each corresponding connection pad 14 in plan view. Then, the solder terminal 12 and the connection pad 14 are pressed so as to contact each other, and in this state, the solder terminal 12 is heated so as to melt at least a part of the solder terminal 12 in contact with the connection pad 14. In a sufficient area. Thereafter, the solder terminal 12 is completely solidified by cooling to complete the soldering to the connection pad 14.

  Here, in the present invention, when the diameter of the columnar electrode 10 is D, and the diameter of the opening 17 of the protective insulating layer 16 on the upper surface 16A side of the protective insulating layer 16 is R, R is 0.9D ≦ R ≦. A range of 0.98D is preferable, and R = 0.940D (* 0.940 = 235/250) ± 0.012D is more preferable. For example, when the diameter of the columnar electrode 10 is 250 μm, R is preferably 225 μm <R <245 μm, and more preferably R = 235 ± 3 μm.

  When R is in the range of 0.9D ≦ R ≦ 0.98D, the lifetime becomes long in the temperature cycle test, and the reliability of bonding can be improved. When the solder terminal 12 breaks, as shown in FIG. 3, a crack 12 a enters from the outer peripheral portion of the joint portion between the solder terminal 12 and the columnar electrode 10, and the outer peripheral portion at the interface between the solder terminal 12 and the protective insulating layer 16. To crack 12b. In this way, since the extension of the cracks 12a and 12b is dispersed in the upper and lower portions of the solder terminal 12 that expands and contracts due to a temperature change, the life becomes longer and the variation in the life can be reduced. As described above, the solder terminal 12 is subject to thermal stress due to the difference in thermal expansion coefficient between the columnar electrode 10 and the connection pad 14 and has a low rigidity, so that the solder terminal 12 is likely to crack.

On the other hand, when R <0.9D, as shown in FIG. 4, a crack 12 a is first formed from the outer peripheral portion of the joint portion between the solder terminal 12 and the columnar electrode 10. Further, when R> 0.98D, as shown in FIG. 5, the crack 12b is first formed from the outer peripheral portion of the interface between the solder terminal 12 and the protective insulating layer 16. For this reason, since the extension of cracks is concentrated on a part of the solder terminal 12, the life is shortened and the variation in the life is increased. Note that the circuit board may not be used as long as the wiring structure has a connection pad and a protective insulating layer formed around the connection pad. Although the diameter of the columnar electrode 10 is 250 μm, the number of failure cycles of 0.1% can be suppressed if the relationship between R and D satisfies 0.9D ≦ R ≦ 0.98D.
Hereinafter, an example is given and demonstrated.

A semiconductor device in which a solder terminal having a diameter of 340 μm was provided on a columnar electrode having a diameter of 250 μm was mounted on a circuit board by a face-down method and a reflow method. The thickness of the protective insulating layer 16 is 40 μm.
[Comparative Example 1]
The openings in the protective insulating layer of the circuit board had an average diameter on the surface side of about 215 μm.
[Example 1]
The openings in the protective insulating layer of the circuit board had an average diameter on the surface side of about 225 μm. The variation distribution of the opening diameters of the openings is shown in the histogram of FIG.
[Example 2]
The openings in the protective insulating layer of the circuit board had an average diameter on the surface side of about 235 μm. The histogram of the opening diameter variation of the opening is shown in the histogram of FIG. In addition, about 85% of the whole Example 2 is the semiconductor device 1 of the opening 17 within the range of R = 235 ± 3 μm.
Example 3
The openings in the protective insulating layer of the circuit board had an average diameter on the surface side of about 245 μm. The variation distribution of the opening diameters of the openings is shown in the histogram of FIG.

[Temperature cycle test conditions]
The mounted semiconductor device and circuit board were heated from −25 ° C. to 125 ° C. in 1 minute and maintained at 125 ° C. for 9 minutes. Then, it cooled from 125 degreeC to -25 degreeC in 1 minute, and maintained at -25 degreeC for 9 minutes. This was taken as one cycle, and the failure rate relative to the number of cycles was determined. Inventor required confirmation. Specifically, after passing through a predetermined cycle, the semiconductor device and the circuit board were cut out, embedded in resin, and then cut out and observed. A broken solder terminal was regarded as a failure.

  FIG. 9 is a Weibull plot in which the number of cycles and the failure rate are plotted. Note that the lower horizontal axis is the number of cycles (t), and the upper horizontal axis is the natural logarithm (tnt) of t. The left vertical axis is the cumulative failure rate (F (t)), and the right vertical axis is ln {ln1 / (1-F (t)}, where ln {ln1 / (1- The slope m of the approximate straight line plotting F (t)} is the Weibull coefficient, and it can be seen that the smaller the Weibull coefficient m, the smaller the variation in life, and ln {ln1 / (1-F (t )} And the value of t at the intersection of F (t) = 0.1, the lifespan with a cumulative failure rate of 0.1% or less can be compared. A diameter, a Weibull coefficient m, an average failure cycle number, and a 0.1% failure cycle number are shown in Table 1. A range in which the 0.1% failure cycle number is 250 or more, that is, 0.9D ≦ R ≦ 0.98D. Range (diameter D of the columnar electrode 10 = 225 μm ≦ R ≦ 24 in terms of 250 μm) μm) is preferable, and the range in which the 0.1% failure cycle number is 500 or more, that is, the range of 0.928D ≦ R ≦ 0.952D (the diameter D of the columnar electrode 10 = 232 μm ≦ R ≦ 238 μm in terms of 250 μm). More preferred.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3, 14 Connection pad 4 Insulating film 5, 7, 17 Opening part 6 Protective film 8 Base metal layer 9 Rewiring 10 Columnar electrode 11 Sealing film 12 Solder terminal 13 Circuit board 16 Protective insulating layer

Claims (3)

A semiconductor device having a columnar electrode with a diameter D and a solder terminal connected to the columnar electrode;
A connection pad connected to the solder terminal and an opening for opening the connection pad are formed, and a diameter R of the opening in a state where the connection pad is connected to the solder terminal is 0.9D ≦ R ≦ 0. A to-be-connected medium having a protective insulating layer satisfying .98D;
A mounting structure of a semiconductor device, comprising:   2. The semiconductor device mounting structure according to claim 1, wherein the columnar electrode has a Young's modulus higher than that of the solder terminal.   The semiconductor device mounting structure according to claim 1, wherein the connection pad has a higher Young's modulus than the solder terminal.

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