JP2007141973A - Wiring circuit board with semiconductor components - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring circuit board with semiconductor components which does not easily generate defect such as crack or the like at solder connector during the reflow process of flip-chip connection. <P>SOLUTION: A semiconductor component 100 is flip-chip connected to a substrate side pad array 40 via an individual solder connection 11 at a component side pad array 41. Under the condition at the solder resists 108, 8 in the semiconductor component side and substrate side that an internal diameter at the bottom surface of a substrate side aperture 8h is defined as D, and an internal diameter at the bottom surface of a component side aperture 108h is defined as D0; D0/D is adjusted to 0.70 or higher but 0.99 or lower. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wiring board with a semiconductor component.

JP 2002-031889 A "Development of highly reliable Sn-Ag lead-free solder" Toyota Central R & D Review Vol. 35 No. 2 (2000) 39 pages

  Among wiring boards used for connecting semiconductor components such as IC or LSI, what is called an organic package board is a dielectric made of a polymer material so that the first main surface is formed of a dielectric layer. A substrate side having a plurality of metal terminal pads disposed on a first main surface formed of a dielectric layer of the wiring laminate portion, wherein the body laminate portion and the conductor layer are alternately laminated; A pad array is formed. On the second main surface side of the semiconductor component, there is formed a component-side terminal array composed of a plurality of terminal pads arranged individually corresponding to the metal terminal pads forming the substrate-side pad array. Flip chip connection is made to the pad array via individual solder connections. The first main surface of the wiring board and the second main surface of the semiconductor component are made of a heat-resistant resin for protecting against molten solder, and are covered with a solder resist layer having openings at individual pad positions (for example, patents) Reference 1).

In recent years, the trend toward high integration and miniaturization of semiconductor components has been remarkable, and the terminal arrangement interval in the array on the component side has also rapidly decreased. In the flip-chip connection structure with reduced terminal spacing as described above, cracks due to stress derived from the difference in linear expansion coefficient between the semiconductor component and the wiring board are more likely to enter the solder connection portion during cooling after the reflow heat treatment. It was found that connection failure is likely to occur. For example, when the semiconductor component is a Si integrated circuit, the linear expansion coefficient of Si is about 4 × 10 ⁻⁶ / ° C., while the linear expansion coefficient of the polymer material forming the dielectric layer of the wiring board is 3 to 4 ^{X10 −5} / ° C., which is nearly 10 times larger, and there is a concern about the generation of stress due to the difference in linear expansion coefficient, and hence the occurrence of cracks. In recent years, so-called Pb-free solder that does not contain Pb has been used instead of the conventional Sn-Pb eutectic solder due to the problem of environmental pollution. Pb-free solder has a high reflow temperature, and cracks are more likely to occur in the solder connection portion after reflow cooling.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring board with a semiconductor component that hardly causes a defect such as a crack in a solder connection part during a reflow process of flip chip connection.

Means for Solving the Invention and Effects of the Invention

In order to solve the above problems, the wiring board of the present invention is:
A wiring laminated portion in which dielectric layers and conductor layers made of a polymer material are alternately laminated so that the first main surface is formed by a dielectric layer, and a dielectric layer of the wiring laminated portion. A board-side pad array composed of a plurality of metal terminal pads arranged on the first main surface, and a metal terminal pad of the board-side pad array arranged on the first main surface of the wiring laminated portion. A wiring board provided with a board-side solder resist layer in which the board-side opening is individually formed;
A component-side terminal array comprising a plurality of terminal pads arranged individually corresponding to the metal terminal pads forming the substrate-side pad array is provided on the second main surface of the substrate, and the substrate-side pad array is formed by the component-side terminal array. And electronic circuit component parts flip-chip connected through individual solder connections,
D0 / D is adjusted to 0.70 or more and 0.99 or less, where D is the bottom inner diameter of the substrate side opening and D0 is the bottom inner diameter of the component side opening.

As a result of further intensive studies by the present inventors, D0 / D is 0.70 or more and 0.99 or less, where D is the bottom inner diameter of the substrate side opening and D0 is the connection cross-sectional diameter of the solder connection part on the semiconductor component side. As a result, it was found that cracks in the solder connection portion can be extremely effectively prevented, and the present invention has been completed. When D0 / D is less than 0.70, the crack occurrence frequency in the solder connection portion increases. Moreover, when D0 / D exceeds 0.99, the short-circuit prevention effect between adjacent solder connection parts will be insufficient. D0 / D is more preferably 0.70 or more and 0.97 or less, and further preferably 0.80 or more and 0.95 or less.

  The effect of the present invention is particularly prominent when the solder connection portion is composed of a combination of a plurality of solder portions each formed of solder having a different composition. That is, a discontinuous interface of a metal structure is likely to occur at the boundary between solder parts having different compositions, and cracks due to thermal stress are particularly likely to occur. However, when the present invention is applied, the occurrence of cracks can be greatly suppressed even when the discontinuous interface is formed. In particular, the plurality of solder parts constituting the solder connection part are in contact with the first solder part in contact with the substrate terminal, the first solder part and the component-side terminal, and have a higher melting point than the first solder part. In the case of having two solder portions, a discontinuous interface of the structure is likely to occur between the high melting point second solder portion on the component side and the low melting point first solder portion on the substrate side. Application is particularly effective.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 3 schematically shows a cross-sectional structure of a wiring board 300 with a semiconductor component according to an embodiment of the present invention. First, the wiring board 1 has dielectric layers V1, V2 made of a polymer material and conductor layers M1, M2, M3 alternately laminated so that the first main surface is formed of the dielectric layer V2. It has a wiring laminated portion L1. On the first main surface formed of the dielectric layer V2 of the wiring laminated portion L1, a plurality of metal terminal pads (hereinafter referred to as substrate-side first pads or simply referred to as first pads) 10 are disposed. As shown in FIG. 1, the substrate-side pad array 40 is formed in a grid (or zigzag) pattern.

  As shown in FIG. 3, on the first main surface of the wiring laminated portion L1, substrate side openings for exposing the first pads (metal terminal pads) 10 of the substrate side pad array 40 are individually provided for 8h. The formed substrate side solder resist layer 8 is disposed. On the other hand, the semiconductor component 100 is flip-chip connected to the board-side pad array 40 via the solder connection portion 11. The semiconductor component 100 is a silicon integrated circuit component, and a plurality of terminal pads (hereinafter also referred to as component-side pads) arranged individually corresponding to the metal terminal pads 10 forming the substrate-side pad array 40 on the second main surface side of the semiconductor component 100. ) 110 is provided. The semiconductor component 100 is flip-chip connected to the substrate-side pad array 40 via the individual solder connection portions 11 at the component-side terminal array 41.

  Hereinafter, details of the structure of the wiring board 1 will be further described. The wiring board 1 has a predetermined pattern on both surfaces of a plate-like core 2 made of a heat-resistant resin plate (for example, bismaleimide-triazine resin plate) or a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin). Core conductor layers M1 and M11 forming a wiring metal layer are formed. These core conductor layers M1 and M11 are formed as a plane conductor pattern that covers most of the surface of the plate-like core 2, and are used as a power supply layer or a ground layer. On the other hand, a through-hole 12 drilled by a drill or the like is formed in the plate-like core 2, and a through-hole conductor 30 that connects the core conductor layers M 1 and M 11 to each other is formed on the inner wall surface thereof. The through hole 12 is filled with a resin filling material 31 such as an epoxy resin.

  In addition, first via layers (buildup layers: dielectric layers) V1 and V11 made of the photosensitive resin composition 6 are formed on the core conductor layers M1 and M11, respectively. Further, first conductor layers M2 and M12 each having a metal wiring 7 are formed on the surface by Cu plating. The core conductor layers M1 and M11 and the first conductor layers M2 and M12 are interconnected by vias 34, respectively. Similarly, second via layers (build-up layers: dielectric layers) V2 and V12 using the photosensitive resin composition 6 are formed on the first conductor layers M2 and M12, respectively. On the surface, second conductor layers M3 and M13 having metal terminal pads 8 and 18 are formed. The first conductor layers M2, M12 and the second conductor layers M3, M13 are connected to each other by vias 34. As shown in FIG. 3, the via 34 has a via hole 34h and a via conductor 34s provided on the inner peripheral surface thereof, a via pad 34p provided so as to be electrically connected to the via conductor 34s on the bottom surface side, and the via pad 34p. On the side, a via pad 34l projecting outward from the peripheral edge of the opening of the via conductor 34h is provided.

  On the first main surface MP1 of the plate-like core 2, the core conductor layer M1, the first via layer V1, the first conductor layer M2, and the second via layer V2 form the first wiring laminated portion L1. Further, on the second main surface MP2 of the plate-like core 2, the core conductor layer M11, the first via layer V11, the first conductor layer M12, and the second via layer V12 form the second wiring laminated portion L2. . In either case, dielectric layers and conductor layers are alternately laminated so that the first main surface CP is formed of the dielectric layer 6. Metal terminal pads 10 to 17 are respectively formed. The metal terminal pad 10 on the first wiring laminated portion L1 side constitutes a solder pad that is a pad for flip-chip connection of an integrated circuit component or the like. Further, the metal terminal pad 17 on the second wiring laminated portion L2 side is used as a back surface pad for connecting the wiring board itself to a mother board or the like by a pin grid array (PGA) or a ball grid array (BGA). . As shown in FIG. 2, the second side pads 17 in the second conductor layer M13 are also arranged in a lattice pattern. Solder resist layers 8 and 18 (SR1 and SR11) made of a photosensitive resin composition are formed on the second conductor layers M3 and M13, respectively. In either case, in order to expose the first side pad 10 or the second side pad 17, openings 8 h and 18 h are formed in a one-to-one correspondence with each pad.

  The via layers V1, V11, V2, V12 and the solder resist layers 8, 18 are manufactured, for example, as follows. That is, a photosensitive adhesive film formed by forming a photosensitive resin composition varnish is laminated (bonded), and a transparent mask (for example, a glass mask) having a pattern corresponding to the via hole 34h is overlaid and exposed. The film portions other than the via hole 34h are cured by this exposure, while the via hole 34h portion remains uncured, so that the via hole 34h can be easily formed in an intended pattern by removing it by dissolving it in a solvent. (So-called photovia process).

  Both the first main surface of the first wiring laminated portion L1 and the second main surface of the second wiring laminated portion L2 are covered with the solder resist layers 8 and 18, and the solder resist layers 8 and 18 The inner peripheral edges of the openings 8 h and 18 h are located so as to protrude inward from the main surface outer peripheral edges of the metal terminal pads 10 and 17.

  As shown in FIG. 4, D0 / D is 0.70 or more and 0.99 or less (preferably 0), where D is the bottom inner diameter of the substrate-side opening 8h and D0 is the connection cross-sectional diameter of the solder connection portion 11 on the semiconductor component side. 70 to 0.97, more preferably 0.80 to 0.95: for example 0.92). In addition, the inner diameter of both the board-side opening 8h and the component-side terminal pad 110 is, for example, 100 μm or more and 150 μm or less.

  When the semiconductor component 100 is flip-chip connected to the wiring substrate 1 via the solder connection portion 11, solder reflow heat treatment for forming the solder connection portion 11 is performed. The temperature of the reflow heat treatment is set higher than the melting point of the solder constituting the solder connection portion 11. When the melting point is Tm and the reflow temperature is Tm + ΔT, ΔT is usually set to 1 ° C. or more and 100 ° C. or less. In FIG. 4, the entire solder connection portion 11 is composed of a single material Sn-based solder. For example, a solder pattern is printed on the substrate side opening 8h side by using a solder paste, or the component side opening is formed. Solder balls are connected in advance to the portion 108h side, and the semiconductor component 100 is mounted on the wiring substrate 1 while being positioned between the corresponding substrate side opening 8h and the component side opening 108h, and inserted into the reflow furnace. The solder connection part 11 is formed by melting the solder and then cooling. As described above, if D0 / D is adjusted to 0.70 or more and 0.99 or less, it is possible to effectively suppress a defect in which a crack C occurs in the solder connection portion 11 during cooling after reflow.

  The substrate-side opening 8h has a distance between the centers of the closest ones of 160 μm or more and 400 μm or less. When the center-to-center distance is less than 160 μm, the connection strength by the solder connection portion 11 is more likely to be insufficient, and the crack is likely to occur. Further, when the semiconductor component 100 is mounted on the wiring board 1, the positioning process of the substrate side opening 8h and the component side opening 108h becomes difficult, and misalignment is likely to occur. On the other hand, the distance between the centers is preferably 180 μm or less. By making the terminal spacing fine, the degree of freedom in wiring design increases. Here, the distance between the centers needs to be equal to or larger than the diameter of the board-side opening 8h, and is preferably 30 μm or more larger than the inner diameter in consideration of a short circuit between adjacent solder connection portions.

  Although the solder connection part 11 can also be comprised by Sn-Pb eutectic solder, in recent years, instead of the conventional Sn-Pb eutectic solder, what is called Pb-free solder which does not contain Pb is replaced with the conventional Sn-Pb eutectic solder. Has come to be used. Most Pb-free solders are composed mainly of Sn as in conventional eutectic solder, but contain Ag, Cu, Zn, Bi, etc. as subcomponents instead of Pb used in eutectic solder. To do. Eclectic solder that contains the main component of subcomponents with these elements but leaves some Pb content is also used.

  Specifically, all or part of the solder connection portion 11 can be an Sn-based high-temperature solder portion made of an Sn alloy having a liquidus temperature of 200 ° C. or higher and lower than 232 ° C. Sn—Pb eutectic solder has a eutectic composition of Sn-38 mass% Pb and a melting point of 183 ° C. Even if shifting from this composition to the Pb rich side or the Sn rich side, the melting point (liquidus) of the alloy rises. A single Sn metal is equivalent to one in which all Pb is simply reduced from eutectic solder, but the melting point is 232 ° C., which is nearly 50 ° C. higher than the melting point of eutectic solder. difficult.

  In this case, for the Sn-based high-temperature solder portion that can be adopted, Sn is the main component (referring to a content of 62% by mass or more in the eutectic solder), and the main eutectic forming component is searched for from elements other than Pb. When an attempt is made to configure a solder member from an Sn alloy having a Pb content significantly reduced from Sn—Pb eutectic solder, it becomes inevitable that the melting point of the solder becomes a high-temperature solder exceeding 200 ° C. (the upper limit is Sn alone) 232 ° C.). For example, even in the Pb-free solders having various compositions listed in Table 1 of Non-Patent Document 1, the melting points (liquidus temperatures) Ts are all 200 ° C. or higher. From the viewpoint of environmental protection, the Sn alloy constituting the high-temperature solder member has a Pb content of 5% by mass or less (more preferably 1% by mass or less, more preferably an inevitable impurity level). Except for those, Pb should not be contained as much as possible).

  The secondary component added to Sn in Sn-based high-temperature solder has the effect of lowering the melting point as much as possible, and the addition amount is small even if the price is low or somewhat expensive, solderability and flowability Is good, and is excellent in corrosion resistance. However, the types of subcomponents having these in a balanced manner are unexpectedly limited, and are only a few elements such as Zn, Bi, Ag, and Cu. The Sn—Zn system has a eutectic point in the vicinity of 15% by mass Zn, and the melting point decreases to about 195 ° C. with this composition. However, Zn has a difficulty in corrosion resistance, and usually the addition amount of about 7 to 10% by mass is kept, but in the binary system in the vicinity of the composition, the melting point is lowered only to about 215 ° C. Then, although 1-5 mass% Bi is added and melting | fusing point adjustment is carried out, it is difficult to finally obtain melting | fusing point below 200 degreeC. Furthermore, since Bi is expensive and is a strategic substance, there is a difficulty in supply stability.

  On the other hand, Ag and Cu alone have a much higher melting point than Sn, but Sn-Ag system is about 5 mass% Ag, and Sn-Cu system is about 2 mass% Cu, both Sn-rich. There is a eutectic point on the side. Further, the Ag—Cu system is also a eutectic system, and the melting point can be further lowered by using a ternary eutectic of Sn—Ag—Cu. However, both the Sn-Ag system and the Sn-Cu system have a binary eutectic temperature of around 220 ° C, and even if a ternary eutectic system is adopted, it is impossible to lower the melting point to 200 ° C or lower. . In the case of Sn—Ag alloy, the recommended composition from the viewpoint of lowering the melting point is that Ag content is 3% by mass or more and 6% by mass or less with respect to Sn. Similarly, in the case of a Sn—Cu based alloy, the Cu content is 1% by mass or more and 3% by mass or less with respect to Sn. Furthermore, in the case of a Sn—Ag—Cu alloy, Ag + Cu is 3% by mass or more and 6% by mass or less, and Cu / (Ag + Cu) is 0.1 or more and 0.5 or less by mass ratio. In either case, the melting point of the solder is 200 ° C. or higher.

  When all of the solder connection portions 11 are Sn-based high-temperature solder portions as described above, the Sn-based high-temperature solder is less ductile than the Sn—Pb eutectic solder, and the reflow heat treatment temperature is increased. Thermal stress levels tend to be high and cracks C tend to be more likely to occur. Therefore, the effect of suppressing the occurrence of cracks C is particularly noticeable by applying the present invention.

  Next, as shown in FIG. 6, only a part of the solder connection portion 11 may be an Sn-based high-temperature solder portion 11 </ b> A, and the remaining portion 11 </ b> B may be formed of solder at a lower temperature than the Sn-based high-temperature solder portion. It is. In this case, a systematic discontinuity is likely to occur at the boundary position between the two solder portions 11A and 11B, and the occurrence of a crack at the boundary may easily proceed. It can be said that it is effective.

  Specifically, the solder connection portion 11 fills the substrate side opening 8h, and also includes an Sn-based low-temperature solder portion 11B made of an Sn alloy having a lower melting point than the Sn-based high-temperature solder portion 11A, and the Sn of the solder connection portion 11. It can comprise as what consists of Sn type | system | group high temperature solder part 11A which makes the remainder part of the system low temperature solder part 11B. In this case, in the two solder parts 11A and 11B, the types and contents of components other than Sn are greatly different, and systematic discontinuities are particularly likely to occur at the boundary positions of the solder parts. The ripple effect of crack suppression is particularly remarkable.

  The Sn-based low-temperature solder part 11B can be composed of Sn—Pb eutectic solder. The Sn—Pb eutectic solder has a low reflow temperature and good solder flowability. For example, as shown in FIG. 5, an Sn-based high-temperature solder portion 11A ′ is formed in the component-side opening 108h in advance, If the bonding auxiliary solder part 11B ′ is filled and formed in the substrate side opening 8h by printing or the like using Sn—Pb eutectic solder paste, the solder connection part 11 after reflow shown in FIG. The amount of Sn-based low-temperature solder portion with a high Pb content can be greatly reduced, and the reflow temperature can be kept low despite the fact that Sn-based high-temperature solder is mainly used. However, in the Sn-Pb eutectic solder, the non-Sn eutectic phase mainly consists of Pb having a large specific gravity, and the amount of the non-Sn eutectic eutectic phase is larger than that of the Sn-based high-temperature solder. A systematic discontinuity is particularly likely to occur between the Sn—Pb eutectic solder portion 11B and cracks at the boundary between both portions are also likely to occur. Therefore, the effect is more effectively exhibited by the application of the present invention.

  In order to confirm the effect of the present invention, the following experiment was conducted. 1-3, the total number of pads arranged in a grid pattern is 3,500, the height of the solder connection portions 11 is 80 μm, the arrangement interval is 200 μm, and the component-side connection cross-sectional diameter D0 and the bottom surface inner diameter D of the substrate side opening 8h were each changed in the range of 110 μm to 175 μm. A Sn-Pb eutectic solder paste is applied onto the pad 10 on the wiring board side, while a Pb-free solder having a ternary eutectic composition of Sn-Ag-Cu is applied to the semiconductor component side made of a silicon integrated circuit component. Bumps were used and flip chip connection was made at a reflow temperature of 227 ° C. After that, the connected parts and the substrate are cut and polished vertically along the central row (60 pieces) of the grid-like solder connection portion array, and the occurrence of cracks inside each solder connection portion is observed with an optical microscope. As a result, the crack over the entire cross section of the connecting portion was identified as mode A, the crack having half or less of the cross section diameter of the connecting portion as mode B, and the crack generated only at the end of the cross section of the connecting portion was identified as mode C. And it is excellent (A) that no cracks in any of modes A to C were detected (A), cracks in modes A and B are not detected, and only one mode C crack is good (O), Two to five cracks in mode C were allowed (Δ), and one in which even one crack in modes A and B was detected was judged as impossible (x). The above results are shown in FIG. From this result, it is clear that good results are obtained when D0 / D is 0.70 or more and 0.99 or less.

The top view which shows one Embodiment of a wiring board. Similarly back view. The figure which shows an example of the cross-section of the wiring board with a semiconductor component which concerns on this invention. The expanded sectional view which shows a solder connection structure typically. The schematic diagram which shows the modification of the formation method of a solder connection structure. The expanded sectional view which shows typically the solder connection structure obtained by the method of FIG. The figure which shows the experimental result done in order to confirm the effect of this invention.

Explanation of symbols

1 Wiring Board 8 Board Side Solder Resist Layer 8h Board Side Opening 10 First Pad (Metal Terminal Pad)
DESCRIPTION OF SYMBOLS 11 Solder connection part 40 Board | substrate side pad array 41 Component side pad array 100 Semiconductor component 108 Component side soldering resist layer 110 Metal terminal pad

Claims (8)

A wiring laminated portion in which a dielectric layer made of a polymer material and a conductor layer are alternately laminated so that the first main surface is formed of a dielectric layer; and the dielectric layer of the wiring laminated portion. A board-side pad array composed of a plurality of metal terminal pads arranged on the formed first main surface, and the metal terminals of the board-side pad array arranged on the first main surface of the wiring laminated portion. A wiring board including a board side solder resist layer in which board side openings for exposing the pads are individually formed;
A component-side terminal array comprising a plurality of terminal pads arranged individually corresponding to the metal terminal pads forming the substrate-side pad array is provided on the second main surface side of the substrate. The component-side terminal array includes the component-side terminal array. A semiconductor component flip-chip connected to the pad array via individual solder connections,
A wiring board with a semiconductor component, wherein D0 / D is adjusted to 0.70 or more and 0.99 or less, where D is a bottom inner diameter of the opening on the substrate side and D0 is a connection cross-sectional diameter on the semiconductor component side of the solder connection portion. 2. The semiconductor according to claim 1, wherein D0 / D is adjusted to 0.70 or more and 0.95 or less, wherein D is an inner diameter of the bottom surface of the opening on the substrate side and D0 is a connection cross-sectional diameter on the semiconductor component side of the solder connection portion. Wiring board with components. 3. The wiring board with a semiconductor component according to claim 1, wherein the distance between the centers of the closest openings in the substrate side is 160 μm or more and 400 μm or less. The wiring board with a semiconductor component according to any one of claims 1 to 3, wherein the solder connection portion is formed of a combination of a plurality of solder portions each formed of solder having a different composition. The plurality of solder parts constituting the solder connection part are in contact with the first solder part in contact with the board-side pad array, the first solder part and the component-side terminal array, and the first solder part. The wiring board with a semiconductor component according to claim 4, further comprising a second solder part having a melting point higher than that of the semiconductor component. 4. The solder connection part according to claim 1, wherein all or a part of the solder connection part is an Sn-based high-temperature solder part made of an Sn alloy having a liquidus temperature of 200 ° C. or higher and lower than 232 ° C. 5. Wiring board with semiconductor parts. The solder connection portion fills the substrate-side opening, and includes an Sn-based low-temperature solder portion made of an Sn alloy having a lower melting point than the Sn-based high-temperature solder portion, and the Sn-based low-temperature solder portion of the solder connection portion. The wiring board with a semiconductor component according to claim 6, comprising the Sn-based high-temperature solder portion forming the remaining portion. The wiring board with a semiconductor component according to claim 7, wherein the Sn-based low-temperature solder portion is composed of Sn—Pb eutectic solder.

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