JP2011061545A - Pll circuit and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To independently set up stability and frequency pull-in speed while suppressing an increase in the circuit scale of a PLL circuit. <P>SOLUTION: A PLL circuit 1 has: a ring oscillator 2 which generates an oscillation signal through a delay closed loop 19 for delaying a signal; a phase comparator 3; a charge pump 4; a smoothing filter 5; a smoothing current source 6; a delay component filter 7; and a correction current source 8. The delay component filter 7 is connected to the output of the charge pump 4 in parallel with the smoothing filter 5 and extracts a response delay component included in the output signal of the charge pump 4. The ring oscillator 2 has a delay section 11, which is operated by a current supplied from at least one of the smoothing current source 6 and the correction current source 8, and delays a signal, as a delay section for delaying a signal in the delay closed loop 19. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit and an electronic device that generate an oscillation signal whose phase is synchronized with a reference signal.

Patent Document 1 discloses a PLL circuit.
This PLL circuit forms a closed loop functioning as a control loop by a phase comparator, a charge pump, a filter, an adder, and a voltage controlled oscillator.
Further, in the PLL circuit of Patent Document 1, the filter includes a first-order response delay unit configured by connecting two or more circuit elements.
The adder has two voltage-current control conversion units and a current-voltage conversion unit.
The current-voltage conversion unit adds the current signals generated by the two voltage-current control conversion units, and outputs a voltage level signal corresponding to the addition result of the signals to the voltage-controlled oscillator.

For this reason, in Patent Document 1, the output current of the charge pump, which is likely to be a noise source that affects jitter, and the attenuation coefficient ζ indicating the stability of the PLL circuit are set to constant values, and the frequency pull-in of the PLL circuit is set. The band ω indicating the speed can be set independently.
Specifically, for example, in the PLL circuit of Patent Document 1, the voltage-current conversion coefficients gm1 and gm2 of the two voltage-current control conversion units can be adjusted while the output current of the charge pump is made constant.
By this adjustment, the attenuation coefficient ζ and the band ω can be set independently in the PLL circuit of Patent Document 1.

Japanese Patent Laid-Open No. 9-312565

  However, as in Patent Document 1, by adjusting the voltage / current conversion coefficients gm1 and gm2 of the two voltage / current control conversion units included in the control loop, the attenuation coefficient ζ and the band ω of the PLL circuit can be set independently. In this case, there are the following problems.

For example, in the PLL circuit of Patent Document 1, an adder having two voltage-current control conversion units and a current-voltage conversion unit is inserted as a circuit to be inserted between a filter in a control loop and a voltage-controlled oscillator. .
For this reason, the circuit scale of the PLL circuit of Patent Document 1 increases.

Further, in order to make it possible to adjust the band ω with fine resolution in the PLL circuit of Patent Document 1, it is necessary to configure the voltage-current conversion coefficients gm1 and gm2 of the two voltage-current control conversion units so that they can be adjusted with fine resolution. is there.
In Patent Document 1, the outputs of the voltage-current conversion coefficients gm1 and gm2 are added by an adding unit. Therefore, it is necessary that the balance between the two voltage-current conversion coefficients gm1 and gm2 to be added does not vary relatively.
As a result, in the PLL circuit of Patent Document 1, in order to make the resolution fine, it is necessary to make the balance between the two voltage-current conversion coefficients gm1 and gm2 relatively not vary depending on the adjustment contents.
In the PLL circuit of Patent Document 1, an adjustment circuit or a compensation circuit for suppressing relative variation is separately required.
Therefore, in the PLL circuit of Patent Document 1, if the band ω is adjusted with a fine resolution, the circuit scale is greatly increased.

  As described above, the PLL circuit is required to be able to independently set the stability and the frequency pull-in speed of the PLL circuit while suppressing an increase in circuit scale.

  A PLL circuit according to a first aspect of the present invention is connected to a ring oscillation unit that generates an oscillation signal by a delay closed loop that delays a signal, a phase comparison unit that compares phases of the oscillation signal and a reference signal, and a phase comparison unit Charge pump, a smoothing filter connected to the charge pump, a smoothing current source connected to the smoothing filter and supplying a smoothing current according to the output signal smoothed by the smoothing filter to the ring oscillation unit, and a smoothing filter Is connected to the output of the charge pump in parallel with the delay component filter for extracting the response delay component included in the output signal of the charge pump, and a ring for generating a correction current according to the response delay component extracted by the delay component filter. A correction current source that supplies the oscillation unit. The ring oscillation unit includes a delay unit that operates as a delay unit that delays a signal in the delay closed loop and that operates by a current supplied from at least one of a smoothing current source and a correction current source to delay the signal.

  Preferably, the ring oscillating unit includes at least one delay unit that delays a signal by a transistor that performs a switching operation under a driving current, and includes a delay closed loop including all or a part of at least one delay unit. An oscillation signal is generated, a smoothing current source is connected to a smoothing filter, and a signal smoothed by a smoothing filter with respect to all or a part of at least one delay unit constituting the ring oscillation unit The correction current source supplies the correction current to all or some of the delay units of at least one stage constituting the ring oscillation unit independently of the smooth current source. The transistor of the delay unit of at least one stage of the ring oscillation unit is switched using at least one of the smoothing current and the correction current as a driving current. Grayed may operate.

  Preferably, the ring oscillation unit has a plurality of delay units to which the smoothing current source and the correction current source are connected together, and the smoothing current source is connected to the entire plurality of delay units connected to the smoothing current source. Then, the smoothing current may be supplied, and the correction current source may supply the correction current to the entirety of the plurality of delay units connected to the correction current source.

  Preferably, the ring oscillating unit includes a plurality of delay units, and the smoothing current source is provided in a one-to-one correspondence with all or part of the plurality of delay units of the ring oscillating unit. The correction current source is connected to each of the delay units connected one by one, and the correction current source is all or part of the plurality of delay units of the ring oscillation unit by the same association as the smooth current source. May be provided in a one-to-one correspondence, connected to each delay unit one by one, and a correction current may be supplied to each connected delay unit.

According to the first aspect, an oscillation signal whose phase is synchronized with a reference signal can be generated by a control loop including a ring oscillation unit, a phase comparison unit, a charge pump, and a smoothing filter.
Further, in the first aspect, a delay component filter is connected in parallel with the smoothing filter to the output of the charge pump so as to be out of the control loop, and the response delay included in the output signal of the charge pump by this delay component filter. Extract ingredients.
The correction current source generates a correction current corresponding to the response delay component included in the output signal of the charge pump and supplies the correction current to the ring oscillation unit.
The ring oscillation unit includes a delay unit that operates using the current supplied from the correction current source and delays the signal as a delay unit that delays the signal in the delay closed loop.
Therefore, when the phase relationship between the oscillation signal and the reference signal that are compared in the phase comparison unit changes and the output signal of the charge pump changes, the response delay component included in the changed output signal causes a delay closed loop of the ring oscillation unit. It is possible to control the amount of delay of the signal at.
Thus, in the first aspect, the control response delay can be improved by the delay component filter and the correction current source extrapolated to the control loop while obtaining the stability of the frequency of the oscillation signal by the control loop.
Moreover, in the first aspect, the above effect is obtained by adding a delay component filter and a smooth current source to the normal control loop of the PLL circuit.
Therefore, from the first viewpoint, an increase in the scale of the PLL circuit can be suppressed.

  An electronic apparatus according to a second aspect of the present invention includes a PLL circuit that outputs an oscillation signal having a phase synchronized with a reference signal, and an input unit to which the oscillation signal is input. A PLL circuit includes a ring oscillation unit that generates an oscillation signal by a delay closed loop that delays a signal, a phase comparison unit that compares phases of the oscillation signal and a reference signal, a charge pump connected to the phase comparison unit, and a charge pump A smoothing filter connected to the smoothing filter, a smoothing current source connected to the smoothing filter and supplying a smoothing current according to the output signal smoothed by the smoothing filter to the ring oscillation unit, and an output of the charge pump in parallel with the smoothing filter A delay component filter that extracts a response delay component included in the output signal of the charge pump, and a correction current that generates a correction current according to the response delay component extracted by the delay component filter and supplies the correction current to the ring oscillation unit With a source. The ring oscillation unit includes a delay unit that operates as a delay unit that delays a signal in the delay closed loop and that operates by a current supplied from at least one of a smoothing current source and a correction current source to delay the signal.

  In the present invention, the stability of the PLL circuit and the frequency pull-in speed can be set independently while suppressing an increase in the circuit scale of the PLL circuit.

FIG. 1 is a block diagram of a PLL circuit according to the first embodiment of the present invention. FIG. 2 is a circuit diagram of the delay unit of FIG. FIG. 3 is a circuit diagram of the charge pump of FIG. FIG. 4 is a circuit diagram showing a configuration of the three first current sources in FIG. FIG. 5 is a block diagram of a PLL circuit according to the second embodiment of the present invention. FIG. 6 is a block diagram of a PLL circuit according to the third embodiment of the present invention. FIG. 7 is a circuit diagram of the third delay unit of FIG. FIG. 8 is a block diagram of a PLL circuit according to the fourth embodiment of the present invention. FIG. 9 is an explanatory diagram of an oscillation signal generated by the ring oscillation unit of FIG. FIG. 10 is a block diagram of a PLL circuit according to the fifth embodiment of the present invention. FIG. 11 is a block diagram of a PLL circuit according to the sixth embodiment of the present invention. FIG. 12 is a block diagram of a PLL circuit according to the seventh embodiment of the present invention. FIG. 13 is a block diagram showing a current source and a control unit of a PLL circuit according to the eighth embodiment of the present invention. FIG. 14 is a block diagram of a PLL circuit according to the ninth embodiment of the present invention. FIG. 15 is a block diagram of a PLL circuit according to the tenth embodiment of the present invention. FIG. 16 is a block diagram of a broadcast signal receiving apparatus according to the eleventh embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The description will be given in the following order.
1. First Embodiment (an example of a PLL circuit that individually supplies both a first current and a second current to all of a plurality of delay units)
2. Second Embodiment (an example of a PLL circuit that supplies both a first current and a second current to all of a plurality of delay units as a whole)
3. Third Embodiment (Example of PLL circuit having a delay unit to which neither the first current nor the second current is supplied)
4). Fourth embodiment (an example of a PLL circuit that individually supplies a second current to all of a plurality of delay units and individually supplies a first current to some delay units)
5. Fifth Embodiment (Example of PLL circuit that supplies a first current individually to all of a plurality of delay units and supplies a second current individually to some delay units)
6). Sixth Embodiment (Example of PLL circuit that individually supplies a first current to a part of a plurality of delay units and supplies a second current individually to the remaining delay units)
7). Seventh Embodiment (Example of PLL circuit having a delay unit to which neither the first current nor the second current is supplied)
8). Eighth embodiment (an example of a PLL circuit in which the control unit switches and controls the first current and the second current)
9. Ninth embodiment (an example of a PLL circuit in which the control unit individually controls the connection of the first current source and the second current source to the delay unit)
10. Tenth Embodiment (Example of PLL Circuit in which Control Unit Individually Controls Disconnection of Connection of First Current Source to Delay Unit)
11. Eleventh Embodiment (Example of electronic device)

<1. First Embodiment>
[Configuration of PLL Circuit 1]
FIG. 1 is a block diagram of a PLL circuit 1 according to the first embodiment of the present invention.
The PLL circuit 1 in FIG. 1 individually supplies both the first current I1 and the second current I2 to all of the plurality of delay units 11 of the ring oscillation unit 2.
The PLL circuit 1 of FIG. 1 includes a ring oscillation unit 2, a phase comparison unit 3, a charge pump 4, a first filter 5, a plurality of first current sources 6, a second filter 7, and a plurality of second current sources 8. .
1 is a closed loop (hereinafter referred to as a control loop 9) in which a ring oscillation unit 2, a phase comparison unit 3, a charge pump 4, a first filter 5, and a plurality of first current sources 6 are connected. Form.

The ring oscillation unit 2 has a plurality of delay units 11.
In the case of FIG. 1, the ring oscillation unit 2 includes a three-stage delay unit 11.

FIG. 2 is a circuit diagram of the delay unit 11 of FIG.
The delay unit 11 includes a first transistor 12, a second transistor 13, and a third transistor 14. The delay unit 11 includes one input terminal 15, one output terminal 16, a first control terminal 17, and a second control terminal 18.
The first transistor 12 is an Nch MOS transistor. The gate electrode of the first transistor 12 is connected to the input terminal 15. The source electrode is connected to the first current source 6. The drain electrode is connected to the output terminal 16.
The second transistor 13 is an Nch MOS transistor. The gate electrode of the second transistor 13 is connected to the input terminal 15. The source electrode is connected to the second current source 8. The drain electrode is connected to the output terminal 16.
The third transistor 14 is a Pch MOS transistor. The gate electrode of the third transistor 14 is connected to the input terminal 15. The source electrode is connected to a VDD power source (not shown). The drain electrode is connected to the output terminal 16.
With the above connection, the first transistor 12 and the third transistor 14 form a CMOS structure. The second transistor 13 is connected in parallel to the first transistor 12.

For example, when the input terminal 15 of the delay unit 11 is at a high level, the first transistor 12 and the second transistor 13 are turned on. Further, the third transistor 14 is turned off.
Thereby, the first transistor 12 can flow the first current I1 supplied from the first current source 6. The second transistor 13 can pass the second current I2 supplied from the second current source 8. As a result, the output terminal 16 of the delay unit 11 becomes low level.
When the input terminal 15 of the delay unit 11 is at a low level, the first transistor 12 and the second transistor 13 are turned off. Further, the third transistor 14 is turned on.
Thereby, the third transistor 14 can flow a current supplied from the VDD power source. As a result, the output terminal 16 of the delay unit 11 becomes high level.
By the switching operation of the first transistor 12, the second transistor 13, and the third transistor 14, each delay unit 11 outputs a signal obtained by inverting and inverting the signal input to the input terminal 15 according to the switching operation time. Output from terminal 16.

As shown in FIG. 1, the three delay units 11 are connected in three stages in series.
Further, the output terminal 16 of the final stage delay unit 11 is connected to the input terminal 15 of the first stage delay unit 11.
Thereby, the delay closed loop 19 is configured.
As shown in FIG. 1, when the delay closed loop 19 is constituted by the three stages of delay units 11, when the output terminal 16 of the last stage delay unit 11 is at a low level, the first delay unit 11 outputs a high level. The delay unit 11 at the second stage outputs a low level.
Therefore, the consideration terminal of the delay unit 11 at the final stage changes to a high level.
In this manner, the delay closed loop 19 generates an oscillation signal having a period determined according to the delay time of the three-stage delay unit 11 by the three-stage delay unit 11 of FIG.

The phase comparison unit 3 is connected to the output terminal 16 of the final delay unit 11 of the ring oscillation unit 2.
In addition, a crystal oscillator 126 (not shown) is connected to the phase comparison unit 3.
As a result, the oscillation signal generated by the ring oscillation unit 2 and the reference signal generated by the crystal oscillator 126 are input to the phase comparison unit 3.
The phase comparator 3 compares the phases of the oscillation signal and the reference signal, and outputs a signal indicating the direction and magnitude of the phase difference.

FIG. 3 is a circuit diagram of the charge pump 4 of FIG.
The charge pump 4 includes a charge constant current source 21, a charge transistor 22, a discharge transistor 23, and a discharge constant current source 24. Further, the charge pump 4 has a charge input terminal 25, a discharge input terminal 26, and one output terminal 27.
The charging transistor 22 is a Pch MOS transistor. The charging constant current source 21 is connected between the VDD power supply line and the source electrode of the charging transistor 22. The gate electrode of the charging transistor 22 is connected to the charging input terminal 25. The drain electrode of the charging transistor 22 is connected to the output terminal 27.
The discharge transistor 23 is an Nch MOS transistor. The discharge constant current source 24 is connected between the ground and the source electrode of the discharge transistor 23. The gate electrode of the discharge transistor 23 is connected to the discharge input terminal 26. The drain electrode of the discharge transistor 23 is connected to the output terminal 27.

The charge input terminal 25 and the discharge input terminal 26 of the charge pump 4 are connected to the phase comparison unit 3, and a signal generated by the phase comparison unit 3 is input to each of them.
The charge pump 4 outputs a signal corresponding to the comparison in the phase comparison unit 3.
The signal output from the charge pump 4 includes a current having a value corresponding to the comparison in the phase comparison unit 3.
Specifically, for example, when the phase of the oscillation signal is delayed from the reference signal, the charge input terminal 25 of the charge pump 4 is controlled to a low level. As a result, the charging transistor 22 is turned on, and the charge pump 4 causes a charging current to flow from the output terminal 27.
When the phase of the oscillation signal is advanced from the reference signal, the discharge input terminal 26 of the charge pump 4 is controlled to a high level. As a result, the discharge transistor 23 is turned on, and the charge pump 4 draws a charging current from the output terminal 27.
When the phases of the reference signal and the oscillation signal are aligned, both the charge transistor 22 and the discharge transistor 23 are turned off in the charge pump 4. In this case, the charge pump 4 does not output a charging current from the output terminal 27.

As shown in FIG. 1, the first filter 5 includes a second capacitor 31.
One electrode of the second capacitor 31 is connected to the output of the charge pump 4 and the other electrode is connected to the ground. The second capacitor 31 is charged / discharged by the charging current of the charge pump 4.
As a result, the second capacitor 31 generates a DC voltage obtained by removing the AC component from the charging current of the output signal of the charge pump 4.
That is, the first filter 5 generates a voltage V1 obtained by smoothing the output signal of the charge pump 4.

The first current source 6 is provided in a one-to-one correspondence with the plurality of delay units 11 of the ring oscillation unit 2, and supplies the first current I 1 to each of the plurality of delay units 11.
In the case of FIG. 1, the number of the first current sources 6 is three.

FIG. 4 is a circuit diagram showing a configuration of the three first current sources 6 of FIG.
The first current source 6 has one current transistor 41 and one output terminal 42.
The current transistor 41 is an Nch MOS transistor. A gate electrode of the current transistor 41 is connected to the first filter 5. The source electrode is connected to the ground. The drain electrode is connected to the output terminal 42.
The output terminal 42 of the first current source 6 is connected to the source electrode of the first transistor 12 of the delay unit 11 by wiring for each delay unit 11. The output terminal 42 and the source electrode are connected in a one-to-one correspondence.
The current transistor 41 of the first current source 6 forms a channel according to the voltage smoothed by the second capacitor 31 of the first filter 5. Thus, the current transistor 41 supplies the first current I1 corresponding to the smoothed voltage to the first transistor 12 of each delay unit 11 of the ring oscillation unit 2.
The value of the first current I1 increases as the smoothed voltage increases.

As shown in FIG. 1, the second filter 7 includes a first capacitor 51 and a resistance element 52.
One end of the resistance element 52 is connected to the output of the charge pump 4, and the other end is connected to one electrode of the first capacitor 51. The other electrode of the first capacitor 51 is connected to the ground.
Hereinafter, a node connecting the other end of the resistance element 52 and one electrode of the first capacitor 51 is referred to as a connection point 53.
The second filter 7 functions as a low pass filter.
The second filter 7 includes a first capacitor 51 and a resistance element 52. For this reason, the signal output from the second filter 7 has a phase advance component due to the resistance element 52 and a phase delay component due to the first capacitor 51.
On the other hand, the first filter 5 includes only the second capacitor 31. For this reason, the signal output from the first filter 5 has only a phase delay component due to the second capacitor 31.

The second current source 8 is provided in a one-to-one correspondence with each delay unit 11 of the ring oscillation unit 2 and supplies a second current I2 to each delay unit 11. In the case of FIG. 1, the number of the second current sources 8 is three.
The circuit configuration of the second current source 8 is the same as that of the first current source 6 shown in FIG. 4, and the same reference numerals are used for the description of each part, and the description is omitted. However, the gate electrode of the current transistor 41 of the second current source 8 is connected to the connection point 53 of the second filter 7. The output terminal 42 of the second current source 8 is connected to the source electrode of the second transistor 13 of the delay unit 11 by the wiring for each delay unit 11. The output terminal 42 and the source electrode are connected in a one-to-one correspondence.
The second current source 8 supplies the second current I2 corresponding to the voltage at the connection point 53 of the second filter 7 to the second transistor 13 of each delay unit 11 of the ring oscillation unit 2.
The value of the second current I2 increases as the voltage V2 due to the first-order response delay component of the output signal of the charge pump 4 extracted by the second filter 7 increases.

[Operation of PLL circuit 1]
The ring oscillator 2 of the PLL circuit 1 of FIG. 1 generates an oscillation signal by a three-stage delay unit 11.
The phase comparator 3 compares the phases of the oscillation signal and the reference signal, and outputs a signal indicating the direction and magnitude of the phase difference.
The charge pump 4 outputs a signal corresponding to the comparison in the phase comparison unit 3.
The first filter 5 generates a voltage V1 obtained by smoothing the output signal of the charge pump 4.
Each first current source 6 supplies a first current I1 corresponding to the voltage V1 smoothed by the first filter 5 to the first transistor 12 of each delay unit 11 connected thereto.

For example, when the phase of the oscillation signal is delayed from the reference signal, the charge pump 4 causes a current to flow from the output terminal 27.
Thereby, the voltage V1 smoothed by the first filter 5 is increased.
Further, the first current I1 supplied from each first current source 6 to each delay unit 11 is also increased.
As the first current I1 increases, the switching speed of the first transistor 12 increases.
The delay time of the oscillation signal in the three-stage delay unit 11 of the ring oscillation unit 2 is shortened.
The frequency of the oscillation signal increases and the phase advances.

On the other hand, when the phase of the oscillation signal is advanced from the reference signal, the charge pump 4 draws current from the output terminal 27.
Thereby, the voltage V1 smoothed by the first filter 5 is reduced.
In addition, the first current I1 supplied from each first current source 6 to each delay unit 11 is also reduced.
As the first current I1 decreases, the switching speed of the first transistor 12 decreases.
The delay time of the oscillation signal in the three-stage delay unit 11 of the ring oscillation unit 2 becomes longer.
The frequency of the oscillation signal is lowered and the phase is also delayed.
By the above control, the phase of the oscillation signal is aligned with the phase of the reference signal.
In addition, the frequency of the oscillation signal is an integral multiple or a fraction of the frequency of the reference signal.

Further, the second filter 7 extracts a first-order response delay component of the output signal of the charge pump 4.
The second current source 8 supplies a second current I2 corresponding to the primary response delay component of the output signal of the charge pump 4 to the second transistor 13 of each delay unit 11 of the ring oscillation unit 2.
For example, when the current included in the signal output from the charge pump 4 increases, the potential V2 at the connection point 53 of the second filter 7 increases.
The second current source 8 increases the second current I2 supplied to the second transistor 13 of each delay unit 11 of the ring oscillation unit 2.
Therefore, during the period in which the current included in the signal output from the charge pump 4 changes, the increased second current I2 increases the switching speed of the second transistor 13 of each delay unit 11.
The three-stage delay unit 11 of the ring oscillation unit 2 operates so as to shorten the delay time of the oscillation signal.
In addition, the frequency of the oscillation signal increases in an accelerated manner, and the phase advances.
On the other hand, the potential at the connection point 53 of the second filter 7 does not change during a period in which the current included in the signal output from the charge pump 4 is constant.
Therefore, the second current I2 does not change, and the delay time of the oscillation signal by the three-stage delay unit 11 of the ring oscillation unit 2 is stabilized at a constant time.

[Explanation of characteristics using mathematical formulas]
Next, the operation of the PLL circuit 1 of FIG.
The open loop transfer function of the PLL circuit 1 of FIG. Here, the voltage-current conversion coefficient of each first current source 6 is gm1 [A / V], the voltage-current conversion coefficient of each second current source 8 is gm2 [A / V], and the gain of the ring oscillation unit 2 is Kcco. [Rad / s / A].
In addition, in the following formula 1, the capacity of the second capacitor 31 is C2, the capacity of the first capacitor 51 is C1, and C2 ≦ C1.
In Expression 1, Icp is the output current of the charge pump 4.

  Further, the bandwidth ωn of the PLL circuit 1 is expressed by Equation 2, and the attenuation coefficient ζ is expressed by Equation 3.

  As is apparent from Equations 2 and 3, the PLL circuit 1 in FIG. 1 adjusts the ratio of gm1 and gm2 at the time of design even when the output current Icp of the charge pump 4 is kept constant. The damping coefficient ζ can be set independently.

The PLL circuit 1 of the first embodiment having the above configuration and operation has the following effects.
First, in the PLL circuit 1 of the first embodiment, a ring oscillation unit 2, a phase comparison unit 3, a charge pump 4, a first filter 5, and a plurality of first current sources 6 are connected by a control loop 9 connected in that order. The signal can be transmitted by an oscillation signal whose phase is synchronized with the reference signal.
Moreover, in the PLL circuit 1 of the first embodiment, the second filter 7 is connected in parallel with the first filter 5 with respect to the output of the charge pump 4. The second filter 7 extracts a primary response delay component of the output signal of the charge pump 4.
The second current source 8 generates a second current I2 corresponding to the primary response delay component of the output signal and supplies the second current I2 to the ring oscillation unit 2.
Further, the ring oscillation unit 2 includes a delay unit 11 that operates using the current supplied from the second current source 8 and delays the signal as the delay unit 11 that delays the signal in the delay closed loop 19.
Therefore, in the first embodiment, when the phase relationship between the oscillation signal compared in the phase comparison unit 3 and the reference signal changes and the output signal of the charge pump 4 changes, the output signal changed by the second filter 7. 1 is extracted, and the delay amount of the signal in the delay closed loop 19 of the ring oscillation unit 2 is controlled.

As described above, in the PLL circuit 1 of the first embodiment, the second filter 7 that extracts and outputs the phase advance component is connected in parallel with the first filter 5, and the phase of the second filter 7 by the resistance element 52. The frequency of the oscillation signal is controlled based on the lead component.
For this reason, in the first embodiment, the phase of the reference signal and the phase of the oscillation signal can be synchronized. The PLL circuit 1 is stably operated by the second filter 7.
That is, in the PLL circuit 1 of the first embodiment, the band indicating the speed of frequency pull-in of the PLL circuit 1 while the output current of the charge pump 4 that is likely to be a noise source that affects jitter is set to a constant value. It can be set by changing ω independently.
Further, in the PLL circuit 1 of the first embodiment, the band ω indicating the speed of the frequency pull-in of the PLL circuit 1 is independently set while the attenuation coefficient ζ indicating the stability of the PLL circuit 1 is set to a constant value. It can be set by changing.
In addition, in the PLL circuit 1 of the first embodiment, the above effect is obtained by connecting the second filter 7 in parallel with the first filter 5.
Specifically, the output signals (the first current I1 and the second current I2) of the two current sources of the second current source 8 and the first current source 6 are Nch of each delay unit 11 of the ring oscillation unit 2. They are connected (joined) at an internal node inside the transistor.
Therefore, from the first viewpoint, an increase in the scale of the PLL circuit 1 can be suppressed.
On the other hand, for example, the same effect can be obtained by inserting an adder having two voltage-current control conversion units and a current-voltage conversion unit between the loop filter of the PLL circuit 1 and the voltage-controlled oscillator. Can do.
However, in this case, an adder having two voltage / current control conversion units and a current / voltage conversion unit is required, which increases the circuit scale.
As described above, the PLL circuit 1 according to the first embodiment can independently set the stability and the frequency pull-in speed of the PLL circuit 1 while effectively suppressing an increase in circuit scale.

In the PLL circuit 1 of FIG. 1, the second current source 8 and the first current source 6 are provided in a one-to-one correspondence with all the delay units 11 of the ring oscillation unit 2.
In addition, for example, even if the second current source 8 and the first current source 6 are provided in a one-to-one correspondence with a part of the delay units 11 of the ring oscillation unit 2, the same effect can be obtained.

<2. Second Embodiment>
[Configuration of PLL Circuit 1]
FIG. 5 is a block diagram of a PLL circuit 1 according to the second embodiment of the present invention.
The PLL circuit 1 in FIG. 5 supplies both the first current I1 and the second current I2 to all of the plurality of delay units 11 of the ring oscillation unit 2 as a whole.
The PLL circuit 1 in FIG. 5 includes a ring oscillation unit 2, a phase comparison unit 3, a charge pump 4, a first filter 5, one first current source 6, a second filter 7, and one second current source 8. Have Each circuit has the same function as that of the first embodiment, and a description thereof will be omitted.
5 forms a control loop 9 in which the ring oscillation unit 2, the phase comparison unit 3, the charge pump 4, the first filter 5, and one first current source 6 are connected.
Further, the output terminal 42 of one first current source 6 is connected to the first transistors of all the delay units 11 of the ring oscillation unit 2 by a common wiring connected to all the delay units 11 of the ring oscillation unit 2. 12 source electrodes are connected.
The output terminal 42 of the first current source 6 and the plurality of source electrodes are connected in a one-to-many correspondence.
In addition, the output terminals 42 of one second current source 8 are connected to the second transistors of all the delay units 11 of the ring oscillation unit 2 by a common wiring connected to all the delay units 11 of the ring oscillation unit 2. 13 source electrodes are connected.
The output terminal 42 of the second current source 8 and the plurality of source electrodes are connected in a one-to-many correspondence.
Connections between other circuits are the same as in the first embodiment.

[Operation of PLL circuit 1]
The phase comparator 3 compares the phases of the oscillation signal and the reference signal, and outputs a signal indicating the direction and magnitude of the phase difference.
When the charge pump 4 outputs a signal corresponding to the comparison in the phase comparison unit 3, the first filter 5 generates a voltage V <b> 1 obtained by smoothing the output signal of the charge pump 4.
Then, the first current source 6 supplies the first current I1 corresponding to the voltage smoothed by the first filter 5 to the first transistors 12 of the plurality of connected delay units 11.
The first transistors 12 of the plurality of delay units 11 perform a switching operation by the first current I1 supplied from the first current source 6 as a whole.
Further, the second filter 7 extracts a first-order response delay component of the output signal of the charge pump 4.
Then, the second current source 8 supplies the second current I2 corresponding to the primary response delay component extracted by the second filter 7 to the second transistors 13 of the plurality of connected delay units 11.
The second transistors 13 of the plurality of delay units 11 perform a switching operation by the second current I2 supplied from the second current source 8 as a whole.

  The PLL circuit 1 according to the second embodiment having the above configuration and operation has the same effects as the PLL circuit 1 according to the first embodiment. However, the oscillation frequency of the oscillation signal is different.

In the PLL circuit 1 of FIG. 5, the second current source 8 and the first current source 6 are connected to all the delay units 11 of the ring oscillation unit 2 in a one-to-many correspondence.
In addition, for example, even if the second current source 8 and the first current source 6 are provided in a one-to-many correspondence with a part of the delay units 11 of the ring oscillation unit 2, the same effect is obtained. Is obtained.
In the second embodiment, the same current source as in FIG. 4 is used as the second current source 8 or the first current source 6.
In addition, for example, as the second current source 8 or the first current source 6, a current source having a plurality of current transistors 41 of the same number as the delay unit 11 and each current transistor 41 being connected to each delay unit 11 is used. May be used.
In this case, the second current source 8 or the first current source 6 can supply the second current I2 or the first current I1 to each delay unit 11.

<3. Third Embodiment>
[Configuration of PLL Circuit 1]
FIG. 6 is a block diagram of a PLL circuit 1 according to the third embodiment of the present invention.
The PLL circuit 1 in FIG. 6 supplies both the first current I1 and the second current I2 to each of some delay units 11 of the ring oscillation unit 2. That is, the ring oscillation unit 2 includes a delay unit 11 to which neither the first current I1 nor the second current I2 is supplied.
The PLL circuit 1 of FIG. 6 includes a ring oscillation unit 2, a phase comparison unit 3, a charge pump 4, a first filter 5, two first current sources 6, a second filter 7, and two second current sources 8. Have
6 forms a control loop 9 in which the ring oscillation unit 2, the phase comparison unit 3, the charge pump 4, the first filter 5, and the two first current sources 6 are connected.

The ring oscillation unit 2 includes a three-stage delay unit 11.
Hereinafter, when the three stages of delay units 11 are distinguished from each other, they are referred to as a first delay unit 11-1, a second delay unit 11-2, and a third delay unit 11-3 in order from the left side in FIG.
FIG. 7 is a circuit diagram of the third delay unit 11-3 in FIG. The third delay unit 11-3 includes a first transistor 12 and a third transistor 14. The delay unit 11 includes one input terminal 15, one output terminal 16, and a first control terminal 17.
The source electrode of the first transistor 12 of the third delay unit 11-3 is connected to the first control terminal 17. In the third embodiment, the first control terminal 17 is connected to the ground.
Also, the output terminal 42 of the first current source 6 on the left side of FIG. 6 is connected to the source electrode of the first transistor 12 of the first delay unit 11-1 of the ring oscillation unit 2 by the wiring for each delay unit 11.
The output terminal 42 of the first current source 6 on the right side of FIG. 6 is connected to the source electrode of the first transistor 12 of the second delay unit 11-2 of the ring oscillation unit 2 by wiring for each delay unit 11.
The output terminal 42 of the first current source 6 and the source electrode are connected in a one-to-one correspondence.
Also, the output terminal 42 of the second current source 8 on the left side of FIG. 6 is connected to the source electrode of the second transistor 13 of the first delay unit 11-1 of the ring oscillation unit 2 by the wiring for each delay unit 11.
The output terminal 42 of the second current source 8 on the right side of FIG. 6 is connected to the source electrode of the second transistor 13 of the second delay unit 11-2 of the ring oscillation unit 2 by wiring for each delay unit 11.
The output terminal 42 of the second current source 8 and the source electrode are connected in a one-to-one correspondence.
The configuration of each other circuit and the connection between the circuits are the same as in the first embodiment, and a description thereof will be omitted.

[Operation of PLL circuit 1]
In the ring oscillation unit 2 of the PLL circuit 1 of FIG. 6, the first delay unit 11-1 and the second delay unit 11-2 perform a switching operation using the first current I1 and the second current I2 as drive currents. In contrast, the third delay unit 11-3 performs a switching operation at high speed using a current supplied from the VDD power supply or the ground as a drive current.
As described above, the three-stage delay unit 11 delays and outputs each input signal, so that the ring oscillation unit 2 generates an oscillation signal.

  The PLL circuit 1 of the third embodiment having the above configuration and operation has the same effects as the PLL circuit 1 of the first embodiment. However, the oscillation frequency of the oscillation signal is different.

The PLL circuit 1 of FIG. 6 includes one delay unit 11 (third delay unit 11-3) as the delay unit 11 that is not connected to either the first current source 6 or the second current source 8.
In addition, even if the PLL circuit 1 has a plurality of delay units 11 as the delay units 11 that are not connected to either the first current source 6 or the second current source 8, the same effect can be obtained. .

<4. Fourth Embodiment>
[Configuration of PLL Circuit 1]
FIG. 8 is a block diagram of a PLL circuit 1 according to the fourth embodiment of the present invention.
The PLL circuit 1 in FIG. 8 individually supplies the second current I2 to all of the plurality of delay units 11 of the ring oscillation unit 2, and supplies the first current I1 to some delay units 11 individually. To do.
The PLL circuit 1 of FIG. 8 includes a ring oscillation unit 2, a phase comparison unit 3, a charge pump 4, a first filter 5, one first current source 6, a second filter 7, and three second current sources 8. Have
The PLL circuit 1 in FIG. 8 forms a control loop 9 in which the ring oscillation unit 2, the phase comparison unit 3, the charge pump 4, the first filter 5, and one first current source 6 are connected.
The ring oscillation unit 2 includes a three-stage delay unit 11.
Hereinafter, when the three stages of delay units 11 are distinguished from each other, they are referred to as a first delay unit 11-1, a second delay unit 11-2, and a third delay unit 11-3 in order from the left side in FIG.
The output terminal 42 of one first current source 6 is connected to the source electrode of the first transistor 12 of the first delay unit 11-1 of the ring oscillation unit 2 by wiring for each delay unit 11.
The output terminal 42 of the second current source 8 on the left side of FIG. 8 is connected to the source electrode of the second transistor 13 of the first delay unit 11-1 of the ring oscillation unit 2 by wiring for each delay unit 11.
The output terminal 42 of the second current source 8 in the center of FIG. 8 is connected to the source electrode of the first transistor 12 of the second delay unit 11-2 of the ring oscillation unit 2 and the second transistor 13 by wiring for each delay unit 11. Connected to the source electrode.
The output terminal 42 of the second current source 8 on the right side of FIG. 8 is connected to the source electrode of the first transistor 12 of the third delay unit 11-3 of the ring oscillation unit 2 and the second transistor 13 by wiring for each delay unit 11. Connected to the source electrode.
The configuration of each other circuit and the connection between the circuits are the same as in the first embodiment, and a description thereof will be omitted.

[Operation of PLL circuit 1]
In the ring oscillation unit 2 of the PLL circuit 1 of FIG. 8, the first delay unit 11-1 performs a switching operation using the first current I1 and the second current I2 as drive currents.
In contrast, the second delay unit 11-2 and the third delay unit 11-3 perform a switching operation using the second current I2 as a drive current.
As described above, the three-stage delay unit 11 delays and outputs each input signal, so that the ring oscillation unit 2 generates an oscillation signal.

FIG. 9 is an explanatory diagram of an oscillation signal generated by the ring oscillation unit 2 of FIG.
FIG. 9A shows a waveform for one cycle of the oscillation signal generated by the ring oscillation unit 2.
FIG. 9B illustrates the breakdown of the delay time for generating a waveform for one period of the oscillation signal.
For example, when the output of the third delay unit 11-3 in the final stage of the ring oscillation unit 2 becomes a high level at the timing T1, the output of the first delay unit 11-1 in the first stage of the ring oscillation unit 2 is changed to the first current. It becomes a low level after a fall time Tf1 determined by I1 and the second current I2.
At timing T2, when the output of the first delay unit 11-1 at the first stage of the ring oscillation unit 2 becomes low level, the output of the second delay unit 11-2 becomes high level after the rise time Tr.
At timing T3, when the output of the second delay unit 11-2 at the second stage of the ring oscillation unit 2 becomes high level, the output of the third delay unit 11-3 is after the fall time Tf2 determined by the second current I2. Become low level.
As a result, the oscillation signal is switched from the high level to the low level.
At timing T4, when the output of the third delay unit 11-3 becomes low level, the output of the first delay unit 11-1 becomes high level after the rise time Tr.
At timing T5, when the output of the first delay unit 11-1 becomes high level, the output of the second delay unit 11-2 becomes low level after the falling time Tf2 determined by the second current I2.
At timing T6, when the output of the second delay unit 11-2 becomes low level, the output of the third delay unit 11-3 becomes high level after the rise time Tr.
As a result, the oscillation signal is switched from the low level to the high level.
Through the above operation, as shown in FIG. 9A, the ring oscillating unit 2 generates an oscillation signal having a constant period.

[Explanation of characteristics using mathematical formulas]
Next, the operation of the PLL circuit 1 of FIG.
In the PLL circuit 1 of FIG. 8, when compared with the PLL circuit 1 of FIG. 1, only the second current source 8 is connected to the second delay unit 11-2 and the third delay unit 11-3 of the ring oscillation unit 2. Is different.
Therefore, the period of the oscillation signal generated by the PLL circuit 1 in FIG.

In the PLL circuit 1 of FIG. 8, the current source is non-uniformly connected to the delay unit.
Therefore, as shown in Equation 4, not only physical adjustment (gm1, gm2) but also time-division adjustment (Tf1, Tf2) is performed as an adjustment means for the control current supplied to the ring oscillation unit 2. ing.
Then, the open loop transfer function of the PLL circuit 1 of FIG. Further, the band ωn is expressed by Equation 6 and the attenuation coefficient ζ is expressed by Equation 7. Here, C2 ≦ C1.

As is clear from Equations 6 and 7, in the PLL circuit 1 of FIG. 8, the first current source 6 determines the number of delay units 11 that supply the first current I1, and the second current source 8 generates the second current I2. The number of delay units 11 to be supplied may be different.
By using different numbers, the PLL circuit 1 of FIG. 8 reduces the number of periods in which the first current I1 is used as the control current per cycle of the oscillation signal, and independently adjusts the band ωn and the attenuation coefficient ζ. can do.
The PLL circuit 1 of the fourth embodiment having the above configuration and operation has the same effects as the PLL circuit 1 of the first embodiment. However, the oscillation frequency of the oscillation signal is different.
Further, in the PLL circuit 1 of the fourth embodiment, the number of first current sources 6 and the number of second current sources 8 for the plurality of delay units 11 are made different from each other without increasing the circuit scale. It is possible to adjust ωn with a fine resolution.

<5. Fifth Embodiment>
[Configuration of PLL Circuit 1]
FIG. 10 is a block diagram of a PLL circuit 1 according to the fifth embodiment of the present invention.
The PLL circuit 1 of FIG. 10 supplies the first current I1 individually to all of the plurality of delay units 11 of the ring oscillation unit 2, and supplies the second current I2 individually to some delay units 11. To do.
The PLL circuit 1 of FIG. 10 includes a ring oscillation unit 2, a phase comparison unit 3, a charge pump 4, a first filter 5, three first current sources 6, a second filter 7, and one second current source 8. Have
5 forms a control loop 9 in which the ring oscillation unit 2, the phase comparison unit 3, the charge pump 4, the first filter 5, and the three first current sources 6 are connected.
The ring oscillation unit 2 includes a three-stage delay unit 11.
Hereinafter, when the three stages of delay units 11 are distinguished from each other, they are referred to as a first delay unit 11-1, a second delay unit 11-2, and a third delay unit 11-3 in order from the left side in FIG.
The output terminal 42 of one second current source 8 is connected to the source electrode of the second transistor 13 of the first delay unit 11-1 of the ring oscillation unit 2 by wiring for each delay unit 11.
The output terminal 42 of the first current source 6 on the left side of FIG. 10 is connected to the source electrode of the first transistor 12 of the first delay unit 11-1 of the ring oscillation unit 2 by wiring for each delay unit 11.
The output terminal 42 of the first current source 6 in the center of FIG. 10 is connected to the source electrode of the first transistor 12 of the first delay unit 11-1 of the ring oscillation unit 2 and the second transistor 13 by the wiring for each delay unit 11. Connected to the source electrode.
The output terminal 42 of the first current source 6 on the right side of FIG. 10 is connected to the source electrode of the first transistor 12 of the third delay unit 11-3 of the ring oscillation unit 2 and the second transistor 13 by wiring for each delay unit 11. Connected to the source electrode.
The configuration of each other circuit and the connection between the circuits are the same as in the first embodiment, and a description thereof will be omitted.

[Operation of PLL circuit 1]
In the ring oscillation unit 2 of the PLL circuit 1 of FIG. 10, the first delay unit 11-1 performs a switching operation using the first current I1 and the second current I2 as drive currents.
In contrast, the second delay unit 11-2 and the third delay unit 11-3 perform a switching operation using the first current I1 as a drive current.
As described above, the three-stage delay unit 11 delays and outputs each input signal, so that the ring oscillation unit 2 generates an oscillation signal having a constant period.

The PLL circuit 1 of the fifth embodiment having the above configuration and operation reduces the number of periods in which the second current I2 is used as the control current per cycle of the oscillation signal, and independently sets the band ωn and the attenuation coefficient ζ. Can be adjusted.
The PLL circuit 1 according to the fifth embodiment has the same effects as the PLL circuit 1 according to the first embodiment. However, the oscillation frequency of the oscillation signal is different.
Further, in the PLL circuit 1 of the fifth embodiment, the number of first current sources 6 and the number of second current sources 8 for the plurality of delay units 11 are made different from each other without increasing the circuit scale. It is possible to adjust ωn with a fine resolution.

<6. Sixth Embodiment>
[Configuration of PLL Circuit 1]
FIG. 11 is a block diagram of a PLL circuit 1 according to the sixth embodiment of the present invention.
The PLL circuit 1 in FIG. 11 individually supplies the first current I1 to a part of the plurality of delay units 11 of the ring oscillation unit 2 and supplies the second current I2 to the remaining delay units 11 individually. To do.
11 includes a ring oscillation unit 2, a phase comparison unit 3, a charge pump 4, a first filter 5, one first current source 6, a second filter 7, and two second current sources 8. Have
The PLL circuit 1 in FIG. 11 forms a control loop 9 in which the ring oscillation unit 2, the phase comparison unit 3, the charge pump 4, the first filter 5, and one first current source 6 are connected.
The ring oscillation unit 2 includes a three-stage delay unit 11. Each delay unit 11 is the delay unit 11 illustrated in FIG. 7, and includes a first transistor 12 and a third transistor 14.
Hereinafter, when the three stages of delay units 11 are distinguished from each other, they are referred to as a first delay unit 11-1, a second delay unit 11-2, and a third delay unit 11-3 in order from the left side in FIG.
The output terminal 42 of one first current source 6 is connected to the source electrode of the first transistor 12 of the first delay unit 11-1 of the ring oscillation unit 2 by wiring for each delay unit 11.
The output terminal 42 of the second current source 8 on the left side of FIG. 11 is connected to the source electrode of the first transistor 12 of the second delay unit 11-2 of the ring oscillation unit 2 by wiring for each delay unit 11.
The output terminal 42 of the second current source 8 on the right side of FIG. 11 is connected to the source electrode of the first transistor 12 of the third delay unit 11-3 of the ring oscillation unit 2 by wiring for each delay unit 11.
The configuration of each other circuit and the connection between the circuits are the same as in the first embodiment, and a description thereof will be omitted.

[Operation of PLL circuit 1]
In the ring oscillation unit 2 of the PLL circuit 1 of FIG. 11, the first delay unit 11-1 performs a switching operation using the first current I1 as a drive current.
In contrast, the second delay unit 11-2 and the third delay unit 11-3 perform a switching operation using the second current I2 as a drive current.
As described above, the three-stage delay unit 11 delays and outputs each input signal, so that the ring oscillation unit 2 generates an oscillation signal having a constant period.

The PLL circuit 1 according to the sixth embodiment having the above-described configuration and operation reduces the number of periods (Tf) in which the first current I1 is used as a control current per cycle of the oscillation signal to one, and the second The number of periods (Tf) in which the current I2 is used as the control current is reduced to two.
Therefore, the PLL circuit 1 of the sixth embodiment can independently adjust the band ωn and the attenuation coefficient ζ. Then, the PLL circuit 1 of the sixth embodiment has the same effects as the PLL circuit 1 of the first embodiment. However, the oscillation frequency of the oscillation signal is different.
In the PLL circuit 1 of the sixth embodiment, the number of the first current sources 6 and the number of the second current sources 8 with respect to the plurality of delay units 11 are made different from each other, so that the circuit scale is not increased. It is possible to adjust ωn with a fine resolution.

<7. Seventh Embodiment>
[Configuration of PLL Circuit 1]
FIG. 12 is a block diagram of a PLL circuit 1 according to the seventh embodiment of the present invention.
The PLL circuit 1 of FIG. 12 individually supplies the first current I1 to a part of the plurality of delay units 11 of the ring oscillation unit 2 and supplies the second current I2 to the remaining delay units 11 individually. To do.
Further, the ring oscillation unit 2 includes a delay unit 11 to which neither the first current I1 nor the second current I2 is supplied.
12 includes a ring oscillation unit 2, a phase comparison unit 3, a charge pump 4, a first filter 5, one first current source 6, a second filter 7, and one second current source 8. Have
12 forms a control loop 9 in which the ring oscillation unit 2, the phase comparison unit 3, the charge pump 4, the first filter 5, and one first current source 6 are connected.
The ring oscillation unit 2 includes a three-stage delay unit 11. Each delay unit 11 is the delay unit 11 illustrated in FIG. 7, and includes a first transistor 12 and a third transistor 14.
Hereinafter, when the three stages of delay units 11 are distinguished from each other, they are referred to as a first delay unit 11-1, a second delay unit 11-2, and a third delay unit 11-3 in order from the left side in FIG.
The output terminal 42 of one first current source 6 is connected to the source electrode of the first transistor 12 of the first delay unit 11-1 of the ring oscillation unit 2 by wiring for each delay unit 11.
The output terminal 42 of one second current source 8 is connected to the source electrode of the first transistor 12 of the second delay unit 11-2 of the ring oscillation unit 2 by wiring for each delay unit 11.
The third delay unit 11-3 is connected between the VDD power supply and the ground.
The configuration of each other circuit and the connection between the circuits are the same as in the first embodiment, and a description thereof will be omitted.

[Operation of PLL circuit 1]
In the ring oscillation unit 2 of the PLL circuit 1 of FIG. 12, the first delay unit 11-1 performs a switching operation using the first current I1 as a drive current.
The second delay unit 11-2 performs a switching operation using the second current I2 as a drive current.
In contrast, the third delay unit 11-3 performs a switching operation at high speed using a current supplied from the VDD power supply or the ground as a drive current.
As described above, the three-stage delay unit 11 delays and outputs each input signal, so that the ring oscillation unit 2 generates an oscillation signal having a constant period.

In the PLL circuit 1 according to the seventh embodiment having the above configuration and operation, the number of periods in which the plurality of delay units 11 use the first current I1 as the control current is reduced to one per cycle of the oscillation signal. ing. Moreover, the number of periods in which the plurality of delay units 11 use the second current I2 as a control current is also reduced to one.
Therefore, the PLL circuit 1 according to the seventh embodiment can independently adjust the band ωn and the attenuation coefficient ζ. The PLL circuit 1 according to the seventh embodiment has the same effects as the PLL circuit 1 according to the first embodiment. However, the oscillation frequency of the oscillation signal is different.
Further, in the PLL circuit 1 of the seventh embodiment, the number of first current sources 6 and the number of second current sources 8 for the plurality of delay units 11 are made different from each other without increasing the circuit scale. It is possible to adjust ωn with a fine resolution.

<8. Eighth Embodiment>
[Configuration of PLL Circuit 1]
The basic configuration of the PLL circuit 1 of the eighth embodiment is the same as that of the PLL circuit 1 of the first embodiment shown in FIG.
However, the circuit configurations of the first current source 6 and the second current source 8 are different, and the control unit 61 that controls the first current source 6 and the second current source 8 is provided.

FIG. 13 is a block diagram illustrating one current source used as the first current source 6 or the second current source 8 and the control unit 61 in the eighth embodiment.
13 includes a plurality of current transistors 41-1 to 41-n, one output terminal 42, and a plurality of current changeover switches 43-1 to 43- (one less than the current transistor 41). n-1) and a plurality of control input terminals 44-1 to 44- (n-1).

The current transistor 41 is an Nch MOS transistor.
The gate electrodes of the plurality of current transistors 41 are connected to the first filter 5 or the second filter 7.
The plurality of source electrodes are connected to the ground by one electron microscope line.
One of the plurality of drain electrodes 43 is directly connected to the output terminal 42, and the other is individually connected to the plurality of current selector switches 43.

Each of the plurality of current changeover switches 43 is connected to each of the plurality of control input terminals 44.
Each current changeover switch 43 opens and closes according to the level of the control signal input from the control input terminal 44.
The plurality of current changeover switches 43 are connected to one output terminal 42.

When the current changeover switch 43 is closed, the current transistor 41 connected to the current changeover switch 43 is connected to the output terminal 42.
On the other hand, when the current selector switch 43 is open, the current transistor 41 connected to the current selector switch 43 is disconnected from the output terminal 42.
Therefore, the current source of FIG. 13 controls the level of the control signal input to the plurality of control input terminals 44-1 to 44- (n-1), thereby the number of current transistors 41 connected to the output terminal 42. Can be controlled.
Further, as the number of current transistors 41 connected to the output terminal 42 increases, the value of the first current I1 or the second current I2 that can be supplied from the output terminal 42 to the delay unit 11 can be increased.

The controller 61 is constituted by, for example, a CPU (Central Processing Unit).
The controller 61 is connected to a plurality of current sources used as the first current source 6 or the second current source 8.
And the control part 61 outputs an individual control signal with respect to several electric current sources.

[Operation of PLL circuit 1]
For example, the control unit 61 outputs a control signal for opening the current changeover switch 43 to all three current sources used as the first current source 6.
Thereby, in each current source used as the first current source 6, one current transistor 41 is connected to the output terminal 42.
The control unit 61 outputs a control signal for opening the current changeover switch 43 to all three current sources used as the second current source 8, for example.
Thereby, in each current source used as the second current source 8, one current transistor 41 is connected to the output terminal 42.
In this state, one current transistor 41 of the first current source 6 and one current transistor 41 of the second current source 8 are connected to each of the three stages of delay units 11 of the ring oscillation unit 2. The
The connection relationship between the three stages of delay units 11 of the ring oscillation unit 2 and a plurality of current sources is the same as that in FIG.
Therefore, the PLL circuit 1 generates an oscillation signal having the same frequency as that of the first embodiment.

In addition to this, for example, the control unit 61 outputs a control signal for closing the current changeover switch 43 to all three current sources used as the first current source 6, for example.
Thereby, in each current source used as the first current source 6, a plurality of current transistors 41 are connected to the output terminal 42.
The control unit 61 outputs a control signal for opening the current changeover switch 43 to all three current sources used as the second current source 8, for example.
Thereby, in each current source used as the second current source 8, one current transistor 41 is connected to the output terminal 42.
In this state, a plurality of current transistors 41 of the first current source 6 and one current transistor 41 of the second current source 8 are connected to each of the three stages of delay units 11 of the ring oscillation unit 2. The
Therefore, the frequency of the oscillation signal generated by the PLL circuit 1 is different from the previous example.

In the PLL circuit 1 of the eighth embodiment having the above configuration and operation, the control unit 61 can control the supply current of the current source, so that the band ωn and the attenuation coefficient ζ are adjusted independently and dynamically. be able to.
Further, in the PLL circuit 1 according to the eighth embodiment, the control unit 61 controls the supply current of the current source to obtain the above-described effect. Therefore, the bandwidth ωn can be finely resolved without increasing the circuit scale. And can be adjusted dynamically.

In the eighth embodiment, the supply current of the first current source 6 and the second current source 8 is controlled using the PLL circuit 1 of the first embodiment of FIG. 1 as a basic configuration.
In addition, the supply currents of the first current source 6 and the second current source 8 may be controlled using the PLL circuit 1 of another embodiment shown in FIGS. 4 to 12 as a basic configuration.

<9. Ninth Embodiment>
[Configuration of PLL Circuit 1]
FIG. 14 is a block diagram of the PLL circuit 1 according to the ninth embodiment.
The PLL circuit 1 according to the ninth embodiment can control the connection between the first current source 6 and the second current source 8 and the delay unit 11 individually.
The basic configuration of the PLL circuit 1 of the ninth embodiment is the same as that of the PLL circuit 1 of the first embodiment shown in FIG.
However, the switch array 71 is connected between the plurality of first current sources 6 and the plurality of second current sources 8 and the plurality of delay units 11.
The control unit 61 is connected to the switch array 71 and controls the switch array 71.

The switch array 71 has a plurality of connection switches 72 and a plurality of control input terminals 73. The switch array 71 of FIG. 14 has four connection switches 72-1 to 72-4.
Hereinafter, when the four connection switches 72 are distinguished from each other, the first connection switch 72-1, the second connection switch 72-2, the third connection switch 72-3, and the fourth connection switch are sequentially arranged from the left side of FIG. It is called 72-4.
Each of the plurality of connection switches 72 is connected to each of the plurality of control input terminals 73.
Each connection switch 72 opens and closes according to the level of the control signal input from the control input terminal 73.
The first connection switch 72-1 is connected between the output terminal 42 of the first current source 6 on the left side of FIG. 14 and the source electrode of the first transistor 12 of the first delay unit 11-1.
The second connection switch 72-2 is connected between the output terminal 42 of the second current source 8 on the left side of FIG. 14 and the source electrode of the second transistor 13 of the first delay unit 11-1.
The third connection switch 72-3 is connected between the output terminal 42 of the first current source 6 in the center of FIG. 14 and the source electrode of the first transistor 12 of the second delay unit 11-2.
The fourth connection switch 72-4 is connected between the output terminal 42 of the second current source 8 in the center of FIG. 14 and the source electrode of the second transistor 13 of the second delay unit 11-2.

When the connection switch 72 is closed, the transistor of the delay unit 11 connected to the connection switch 72 is disconnected from the current source.
When the connection switch 72 is open, the transistor of the delay unit 11 connected to the connection switch 72 is connected to the current source.

The control unit 61 is constituted by a CPU, for example. The control unit 61 is connected to a plurality of control input terminals 73 of the switch array 71.
Then, the control unit 61 outputs individual control signals to the plurality of control input terminals 73.

[Operation of PLL circuit 1]
For example, the control unit 61 outputs a control signal for closing all the connection switches 72 to the switch array 71.
Accordingly, the first current source 6 and the second current source 8 are connected to the first delay unit 11-1. The first current source 6 and the second current source 8 are also connected to the second delay unit 11-2.
In this state, the first current I 1 of the first current source 6 and the second current I 2 of the second current source 8 are supplied to each of the three stages of delay units 11 of the ring oscillation unit 2.
Therefore, the PLL circuit 1 generates an oscillation signal having the same frequency as that of the first embodiment.

In addition to this, for example, the control unit 61 outputs a control signal for opening the first connection switch 72-1 and the third connection switch 72-3 and closing the second connection switch 72-2 and the fourth connection switch 72-4. Output to the switch array 71.
As a result, only the second current source 8 is connected to the first delay unit 11-1. Further, only the second current source 8 is also connected to the second delay unit 11-2.
In this state, one first current source 6 and three second current sources 8 are connected to the three-stage delay unit 11 of the ring oscillation unit 2 as in FIG.
Therefore, the PLL circuit 1 generates an oscillation signal having the same frequency as that in the fourth embodiment.

In the PLL circuit 1 of the ninth embodiment having the above configuration and operation, the control unit 61 can control the number and ratio of the current sources connected to the ring oscillation unit 2, so that the band ωn and the attenuation coefficient ζ can be adjusted independently and dynamically.
In the PLL circuit 1 of the ninth embodiment, the control unit 61 controls the number and ratio of the current sources connected to the ring oscillation unit 2 to obtain the above-described effect.
Therefore, the PLL circuit 1 according to the ninth embodiment can dynamically adjust the band ωn with fine resolution without increasing the circuit scale.

In the ninth embodiment, the connection between the first current source 6 and the second current source 8 and the delay unit 11 is controlled based on the PLL circuit 1 of the first embodiment shown in FIG.
In addition, the connection between the first current source 6 and the second current source 8 and the delay unit 11 may be controlled based on the PLL circuit 1 according to another embodiment shown in FIGS.

<10. Tenth Embodiment>
[Configuration of PLL Circuit 1]
FIG. 15 is a block diagram of the PLL circuit 1 according to the tenth embodiment.
The PLL circuit 1 according to the tenth embodiment can individually control the connection between all the first current sources 6 and the delay units 11.
The basic configuration of the PLL circuit 1 of the tenth embodiment is the same as that of the PLL circuit 1 of the second embodiment shown in FIG.
However, the switch array 71 is connected between the plurality of first current sources 6 and the plurality of delay units 11. The control unit 61 is connected to the switch array 71 and controls the switch array 71.

The switch array 71 has a plurality of connection switches 72 and a plurality of control input terminals 73. The switch array 71 in FIG. 15 includes three connection switches 72-1 to 72-3.
Hereinafter, when the three connection switches 72 are distinguished from each other, they are referred to as a first connection switch 72-1, a second connection switch 72-2, and a third connection switch 72-3 in order from the left side of FIG.
Each of the plurality of connection switches 72 is connected to each of the plurality of control input terminals 73.
Each connection switch 72 opens and closes according to the level of the control signal input from the control input terminal 73.
The first connection switch 72-1 is connected between the output terminal 42 of the first current source 6 and the source electrode of the first transistor 12 of the first delay unit 11-1.
The second connection switch 72-2 is connected between the output terminal 42 of the first current source 6 and the source electrode of the first transistor 12 of the second delay unit 11-2.
The third connection switch 72-3 is connected between the output terminal 42 of the first current source 6 and the source electrode of the first transistor 12 of the third delay unit 11-3.

When the connection switch 72 is closed, the transistor of the delay unit 11 connected to the connection switch 72 is disconnected from the first current source 6.
When the connection switch 72 is open, the transistor of the delay unit 11 connected to the connection switch 72 is connected to the first current source 6.

  The control unit 61 is constituted by a CPU, for example. The control unit 61 is connected to a plurality of control input terminals 73 of the switch array 71. Then, the control unit 61 outputs individual control signals to the plurality of control input terminals 73.

[Operation of PLL circuit 1]
For example, the control unit 61 outputs a control signal for closing all the connection switches 72 to the switch array 71.
Thereby, the first current source 6 and the second current source 8 are connected to all the delay units 11 from the first delay unit 11-1 to the third delay unit 11-3.
In this state, the first current I1 of the first current source 6 and the second current I2 of the second current source 8 are supplied to all three delay units 11 of the ring oscillation unit 2.
Therefore, the PLL circuit 1 generates an oscillation signal having the same frequency as that of the second embodiment shown in FIG.

In addition to this, for example, the control unit 61 outputs a control signal to the switch array 71 that opens the second connection switch 72-2 and the third connection switch 72-3 and closes the first connection switch 72-1.
As a result, the first current I1 of the first current source 6 and the second current I2 of the second current source 8 are supplied to the first delay unit 11-1. Further, only the second current source 8 is connected to the second delay unit 11-2 and the third delay unit 11-3.
Therefore, the PLL circuit 1 generates an oscillation signal having a frequency different from that of the second embodiment.

In the PLL circuit 1 of the tenth embodiment having the above configuration and operation, the control unit 61 can control the number and ratio of the delay units 11 connected to the current source. Can be adjusted independently and dynamically.
In the PLL circuit 1 according to the tenth embodiment, the control unit 61 controls the number and ratio of the delay units 11 connected to the current source to obtain the above-described effect.
Therefore, the PLL circuit 1 according to the tenth embodiment can dynamically adjust the band ωn with a fine resolution without increasing the circuit scale.

In the tenth embodiment, the connection between the first current source 6 and the delay unit 11 is controlled using the PLL circuit 1 of the second embodiment in FIG. 5 as a basic configuration.
In addition, the connection between the second current source 8 and the delay unit 11 may be controlled, or the connection between the first current source 6 and the delay unit 11 and the connection between the second current source 8 and the delay unit 11. May be controlled.
Further, the connection between the first current source 6 and the delay unit 11 may be controlled using the PLL circuit 1 according to another embodiment shown in FIGS. 1 and 6 to 13 as a basic configuration.
For example, the current source of FIG. 13 may be used for the first current source 6 and the second current source 8.
In this case, the control unit 61 may output, for example, a control signal that opens the second connection switch 72-2 and the third connection switch 72-3 and closes the first connection switch 72-1 to the switch array 71. .
In addition to this, the control unit 61 may control the second current source 8 to connect the three current transistors 41 to the output terminal 42.
As a result, a current source can be connected to the three-stage delay unit 11 as in the fourth embodiment of FIG.

<11. Eleventh Embodiment>
[Configuration and operation of broadcast signal receiving apparatus 101]
FIG. 16 is a block diagram of the broadcast signal receiving apparatus 101 of the tenth embodiment.
A broadcast signal receiving apparatus 101 in FIG. 16 is an example of an electronic device that uses an oscillation signal generated by the PLL circuit 1 for generating a local signal.
The broadcast signal receiving apparatus 101 includes an antenna 102, an input circuit 103, and a tuner 104.

The antenna 102 is a parabolic antenna, for example. The antenna 102 receives a broadcast signal.
Broadcast signals include, for example, satellite broadcast signals.
Examples of satellite broadcast signals that can be used in Japan include a signal relayed by a BS (Broadcast Satellite) broadcast satellite and a signal relayed by a CS (Communications Satellite) communication satellite.

The input circuit 103 is connected to the antenna 102.
The input circuit 103 includes a band pass filter 111 and a high frequency amplifier 112.
The band pass filter 111 extracts a broadcast band component from the signal received by the antenna 102. The band pass filter 111 extracts a signal component in a band of 950 to 2150 MHz, for example.
The high frequency amplifier 112 amplifies the signal component extracted by the band pass filter 111.

The tuner 104 includes an (Auto Gain Controller) AGC circuit 121, a receiving circuit 122, a first low-pass filter 123, a second low-pass filter 124, a digital demodulation unit 125, a control unit 61, and a crystal oscillator 126.
The reception circuit 122 includes a PLL circuit 1, a local oscillator 131, a phase conversion circuit 132, a first mixer 133, and a second mixer 134.

The AGC circuit 121 is connected to the high frequency amplifier 112 of the input circuit 103.
Then, the AGC circuit 121 automatically amplifies the amplified signal component to generate a reception signal at a certain level.

The PLL circuit 1 is the PLL circuit 1 according to the tenth embodiment of FIG.
The PLL circuit 1 is connected to the crystal oscillator 126.
The PLL circuit 1 uses the signal generated by the crystal oscillator 126 as a reference signal, and generates an oscillation signal synchronized with the reference signal.

The local oscillator 131 is connected to the PLL circuit 1.
Then, the local oscillator 131 generates a local signal based on the oscillation signal generated by the PLL circuit 1.

The phase conversion circuit 132 is connected to the local oscillator 131.
Then, the phase conversion circuit 132 shifts the phase of the local signal.

The first mixer 133 is connected to the AGC circuit 121 and the local oscillator 131.
Then, the first mixer 133 mixes the reception signal input from the AGC circuit 121 and the local signal. As a result, the frequency of the received signal is converted.

The first low-pass filter 123 is connected to the first mixer 133.
Then, the first low-pass filter 123 removes unnecessary harmonic components from the signal frequency-converted by the first mixer 133 and generates an I signal (in-phase signal).

The second mixer 134 is connected to the AGC circuit 121 and the phase conversion circuit 132.
Then, the second mixer 134 mixes the reception signal input from the AGC circuit 121 and the local signal that is 90 degrees out of phase.
As a result, the frequency of the received signal is converted.

The second low pass filter 124 is connected to the second mixer 134.
Then, the second low-pass filter 124 removes unnecessary harmonic components from the signal frequency-converted by the second mixer 134 and generates a Q signal (orthogonal signal).

Through the processing of the receiving circuit 122 described above, a baseband signal composed of an I signal and a Q signal is generated.
The digital demodulator 125 is connected to the first low-pass filter 123 and the second low-pass filter 124. Then, the digital demodulator 125 digitally demodulates the I signal and the Q signal.
Thereby, the digital demodulator 125 generates a digital streaming signal included in the broadcast signal. Digital streaming signals include MPEG-TS signals.
This digital streaming signal is transmitted to, for example, a liquid crystal monitor connected to the broadcast signal receiving apparatus 101.
The liquid crystal monitor reproduces an audio data signal and a video data signal included in the digital streaming signal.
Thereby, the audio content and the video content included in the broadcast signal can be reproduced.

[Function of PLL circuit 1]
In such a receiving operation, the control unit 61 is connected to the PLL circuit 1 and outputs a control signal to the PLL circuit 1.
For example, when a broadcast channel to be received is selected, the control unit 61 outputs a control signal to the PLL circuit 1 in order to generate a local signal corresponding to the broadcast channel.
When this control signal is input, the switch array 71 of the PLL circuit 1 in FIG. 15 individually opens and closes the first connection switch 72-1, the second connection switch 72-2, and the third connection switch 72-3. Control.

For example, when the frequency of the local signal is increased to the maximum, the switch array 71 closes all of the first connection switch 72-1, the second connection switch 72-2, and the third connection switch 72-3.
In this case, the first current I1 and the second current I2 are all supplied to the three stages of the delay units 11 of the ring oscillation unit 2 of FIG.
As a result, the frequency of the oscillation signal generated by the ring oscillation unit 2 is maximized, and the frequency of the local signal is also maximized.

In addition, for example, when the frequency of the local signal is lowered to the minimum, the switch array 71 opens all of the first connection switch 72-1, the second connection switch 72-2, and the third connection switch 72-3. .
In this case, only the second current I2 is supplied to all the three stages of the delay units 11 of the ring oscillation unit 2 of FIG.
As a result, the frequency of the oscillation signal generated by the ring oscillation unit 2 is minimized, and the frequency of the local signal is also minimized.

Further, when the frequency is switched, a phase difference between the phase of the oscillation signal generated by the ring oscillation unit 2 and the signal generated by the crystal oscillator 126 is generated.
The charge pump 4 outputs a signal including a current corresponding to the phase difference detected by the phase comparison unit 3.
The voltage at the connection point 53 of the second filter 7 increases in accordance with the AC component included in the output signal of the charge pump 4.
The second current source 8 increases the second current I2 supplied to the plurality of delay units 11.
Therefore, when the frequency is switched, the second current I2 supplied from the second current source 8 to the plurality of delay units 11 temporarily increases, so that the frequency of the oscillation signal generated by the ring oscillation unit 2 is accelerated. Change.
As a result, the oscillation signal is switched to a new frequency earlier than when the supply current is controlled only by the first current I1, and is stabilized at the new frequency.

  Each of the above embodiments is an example of a preferred embodiment of the present invention, but the present invention is not limited to this, and various modifications or changes can be made without departing from the scope of the invention. .

For example, in each of the above-described embodiments, the ring oscillation unit 2 of the PLL circuit 1 has one delay closed loop 19 by the three-stage delay unit 11.
In addition to this, for example, the delay closed loop of the ring oscillating unit 2 may include one or more delay units 11.

Further, the ring oscillation unit 2 may be configured to switch a plurality of delay closed loops 19.
For example, a configuration in which the outputs of the plurality of stages of delay units 11 are connected to a selector and a signal selected by the selector is returned to the first stage of delay unit 11 may be employed.

In the above-described embodiments, in the control loop 9, the first filter 5 is connected to the first current source 6, and the first current source 6 is further connected to the ring oscillation unit 2.
In addition, for example, a voltage controlled oscillator may be used in the control loop 9 and the first filter 5 may be connected to the voltage controlled oscillator.

In each of the embodiments described above, the second filter 7 has a configuration in which the first capacitor 51 and the resistance element 52 are connected in series, and extracts the first-order response delay component of the output signal of the charge pump 4. Yes.
In addition to this, for example, the second filter 7 may extract a second or higher order response delay component of the output signal of the charge pump 4 by a circuit configuration in which a capacitor, a resistance element 52, and an inductor are appropriately combined. The second filter 7 may extract a plurality of response delay components.

In each of the above-described embodiments, as shown in FIG. 2, in the delay unit 11, the second transistor 13 is connected in parallel to the first transistor 12, and the first current I <b> 1 of the first transistor 12 and the second transistor 13 are The second current I2 is controlled.
Thereby, the fall time Tf of each delay part 11 can be adjusted.
In addition, for example, a fourth transistor may be connected in parallel to the third transistor 14 of the delay unit 11 to control the third current of the third transistor 14 and the fourth current of the fourth transistor. .
In this case, the rise time Tr of each delay unit 11 can be adjusted.

In addition, an oscillation signal generated by a crystal oscillator 126 (not shown) is input as a reference signal to the phase comparison unit 3 of each embodiment described above.
In addition, for example, an oscillation signal other than the crystal oscillator 126, for example, an oscillation signal component included in the reception signal, may be input to the phase comparison unit 3 as a reference signal.

In the eleventh embodiment described above, the PLL circuit 1 is used for the broadcast signal receiving apparatus 101.
In addition, for example, the PLL circuit 1 may be used in other electronic devices such as a transmitter, a receiver, and an image processing apparatus.
In this case, the oscillation signal of the PLL circuit 1 may be used for purposes other than generating a local signal in the reception circuit 122.
For example, a transmission signal may be generated from the oscillation signal, or a timing signal synchronized with the synchronization signal may be generated from the oscillation signal.

DESCRIPTION OF SYMBOLS 1 ... PLL circuit, 2 ... Ring oscillation part, 3 ... Phase comparison part, 4 ... Charge pump, 5 ... 1st filter (smoothing filter), 6 ... 1st current source (smoothing current source), 7 ... 2nd filter ( Delay component filter), 8 ... second current source (correction current source), 9 ... control loop (closed loop), 11 ... delay unit, 12 ... first transistor (transistor), 13 ... second transistor (transistor), 19 ... Delayed closed loop, 31 ... second capacitor, 41 ... current transistor, 42 ... output terminal, 43 ... current changeover switch, 51 ... first capacitor (capacitance element), 52 ... resistance element, I1 ... first current (smooth current), I2 ... second current (correction current), 61 ... control unit, 72-1 ... first connection switch, 72-2 ... second connection switch, 101 ... broadcast signal receiving device (electronic device), 131 ... local oscillator Radical 19)

Claims (15)

A ring oscillation unit that generates an oscillation signal by a delay closed loop that delays the signal;
A phase comparator for comparing the phase of the oscillation signal and a reference signal;
A charge pump connected to the phase comparator;
A smoothing filter connected to the charge pump;
A smoothing current source connected to the smoothing filter and supplying a smoothing current according to an output signal smoothed by the smoothing filter to the ring oscillation unit;
A delay component filter that is connected to the output of the charge pump in parallel with the smoothing filter and extracts a response delay component included in the output signal of the charge pump;
A correction current source that generates a correction current corresponding to the response delay component extracted by the delay component filter and supplies the correction current to the ring oscillation unit, and
The ring oscillation unit is
A PLL circuit having a delay unit that operates by a current supplied from at least one of the smoothing current source and the correction current source to delay a signal as a delay unit that delays a signal in the delay closed loop. The ring oscillation unit is
A delay unit having at least one stage for delaying a signal by a transistor that performs a switching operation under a drive current, and generating an oscillation signal by a delay closed loop by all or part of the at least one stage delay unit;
The smoothing current source is
A smoothing current corresponding to the signal smoothed by the smoothing filter is supplied to all or a part of the at least one or more delay parts constituting the ring oscillator connected to the smoothing filter. And
The correction current source is
Supplying the correction current to all or a part of the delay units of the at least one stage constituting the ring oscillation unit independently of the smoothing current source;
The transistors of the delay unit of at least one stage of the ring oscillation unit are:
The PLL circuit according to claim 1, wherein a switching operation is performed using at least one of the smoothing current and the correction current as a drive current. The ring oscillation unit is
A plurality of delay units connected together with the smoothing current source and the correction current source;
The smoothing current source is
Supplying a smoothing current to the entirety of a plurality of delay units connected to the smoothing current source,
The correction current source is
The PLL circuit according to claim 2, wherein a correction current is supplied to all of a plurality of delay units connected to the correction current source. The ring oscillation unit includes a plurality of delay units,
The smoothing current source is
Provided in a one-to-one correspondence with all or part of the plurality of delay units of the ring oscillation unit, connected to each delay unit one by one, and supplies a smoothing current to each connected delay unit And
The correction current source is
With the same correspondence as the smoothing current source, one or one correspondence is provided for all or a part of the plurality of delay units of the ring oscillation unit, and one is connected to each delay unit. The PLL circuit according to claim 2, wherein a correction current is supplied to each delay unit. The ring oscillation unit is
The PLL circuit according to claim 4, further comprising a delay unit that is not connected to either the smoothing current source or the correction current source. The ring oscillation unit includes a plurality of delay units,
The smoothing current source is
Provided in a one-to-one correspondence with all or part of the plurality of delay units of the ring oscillation unit, connected to each delay unit one by one, and supplies a smoothing current to each connected delay unit And
The correction current source is
Due to the association different from that of the smoothing current source, all or part of the plurality of delay units of the ring oscillation unit are provided in a one-to-one correspondence, and each delay unit is connected and connected one by one. The PLL circuit according to claim 2, wherein a correction current is supplied to each delay unit. The correction current source is
A one-to-one correspondence with all or part of the plurality of delay units of the ring oscillation unit;
The smoothing current source is
The PLL circuit according to claim 6, wherein the PLL circuit is provided in a one-to-one correspondence with a part of the delay unit to which the correction current source is connected. The smoothing current source is
A one-to-one correspondence with all or part of the plurality of delay units of the ring oscillation unit;
The correction current source is
The PLL circuit according to claim 6, wherein the PLL circuit is provided in a one-to-one correspondence with a part of the delay unit to which the smoothing current source is connected. The smoothing current source is
A one-to-one correspondence is provided for some of the plurality of delay units of the ring oscillation unit,
The correction current source is
The PLL circuit according to claim 6, wherein the PLL circuit is provided in a one-to-one correspondence with all or a part of the delay unit to which the smoothing current source is not connected. The ring oscillation unit is
The PLL circuit according to claim 9, further comprising a delay unit that is not connected to either the smoothing current source or the correction current source. At least one current source of the smoothing current source and the correction current source that supplies current to the ring oscillation unit is:
A plurality of current transistors having a control electrode, a first electrode and a second electrode, connected in parallel to each other;
One output terminal connected to the delay unit;
A current selector switch connected to the output terminal and having a smaller number of current switches than the plurality of current transistors;
The control electrodes of the plurality of current transistors are:
Commonly connected to the smoothing filter or the delay component filter,
The first electrodes of the plurality of current transistors are
Connected to one common power line,
The second electrodes of the plurality of current transistors are
A part is connected to the terminal via the current changeover switch, and the rest is directly connected to the terminal,
The PLL circuit includes:
11. The PLL circuit according to claim 2, further comprising a control unit configured to switch and control a current supplied from the current source to the ring oscillating unit by opening and closing the current switching switch. At least one delay unit of the ring oscillation unit is:
As the transistor that performs a switching operation under a driving current,
A first transistor that delays a signal by a switching operation;
A second transistor connected in parallel with the first transistor and delaying a signal by performing a switching operation in phase with the first transistor;
The smoothing current source is
Supplying current to the first transistor;
The correction current source is
Supplying current to the second transistor;
The PLL circuit includes:
A first connection switch connected between the smoothing current source and the first transistor;
The PLL circuit according to claim 2, further comprising: a control unit that controls a cycle of the oscillation signal by opening and closing the first connection switch. The PLL circuit includes:
A second connection switch connected between the correction current source and the second transistor;
The controller is
The PLL circuit according to claim 12, wherein the second connection switch is opened / closed independently of the first connection switch to control a cycle of the oscillation signal. The delay component filter is:
With a circuit configuration in which a resistive element and a capacitive element are connected in series, a voltage corresponding to a first-order response delay component included in the output signal of the charge pump is generated at a connection point between the resistive element and the capacitive element,
The correction current source is
The PLL circuit according to claim 1, wherein a correction current corresponding to a voltage level at a connection point between the resistance element and the capacitive element is supplied. A PLL circuit that outputs an oscillation signal having a phase synchronized with a reference signal;
An input unit to which the oscillation signal is input;
The PLL circuit includes:
A ring oscillation unit that generates an oscillation signal by a delay closed loop that delays the signal;
A phase comparator for comparing the phase of the oscillation signal and a reference signal;
A charge pump connected to the phase comparator;
A smoothing filter connected to the charge pump;
A smoothing current source connected to the smoothing filter and supplying a smoothing current according to an output signal smoothed by the smoothing filter to the ring oscillation unit;
A delay component filter that is connected to the output of the charge pump in parallel with the smoothing filter and extracts a response delay component included in the output signal of the charge pump;
A correction current source that generates a correction current corresponding to the response delay component extracted by the delay component filter and supplies the correction current to the ring oscillation unit, and
The ring oscillation unit is
An electronic apparatus having a delay unit that delays a signal by operating with a current supplied from at least one of the smoothing current source and the correction current source as a delay unit that delays a signal in the delay closed loop.

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