JP2011061512A - A/d conversion processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To store each piece of A/D converted data in a memory after performing A/D conversion, at a predetermined sampling interval, of an analog signal from a sensor without increasing a process load of a CPU, and without providing a special hardware for transferring the A/D converted data to the memory accompanied with termination of the A/D conversion. <P>SOLUTION: In a microcomputer 11 mounted on an ECU for controlling an engine, A/D conversion of injector pressure signals P1 to P4 is performed by activating an A/D converter 17 after occurrence of a trigger A (TrgA) in every occurrence of a rising edge (periodical edge) of a PWM signal from a PWM signal output circuit 21, while DMA transfer of the A/D converted data to a RAM 15 from the A/D converter 17 is performed by activating a DMA controller 19 after occurrence of a trigger B (TrgB) in every occurrence of a trailing edge (duty edge) of the PWM signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention performs A / D conversion on an analog signal from a sensor at a predetermined sampling interval, and stores each A / D conversion data which is digital data after the A / D conversion in a memory. Relates to the device.

  For example, as an electronic control device for controlling an engine of an automobile, an analog signal from a sensor that detects a predetermined physical quantity (for example, a combustion pressure in a cylinder or a pressure of fuel to be injected) used for engine control is specified. In the processing target period, the A / D converter performs A / D conversion at a predetermined sampling interval, and each A / D conversion data that is digital data after A / D conversion is sequentially stored in the RAM. Some A / D conversion data in the RAM performs processing for controlling the engine (see, for example, Patent Documents 1 and 2).

  As a technique for performing A / D conversion of an analog signal and storing A / D conversion data in a RAM, Japanese Patent Application Laid-Open Publication No. 2004-259542 discloses that the CPU performs an interrupt process at regular intervals from an A / D converter. It describes that a process of reading A / D conversion data and storing it in a RAM and a process of starting an A / D converter for the next A / D conversion are performed.

  In Patent Document 2, as <Method 1>, the CPU starts the A / D converter every time a timing signal is output from the timing generator, and when the A / D conversion is completed, It describes that A / D conversion data is read from a D converter and stored in a RAM.

  In Patent Document 2, as <Method 2>, the A / D converter is activated at an interval shorter than the output interval of the timing signal, and the CPU is output every time the timing signal is output. However, the latest A / D conversion data at that time is read from the A / D converter and stored in the RAM.

  On the other hand, a PWM signal output circuit (PWM signal generation circuit) that outputs a PWM (pulse width modulation) signal having a period and a pulse width set by the CPU is known (for example, see Patent Documents 3 and 4).

JP-A-2002-89346 (especially S710 and S730 in FIG. 7) Japanese Patent Laying-Open No. 2005-220796 (particularly paragraphs [0095] and [0096]) JP 11-214970 A Japanese Patent Laid-Open No. 10-2248

  In the technique of Patent Document 1, since the CPU performs the start of the A / D converter and the transfer of A / D conversion data from the A / D converter to the RAM, the processing load on the CPU increases. Therefore, there is a possibility that the process for controlling the control target cannot be performed smoothly. The problem that the processing load on the CPU increases becomes more prominent as the activation interval (sampling interval) of the A / D converter is shortened.

Further, such a problem occurs in the same manner even in <Method 1> of Patent Document 2.
On the other hand, in the above <Method 1> and <Method 2> of Patent Document 2, it is assumed that the A / D converter is started up in hardware, regardless of the processing of the CPU. The problem that the processing load of the CPU becomes large can be completely solved because the CPU still has to execute the process of transferring the A / D conversion data from the A / D converter to the RAM. Can not.

  In addition, in Patent Documents 1 and 2, if A / D conversion by the A / D converter is completed, it is difficult to transfer A / D conversion data from the A / D converter to the RAM regardless of the processing of the CPU. If it is configured so as to be implemented, the CPU processing load for the data transfer can be eliminated, but the A / D conversion data is transferred to the RAM in conjunction with the completion of the A / D conversion. Of hardware will be required.

  The present invention has been made in view of these problems, and the processing load of the CPU is that A / D conversion is performed on an analog signal from a sensor at a predetermined sampling interval and each A / D conversion data is stored in a memory. It is an object of the present invention to achieve without realizing the above and without providing dedicated hardware for transferring A / D conversion data to a memory in conjunction with completion of A / D conversion.

  The A / D conversion processing device according to claim 1 is provided in an electronic control device together with a CPU that performs processing for controlling a controlled object, and A / D converts an analog signal output from a sensor at a predetermined sampling interval. Each A / D conversion data which is digital data after the A / D conversion is stored in the memory. In order to realize this function, the A / D conversion processing apparatus according to claim 1 includes an A / D converter, a DMA (Direct Memory Access) controller, an A / D conversion request generation means, and a transfer request generation. In addition to the means, a signal generation circuit is provided.

When the analog signal is input and the A / D converter receives an A / D conversion request signal instructing execution of A / D conversion, the A / D converter performs A / D conversion on the analog signal.
When the DMA controller receives a DMA transfer request signal for instructing DMA transfer of A / D conversion data from the A / D converter to the memory, the DMA controller transmits the A / D conversion data from the A / D converter to the memory. Along with the transfer, each time the DMA transfer request signal is received, the transfer destination address of the A / D conversion data in the memory is changed, thereby storing a plurality of A / D conversion data in the memory. That is, every time the DMA controller receives a DMA transfer request signal, the DMA controller transfers A / D conversion data from the A / D converter to a different address in the memory.

  On the other hand, when the first signal edge, which is one of the rising edge and the falling edge, is generated in the signal input to the A / D conversion request generation means, the A / D conversion is sent to the A / D converter. A conversion request signal is given. Then, the A / D converter is activated to A / D convert the analog signal.

  The transfer request generating means gives a DMA transfer request signal to the DMA controller when a second signal edge, which is one of a rising edge and a falling edge, is generated in a signal input to the transfer request generating means. Then, the DMA controller is activated to perform data transfer from the A / D converter to the memory (that is, transfer of A / D conversion data).

  The signal generation circuit operates in parallel with the CPU and supplies signals to the A / D conversion request generation means and the transfer request generation means. The first signal edge is generated at each sampling interval, and the second signal edge is generated at a timing delayed from the generation timing of the first signal edge in the signal to the transfer request generating means.

  Therefore, in the A / D conversion processing device according to the first aspect, the A / D converter is activated each time the first signal edge is generated in the signal from the signal generation circuit to the A / D conversion request generation means. A / D conversion of the analog signal is performed, and a second signal edge is generated in the signal from the signal generation circuit to the transfer request generation means at each timing delayed from the activation of the A / D converter. Thus, the DMA controller is activated, and data transfer from the A / D converter to the memory is performed.

  A series of operations such as A / D conversion of analog signals and transfer of A / D conversion data to the memory by the A / D conversion are performed separately from the processing of the CPU. In addition, dedicated hardware for transferring A / D conversion data to the memory in conjunction with completion of A / D conversion is not required.

  Therefore, according to the A / D conversion processing apparatus of the first aspect, the analog signal from the sensor is A / D converted at a predetermined sampling interval, and each of the A / D conversion data is stored in the memory. This can be realized without increasing the processing load and without providing dedicated hardware for transferring A / D conversion data to the memory in conjunction with the completion of A / D conversion.

  By the way, as described in claim 2, the delay time Tdelay from the generation timing of the first signal edge to the generation of the second signal edge is determined by the A / D converter receiving the A / D conversion request signal. Is longer than the A / D conversion time Tad until the A / D conversion of the analog signal is completed, and shorter than the first signal edge generation interval (sampling interval) Ts. “A / D converter completes A / D conversion” means that “A / D conversion data is finalized and the A / D conversion data can be read correctly”. It is.

  If such a time relationship (Tad <Tdelay <Ts) is satisfied, the A / D converter completes the A / D conversion of the analog signal and the A / D conversion data for that time is determined. Before the A / D converter starts the next A / D conversion, data transfer from the A / D converter to the memory can be started, and indefinite A / D conversion during the A / D conversion is being performed. This is because it is possible to avoid transferring data to the memory.

  Further, as described in claim 3, the delay time Tdelay is a DMA transfer time Tdma from when the DMA controller receives the DMA transfer request signal until the transfer of A / D conversion data to the memory is completed. It is preferable that the time is less than the time (Ts−Tdma) subtracted from the generation interval Ts of one signal edge.

  If such a time relationship (Tad <Tdelay <Ts−Tdma) is satisfied, the data transfer from the A / D converter to the memory is performed before the A / D converter starts the next A / D conversion. This is because the A / D conversion data can be transferred to the memory more reliably.

  Next, in the A / D conversion processing device according to claim 4, in the A / D conversion processing device according to claims 1 to 3, the first signal edge and the second signal edge are edges in opposite directions. The signal generation circuit is a circuit that outputs a high / low signal having a predetermined duty ratio with the sampling interval as a cycle, and outputs the high / low signal from the A / D conversion request generation means and the transfer request generation means. And supply to both. Furthermore, one of the rising and falling edges of the high / low signal from the signal generating circuit is the first signal edge, and the other edge is the second signal edge. The high / low signal is a rectangular wave signal.

  That is, in the A / D conversion processing device according to claim 4, the A / D converter is activated at the timing when one edge is generated in the high / low signal output from the signal generating circuit, and the timing when the other edge is generated. In this way, the DMA controller is activated.

According to this A / D conversion processing apparatus, the signal generation circuit only outputs one high / low signal, and therefore the configuration can be simplified.
Next, in the A / D conversion processing device according to claim 5, in the A / D conversion processing device according to claim 4, the signal generation circuit performs PWM with a period and a pulse width set by the CPU as the high / low signal. It is a PWM signal output circuit that outputs a signal.

  According to this configuration, since the cycle of the PWM signal becomes the first signal edge generation interval (that is, the sampling interval), the sampling interval is arbitrarily set according to the cycle value set in the PWM signal output circuit by the CPU. can do. Further, the delay time Tdelay from the generation timing of the first signal edge to the generation of the second signal edge can be arbitrarily set by the value of the pulse width set in the PWM signal output circuit by the CPU. Therefore, versatility is high.

  As for the edge of the PWM signal, the generation interval varies depending on the period value among the period and pulse width values set in the PWM signal output circuit by the CPU, and the generation timing depends on the pulse width value. There is a periodic edge that is an edge that does not change, and a duty edge that is an edge in the opposite direction to the periodic edge and whose generation interval from the periodic edge changes depending on the value of the pulse width. When the periodic edge is the first signal edge and the duty edge is the second signal edge, the value of the pulse width is the delay time Tdelay. Conversely, when the duty edge is the first signal edge and the period edge is the second signal edge, the value of “period-pulse width” is the delay time Tdelay. Also, the generation interval of the duty edge is the same as the generation interval of the periodic edge and changes depending on the value of the period set in the PWM signal output circuit. Therefore, in any of the above cases, the value of the period is the sampling interval. Become.

  Next, in the A / D conversion processing device according to claim 6, in the A / D conversion processing device according to claim 4, the signal generation circuit outputs the high / low signal every time the crankshaft of the engine rotates by a predetermined angle. The crank angle signal output circuit outputs a crank angle signal at which an effective edge that is one of a rising edge and a falling edge is generated.

  According to this configuration, every time the crankshaft of the engine rotates by a predetermined angle, the A / D converter is activated. Therefore, it is effective when the interval at which the crankshaft rotates by a predetermined angle is desired as the sampling interval.

  Of the edges of the crank angle signal, if the effective edge is the first signal edge and the non-effective edge in the opposite direction is the second signal edge, the A / D converter is activated. Although it is preferable because the crank angle becomes clear, conversely, the non-effective edge can be the first signal edge, and the effective edge can be the second signal edge. In general, since the duty ratio of the crank angle signal is almost 50% without changing, the A / D converter is activated every time the crankshaft rotates by a predetermined angle even in the latter case. It is.

  On the other hand, in the A / D conversion processing device according to claim 7, in the A / D conversion processing device according to claims 1 to 3, the first signal edge and the second signal edge are edges in the same direction. The signal generation circuit outputs a high / low signal having a predetermined duty ratio with the sampling interval as a cycle, and delays the high / low signal output from the signal output circuit by a predetermined time and outputs the signal And a high / low signal from the signal output circuit to the A / D conversion request generating means, and a high / low signal from the delay circuit to the transfer request generating means. Further, an edge in a specific direction which is one of a rising edge and a falling edge of the high / low signal output from the signal output circuit becomes a first signal edge, and the high signal output from the delay circuit. / The edge in the specific direction of the low signal is the second signal edge.

  That is, in the A / D conversion processing device according to claim 7, the A / D converter is activated at the timing when the edge in the specific direction is generated in the high / low signal from the signal output circuit, and the high / low signal from the delay circuit is generated. The DMA controller is activated at the timing when an edge in a specific direction occurs.

  Also with this configuration, the A / D conversion processing device according to claims 1 to 3 can be realized. Further, the sampling interval can be changed according to the period of the high / low signal output from the signal output circuit, and the delay time Tdelay can be changed according to the delay time (the predetermined time) in the delay circuit.

It is a block diagram showing ECU (electronic control apparatus) of 1st Embodiment. It is a time chart showing operation | movement of each part in the microcomputer of ECU of 1st Embodiment. It is explanatory drawing explaining what value the pulse width Tduty (= delay time Tdelay) of a PWM signal is set to. It is a block diagram showing ECU of 2nd Embodiment. It is a block diagram showing ECU of 3rd Embodiment. It is a time chart showing operation of each part in a microcomputer of ECU of a 3rd embodiment. It is a block diagram showing ECU of 4th Embodiment.

Hereinafter, an electronic control device according to an embodiment to which the present invention is applied will be described. The electronic control device according to the present embodiment controls, for example, a diesel engine of an automobile, but hereinafter, a portion directly related to the present invention will be described.
[First Embodiment]
As shown in FIG. 1, the electronic control device (hereinafter referred to as ECU) 1 of the first embodiment includes a microcomputer 11.

  The microcomputer 11 executes the ROM 12 in which the program is stored, the CPU 13 that performs various processes for controlling the engine 3 by executing the program in the ROM 12, the calculation results by the CPU 13, and the CPU 13 controls the engine 3. And a RAM 15 for temporarily storing data and the like used for the above.

  Further, the microcomputer 11 includes an A / D converter (ADC) 17, a DMA controller (DMAC) 19, a PWM signal output circuit 21, an A / D conversion request generation circuit 23, and a DMA transfer request generation circuit 25. I have.

  The A / D converter 17 has a plurality of input terminals (four in this example) to which analog signals are input, and an A / D conversion request signal (TrgA in FIG. 1) for instructing execution of A / D conversion. Upon receipt, A / D conversion is performed on a plurality of analog signals from each input terminal.

  The A / D converter 17 in this example is a multi-channel A / D converter that sequentially switches analog signals at each input terminal and performs A / D conversion by one A / D conversion circuit. The channels ch1 to ch4 for A / D conversion are provided. In addition, since the A / D conversion request signal is a trigger for performing A / D conversion, the A / D conversion request signal is hereinafter referred to as TrgA meaning trigger A.

  When the DMA controller 19 receives a DMA transfer request signal (TrgB in FIG. 1) for instructing DMA transfer, the channel (A / D converter 17 channel set by the CPU 13 in advance as a DMA transfer target ( The A / D conversion data of the transfer target A / D channel is transferred from the A / D converter 17 to the RAM 15 (DMA transfer). In the DMA controller 19, the CPU 13 is also configured to set the start address (hereinafter referred to as the storage start address) of the RAM 15 in which A / D conversion data is stored and the number of continuous transfers.

  When the DMA controller 19 is initialized by the CPU 13 with the transfer target A / D channel, storage head address, and continuous transfer count set, the DMA transfer execution count reaches the continuous transfer count. Until the DMA transfer request signal is received, the A / D conversion data of the transfer target A / D channel is transferred to the RAM 15, and the transfer destination address of the A / D conversion data in the RAM 15 is set to one from the storage head address. Proceed step by step. Therefore, every time the DMA controller 19 receives a DMA transfer request signal, the DMA controller 19 stores the A / D conversion data of the transfer target A / D channel in the A / D converter 17 one by one from the storage head address of the RAM 15 one by one. If the number of DMA transfer implementations reaches the number of continuous transfers, the DMA transfer implementation is stopped until the CPU 13 initializes again.

  The initialization of the DMA controller 19 performed by the CPU 13 is a counter that counts the number of DMA transfers performed by the DMA controller 19 or a counter that counts the number of advances from the storage start address of the transfer destination address. Is cleared to 0. On the other hand, since the DMA transfer request signal is a trigger for implementing DMA transfer, the DMA transfer request signal is hereinafter referred to as TrgB meaning trigger B.

  The PWM signal output circuit 21 includes a period value register 21a and a pulse width value register 21b in which a period value (period value) and a pulse width value (pulse width value) of the PWM signal are written by the CPU 13, respectively. Are circuits operating in parallel. The PWM signal output circuit 21 generates a PWM signal having the period of the value written in the period value register 21a and the pulse width of the value written in the pulse width value register 21b. The PWM signal is output from the signal output terminal J3 of the microcomputer 11 to the outside. Such a PWM signal output circuit 21 is described in, for example, the above-mentioned Patent Document 3, and in Patent Document 3, the pulse width value of the PWM signal is referred to as a duty value.

In this embodiment, among the edges of the PWM signal, the rising edge is the above-described periodic edge, and the falling edge is the above-described duty edge.
As shown in FIG. 2, in the PWM signal in this embodiment, the high time from the rising edge to the falling edge (from the cycle edge to the duty edge) is a pulse width Tduty corresponding to the value of the pulse width value register 21b. is there. In FIG. 2, Tpwm is the period of the PWM signal and is the interval between the periodic edges, but the interval between the duty edges is also the same as Tpwm.

  The A / D conversion request generation circuit 23 adds one of a rising edge and a falling edge (corresponding to a first signal edge) to a signal input via the signal input terminal J1 of the microcomputer 11. In this embodiment, when a rising edge) occurs, TrgA (A / D conversion request signal) is given to the A / D converter 17.

  Further, the DMA transfer request generation circuit 25 corresponds to one of the rising edge and the falling edge (corresponding to the second signal edge) to the signal input via the signal input terminal J2 of the microcomputer 11. In this embodiment, when a falling edge occurs, TrgB (DMA transfer request signal) is given to the DMA controller 19.

  Such an A / D conversion request generation circuit 23 and a DMA transfer request generation circuit 25 generally include a free-run timer circuit, a circuit for generating a timer interrupt, and a circuit for an input capture function in a microcomputer. Etc. are provided in a timer unit which is a block having.

  The two signal input terminals J1 and J2 are connected in common with the signal output terminal J3 by wiring outside the microcomputer 11. For this reason, the PWM signal from the PWM signal output circuit 21 is input to both the A / D conversion request generation circuit 23 and the DMA transfer request generation circuit 25 via the wiring outside the microcomputer 11.

  Therefore, the A / D conversion request generation circuit 23 outputs TrgA to the A / D converter 17 when a periodic edge which is a rising edge occurs in the PWM signal from the PWM signal output circuit 21, and the DMA transfer request generation circuit When a duty edge that is a falling edge occurs in the PWM signal from the PWM signal output circuit 21, TrgB 25 is output to the DMA controller 19.

  On the other hand, as shown in FIG. 1, in the engine 3 that is the control target of the ECU 1, each injector IJ <b> 1 that injects fuel from a common rail (not shown) to each cylinder (four cylinders in this embodiment) of the engine 3. ˜IJ4 are provided with pressure sensors S1 to S4 for detecting fuel pressure in the injectors IJ1 to IJ4 (hereinafter referred to as injector pressure).

  The injector pressure signals P1 to P4, which are analog signals output from the pressure sensors S1 to S4, are input to the channels of the A / D converter 17 in the microcomputer 11 via the input circuit 5 provided in the ECU 1. (Each input terminal) It inputs into ch1-ch4.

The engine 3 is provided with a known crank angle sensor 7 that outputs a pulse each time the crankshaft of the engine 3 rotates by a predetermined angle (for example, 10 °).
The pulse signal from the crank angle sensor 7 is shaped into a high / low signal by the waveform shaping circuit 9 provided in the ECU 1, so that the rising edge rises and falls every time the crankshaft rotates by the predetermined angle. This is a crank angle signal in which an effective edge (rising edge in this embodiment) that is one of the falling edges is generated. Further, the crank angle signal from the waveform shaping circuit 9 is input to the microcomputer 11. The microcomputer 11 detects the rotational position and rotational speed of the crankshaft (that is, the engine speed) based on the crank angle signal. Moreover, as a general matter, the duty ratio of the crank angle signal is 50%.

Next, the operation of each part in the microcomputer 11 will be described.
As shown in FIG. 2, in the microcomputer 11, the PWM signal output circuit 21 outputs a PWM signal having a cycle Tpwm and a pulse width Tduty set by the CPU 13.

  Every time a periodic edge (rising edge) occurs in the PWM signal, TrgA is output from the A / D conversion request generation circuit 23 to the A / D converter 17 and the A / D converter 17 is activated. Then, the A / D converter 17 sequentially converts the analog signals of the channels ch1 to ch4 (that is, the injector pressure signals P1 to P4 of each cylinder) in order (in order of increasing channel numbers in this embodiment). To do.

  Further, every time a duty edge (falling edge) occurs in the PWM signal, TrgB is output from the DMA transfer request generation circuit 25 to the DMA controller 19 and the DMA controller 19 is activated. Then, as described above, the DMA controller 19 transfers the A / D conversion data of the transfer target A / D channel set by the CPU 13 from the A / D converter 17 to the RAM 15 (DMA transfer).

  Therefore, the A / D converter 17 is activated at the generation timing of the periodic edge of the PWM signal, the injector pressure signals P1 to P4 are A / D converted, and the generation timing of the duty edge of the PWM signal (that is, the periodic edge) At a timing delayed by the pulse width Tduty), the DMA controller 19 is activated, and the A / D conversion data of the transfer target A / D channel is transferred from the A / D converter 17 to the RAM 15. It will be.

  The period Tpwm of the PWM signal is the sampling interval (A / D conversion interval, which is also the sampling period) Ts of the injector pressure signals P1 to P4. The pulse width Tduty of the PWM signal is a delay time Tdelay from the generation of the periodic edge and TrgA to the generation of the duty edge and TrgB, and the A / D conversion data after the A / D converter 17 is activated. This is also the delay time Tdelay until the DMA transfer to the RAM 15 starts.

From the above, in this embodiment, the period Tpwm of the PWM signal is set to an interval (for example, 20 μs) at which the injector pressure signals P1 to P4 should be sampled.
Also, the pulse width Tduty of the PWM signal is “the DMA controller 19 starts DMA transfer after the A / D conversion data in the A / D converter 17 is confirmed, and the next A / D conversion is started. Is set to a time during which the operation condition “DMA controller 19 completes DMA transfer by the time when it is completed” can be satisfied. The reason for setting in this way is to ensure that the A / D conversion data can be stored in the RAM 15.

  Then, in order to satisfy the above operating conditions, what value the pulse width Tduty (= the delay time Tdelay) of the PWM signal is set will be described in more detail with reference to FIG. In the following description based on FIG. 3, the pulse width Tduty of the PWM signal is referred to as a delay time Tdelay, and the period Tpwm of the PWM signal is referred to as a sampling interval Ts.

  In FIG. 3, “Ts” is a sampling interval (= Tpwm) of the injector pressure signals P1 to P4. “Tad” is an A / D conversion time from when the A / D converter 17 receives TrgA until A / D conversion is completed (until A / D conversion data is determined), and “Tdma”. Is the DMA transfer time from when the DMA controller 19 receives TrgB to when the transfer of A / D conversion data to the RAM 15 is completed.

  In the present embodiment, in order to satisfy the above operating conditions, the delay time Tdelay (= Tduty) is set to a value satisfying the magnitude relationship of “Tad <Tdelay <Ts−Tdma”. That is, the delay time Tdelay is set to be longer than the A / D conversion time Tad and shorter than the time obtained by subtracting the DMA transfer time Tdma from the sampling interval Ts (= Ts−Tdma).

  In addition, this means that when the time obtained by subtracting the A / D conversion time Tad from the delay time Tdelay (= Tdelay−Tad) is “T1”, the T1 is “0 <T1 <Ts−Tad−Tdma”. The delay time Tdelay is set so as to satisfy the condition, but in particular, the delay time Tdelay is set so that T1 becomes a value of “(Ts−Tad−Tdma) / 2”. In this case, a margin time from the completion of A / D conversion to the start of DMA transfer (when TrgB occurs) and the start of the next A / D conversion from the completion of DMA transfer (when the next TrgA occurs) ), And the most reliable operation can be expected.

  The DMA transfer time Tdma is shorter than the minimum time from when the A / D converter 17 starts A / D conversion until the A / D conversion data in the A / D converter 17 changes. In this case, it is sufficient that the delay time Tdelay satisfies the relationship of “Tad <Tdelay <Ts” at the minimum. As long as this relationship is satisfied, the DMA controller 19 performs the DMA transfer of the A / D conversion data before the next A / D conversion is started after the A / D converter 17 completes the A / D conversion. Because it can start.

  On the other hand, the CPU 13 sets the transfer target A / D channel to be set in the DMA controller 19 at this time every time the processing target period for a predetermined crank angle (for example, 120 ° CA) including the fuel injection timing of each cylinder starts. The DMA controller 19 is initialized while being switched (reset) to a channel in which the injector pressure signals P1 to P4 of the cylinder at which the fuel injection timing arrives during the processing target period.

  CA is an idiomatic term meaning the rotation angle (crank angle) of the crankshaft of the engine 3. In the present embodiment, the CPU 13 sets the initial values for the storage head address and the number of continuous transfers, for example, in the DMA controller 19 in the process immediately after the start of the operation, and does not change thereafter, but continues with the storage head address. Both or one of the transfer counts may be reset to a different value for each processing target period.

  Therefore, in the processing target period for each cylinder, for example, in the processing target period including the fuel injection timing of the third cylinder, as shown in FIG. 2, among the channels ch1 to ch4 of the A / D converter 17, The channel ch3 to which the injector pressure signal P3 for the third cylinder is input is set as the transfer target A / D channel. The DMA controller 19 DMA-transfers the A / D conversion data of the channel ch3 (that is, the A / D conversion data of the injector pressure signal P3 of the third cylinder) to the RAM 15 every time TrgB is received.

Thus, in this embodiment, the A / D conversion data of the injector pressure signal of the injection target cylinder where fuel injection is performed is DMA-transferred to the RAM 15 at the same interval as the A / D conversion interval.
Then, every time the processing target period ends, the CPU 13 analyzes (for example, integrates) the A / D conversion data stored in the RAM 15 to calculate the actual fuel injection amount, and the fuel to the engine 3 is calculated. The injection amount is controlled with high accuracy. For example, the subsequent fuel injection amount is corrected according to the calculation result of the actual fuel injection amount.

  According to the ECU 1 of the first embodiment as described above, every time a periodic edge occurs in the PWM signal from the PWM signal output circuit 21 in the microcomputer 11, TrgA is generated and the A / D converter 17 is activated. As a result, the A / D conversion of the injector pressure signals P1 to P4 is performed, and whenever the duty edge is generated in the PWM signal, TrgB is generated and the DMA controller 19 is started, whereby the A / D converter 17 DMA transfer of A / D conversion data to the RAM 15 is performed.

  A series of operations such as A / D conversion and transfer of A / D conversion data to the RAM 15 are performed separately from the processing of the CPU 13. In addition, dedicated hardware for transferring A / D conversion data to the RAM 15 in conjunction with completion of A / D conversion is not required.

  Therefore, the subject of this application can be solved. That is, A / D conversion of the injector pressure signal at a predetermined sampling interval and storing the A / D conversion data in the RAM 15 are linked to completion of the A / D conversion without increasing the processing load on the CPU 13. This can be realized without providing dedicated hardware for transferring the A / D conversion data to the RAM 15.

  In addition, the PWM signal output circuit 21 only needs to output one PWM signal, and the PWM signal output circuit 21 is a circuit originally provided in the microcomputer 11, which increases the size of the apparatus configuration. There is no.

  Further, the sampling interval (A / D conversion interval) can be arbitrarily set by the period value set in the PWM signal output circuit 21 by the CPU 13, and the pulse width value set in the PWM signal output circuit 21 by the CPU 13 can be set. Since the delay time Tdelay can be arbitrarily set, the versatility is very high.

  In this embodiment, the part other than the CPU 13 and the ROM 12 in the microcomputer 11 in FIG. 4 corresponds to an A / D conversion processing device. The RAM 15 corresponds to a memory, the A / D conversion request generation circuit 23 corresponds to an A / D conversion request generation means, the DMA transfer request generation circuit 25 corresponds to a transfer request generation means, and the PWM signal output circuit 21 This corresponds to a signal generation circuit.

  On the other hand, in the above embodiment, among the edges of the PWM signal, the periodic edge is the first signal edge (that is, the edge on which the A / D conversion request generation circuit 23 generates TrgA), and the duty edge is Is the second signal edge (that is, the edge on which the DMA transfer request generation circuit 25 generates TrgB). Conversely, the duty edge is the first signal edge, and the periodic edge is the second edge. The signal edge may be used. In that case, the value of “period Tpwm−pulse width Tduty” becomes a delay time Tdelay from the occurrence of TrgA to the occurrence of TrgB, and the pulse of the PWM signal so that the delay time Tdelay satisfies the above magnitude relationship. The width Tduty may be set.

  Further, the first signal edge may be a falling edge and the second signal edge may be a rising edge. Further, the periodic edge of the PWM signal may be a falling edge and the duty edge may be a rising edge.

Although not versatile, a clock generation circuit that outputs a high / low signal with a fixed duty ratio can be used instead of the PWM signal output circuit 21.
[Second Embodiment]
The ECU 31 of the second embodiment shown in FIG. 4 differs from the first embodiment in the following points.

  That is, both the A / D conversion request generation circuit 23 and the DMA transfer request generation circuit 25 in the microcomputer 11 are connected to the crank signal from the waveform shaping circuit 9 instead of the PWM signal via the two signal input terminals J1 and J2. An angular signal is input. Note that the microcomputer 11 according to the second embodiment may or may not include the PWM signal output circuit 21.

Therefore, the ECU 31 of the second embodiment performs an operation in which the “PWM signal” in FIG. 2 is replaced with the “crank angle signal”.
That is, the A / D converter 17 is activated at the timing of occurrence of the valid edge (rising edge) of the crank angle signal, the injector pressure signals P1 to P4 are A / D converted, and the ineffective edge (rising edge) of the crank angle signal is generated. The DMA controller 19 is activated at the occurrence timing of the falling edge), and the operation of transferring the A / D conversion data of the transfer target A / D channel from the A / D converter 17 to the RAM 15 is repeated. The cycle of the crank angle signal becomes the sampling interval (A / D conversion interval) Ts of the injector pressure signals P1 to P4.

  According to such a second embodiment, the problem of the present application can be solved as in the first embodiment. In particular, it is effective when the interval at which the crankshaft of the engine 3 rotates by a predetermined angle (10 ° in this embodiment) is set as the sampling interval.

Incidentally, the duty ratio of the crank angle signal is fixed unlike the PWM signal from the PWM signal output circuit 21 and is generally 50%, but there is no problem.
For example, even when the engine speed is 6000 rpm, the time for 10 ° CA, which is one cycle (= Ts) of the crank angle signal, is about 280 μs, and the delay time Tdelay ( That is, the high time from the effective edge to the non-effective edge of the crank angle signal is about 140 μs. Each of the A / D conversion time Tad and the DMA transfer time Tdma in FIG. 3 is generally several μs. Therefore, even when the duty ratio of the crank angle signal is 50%, the above-described magnitude relationship of “Tad <Tdelay <Ts−Tdma” can be sufficiently satisfied. Further, even if the conditions are further strict, even if one cycle of the crank angle signal is a time of 1 ° CA and “Ts = 28 μs, Tdelay = 14 μs”, if Tad and Tdma are several μs, The above-mentioned magnitude relationship can be satisfied.

  On the other hand, in the above-described embodiment, the effective edge of the crank angle signal edges is the first signal edge (that is, the edge on which the A / D conversion request generation circuit 23 generates TrgA), and the ineffective edge. Is the second signal edge (that is, the edge on which the DMA transfer request generation circuit 25 generates TrgB), but the non-effective edge is the first signal edge and the effective edge is May be the second signal edge.

  Although described as a modification of the first embodiment, the first signal edge may be a falling edge and the second signal edge may be a rising edge. The effective edge of the crank angle signal may be a falling edge, and the ineffective edge may be a rising edge.

In the second embodiment, the waveform shaping circuit 9 corresponds to a signal output circuit and a crank angle signal output circuit.
Further, in the engine control ECU, an effective edge is obtained for each constant crank angle (for example, 1 ° CA) smaller than the predetermined angle (10 °) from the crank angle signal after waveform shaping by the waveform shaping circuit 9. There is a case where a crank angle signal processing circuit for generating and outputting a crank angle signal for generating the. Therefore, the crank angle signal from such a crank angle signal processing circuit may be input to both the A / D conversion request generation circuit 23 and the DMA transfer request generation circuit 25. In this case, the crank angle signal processing circuit corresponds to a signal output circuit and a crank angle signal output circuit.
[Third Embodiment]
The ECU 33 of the third embodiment shown in FIG. 5 differs from the first embodiment in the following points (1) and (2).

  (1) The DMA transfer request generation circuit 25 gives TrgB to the DMA controller 19 when a rising edge occurs in the signal input via the signal input terminal J2. That is, the second signal edge that generates TrgB is an edge in the same direction as the first signal edge that generates TrgA.

  (2) In the ECU 33, a delay circuit 27 is provided outside the microcomputer 11, and the delay circuit 27 outputs a PWM output from the PWM signal output circuit 21 to the outside of the microcomputer 11 via the signal output terminal J3. A signal is input. The delay circuit 27 delays the PWM signal from the PWM signal output circuit 21 by a predetermined time and outputs the delayed signal to the signal input terminal J2 of the microcomputer 11.

  For this reason, the PWM signal from the PWM signal output circuit 21 (referred to as signal A in the following description of the third embodiment) is directly input to the A / D conversion request generation circuit 23, but a DMA transfer request is generated. The circuit 25 is supplied with a PWM signal from the delay circuit 27, which is obtained by delaying the signal A by a predetermined time (referred to as signal B in the following description of the third embodiment).

  In the ECU 33 of the third embodiment, as shown in FIG. 6, the A / D converter 17 is activated at the timing of the rising edge of the signal A, and the injector pressure signals P1 to P4 are A / D converted. Then, the DMA controller 19 is activated at the timing of occurrence of the rising edge of the signal B, and the operation in which the A / D conversion data of the transfer target A / D channel is transferred from the A / D converter 17 to the RAM 15 is repeated. It is.

  In the third embodiment, the delay circuit 27 delays the signal A, and the delay time Tdelay in FIG. 6 corresponds to the delay time Tdelay in FIG. 3. The delay time Tdelay in FIG. It is set to a value satisfying the magnitude relationship of “Tad <Tdelay <Ts−Tdma”. In the third embodiment, the period of the signal A (PWM signal) is the sampling interval Ts of the injector pressure signals P1 to P4.

  According to the third embodiment, the problem of the present application can be solved as in the first embodiment. Even if a clock generation circuit that outputs a high / low signal with a fixed duty ratio is used instead of the PWM signal output circuit 21, the delay time Tdelay from TrgA to TrgB is adjusted by the delay time in the delay circuit 27. can do.

  In the present embodiment, the PWM signal output circuit 21 and the delay circuit 27 correspond to a signal output circuit. The rising edges of the signals A and B correspond to edges in a specific direction according to claim 7.

On the other hand, both the first signal edge for generating TrgA and the second signal edge for generating TrgB may be falling edges. In this case, the A / D converter 17 is activated at the occurrence timing of the falling edge of the signal A, and the DMA controller 19 is activated at the occurrence timing of the falling edge of the signal B.
[Fourth Embodiment]
The ECU 35 of the fourth embodiment shown in FIG. 7 differs from the third embodiment in the following points.

  That is, the PWM signal output from the PWM signal output circuit 21 to the outside of the microcomputer 11 via the signal output terminal J3 is directly input to the signal input terminal J2 of the microcomputer 11, and the signal is input from the signal input terminal J2 in the microcomputer 11. The input PWM signal is delayed by a predetermined time by the delay circuit 29 and input to the DMA transfer request generation circuit 25.

  That is, in the fourth embodiment, the delay circuit 29 having the same role as the delay circuit 27 in FIG. The delay circuit 29 may be any circuit that delays the signal in the microcomputer 11. For example, the delay circuit 29 samples the input signal in synchronization with the clock, and the level at which the sampling result is the same continuously for a predetermined number of times or more. A circuit such as an output signal level can be used. In the case of this circuit, the output signal changes to the same level as the input signal when the predetermined number of times of sampling is performed after the input signal has changed in level. For this reason, the delay time can be changed by the predetermined number of times.

  And also by such 4th Embodiment, the same effect | action and effect as 3rd Embodiment are acquired. Moreover, compared with 3rd Embodiment, there exists an advantage which can reduce the component of ECU35.

  As mentioned above, although one Embodiment of this invention was described, this invention is not limited to such Embodiment at all, Of course, in the range which does not deviate from the summary of this invention, it can implement in a various aspect. .

  For example, the sensor is not limited to the pressure sensors S1 to S4 described above, and may be a sensor that detects the combustion pressure in the cylinder. Further, the control target may be other than the engine.

  DESCRIPTION OF SYMBOLS 1,31,33,35 ... ECU (electronic control unit), 3 ... Engine, 5 ... Input circuit, 7 ... Crank angle sensor, 9 ... Waveform shaping circuit, 11 ... Microcomputer, 12 ... ROM, 13 ... CPU, 15 ... RAM, 17 ... A / D converter, 19 ... DMA controller, 21 ... PWM signal output circuit, 21a ... period value register, 21b ... pulse width value register, 23 ... A / D conversion request generation circuit, 25 ... DMA transfer request Generation circuit, 27, 29 ... delay circuit

Claims (7)

Provided in the electronic control unit together with a CPU that performs processing for controlling the controlled object,
An A / D conversion processing apparatus that performs A / D conversion on an analog signal output from a sensor at a predetermined sampling interval and stores each A / D conversion data that is digital data after the A / D conversion in a memory. There,
When the analog signal is input and an A / D conversion request signal instructing execution of A / D conversion is received, an A / D converter that A / D converts the analog signal;
When receiving a DMA transfer request signal for instructing DMA transfer of the A / D conversion data from the A / D converter to the memory, the A / D conversion data is transferred from the A / D converter to the memory. A DMA controller that stores a plurality of the A / D conversion data in the memory by changing a transfer destination address of the A / D conversion data in the memory each time the DMA transfer request signal is received; ,
A / D conversion request generating means for providing the A / D conversion request signal to the A / D converter when a first signal edge, which is one of a rising edge and a falling edge, is generated in the input signal. When,
When a second signal edge that is one of a rising edge and a falling edge occurs in the input signal, transfer request generating means for supplying the DMA transfer request signal to the DMA controller;
A circuit that operates in parallel with the CPU and supplies a signal to the A / D conversion request generation means and the transfer request generation means; and the signal to the A / D conversion request generation means A signal generation circuit for generating one signal edge at each sampling interval and generating the second signal edge at a timing delayed from the generation timing of the first signal edge in the signal to the transfer request generation means; ,
An A / D conversion processing apparatus comprising: The A / D conversion processing device according to claim 1,
The delay time from the generation timing of the first signal edge to the generation of the second signal edge is the A / D conversion of the analog signal after the A / D converter receives the A / D conversion request signal. Longer than the A / D conversion time until the completion of, and shorter than the generation interval of the first signal edge,
A / D conversion processing device characterized by the above. The A / D conversion processing device according to claim 2,
The delay time is defined as the DMA transfer time from when the DMA controller receives the DMA transfer request signal until the transfer of the A / D conversion data to the memory is completed, from the generation interval of the first signal edge. Less than the time you subtract,
A / D conversion processing device characterized by the above. In the A / D conversion processing device according to any one of claims 1 to 3,
The first signal edge and the second signal edge are edges in opposite directions;
The signal generation circuit is a circuit that outputs a high / low signal having a predetermined duty ratio with the sampling interval as a cycle, and the A / D conversion request generation means and the transfer request generation of the one high / low signal. Supply both with the means,
Of the rising and falling edges of the high / low signal, one edge is the first signal edge and the other edge is the second signal edge,
A / D conversion processing device characterized by the above. The A / D conversion processing device according to claim 4,
The signal generation circuit is a PWM signal output circuit that outputs a PWM signal having a period and a pulse width set by the CPU as the high / low signal;
A / D conversion processing device characterized by the above. The A / D conversion processing device according to claim 4,
The signal generation circuit outputs, as the high / low signal, a crank angle signal for generating an effective edge that is one of a rising edge and a falling edge each time the crankshaft of the engine rotates by a predetermined angle. Output circuit,
A / D conversion processing device characterized by the above. In the A / D conversion processing device according to any one of claims 1 to 3,
The first signal edge and the second signal edge are edges in the same direction,
The signal generation circuit outputs a high / low signal having a predetermined duty ratio with the sampling interval as a cycle, and delays and outputs the high / low signal output from the signal output circuit by a predetermined time. Comprising a delay circuit, supplying a high / low signal from the signal output circuit to the A / D conversion request generating means, and supplying a high / low signal from the delay circuit to the transfer request generating means,
An edge in a specific direction which is one of a rising edge and a falling edge of the high / low signal output from the signal output circuit becomes the first signal edge, and the high / low signal output from the delay circuit. The edge in the specific direction of the signal is the second signal edge;
A / D conversion processing device characterized by the above.