JP2001248493A - Pulse output control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately output pulses, even if a duty ratio is in the vicinity of 0%. SOLUTION: A CPU starts the execution of a processing for storing fuel injection timing t1 and fuel injection time as a rising point of time of a pulse and a falling point of time, respectively, for a first pulse output unit at a processing starting point t0 earlier than a starting point of a reference period by a prescribed margin. The processing is terminated within the prescribed margin. At the next processing starting point t2, the execution of the same processing is started for a second pulse output unit. Subsequently, the execution of the same processing is alternately started for both units for every processing starting point. The first pulse output unit raises the pulse at the stored rising point of time t1 and lets down the pulse at the falling point of time. The second pulse output unit outputs pulses in the same way. Because pulses outputted from both the units are outputted via an OR device, pulses are outputted for every reference period as a result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a pulse output control device used for various controls for outputting a pulse.

[0002]

2. Description of the Related Art Conventionally, there is a control device for controlling, for example, an internal combustion engine using a microcomputer. Some devices of this type include a pulse output unit for controlling the internal combustion engine in order to reduce the computational load on the CPU.

Here, the pulse output unit is a device having a management function of outputting a desired signal when a predetermined time has been reached. For example, a pulse output unit counts a clock signal output from a clock oscillator at predetermined time intervals. A free-running counter as a timing unit for performing time counting, an on-comparison register as a storage unit for storing the fuel injection timing calculated by the CPU, and a storage unit for storing the fuel injection time calculated by the CPU. Off compare register.

This pulse output unit starts a pulse when the value stored in the on-compare register matches the count value of the free running counter,
When the value stored in the off compare register matches the count value of the free running counter, the pulse is dropped to output a pulse.

According to this pulse output unit, the CPU
The CPU only sets the fuel injection timing and the fuel injection time, etc., and executes the subsequent injection execution processing and the processing of driving the fuel injection valve for a predetermined time at a predetermined rotation angle position and executing the fuel injection. Can be performed without intervention.

[0006]

However, with such a pulse output unit, it has been difficult to output a pulse whose duty ratio (the ratio of the pulse width to the reference period) is close to 0% or 100%.

That is, when the duty ratio is near 0%, C
The PU writes the fuel injection timing to the on-compare register and writes the fuel injection time to the off-comparison register.
In the case where it takes longer than a short pulse width time of about%, there is a problem that no pulse is generated in the reference period.

In order to solve this problem, for example, it is conceivable to slightly delay the fuel injection timing. However, when the duty ratio is close to 100%, the off-time of the pulse is shifted to the next reference cycle. The problem arises. Therefore, at present, for example, when the duty ratio is less than 5%, it is handled as zero, and when it is more than 95%, it is handled as 100%.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems.
It is an object of the present invention to provide a pulse output control device that outputs a pulse accurately even in the vicinity.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a pulse output control device for outputting a pulse every reference period, comprising a plurality of pulse output means, and a plurality of pulse output means. Storage means for sequentially storing the rising time and the falling time of the pulse in the means, and logical sum output means for outputting the logical sum of the pulses output from the plurality of pulse output means to the outside. The storage control means starts the process of storing the rising time and the falling time of the pulse in each pulse output means at a point earlier by a predetermined margin time than the start point of the reference cycle. .

In describing the present invention, the plurality of pulse output means will be described as first pulse output means, second pulse output means,..., N-th pulse output means (N is an integer of 2 or more). The storage control means performs a process of first storing the rising time and the falling time of the pulse in the first pulse output means at a time earlier than the start point of the reference cycle by a predetermined margin time (hereinafter referred to as “processing start point”). Start execution. Here, the start point of the reference period is stored as the rising point of the pulse, and a value calculated in advance (or a value referred to in a map or a table) is stored as the falling point of the pulse. Then, at the next processing start point, the same processing is started on the second pulse output means, and thereafter, every time the processing start point is reached, the same processing is sequentially started on the pulse output means. After the similar processing is started for the N-th pulse output means, the same processing is again started for the first pulse output means at the next processing start point.

The first pulse output means starts the pulse when the time measured by the timer section reaches the rising point of the pulse stored in the storage section, that is, the start point of the reference period, after the processing by the storage control means is completed. When the pulse falls, the pulse falls,
Output pulse. Other pulse output means similarly output pulses. Since the first to N-th pulse output means sequentially output pulses, each pulse output means outputs a pulse in each cycle having a length N times the reference cycle (hereinafter, referred to as “control reference cycle”). Will be.

The logical sum of the pulses sequentially output from the plurality of pulse output means is output to the outside by the logical sum output means. Here, since the pulses output from the plurality of pulse output units rise at each start point of the reference period, if the logical sum of these pulses is calculated, the pulse is output every reference period. As described above, a pulse is output for each reference cycle.

Here, a feature of the present invention is that the storage control means does not start the process of storing the rising time and the falling time of the pulse in each pulse output means at the start point of the reference cycle, but at the reference point. The point is that the execution is started at a point earlier than the start point of the cycle by a predetermined margin time.

For this reason, even if the duty ratio is near 0% (that is, the difference between the rising time and the falling time of the pulse is small), the rising time and the falling time for realizing the duty ratio are stored. It does not happen that the falling point is passed during the process of causing the falling. Therefore, it is possible to surely perform a pulse output such that the pulse rises at the same time as the start point of the reference period, and the pulse falls after a short time.

Even if the duty ratio is close to 100%, the pulse can rise at the same time as the starting point of the reference cycle, so that the falling point of the pulse is shifted after the starting point of the next reference cycle. Nor. As described above, according to the present invention, when the duty ratio is close to 0% or 10%.
Even if it is near 0%, a pulse can be output accurately and reliably.

In the present invention, the number of pulse output means may be two, and the storage control means may alternately store the rising time and the falling time of the pulse in the two pulse output means. This case is preferable because the effects of the present invention can be obtained without unnecessarily increasing the number of pulse output units. Note that the control reference cycle of the pulse output means at this time is twice the reference cycle.

It is preferable that the predetermined margin time in the present invention is set to be sufficiently longer than the time required for the storage control means to store the rising time and the falling time of the pulse in the pulse output means. That is, the predetermined margin time may be set to the time required for the above processing, but is set to be sufficiently longer than the time required for the above processing in consideration of a delay when another interrupt processing is executed. It is preferred that

For example, the predetermined margin time may be half the length of the reference cycle. In particular, when there are two pulse output means, if the predetermined margin time is set to half of the reference cycle, a pulse is output in a range of 25 to 75% of the control reference cycle. This is preferable because it is considered to be the optimum range in which the process can be performed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a schematic configuration of the microcomputer according to the present embodiment. The microcomputer 10 according to the present embodiment corresponds to a pulse output control device according to the present invention, and mainly includes a ROM 1
1, a RAM 12, a CPU 13, and an input / output unit 14, which are connected by a data bus 17 so that data can be transmitted and received.

The ROM 11 stores a fuel injection amount control program and an ignition timing control program executed by the microcomputer 10 and a valve opening time (fuel injection time) of a fuel injection valve for injecting a required fuel injection amount. ) Is a memory for storing various tables and the like used for calculating (1).

The RAM 12 is a memory for temporarily storing the operation results. The CPU 13 is a main processing unit that performs calculations based on a fuel injection amount control program and an ignition timing control program stored in the ROM 11. This CP
The U13 inputs various signals from various sensors (not shown) and the RAM 12 connected to the microcomputer 10 as necessary, and executes the fuel injection amount control and the ignition timing control described above. Further, it writes the calculation result in the RAM 12 and outputs a control signal to various devices (not shown) such as an injector and an igniter connected to the microcomputer 10 via the input / output unit 14.

The input / output unit 14 includes a pulse input unit 15 and a pulse output unit 20. Of these, the pulse input unit 15
Is generally called input capture, and has a function of latching the value of the free running counter 213 when a designated valid edge (for example, a rising edge or a falling edge of a rotation angle signal) is input. Have. The pulse input unit 15 is used, for example, when measuring the pulse interval from the latched time (effective edge time) and calculating the engine speed.

The pulse output section 20 is configured by combining a first pulse output unit 21 and a second pulse output unit 22 with an OR element 23. The OR element 23 is provided when the first pulse output unit 21 is connected to one input terminal, the second pulse output unit 22 is connected to the other input terminal, and an ON signal is applied to at least one of both input terminals. Is an element that outputs an ON signal to the device.

The first pulse output unit 21 includes an on-compare register 211 and an off-comparison register 21.
2, a free running counter 213, an on-match detection circuit 214, an off-match detection circuit 215, and an RS flip-flop circuit 216.

The on-compare register 211 includes a CPU
13 is a register in which the calculated fuel injection timing is stored.
This is a register in which the fuel injection time calculated by the PU 13 is stored. These data are stored (updated by overwriting) in both compare registers 211 and 212 by the CPU 13.

The free-running counter 213 is a counter that counts a clock signal output from a clock generator (not shown) every predetermined time and counts time, and is reset at a timing of a carry of a predetermined bit. The ON match detection circuit 214 is provided with an ON compare register 2
11 is a circuit for outputting a detection signal to the RS flip-flop circuit 216 when the measured time of the free running counter 213 coincides with the measurement time of the free running counter 213.
Is a circuit that outputs a detection signal to the RS flip-flop circuit 216 when the measurement time of the off compare register 212 and the measurement time of the free running counter 213 match.

In the RS flip-flop circuit 216, the input terminal S is connected to the output terminal of the on-match detection circuit 214, the input terminal R is connected to the output terminal of the off-match detection circuit 215, and the output terminal Q is ORed. It is connected to one input terminal of the element 23. On the other hand, like the first pulse output unit 21, the second pulse output unit 22 includes an ON compare register 221 and an OFF compare register 22.
2, a free running counter 223, an on-match detection circuit 224, an off-match detection circuit 225, and an RS flip-flop circuit 226. The components are the same as those of the first pulse output unit 21, and the description thereof is omitted. The free running counter 223
Is assigned a different symbol from the free running counter 213 for the sake of convenience, but this embodiment has only one free running counter, and both counters 213 and 223
Are the same.

Next, the operation of the microcomputer 10 of the present embodiment will be described. The reference cycle when the CPU 13 performs the timer interrupt is obtained as follows. That is, the free-running counter 213 counts up every 1 μsec. The timing of the carry of the 12th bit, that is, 2 ¹² μsec = 4.096.
msec (referred to as 4 msec for convenience) is obtained in hardware as a reference cycle.

Further, the CPU 13 generates an event at each timing earlier than the start point of the reference cycle by 2 msec (half of the reference cycle) as a predetermined margin time, and executes a pulse output control program from the ROM 11 every time an event occurs. Read and interrupt. Here, since the reference cycle is 4 msec, the CPU 13
Will be interrupted every time.

In this pulse output control, as shown in FIG. 2, the CPU 13 alternately selects the first pulse output unit 21 and the second pulse output unit 22 every time an event occurs (S100). The fuel injection timing is written into the ON compare register of the selected pulse output unit (S110), the fuel injection time is written into the OFF compare register (S120), and this program processing ends. Note that the fuel injection timing coincides with the start point of the reference cycle. The fuel injection time is a value calculated in advance by the CPU 13 by the fuel injection amount control program.

The subsequent injection execution processing is executed by the first pulse output unit 21 and the second pulse output unit 22 of the pulse output unit 20 without the intervention of the CPU 13. This execution procedure will be described with reference to FIGS. 1 and 3 taking the first pulse output unit 21 as an example. FIG. 3 is a time chart showing a signal state of each part of the pulse output unit.

That is, in the first pulse output unit 21,
When the fuel injection timing stored in the on-comparing register 211 matches the time measured by the free running counter 213, a detection signal is output from the on-coincidence detecting circuit 214.
6, the input terminal S is “1”, the input terminal R is “0”,
“1”, that is, an ON signal is continuously output from the output terminal Q.

On the other hand, the fuel injection time stored in the off compare register 212 and the free running counter 21
3. When the measurement time of the counter 3 matches, the off-coincidence detection circuit 2
Since the detection signal is output from 15, the input terminal S of the RS flip-flop circuit 216 becomes “0”, the input terminal R becomes “1”, and the output terminal Q continuously outputs “0”, that is, an off signal. .

That is, the output signal of the first pulse output unit 21 rises to an ON signal at the start point of the reference cycle which is the fuel injection timing, and falls to an OFF signal when the fuel injection time elapses after the rise. The second pulse output unit 22 performs processing in the same procedure. That is, the output signal of the second pulse output unit 22 also rises to an ON signal at the start point of the reference cycle, which is the fuel injection timing, and falls to an OFF signal when the fuel injection time elapses after the rise.

Here, the operation of the first and second pulse output units 21 and 22 will be further described with reference to FIG. FIG. 4 is a time chart showing transition of a pulse with time. In FIG. 4, “Δ” (open inverted triangle) indicates the processing start point of the pulse output control, and “▼” (solid inverted triangle) indicates the start point of the reference cycle.

At time t0 (processing start point) which is earlier by a predetermined margin time than the start point of the reference cycle, the CPU 13 first stores the reference cycle, which is the fuel injection timing, in the ON compare register 211 of the first pulse output unit 21. Is stored as the rising point of the pulse,
Execution of the process of storing the fuel injection time as the falling time point in the off compare register 212 is started.
Then, at the next processing start point t2, the same processing is started for the second pulse output unit 22 this time. Thereafter, each time the processing start point is reached, the same processing is started alternately for the first and second pulse output units 21 and 22. The processing started at each processing start point is
It is completed within 2 msec which is a predetermined margin time.

After the end of the above processing by the CPU 13 started at the processing start point t0, the first pulse output unit 21 measures the time measured by the free running counter 213 at the rising edge of the pulse stored in the on compare register 211, When the start point t1 of the reference cycle is reached, a pulse is started up and the off compare register 21 is turned on.
When the pulse reaches the falling point of the pulse stored in 2, the pulse is dropped to output the pulse.

Further, the second pulse output unit 22 measures the time measured by the free running counter 223 after the end of the above-described processing by the CPU 13 started at the processing start point t 2, the rise of the pulse stored in the on-compare register 221. A pulse is output when the pulse rises at a time point, that is, at the start point t3 of the reference period, and falls when the pulse reaches the fall time point of the pulse stored in the off compare register 222.

As a result, the first and second pulse output units 21 and 22 alternately output a pulse at each start point of the reference cycle, so that each pulse output unit 21 and 22 has N times the reference cycle. A pulse is output every period of the length (control reference period, here, 8 msec).

The pulses output from the first and second pulse output units 21 and 22 are output to the outside as pulses of the pulse output unit 20 through the OR element 23. Here, the first and second pulse output units 21 and 2
Since the pulse output from 2 rises at each start point of the reference cycle, a pulse is output every reference cycle, that is, every time t1, t3, t5, t7, t9 is reached when the OR of these pulses is calculated. Will be.

Of the pulses output from the pulse output unit 20 for each reference cycle, the first, third, and fifth odd-numbered pulses are output by the first pulse output unit 21 and the second, fourth, and sixth pulses are output. An even-numbered pulse, such as a pulse, is output by the second pulse output unit 22.

Here, the correspondence between the components of the present embodiment and the components of the present invention will be described. The first and second pulse output units 21 and 22 of the present embodiment correspond to a plurality of pulse output units of the present invention, and include on-compare registers 211 and 221 and off-comparison registers 212 and 2.
Reference numeral 22 corresponds to the storage unit, and the free running counter 21
Reference numerals 3 and 223 correspond to a timing unit. The CPU 13 corresponds to a storage control unit, and the OR element 23 corresponds to an OR output unit.

According to the above embodiment, the CPU 13
Does not start execution of the pulse output control program at the start point of the reference cycle, but starts execution of the pulse output control program at a processing start point earlier by a predetermined margin time than the start point of the reference cycle. Therefore, as shown in FIG. 5A, even if the duty ratio is close to 0% (that is, the difference between the rising point and the falling point of the pulse is small),
Since the pulse output control for realizing the duty ratio is completed within a predetermined margin time, the pulse output control does not exceed the falling time point during the execution of the pulse output control, and the pulse output control does not exceed the start point of the reference cycle. At the same time, a pulse output such that a pulse rises and a pulse falls shortly after that can be reliably performed.

On the other hand, as shown in FIG. 5B, even if the duty ratio is near 100%, the pulse can rise at the same time as the start point of the reference period, so that the pulse falls at the next time. Does not shift after the start point of the reference cycle. As described above, an effect is obtained in which a pulse can be accurately and reliably output even when the duty ratio is near 0% or 100%.

Further, in this embodiment, the number of pulse output units is two, and the above-described effect can be effectively obtained without increasing the number of pulse output units and with a configuration as simple as possible and without cost. Further, the predetermined margin time is set so as to be longer than the time required for the CPU 13 to execute the pulse output control, in consideration of a delay when another interrupt process is executed, and the like. . For this reason, the above effects can be obtained reliably.

In particular, in the present embodiment, the predetermined margin time is set to half the length of the reference cycle, so that each of the pulse output units 21 and 22 operates as shown in FIG. %, The pulse is output. However, this area is preferable because it is considered to be an optimum range in which pulse output can be performed stably and reliably.

It should be noted that the embodiments of the present invention are not limited to the above embodiments at all, and it goes without saying that various forms can be adopted as long as they fall within the technical scope of the present invention. For example, in the above-described embodiment, the case where the present invention is applied to the fuel injection control is described as an example. However, the present invention is not limited to the fuel injection control, and any control that outputs a pulse may be applied to the present invention. The invention is applicable. For example, the present invention may be applied to idle speed control (ISC) of an internal combustion engine.
That is, as an ISC, a duty control of an actuator (ISC actuator) that opens and closes an air amount adjustment valve (ISCV) provided in a bypass pipe that bypasses a throttle valve is known. The target rotational speed of the engine at idle is stored in the ECU, and the flow rate of air taken into the internal combustion engine at idle is adjusted by the ISCV using an ISC actuator. Control to be equal. If the idle speed is controlled in this way, a shift in the idle speed due to a change over time,
It is possible to set a low idle speed without being affected by disturbances caused by load fluctuations of various electric loads such as an air conditioner and a power steering, thereby improving engine fuel efficiency while preventing engine stall. In this idle speed control, it is necessary to output the duty with high accuracy, so that the effect is effectively exhibited by applying the present invention.

The present invention may be applied to a multi-stage injection or the like in a diesel internal combustion engine.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a microcomputer according to an embodiment.

FIG. 2 is a flowchart of pulse output control according to the embodiment.

FIG. 3 is a time chart illustrating a signal state of each unit of the pulse output unit according to the embodiment.

FIG. 4 is a time chart showing a transition of a pulse with time according to the embodiment.

FIGS. 5A and 5B are time charts showing transition of a pulse with time according to the embodiment; FIG.
When the duty ratio is around 100%, (b) indicates when the duty ratio is around 100%.

[Explanation of symbols]

10: microcomputer, 11: ROM,
12 RAM, 13 CPU, 14 input / output unit, 15 pulse input unit, 20 pulse output unit, 21 first pulse output unit, 22 ... 2nd pulse output unit, 23... OR element, 21
1, 221... ON compare register, 212, 2
22 ... off compare register, 213, 223
..Free running counters, 214, 224,...
ON match detection circuits, 215, 225... OFF match detection circuits, 216, 226... RS flip-flop circuits.

Claims (4)

[Claims] 1. A pulse output control device for outputting a pulse for each reference cycle, comprising: a storage unit for storing a rising time and a falling time of a pulse; and a time measuring unit for measuring time, and the time measured by the time measuring unit. A plurality of pulse output means for raising a pulse when the time reaches the rising point of the pulse stored in the storage unit, and for lowering the pulse when reaching the falling point of the pulse; At the start of
The value calculated in advance is defined as the falling point of the pulse.
Storage control means for sequentially storing the plurality of pulse output means, and logical sum output means for outputting a logical sum of the pulses output from the plurality of pulse output means to the outside, wherein the storage control means A pulse output control device which starts the process of storing the rising time and the falling time of the reference cycle in each pulse output means at a time earlier by a predetermined margin time than the start point of the reference cycle. 2. The apparatus according to claim 1, wherein said pulse output means comprises two pulse output means, and said storage control means alternately stores a rising time and a falling time of a pulse in said two pulse output means. 2. The pulse output control device according to 1. 3. The method according to claim 1, wherein the predetermined margin time is set to be sufficiently longer than a time required for the storage control means to store the rising time and the falling time of the pulse in the pulse output means. Claim 1
Or the pulse output control device according to 2. 4. The apparatus according to claim 1, wherein the predetermined margin time is set to a half of a reference cycle.
3. The pulse output control device according to any one of 3.