JP2011054589A - Dicing tape and method of working semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dicing tape and a method of working a semiconductor wafer capable of appropriately fixing a semiconductor wafer in dicing treatment and fully widening a gap of a plurality of semiconductor chips in expand treatment. <P>SOLUTION: The dicing tape includes, in double-layer structure, a low-tension layer 21 for detachably bonding the semiconductor wafer 10 positioned in a hollow part 2 of a frame 1 while covering the hollow part 2 by a tape for holding the semiconductor wafer 10 bonded to the frame 1 for dicing by bonding to the back of the frame 1, and a high-tension layer 24 detachably bonded to the back of the low-tension layer 21, thus enabling the adhesive force of the low-tension layer 21 to be higher than that of the high-tension layer 24. When performing expand treatment, the high-tension layer 24 is peeled and the dicing tape 20 is set to be the low-tension layer 21 only, thus fully widening a gap among a plurality of semiconductor chips and preventing subsequent work from being impeded. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a dicing tape used in a semiconductor wafer dicing process, an expanding process, a die bonding process, or the like, and a semiconductor wafer processing method.

  Conventionally, when processing a semiconductor wafer, a dicing tape that holds the semiconductor wafer is adhered to a hollow frame (not shown), and a dicing process is performed on the semiconductor wafer to divide and form a plurality of semiconductor chips (die). Each of the semiconductor chips is picked up from the dicing tape after expanding the interval between the plurality of semiconductor chips by subjecting the tape to an expansion process and stretching (see Patent Documents 1 and 2). The dicing tape is formed by laminating an adhesive on a single base material.

JP 2000-124169 A JP 2009-94126 A

By the way, in recent years, semiconductor wafers have been increased in diameter from φ200 mm to φ300 and 450 mm from the viewpoint of increasing the chip size and improving productivity, and there has been a demand for reliable fixing during the dicing process.
In order to realize such a request, it is only necessary to change the base material of the dicing tape to a high tension type, but when doing so, when the dicing tape is subjected to the expansion process, the interval between the plurality of semiconductor chips cannot be sufficiently widened, There is a problem that it hinders later work.

  The present invention has been made in view of the above, and a dicing tape and a semiconductor wafer capable of appropriately fixing a semiconductor wafer at the time of dicing processing and capable of sufficiently widening the interval between a plurality of semiconductor chips at the time of expanding processing. It aims to provide a processing method.

In the present invention, in order to solve the above-described problem, a semiconductor wafer that is attached to a hollow frame and diced is held,
A low tension layer that includes a low tension layer that is attached to a frame to cover the hollow and adheres a semiconductor wafer located in the hollow of the frame, and a high tension layer that is detachably adhered to the low tension layer. The adhesive strength of is higher than the adhesive strength of the high-tensile layer.

  In the present invention, in order to solve the above-mentioned problem, a dicing tape according to claim 1 is attached to a hollow frame to hold a semiconductor wafer, and a dicing process is performed on the semiconductor wafer to form a plurality of semiconductor chips. After the high tension layer is peeled from the low tension layer of the dicing tape, the low tension layer of the dicing tape is subjected to an expanding process to widen the interval between the plurality of semiconductor chips.

  Here, the frame in the claims does not particularly need to be made of metal or resin. The semiconductor wafer includes a semiconductor wafer having a large diameter of at least φ300, 450, and 600 mm.

According to the present invention, when the semiconductor wafer held on the frame is diced, the dicing tape is formed of the low tension layer and the high tension type high tension layer, so that the semiconductor wafer is appropriately fixed. be able to.
On the other hand, when the dicing tape is expanded, the high tension layer is peeled off to make the dicing tape only the low tension layer, so that the low tension layer can be stretched to sufficiently widen the interval between the plurality of semiconductor chips. it can.

  According to the present invention, a dicing tape is formed from a low-tensile layer and a high-tensile layer, and the high-tensile layer is peeled off as needed from the low-tensile layer, so that the semiconductor wafer can be appropriately fixed during the dicing process, There is an effect that the intervals between the plurality of semiconductor chips can be sufficiently widened during the expanding process.

It is a perspective explanatory view showing typically the frame in the embodiment of the processing method of the semiconductor wafer concerning the present invention. It is a section explanatory view showing typically the frame in the embodiment of the processing method of the semiconductor wafer concerning the present invention. FIG. 3 is a partial cross-sectional explanatory view schematically showing a part of the dicing tape of FIG. 2. It is a section explanatory view showing typically the state where a high tension layer of a dicing tape in an embodiment of a processing method of a semiconductor wafer concerning the present invention is exfoliated. It is a section explanatory view showing typically the state just before performing an expansion process to a low tension layer of a dicing tape in an embodiment of a processing method of a semiconductor wafer concerning the present invention. It is a section explanatory view showing typically the state where an expansion process was performed to a low tension layer of a dicing tape in an embodiment of a processing method of a semiconductor wafer concerning the present invention.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. As shown in FIGS. 1 to 6, the dicing tape in the present embodiment is a semiconductor wafer 10 that is adhered to a frame 1 and diced in a dicing process. A low tension layer 21 that adheres to the frame 1 to adhere the semiconductor wafer 10 with a tape to be held, and a high tension layer 24 that adheres to the low tension layer 21. Different adhesive strengths are used.

  As shown in FIGS. 1 and 2, the frame 1 is formed into a plane substantially ring-shaped flat plate using a predetermined material, and functions to accommodate the semiconductor wafer 10 in the round hollow 2 with a gap. The predetermined material of the frame 1 is not particularly limited. For example, when the frame 1 is formed of a metal material, a material capable of preventing the occurrence of rust by plating stainless steel or the surface. Is preferably formed. On the other hand, when the frame 1 is molded from a molding material containing a resin, it may be molded from a molding material containing polyphenylene sulfide, polyamide, polycarbonate, or the like.

  The inner peripheral surface of the frame 1 is tapered to an inclined guide surface 3, and this guide surface 3 functions to properly drain the cleaning water used in the dicing process to the outside. The outer peripheral surface of the frame 1 is linearly formed on the front, rear, left and right sides, and positioning cutouts 4 are formed in a substantially triangular shape on both sides of the front part.

  The semiconductor wafer 10 is made of a silicon wafer having a large diameter of, for example, φ300 and 450 mm, and is thinned to a thickness of 250 μm or less, specifically about 25 to 100 μm by the backgrinding in the backgrinding process according to the application, and then dicing. Provided to the process.

  As shown in FIGS. 2 and 3, the dicing tape 20 is detachably adhered to the back surface, which is the lower surface of the frame 1, to cover the hollow 2, and the semiconductor wafer 10 located in the hollow 2 of the frame 1 is attached to and detached from the dicing tape 20. A stretchable low-tension layer 21 that freely adheres and holds, and a high-tension layer 24 that is detachably adhered to the back surface of the low-tension layer 21 are provided in an upper and lower two-layer structure, and the adhesive strength of the low-tension layer 21 is high. It is set larger than the adhesive force of the tension layer 24.

  The low-tension layer 21 is formed by laminating the adhesive 23 on the surface of the low-tension base material 22 with a thickness of 3 to 100 μm, preferably 10 to 50 μm. The back surface and the semiconductor wafer 10 are adhered to each other.

  The low-tensile substrate 22 includes low-density polyethylene (LDPE), linear low-density polyethylene (LLDPE), ethylene-propylene copolymer, polypropylene (unstretched), polybutene, polybutadiene, polymethylpentene, and ethylene-vinyl acetate. Copolymer, ethylene- (meth) acrylic acid copolymer, ethylene- (meth) methyl acrylate copolymer, ethylene- (meth) ethyl acrylate copolymer, polyvinyl chloride, vinyl chloride / vinyl acetate copolymer Examples thereof include a flexible film made of a polymer, ethylene / vinyl chloride / vinyl acetate copolymer, polyurethane, polyamide, ionomer, styrene-butadiene rubber, a water additive thereof, or a modified product thereof.

  The pressure-sensitive adhesive 23 is not particularly limited, and various pressure-sensitive adhesives are used. For example, rubber-based, acrylic-based, silicone-based, and polyvinyl ether-based pressure-sensitive adhesives can be used. Further, an energy ray curable adhesive or a heat-foaming adhesive typified by ultraviolet rays can also be used. Furthermore, an adhesive that can be used for dicing or die bonding may be used. The adhesive strength of the adhesive 23 is adjusted by adding various fillers or different materials.

  The high tension layer 24 is formed by thinly laminating the pressure-sensitive adhesive 26 to a thickness of 3 to 100 μm, preferably 10 to 50 μm, on the surface of the high-tension base material 25. It adheres to the back surface, that is, the base material 22 in a detachable manner. The high-strength substrate 25 is not particularly limited, but may be made of, for example, biaxially stretched polyester, biaxially stretched polypropylene, polyimide, polystyrene, polyethersulfone, polyphenylene sulfide, polyetherimide, polyamideimide, or the like. A flexible film is used. Moreover, as the adhesive 26, the adhesive similar to the adhesive 23 of the low tension layer 21 is used, and adhesive force is adjusted by addition of various fillers or different materials.

  In the above configuration, when processing a thinned large-diameter semiconductor wafer 10, first, the dicing tape 20 holding the semiconductor wafer 10 on the back surface of the frame 1, specifically an adhesive for the low-tensile layer 21. 23, the semiconductor wafer 10 is positioned in the hollow 2 of the frame 1 (see FIGS. 1 and 2), the excess portion of the dicing tape 20 protruding from the periphery of the frame 1 is cut, and the semiconductor is processed in the dicing process. A dicing process is performed on the wafer 10 to divide and form a plurality of semiconductor chips (die) 11.

  At this time, the dicing tape 20 having a multilayer structure may be adhered to the back surface of the frame 1, but the low tension layer 21 holding the semiconductor wafer 10 is adhered, and then the substrate 22 of the low tension layer 21 is subjected to high tension. The layer 24 may be adhered. In the dicing process of the semiconductor wafer 10, the frame 1 is positioned and fixed on the chuck table, and the cleaning water is sprayed and supplied from the side while the semiconductor wafer 10 is sprayed and supplied to the semiconductor wafer 10 by a blade that rotates a plurality of narrow grooves at high speed. This is performed by separating the semiconductor chips 11 into individual semiconductor chips 11.

  When a plurality of semiconductor chips 11 are formed, the adhesive high tension layer 24 is peeled off from the base material 22 of the low tension layer 21 of the dicing tape 20 (see FIG. 4). Is lower than the adhesive strength of the low tension layer 21, the high tension layer 24 can be easily peeled off from the low tension layer 21. When the high tension layer 24 is peeled off in this way, the low tension layer 21 of the dicing tape 20 is set on the expandable stage 30 of the expander that can be moved up and down to perform an expansion process (see FIGS. 5 and 6).

  Specifically, by narrowing the low tension layer 21 of the dicing tape 20 from the outer periphery by the press contact of the expanding stage 30 that rises, the narrow interval between the plurality of divided semiconductor chips 11 is expanded. When the interval between the plurality of semiconductor chips 11 is expanded, each semiconductor chip 11 may be picked up from the dicing tape 20.

  According to the above configuration, when the semiconductor wafer 10 is diced, since the dicing tape 20 is a multilayer structure of the low tension layer 21 and the high tension type high tension layer 24, the large-diameter semiconductor wafer 10 is removed during the dicing process. It can be fixed securely. Further, when the dicing tape 20 is subjected to an expanding process, the high-tensile layer 24 is peeled off to make the dicing tape 20 only the low-tensile layer 21, so that the interval between the plurality of semiconductor chips 11 can be sufficiently widened. There is no hindrance to later work.

  In the above embodiment, the high tension layer 24 is simply peeled from the low tension layer 21 of the dicing tape 20, but the peeled high tension layer 24 may be discarded as it is or may be used repeatedly.

DESCRIPTION OF SYMBOLS 1 Frame 2 Hollow 10 Semiconductor wafer 11 Semiconductor chip 20 Dicing tape 21 Low tension layer 22 Base material 23 Adhesive 24 High tension layer 25 Base material 26 Adhesive 30 Expanding stage

Claims (2)

A dicing tape for holding a semiconductor wafer to be diced by being attached to a hollow frame,
A low tension layer that includes a low tension layer that is attached to a frame to cover the hollow and adheres a semiconductor wafer located in the hollow of the frame, and a high tension layer that is detachably adhered to the low tension layer. A dicing tape characterized in that the adhesive strength of is higher than the adhesive strength of the high-tensile layer.   The dicing tape according to claim 1, which holds a semiconductor wafer, is attached to a hollow frame, the semiconductor wafer is diced to form a plurality of semiconductor chips, and the high tension layer is peeled from the low tension layer of the dicing tape. Then, the processing method of the semiconductor wafer characterized by expanding the space | interval of a several semiconductor chip by giving an expansion process to the low tension layer of a dicing tape.

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