JP2011044497A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
JP2011044497A
JP2011044497A JP2009190397A JP2009190397A JP2011044497A JP 2011044497 A JP2011044497 A JP 2011044497A JP 2009190397 A JP2009190397 A JP 2009190397A JP 2009190397 A JP2009190397 A JP 2009190397A JP 2011044497 A JP2011044497 A JP 2011044497A
Authority
JP
Japan
Prior art keywords
chip
semiconductor chip
semiconductor
wafer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009190397A
Other languages
Japanese (ja)
Inventor
Tadashi Kataoka
忠 片岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2009190397A priority Critical patent/JP2011044497A/en
Publication of JP2011044497A publication Critical patent/JP2011044497A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which an image can be accurately acquired even by a semiconductor chip thin in chip thickness. <P>SOLUTION: In a series of processes of manufacturing the semiconductor device having a plurality of chips laminated on a substrate, a semiconductor chip warped owing to stress as a result of thinning of the semiconductor chip is flattened (STEP 8-1) by pressing a transparent correction plate before the semiconductor chip is picked up from a sheet for fixation such as a dicing tape (STEP 8-3), and the semiconductor chip is imaged in this state to confirm the position and direction, and non-defective/defective mark of the semiconductor chip (STEP 8-2). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体チップを基板上に積層する半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device in which semiconductor chips are stacked on a substrate.

半導体パッケージの高密度化に伴い、半導体チップの高密度実装技術が必要になる。半導体装置の製造工程においては、まず、半導体ウエハの表面に素子を形成し、半導体ウエハの裏面を研削して半導体ウエハの厚みを薄くするとともに、半導体ウエハを個々の半導体チップにダイシングし、これら個片化された半導体チップを順にピックアップする。次いで、ピックアップした半導体チップを配線基板やリードフレーム等の基板上にダイボンディングする。この後、基板上に実装された半導体チップと基板との間でワイヤボンディング及び樹脂封止を実施することによって、各種形状の半導体装置が作製される。   As the density of semiconductor packages increases, high-density mounting technology for semiconductor chips is required. In the manufacturing process of a semiconductor device, first, elements are formed on the surface of the semiconductor wafer, the back surface of the semiconductor wafer is ground to reduce the thickness of the semiconductor wafer, and the semiconductor wafer is diced into individual semiconductor chips. The separated semiconductor chips are picked up in order. Next, the picked-up semiconductor chip is die-bonded on a substrate such as a wiring board or a lead frame. Thereafter, by performing wire bonding and resin sealing between the semiconductor chip mounted on the substrate and the substrate, semiconductor devices of various shapes are manufactured.

なお、ダイシングシートから半導体チップをピックチップする際、これに先立って、ウエハ検出器(たとえばウエハ認識カメラ)で、半導体チップの位置・方向および良/不良マークの確認を行う。従来、半導体チップを認識する場合、半導体チップにハロゲン照明やLED照明などの同軸落射照明を使用し、その反射光をウエハ検出器で撮像することにより、半導体チップの位置・方向および良/不良マークの確認を行い、半導体チップが良品か否かを判断しピックアップを行っている。   Prior to picking a semiconductor chip from the dicing sheet, the position / direction of the semiconductor chip and the good / bad mark are confirmed by a wafer detector (for example, a wafer recognition camera). Conventionally, when recognizing a semiconductor chip, a coaxial incident illumination such as halogen illumination or LED illumination is used for the semiconductor chip, and the reflected light is imaged by a wafer detector. And confirming whether the semiconductor chip is a non-defective product or not.

半導体チップは、チップ厚が100μm程度の薄膜化では、ほとんど変形は発生しない。しかしながら更に薄膜化を進めて85μm程度にすると、半導体チップの内部応力によって凹状または凸状に変形する。そのため、従来の同軸落射照明では半導体チップからの光が均一に反射されず、ウエハ検出器で光を正確に捉えることができなくなり、認識率が低下し、半導体チップの位置・方向および良/不良マークの確認ができなくなる。   The semiconductor chip is hardly deformed when the chip thickness is reduced to about 100 μm. However, when the film thickness is further reduced to about 85 μm, it is deformed into a concave shape or a convex shape due to internal stress of the semiconductor chip. For this reason, the light from the semiconductor chip is not uniformly reflected in the conventional coaxial incident illumination, the light cannot be accurately captured by the wafer detector, the recognition rate is lowered, the position / direction of the semiconductor chip, and good / bad The mark cannot be confirmed.

これに対して従来、面発光照明を用い、さらにその面発光照明からの照射光を拡散板を透過させた後にピックアップ対象の半導体チップの主面に照射し、その反射光をウエハ検出器によって受光することによって、ピックアップ対象の半導体チップの主面の画像を取得することが提案されている(例えば、特許文献1)。   In contrast to this, conventionally, surface emitting illumination is used, and further, the light emitted from the surface emitting illumination is transmitted through the diffuser plate and then irradiated to the main surface of the semiconductor chip to be picked up, and the reflected light is received by the wafer detector. Thus, it has been proposed to acquire an image of the main surface of the semiconductor chip to be picked up (for example, Patent Document 1).

特開2008−66452号公報JP 2008-66452 A

しかしながら、上記面発光照明からの照射光を拡散板を透過させた後に半導体チップの主面に照射する方法においては、半導体チップの変形量が小さい場合はよいが、変形量が大きくなると照明の数と光の入射角度などの調整が難しく、半導体チップの種類やサイズによって配置を変化させる必要があり調整に時間を有する。チップ厚が85μm以下に薄厚化されている場合、UV照射後の接着剤層の硬さとエキスパンドによる固定用シートの張りにより、40μm〜60μmもの反りが発生し、この方法では対処しきれず実質的に不可能であるという問題があった。   However, in the method of irradiating the main surface of the semiconductor chip after the irradiation light from the surface-emitting illumination is transmitted through the diffusion plate, it is good if the deformation amount of the semiconductor chip is small, but if the deformation amount is large, the number of illuminations It is difficult to adjust the incident angle of light and the like, and it is necessary to change the arrangement depending on the type and size of the semiconductor chip. When the chip thickness is reduced to 85 μm or less, the warp of 40 μm to 60 μm occurs due to the hardness of the adhesive layer after UV irradiation and the tension of the fixing sheet by the expand, and this method cannot substantially cope with it. There was a problem that it was impossible.

さらにチップ厚が85μm以下に薄厚化されている場合、UV照射後の硬化した接着剤層の影響により、半導体チップのピックアップ時(剥離時)に大きな力が必要となり、半導体チップを固定用シートから剥離する際にクラックが発生するという問題もあった。   Further, when the chip thickness is reduced to 85 μm or less, a large force is required at the time of picking up the semiconductor chip (during peeling) due to the effect of the cured adhesive layer after UV irradiation, and the semiconductor chip is removed from the fixing sheet. There was also a problem that cracks occurred when peeling.

本発明は、上記に鑑みてなされたものであって、半導体チップの位置認識を画像取得によって行う工程において、チップ厚が薄く変形量が大きい半導体チップであっても、正確に画像取得を行うことができ、正確な位置認識を行うことができる半導体装置の製造方法を提供することを目的とする。   The present invention has been made in view of the above, and in a step of performing position recognition of a semiconductor chip by image acquisition, even if the chip has a thin chip thickness and a large amount of deformation, the image acquisition is accurately performed. An object of the present invention is to provide a method of manufacturing a semiconductor device that can perform accurate position recognition.

上述した課題を解決し、目的を達成するために、本発明にかかる半導体装置の製造方法は、基板上に複数のチップを積層する半導体装置の製造方法において、半導体素子が形成されたウエハのダイシングラインまたはチップ分割ラインに沿って、半導体素子の形成面側から完成時のチップの厚さよりも深い溝を形成し、ウエハの半導体素子の形成面上に表面保護シートを貼り付け、ウエハの裏面を完成時のチップの厚さまで研削して、ウエハを個々のチップに分離し、表面に接着剤層が形成された固定用シートを分離されたチップの裏面に貼り付け、表面保護シートを剥離し、分離されたチップに対応して、接着剤層を切断し、固定用シートをエキスパンドして、チップを剥がれやすい状態にし、チップの半導体素子の形成面を透明矯正板で押圧してチップの反りを矯正し、チップを撮像し得られた画像からチップの位置誤差を検出し、チップを固定用シートからピックアップし、ピックアップしたチップを位置誤差を補正して基板上にダイボンディングすることを特徴とする。   In order to solve the above-described problems and achieve the object, a semiconductor device manufacturing method according to the present invention includes a semiconductor device manufacturing method in which a plurality of chips are stacked on a substrate. Along the line or chip dividing line, a groove deeper than the chip thickness at the time of completion is formed from the semiconductor element formation surface side, a surface protection sheet is pasted on the semiconductor element formation surface of the wafer, and the back surface of the wafer is attached Grinding to the thickness of the chip at completion, separating the wafer into individual chips, attaching a fixing sheet with an adhesive layer formed on the surface to the back of the separated chip, peeling the surface protection sheet, Corresponding to the separated chip, the adhesive layer is cut, the fixing sheet is expanded, the chip is easily peeled off, and the semiconductor element formation surface of the chip is formed with a transparent straightening plate. Chip to correct the warp of the chip, detect the chip position error from the image obtained by picking up the chip, pick up the chip from the fixing sheet, correct the position error of the picked chip and die bond on the substrate It is characterized by doing.

本発明にかかる半導体装置の製造方法によれば、チップ厚の薄い半導体チップであっても、正確に画像取得を行うことができ、これにより半導体チップの位置認識を正確に行うことができるという効果を奏する。   According to the method for manufacturing a semiconductor device according to the present invention, it is possible to accurately acquire an image even with a semiconductor chip having a thin chip thickness, thereby enabling accurate position recognition of the semiconductor chip. Play.

図1は、実施の形態1の半導体装置の製造方法の各工程を示すフローチャートである。FIG. 1 is a flowchart showing each step of the manufacturing method of the semiconductor device of the first embodiment. 図2は、ウエハの表面部に半導体素子を形成する半導体素子形成工程を示す図である。FIG. 2 is a diagram showing a semiconductor element forming process for forming a semiconductor element on the surface portion of the wafer. 図3は、形成された個々の半導体素子に基づいてウエハに溝を形成する工程を示す図である。FIG. 3 is a diagram showing a process of forming grooves in the wafer based on the formed individual semiconductor elements. 図4は、ウエハに表面保護テープを貼り付ける工程を示す図である。FIG. 4 is a diagram showing a process of attaching a surface protection tape to the wafer. 図5は、ウエハの裏面部を研削及び研磨して複数の半導体チップに分割する工程を示す図である。FIG. 5 is a diagram showing a process of grinding and polishing the back surface of the wafer and dividing it into a plurality of semiconductor chips. 図6は、ウエハを固定用シートに搭載する工程を示す図である。FIG. 6 is a diagram illustrating a process of mounting the wafer on the fixing sheet. 図7は、ウエハを固定用シートに搭載する工程を示す図である。FIG. 7 is a diagram illustrating a process of mounting the wafer on the fixing sheet. 図8は、ウエハから表面保護テープを剥離する工程を示す図である。FIG. 8 is a diagram illustrating a process of peeling the surface protection tape from the wafer. 図9は、レーザにて接着剤層を切断する工程を示す図である。FIG. 9 is a diagram illustrating a process of cutting the adhesive layer with a laser. 図10は、ダイシングテープをエキスパンドして接着剤層を割断する工程を示す図である。FIG. 10 is a diagram showing a process of expanding the dicing tape to cleave the adhesive layer. 図11は、分離した半導体チップをピックアップする工程を示す図である。FIG. 11 is a diagram illustrating a process of picking up the separated semiconductor chip. 図12は、ピックアップした半導体チップをリードフレームにダイボンディングする工程を示す図である。FIG. 12 is a diagram illustrating a process of die-bonding a picked-up semiconductor chip to a lead frame. 図13は、半導体チップを樹脂にてモールドする工程を示す図である。FIG. 13 is a diagram illustrating a process of molding a semiconductor chip with a resin. 図14は、図1のピックアップ・ダイボンディングの工程の詳細を示すフローチャートである。FIG. 14 is a flowchart showing details of the pick-up die bonding process of FIG. 図15は、実施の形態1のダイボンダ装置の斜視図である。FIG. 15 is a perspective view of the die bonder device according to the first embodiment. 図16は、ウエハ検出器の模式側面図である。FIG. 16 is a schematic side view of the wafer detector. 図17は、透明矯正板の斜視図である。FIG. 17 is a perspective view of a transparent correction plate. 図18は、透明矯正板、ウエハ検出器及びピックアップコレットの動作を示す模式図である。FIG. 18 is a schematic diagram showing the operations of the transparent straightening plate, the wafer detector, and the pickup collet. 図19は、ウエハ検出器の他の例を示す、透明矯正板、ウエハ検出器及びピックアップコレットの動作を示す模式図である。FIG. 19 is a schematic diagram showing operations of the transparent correction plate, the wafer detector, and the pickup collet, showing another example of the wafer detector. 図20は、実施の形態2のダイボンダの斜視図である。FIG. 20 is a perspective view of the die bonder according to the second embodiment. 図21は、本実施の形態のピックアップコレットの下面図である。FIG. 21 is a bottom view of the pickup collet of the present embodiment. 図22は、図21のピックアップコレットの側断面図である。FIG. 22 is a side sectional view of the pickup collet of FIG. 図23は、実施の形態2のピックアップコレット及びウエハ検出器の動作を示す模式図である。FIG. 23 is a schematic diagram illustrating operations of the pickup collet and the wafer detector according to the second embodiment. 図24は、透明矯正板兼用型のピックアップコレットの他の例を示す下面図である。FIG. 24 is a bottom view showing another example of a pickup collet that is also used as a transparent straightening plate. 図25は、図24のピックアップコレットの側断面図である。FIG. 25 is a side sectional view of the pickup collet of FIG.

以下に、半導体装置の製造方法の実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。   Hereinafter, embodiments of a method for manufacturing a semiconductor device will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

実施の形態1.
図13は、本実施の形態の半導体装置の製造方法により製造された半導体装置を模式的に示す横断面図である。半導体装置50は、配線基板或いはリードフレームなどの基板41上に積層された9枚の半導体チップ(チップ)40を有している。個々の半導体チップ40は、ボンディングワイヤ42により基板41と電気的に接続されている。基板41及び個々の半導体チップ40は、相互間に挟まれた接着剤層16により固着されている。そして、積層された半導体チップ40とボンディングワイヤ42は、封止樹脂43によって封止されている。基板41の裏面には、はんだボール44が設けられている。
Embodiment 1 FIG.
FIG. 13 is a cross-sectional view schematically showing a semiconductor device manufactured by the semiconductor device manufacturing method of the present embodiment. The semiconductor device 50 has nine semiconductor chips (chips) 40 stacked on a substrate 41 such as a wiring board or a lead frame. Each semiconductor chip 40 is electrically connected to the substrate 41 by bonding wires 42. The substrate 41 and the individual semiconductor chips 40 are fixed by an adhesive layer 16 sandwiched between them. The stacked semiconductor chip 40 and bonding wire 42 are sealed with a sealing resin 43. Solder balls 44 are provided on the back surface of the substrate 41.

9枚の半導体チップ40は、NAND型フラッシュメモリを内蔵する8枚の半導体チップと、コントローラとしてのドライブ制御回路を内蔵する1枚の半導体チップとからなる。個々の半導体チップ40は薄厚化され、その厚さは約20μmである。また、接着剤層16の厚さは約40μm、基板41の厚さは約110μm、半導体装置50全体の厚さは約770μmである。   The nine semiconductor chips 40 are composed of eight semiconductor chips incorporating NAND flash memory and one semiconductor chip incorporating a drive control circuit as a controller. Each semiconductor chip 40 is thinned, and its thickness is about 20 μm. The thickness of the adhesive layer 16 is about 40 μm, the thickness of the substrate 41 is about 110 μm, and the thickness of the entire semiconductor device 50 is about 770 μm.

このような薄厚化された半導体チップ40を積層して実装する半導体装置50(実装する半導体チップ40の厚さが概ね85μm以下)の製造方法について説明する。なお、最初に極薄の半導体装置50の一連の製造方法を最初から最後まで説明し、次いで特定の工程について詳細に説明する。   A manufacturing method of the semiconductor device 50 (the thickness of the semiconductor chip 40 to be mounted is approximately 85 μm or less) in which such thinned semiconductor chips 40 are stacked and mounted will be described. First, a series of manufacturing methods of the ultrathin semiconductor device 50 will be described from the beginning to the end, and then specific steps will be described in detail.

図1は、本実施の形態の半導体装置の一連の製造方法の各工程を示すフローチャートである。また、図2は、ウエハの表面部に半導体素子を形成する半導体素子形成工程、図3は、形成された個々の半導体素子に基づいてウエハに溝を形成する工程、図4は、ウエハに表面保護テープを貼り付ける工程、図5は、ウエハの裏面部を研削及び研磨して複数の半導体チップに分割する工程、図6及び図7は、ウエハを固定用シート(ダイシングテープ)に搭載する工程、図8は、ウエハから表面保護テープを剥離する工程、図9は、レーザにて接着剤層を切断する工程、図10は、固定用シート(ダイシングテープ)をエキスパンドして接着剤層を割断する工程、図11は、分離した半導体チップをピックアップする工程、図12は、ピックアップした半導体チップをリードフレームにダイボンディングする工程、及び図13は、半導体チップを樹脂にてモールドする工程を示す図である。   FIG. 1 is a flowchart showing each step of a series of manufacturing methods of the semiconductor device of the present embodiment. 2 is a semiconductor element forming step for forming a semiconductor element on the surface portion of the wafer, FIG. 3 is a step for forming a groove in the wafer based on each formed semiconductor element, and FIG. 4 is a surface on the wafer. 5 is a process of grinding and polishing the back surface of the wafer to divide it into a plurality of semiconductor chips, and FIGS. 6 and 7 are processes of mounting the wafer on a fixing sheet (dicing tape). 8 is a process of peeling the surface protection tape from the wafer, FIG. 9 is a process of cutting the adhesive layer with a laser, and FIG. 10 is a cleaved adhesive layer by expanding a fixing sheet (dicing tape). 11 shows a step of picking up the separated semiconductor chip, FIG. 12 shows a step of die-bonding the picked-up semiconductor chip to the lead frame, and FIG. The flop is a diagram showing a process for molding a resin.

図1のフローチャートに沿って、上記半導体装置50の製造方法について説明する。実装する半導体チップ40の厚さが概ね85μm以下の非常に薄い半導体装置50の製造においては、例えば以下のように行われる。
[半導体素子の形成]
まず、図2に示す如く、ウエハ11の主表面に、周知のプロセスにより種々の半導体素子12を形成する(STEP1)。
A method for manufacturing the semiconductor device 50 will be described with reference to the flowchart of FIG. For example, the manufacturing of the very thin semiconductor device 50 in which the thickness of the semiconductor chip 40 to be mounted is approximately 85 μm or less is performed as follows.
[Formation of semiconductor elements]
First, as shown in FIG. 2, various semiconductor elements 12 are formed on the main surface of the wafer 11 by a known process (STEP 1).

[ウエハのハーフカット]
次に、図3に示す如く、主表面に各種の半導体素子12が形成されたウエハ11を、半導体素子形成面側を上にしてダイシング装置のチャックテーブル23にバキュームその他の方法で吸着して固定する。そして、ダイシング用ブレード24を任意の回転数で回転させ、切削水を掛けながら、ダイシングラインまたはチップ分割ラインに沿って、所定の深さまで溝22を切り込む。この溝22の深さは、完成時のチップの厚さよりも少なくとも5μm深くする(STEP2)。その後、ウエハ11の洗浄と乾燥処理を行う。
[Half cut of wafer]
Next, as shown in FIG. 3, the wafer 11 on which the various semiconductor elements 12 are formed on the main surface is adsorbed and fixed to the chuck table 23 of the dicing apparatus with the semiconductor element forming surface side up by vacuum or other methods. To do. Then, the dicing blade 24 is rotated at an arbitrary number of revolutions, and the groove 22 is cut to a predetermined depth along the dicing line or the chip dividing line while applying cutting water. The depth of the groove 22 is at least 5 μm deeper than the thickness of the chip at the time of completion (STEP 2). Thereafter, the wafer 11 is cleaned and dried.

[表面保護テープ貼付]
その後、ウエハ11の素子形成面側を保護する目的と、次工程のウエハ裏面研削により分割された半導体チップが互いに離れてしまうのを防止する目的で、図4に示す如く、ローラー26等を用いてウエハ11の素子形成面にUV保護テープ(表面保護テープ)14を貼り付ける(STEP3)。なお、UV保護テープ14は、後の工程にて糊材の接着力を低下させる目的で行うUV照射を行わないのであれば、UV保護機能のないテープであってもよい。また、UV保護テープ14は、ローラー26に限らず他の方法にて貼り付けられてもよい。
[Attaching surface protection tape]
Thereafter, a roller 26 or the like is used as shown in FIG. 4 for the purpose of protecting the element forming surface side of the wafer 11 and preventing the semiconductor chips divided by the wafer back surface grinding in the next step from separating from each other. Then, a UV protection tape (surface protection tape) 14 is attached to the element forming surface of the wafer 11 (STEP 3). Note that the UV protection tape 14 may be a tape having no UV protection function as long as UV irradiation performed for the purpose of reducing the adhesive strength of the paste material in a later step is not performed. Further, the UV protection tape 14 is not limited to the roller 26 and may be attached by other methods.

[ウエハ裏面研削]
次いで、図示しない研削装置によりウエハ11の裏面研削及び研磨を行ってウエハ11の切断分離を行い、個々の半導体チップ40に分割する(STEP4)。図5に示す如く、砥石28aのついたホイール28を4000〜6000rpmの高速で回転させながら、回転テーブル29上のウエハ11の裏面を研削してウエハ11の厚さを薄くする。上記砥石は、例えば人工ダイヤモンドをフェノール樹脂で固めて成形したものである。回転テーブル29とホイール28を回転させながら砥石28aを降下させ、ウエハ11の裏面を溝22に達するまで削ると、ウエハ11は個々の半導体チップ40に分割される。
[Wafer back grinding]
Next, backside grinding and polishing of the wafer 11 is performed by a grinding apparatus (not shown), the wafer 11 is cut and separated, and divided into individual semiconductor chips 40 (STEP 4). As shown in FIG. 5, while the wheel 28 with the grindstone 28 a is rotated at a high speed of 4000 to 6000 rpm, the back surface of the wafer 11 on the rotary table 29 is ground to reduce the thickness of the wafer 11. The grindstone is formed, for example, by hardening artificial diamond with a phenol resin. When the grindstone 28 a is lowered while rotating the rotary table 29 and the wheel 28 and the back surface of the wafer 11 is scraped until reaching the groove 22, the wafer 11 is divided into individual semiconductor chips 40.

この裏面研削工程は、2軸で行うことが多い。1軸で予め320〜600番で荒削りした後、2軸で1500〜2000番で鏡面に仕上げ削り(研磨)を行い、ウエハ11裏面研削の条痕を除去する。ウエハ11が個々の半導体チップ40に分割された後も研削及び研磨を続け、少なくとも溝22に達した後5μm以上研削及び研磨する。これによって、ダイシングによって形成された面と研削及び研磨によって形成された面とが交わる部分にチッピングが発生していても、この領域を除去することができる(ストレスリリーフ)。研削及び研磨する量を増加させれば、より大きなチッピングを除去できるが、この研削及び研磨量はウエハ11の厚さや完成時の半導体チップ40の厚さ等必要に応じて設定すれば良い。これによって、半導体チップ40の完成時の厚さは、例えば20μm程度まで薄厚化が可能となる。   This back grinding process is often performed with two axes. After roughing with No. 320-600 in advance with one axis, finish grinding (polishing) is performed on the mirror surface with No. 1500-2000 with two axes, and the streak of the back surface grinding of the wafer 11 is removed. After the wafer 11 is divided into individual semiconductor chips 40, grinding and polishing are continued, and at least the grooves 22 are ground and polished for 5 μm or more. As a result, even if chipping occurs at a portion where the surface formed by dicing and the surface formed by grinding and polishing intersect, this region can be removed (stress relief). If the amount to be ground and polished is increased, larger chipping can be removed. However, the amount of grinding and polishing may be set as required, such as the thickness of the wafer 11 and the thickness of the semiconductor chip 40 when completed. As a result, the thickness of the completed semiconductor chip 40 can be reduced to about 20 μm, for example.

[固定用シートへ搭載]
その後、個々の半導体チップ40に分割されたウエハ11を、半導体チップ40が互いに離れないようにする目的と、搬送を容易にする目的で、素子形成面側を上に向けて固定用シート(ダイシングテープ)上に載置する(STEP5)。図6に示すような環状のフラットリング30の枠内に固定用シート(ダイシングテープ)31を張り、固定用シート31の弛みや皺などの発生を防止した状態で、図6及び図7に示す如く、フラットリング30の開口内の固定用シート31上にウエハ11を載置する。ここで固定用シート31上には、DAF(Die Attach Film)と呼ばれる接着剤層16が形成されている。ウエハ11は、この接着剤層16上に固着される。
[Installed on fixing sheet]
Thereafter, for the purpose of preventing the semiconductor chips 40 from separating from each other and for facilitating the conveyance of the wafer 11 divided into the individual semiconductor chips 40, the fixing sheet (dicing) is faced upward. (STEP 5). 6 and 7 in a state where a fixing sheet (dicing tape) 31 is stretched in the frame of the annular flat ring 30 as shown in FIG. 6 to prevent the fixing sheet 31 from being loosened or wrinkled. As described above, the wafer 11 is placed on the fixing sheet 31 in the opening of the flat ring 30. Here, an adhesive layer 16 called DAF (Die Attach Film) is formed on the fixing sheet 31. The wafer 11 is fixed on the adhesive layer 16.

次に、UV照射を行ってUV保護テープ14の糊材の接着力を低下させたのち、図8に示す如く、UV保護テープ14をウエハ11から剥離する。   Next, after UV irradiation is performed to reduce the adhesive strength of the paste material of the UV protection tape 14, the UV protection tape 14 is peeled from the wafer 11 as shown in FIG. 8.

[レーザによる接着剤層を切断]
その後、図9に示す如く、ウエハ11を固着した固定用シート31及びフラットリング30を、図示しないチャックテーブルに固定し、上記ウエハハーフカット工程にて形成した溝22に沿ってレーザノズル33を移動させ、接着剤層16を個々の半導体チップ40に対応させて切断する(STEP6)。この接着剤層16の切断工程が完了した時点では、個々の半導体チップ40に対応して接着剤層16に微細な切り込みが入った状態となる。
[Cutting the adhesive layer by laser]
Thereafter, as shown in FIG. 9, the fixing sheet 31 and the flat ring 30 to which the wafer 11 is fixed are fixed to a chuck table (not shown), and the laser nozzle 33 is moved along the groove 22 formed in the wafer half-cut process. Then, the adhesive layer 16 is cut corresponding to each semiconductor chip 40 (STEP 6). When the cutting process of the adhesive layer 16 is completed, the adhesive layer 16 is in a state of being finely cut corresponding to each semiconductor chip 40.

[エキスパンド・接着剤層の割段]
このようにしてレーザにて接着剤層16が切断されたウエハ11は、UV照射を行って接着剤層16を硬化させて接着力を低下させたのち、後で説明するダイボンダ装置のウエハリングホルダ55にセットされる。そして、図10に示す如く、固定用シート31を周囲に向けて広げるようにエキスパンドすることにより、隣接する接着剤層16間を広げるように割段して、半導体チップ40(接着剤層16)を固定用シート31から剥がれやすくした状態にする(STEP7)。この時点で、切断分離された半導体チップ40が固定用シート31上に整列して担持されている状態にある。
[Expansion and adhesive layer split]
The wafer 11 from which the adhesive layer 16 has been cut by the laser in this way is irradiated with UV to cure the adhesive layer 16 to reduce the adhesive force, and then a wafer ring holder of a die bonder device described later. Set to 55. Then, as shown in FIG. 10, the fixing sheet 31 is expanded so as to spread toward the periphery, so that the space between adjacent adhesive layers 16 is expanded so that the semiconductor chip 40 (adhesive layer 16). Is made to be easily peeled off from the fixing sheet 31 (STEP 7). At this time, the cut and separated semiconductor chip 40 is in a state of being held in alignment on the fixing sheet 31.

[ピックアップ・ダイボンディング]
その後、ダイボンダ装置にて半導体チップ40のピックアップ及びダイボンディングを行う(STEP8)。切断分離され整列して担持されている半導体チップ40の固定用シート31からの引き剥がしは、次のようにして行われる。すなわち、図11に示す如く、目標の半導体チップ40を、ウエハリングホルダ55の所定の場所に設けられた突き上げ部34上に移動させ、固定用シート31側をバッキューム吸着して保持する一方、多段突き上げジグ35で半導体チップ40の裏面を突き上げて、固定用シート31の伸張性を利用して、固定用シート31から半導体チップ40を引き離すとともに、ピックアップコレット71で半導体チップ40を吸着把持して、図示しない位置修正ステージに移載する。そして、半導体チップ40の位置・方向や必要に応じて表裏を修正した後、図12に示す如く、ダイボンディングヘッド53により基板41上に移送する。
[Pickup / Die Bonding]
Thereafter, the semiconductor chip 40 is picked up and die-bonded by a die bonder device (STEP 8). The semiconductor chip 40 that is cut, separated, aligned, and supported is peeled off from the fixing sheet 31 as follows. That is, as shown in FIG. 11, the target semiconductor chip 40 is moved onto the push-up portion 34 provided at a predetermined position of the wafer ring holder 55, and the fixing sheet 31 side is vacuum-sucked and held. The semiconductor chip 40 is pushed up by the push-up jig 35, and the semiconductor chip 40 is pulled away from the fixing sheet 31 using the stretchability of the fixing sheet 31, and the semiconductor chip 40 is sucked and held by the pickup collet 71. Transfer to a position correction stage (not shown). Then, after correcting the position and direction of the semiconductor chip 40 and the front and back as required, the semiconductor chip 40 is transferred onto the substrate 41 by the die bonding head 53 as shown in FIG.

[ワイヤボンディング・モールド等]
次いで、図13に示す如く、各半導体チップ40の電極端子と基板41のインナリードとの間をボンディングワイヤ42で電気的に接続し、半導体チップ40とボンディングワイヤ42を封止樹脂43によって封止し、基板41の裏面にはんだボール44を形成する等を行って、半導体装置50が完成する(STEP9)。
[Wire bonding, mold, etc.]
Next, as shown in FIG. 13, the electrode terminals of each semiconductor chip 40 and the inner leads of the substrate 41 are electrically connected by bonding wires 42, and the semiconductor chips 40 and the bonding wires 42 are sealed with a sealing resin 43. Then, a solder ball 44 is formed on the back surface of the substrate 41, and the semiconductor device 50 is completed (STEP 9).

[ピックアップ・ダイボンディングの工程の詳細]
次に、上記ピックアップ・ダイボンディングの工程をさらに詳細に説明する。ピックアップ・ダイボンディングの工程は、図14に示すように、目標とする半導体チップ40の反りを矯正する工程(STEP8−1)と、反りが矯正された状態の半導体チップ40の位置・方向及び良/不良マークを確認する工程(STEP8−2)と、位置・方向及び良/不良マークの確認が終了した半導体チップ40をピックアップする工程(STEP8−3)と、ピックアップした半導体チップ40を基板41にダイボンディングする工程(STEP8−4)とを含んでいる。そして、半導体チップ40を1枚引き剥がすたびに、上記STEP8−1〜STEP8−4の工程を繰り返す。
[Details of pickup / die bonding process]
Next, the pickup / die bonding process will be described in more detail. As shown in FIG. 14, the pick-up and die-bonding steps include a step of correcting the warp of the target semiconductor chip 40 (STEP 8-1), the position / direction of the semiconductor chip 40 with the warp corrected, and the good / Step of confirming defect mark (STEP 8-2), Step of picking up semiconductor chip 40 after confirmation of position / direction and good / bad mark (STEP 8-3), and picked-up semiconductor chip 40 on substrate 41 And a step of die bonding (STEP 8-4). Then, every time one semiconductor chip 40 is peeled off, the above steps 8-1 to STEP8-4 are repeated.

[ダイボンダ装置]
図15は、これらの工程にて用いられる本実施の形態のダイボンダ装置(半導体製造装置)の斜視図である。図16は、ウエハ検出器の模式側面図である。図17は、透明矯正板の斜視図である。図18は、透明矯正板、ウエハ検出器及びピックアップコレットの動作を示す模式図である。図15に示すように、ダイボンダ装置100は、レーザにて接着剤層16が切断分離されたウエハ11が供給されるウエハ供給部51と、供給されたウエハ11がウエハ供給部51を介して装着されるウエハリングホルダ55と、半導体チップ40を実装する基板41を搬送するフィーダー52と、半導体チップ40を基板41に圧着するダイボンディングヘッド53と、半導体チップ40の位置・方向を修正する位置修正ステージ56と、半導体チップ40を吸着して把持するピックアップコレット71及びこのピックアップコレット71を移動させるピックアップヘッド70と、ウエハ検出器(ウエハ認識カメラ)60とを備えている。また、マン・マシンインターフェースとしてモニタ81、カラータッチパネル82、ジョイスティック83が装備されている。そして、本実施の形態のダイボンダ装置100においては、半導体チップ40の反りを矯正する透明矯正板76と、この透明矯正板76を移動させる透明矯正板移動用ヘッド75が設けられている。ここで、ピックアップヘッド70は、ピックアップコレット71を移動させる移動手段を構成している。また、透明矯正板移動用ヘッド75は、透明矯正板76を移動させる移動手段を構成している。
[Die bonder equipment]
FIG. 15 is a perspective view of the die bonder apparatus (semiconductor manufacturing apparatus) of the present embodiment used in these steps. FIG. 16 is a schematic side view of the wafer detector. FIG. 17 is a perspective view of a transparent correction plate. FIG. 18 is a schematic diagram showing the operations of the transparent straightening plate, the wafer detector, and the pickup collet. As shown in FIG. 15, the die bonder apparatus 100 includes a wafer supply unit 51 to which the wafer 11 from which the adhesive layer 16 has been cut and separated by a laser is supplied, and the supplied wafer 11 is mounted via the wafer supply unit 51. Wafer ring holder 55, feeder 52 for transporting the substrate 41 on which the semiconductor chip 40 is mounted, die bonding head 53 for crimping the semiconductor chip 40 to the substrate 41, and position correction for correcting the position and direction of the semiconductor chip 40 A stage 56, a pickup collet 71 that sucks and holds the semiconductor chip 40, a pickup head 70 that moves the pickup collet 71, and a wafer detector (wafer recognition camera) 60 are provided. In addition, a monitor 81, a color touch panel 82, and a joystick 83 are provided as man-machine interfaces. In the die bonder device 100 of the present embodiment, a transparent correction plate 76 that corrects the warp of the semiconductor chip 40 and a transparent correction plate moving head 75 that moves the transparent correction plate 76 are provided. Here, the pickup head 70 constitutes a moving means for moving the pickup collet 71. The transparent correction plate moving head 75 constitutes a moving means for moving the transparent correction plate 76.

ウエハリングホルダ55は、固定用シート31の周縁をクランプして周囲に広げるエキスパンド構造を有している。また、ウエハリングホルダ55は、目標となる半導体チップ40を所定の位置へ移動させるために、X軸、Y軸の移動及びθ軸(Z軸回り)の回転ができるようにされている。ピックアップヘッド70は、ピックアップコレット71をY軸及びZ軸に沿って移動可能に支持する。ピックアップコレット71には、半導体チップ40を把持する吸着構造が設けられている。透明矯正板移動用ヘッド75は、ピックアップヘッド70から独立した状態で、透明矯正板76をY軸及びZ軸に沿って移動可能に支持する。ダイボンディングヘッド53においては、半導体チップ吸着把持部53aが、X軸、Y軸、Z軸の移動及びθ軸(Z軸回り)の回転をするようにされており、位置修正ステージ56からピックアップした半導体チップ40の位置・向きを補正して基板41上に押圧(ダイボンディング)できるようにされている。なお、位置修正ステージ56を経由せず、ウエハリングホルダ55から基板41上にピックアップコレット71により直接移送する場合もある。   The wafer ring holder 55 has an expanded structure that clamps the periphery of the fixing sheet 31 and spreads it around. Further, the wafer ring holder 55 is configured to be able to move the X axis and the Y axis and rotate the θ axis (around the Z axis) in order to move the target semiconductor chip 40 to a predetermined position. The pickup head 70 supports the pickup collet 71 so as to be movable along the Y axis and the Z axis. The pickup collet 71 is provided with a suction structure for holding the semiconductor chip 40. The transparent correction plate moving head 75 supports the transparent correction plate 76 so as to be movable along the Y-axis and the Z-axis while being independent of the pickup head 70. In the die bonding head 53, the semiconductor chip suction gripping portion 53a is adapted to move on the X axis, the Y axis, and the Z axis and rotate on the θ axis (around the Z axis), and is picked up from the position correction stage 56. The position / orientation of the semiconductor chip 40 is corrected so that it can be pressed (die bonding) onto the substrate 41. In some cases, the pickup collet 71 directly transfers the wafer ring holder 55 onto the substrate 41 without passing through the position correction stage 56.

[ウエハ検出器]
ウエハ検出器(ウエハ認識カメラ)60は、ウエハリングホルダ55上のウエハ11(半導体チップ40)が撮像可能な位置に取り付けられ、図16に示すように、筒状の鏡筒61と、鏡筒61の一方の開口端部に設けられたカメラ62と、鏡筒61の他方の開口端外周部に設けられたリング照明63とを有している。リング照明63から照射された光が、半導体チップ40の表面にてはね返り、鏡筒61を介してカメラ62に入射されて、半導体チップ40の画像が撮像される。なお、図16は、本実施の形態の透明矯正板76を用いずに半導体チップ40を撮像する様子を示している。半導体チップ40の薄厚化に伴い、半導体チップ40の内部応力及び裏面の接着剤層16の影響により半導体チップ40が沿ってしまい光が正常に戻らないので正確に撮像することが困難となる場合がある。
[Wafer detector]
A wafer detector (wafer recognition camera) 60 is mounted at a position where the wafer 11 (semiconductor chip 40) on the wafer ring holder 55 can be imaged, and as shown in FIG. A camera 62 provided at one opening end of 61 and a ring illumination 63 provided at the outer periphery of the other opening end of the lens barrel 61 are included. The light emitted from the ring illumination 63 rebounds on the surface of the semiconductor chip 40 and is incident on the camera 62 through the lens barrel 61 to capture an image of the semiconductor chip 40. FIG. 16 shows a state where the semiconductor chip 40 is imaged without using the transparent correction plate 76 of the present embodiment. As the thickness of the semiconductor chip 40 is reduced, the semiconductor chip 40 follows along with the internal stress of the semiconductor chip 40 and the influence of the adhesive layer 16 on the back surface, and the light does not return to normal. is there.

[透明矯正板]
透明矯正板76は、図17に示す如く、矩形平板状を成し、アクリル等の透明樹脂で、半導体チップ40のパターンが認識できる透過率の材料で作製されている。そして、XY方向大きさは、対象となる半導体チップ40のXY方向大きさと同じかそれ以上の大きさになっている。透明矯正板76は、半導体チップ40のパターンが認識できる透過率の材料であればよく、例えばガラスなどにより作製されてもよい。なお、透明矯正板76の大きさを半導体チップ40のダイシングラインまたはチップ分割ラインを超える大きさとしてもよい。このような大きさとすることにより、隣接する半導体チップの変形による固定用シート31の変形も矯正することができる。
[Transparent straightening plate]
As shown in FIG. 17, the transparent correction plate 76 has a rectangular flat plate shape, and is made of a transparent resin such as acrylic and made of a material having a transmissivity that can recognize the pattern of the semiconductor chip 40. The size in the XY direction is equal to or larger than the size in the XY direction of the target semiconductor chip 40. The transparent correction plate 76 may be any material having a transmittance that allows the pattern of the semiconductor chip 40 to be recognized, and may be made of glass, for example. The size of the transparent correction plate 76 may be larger than the dicing line or chip dividing line of the semiconductor chip 40. By setting it as such a magnitude | size, the deformation | transformation of the sheet | seat 31 for fixation by deformation | transformation of an adjacent semiconductor chip can also be corrected.

次に、上記目標とする半導体チップ40の反りを矯正する工程(STEP8−1)と、反りが矯正された状態の半導体チップ40の位置及び良/不良マークを確認する工程(STEP8−2)と、位置及び良/不良マークの確認が終了した半導体チップ40をピックアップする工程(STEP8−3)の動作を図18に沿って説明する。まず、上記レーザによる接着剤層16を切断の工程を終了したウエハ11が、ウエハ供給部51からウエハリングホルダ55にセットされる。そして、このウエハリングホルダ55上にて、固定用シート31を周囲に向けて広げるエキスパンドが行われる。   Next, the step of correcting the warpage of the target semiconductor chip 40 (STEP 8-1), the step of confirming the position of the semiconductor chip 40 in which the warp has been corrected and the good / bad mark (STEP 8-2), The operation of the step (STEP 8-3) of picking up the semiconductor chip 40 whose position and good / bad mark have been confirmed will be described with reference to FIG. First, the wafer 11 that has finished the step of cutting the adhesive layer 16 by the laser is set from the wafer supply unit 51 to the wafer ring holder 55. Then, an expansion is performed on the wafer ring holder 55 to spread the fixing sheet 31 toward the periphery.

その後、ウエハリングホルダ55をX軸Y軸にて移動させて、これからピックアップしようとする半導体チップ40がウエハ検出器60の撮像位置(本実施の形態においてはウエハ検出器60の鉛直下)に来るようにする。次いで、透明矯正板移動用ヘッド75は、ピックアップしようとする半導体チップ40の上方に透明矯正板76を移動させ(図18の(a))、その後、所定の高さまで透明矯正板76を下げる。これにより、透明矯正板76は、半導体チップ40の素子形成面を所定の圧力で押圧する。目標の半導体チップ40は、透明矯正板76の下面にて押圧されて押し広げられるように延びて平坦化する。   Thereafter, the wafer ring holder 55 is moved along the X axis and the Y axis, and the semiconductor chip 40 to be picked up comes to the imaging position of the wafer detector 60 (in this embodiment, vertically below the wafer detector 60). Like that. Next, the transparent correction plate moving head 75 moves the transparent correction plate 76 above the semiconductor chip 40 to be picked up (FIG. 18A), and then lowers the transparent correction plate 76 to a predetermined height. Thereby, the transparent correction plate 76 presses the element forming surface of the semiconductor chip 40 with a predetermined pressure. The target semiconductor chip 40 is flattened so as to be pressed and spread on the lower surface of the transparent correction plate 76.

この状態でウエハ検出器60が半導体チップ40の表面を撮像し、この撮像により得た画像データを二値化もしくは多値化して半導体チップ40の位置検出、及び良品/不良品を判別するためのマーク検出等を行う。ウエハ検出器60から照射された光は、半導体チップ40の表面で均一に反射する。なお、半導体チップ40の良品/不良品の判別は、上位工程にてウエハ11内に記憶させた良品/不良品の存在位置のデータを使用して行ってもよい。そして、不良品と判断した場合には、該当する半導体チップ40を破棄する等の動作をする。その後、透明矯正板移動用ヘッド75は、透明矯正板76は、ピックアップコレット71の稼動範囲外に退避する(図18の(b))。   In this state, the wafer detector 60 images the surface of the semiconductor chip 40, and the image data obtained by the imaging is binarized or multi-valued to detect the position of the semiconductor chip 40 and discriminate between good and defective products. Mark detection is performed. The light emitted from the wafer detector 60 is reflected uniformly on the surface of the semiconductor chip 40. The determination of the non-defective product / defective product of the semiconductor chip 40 may be performed by using the data on the location of the non-defective product / defective product stored in the wafer 11 in the upper process. When it is determined that the product is defective, the corresponding semiconductor chip 40 is discarded. Thereafter, the transparent correction plate moving head 75 retracts the transparent correction plate 76 out of the operating range of the pickup collet 71 ((b) of FIG. 18).

続く工程は、周知の半導体装置の製造方法と同様に、多段突き上げジグ35にて裏面より突き上げることで(図11)、固定用シート31の伸張性を利用して固定用シート31から半導体チップ40を引き剥がすとともに、半導体チップ40をピックアップコレット71で吸着把持して、位置修正ステージ56に移載する。そして、半導体チップ40の位置や方向、必要に応じて表裏を修正した後、半導体チップ40をダイボンディングヘッド53によりリードフレーム上に移送し、基板41或いは先に実装されている半導体チップ40に重ねて圧着する(図18の(c))。   In the subsequent process, as in the known method for manufacturing a semiconductor device, the multi-stage push-up jig 35 pushes up from the back surface (FIG. 11), and the extensibility of the fixing sheet 31 is utilized to make the semiconductor chip 40 from the fixing sheet 31. The semiconductor chip 40 is sucked and held by the pickup collet 71 and transferred to the position correction stage 56. Then, after correcting the position and direction of the semiconductor chip 40 and the front and back as necessary, the semiconductor chip 40 is transferred onto the lead frame by the die bonding head 53 and overlapped with the substrate 41 or the semiconductor chip 40 previously mounted. And crimping (FIG. 18 (c)).

なお、ウエハ検出器60は、図16に示すタイプのものに限らず、図19に示すようなタイプのものであってもよい。図19に示すウエハ検出器60Bにおいては、装置の側部に設けられた面発光照明66から照射された平行光が、ハーフミラー67にて半導体チップ40方向に屈折される。リング照明63からの光の照射も同時に行われる。両照明の光が組合わされ、その平行光が半導体チップ表面にてはね返り、鏡筒61を介してカメラ62に入射されて、半導体チップ40の画像が撮像される。このようなタイプのウエハ検出器60Bを用いると、より解像度の高い画像が得られ、信頼性が向上する。   The wafer detector 60 is not limited to the type shown in FIG. 16, but may be of the type shown in FIG. In the wafer detector 60 </ b> B shown in FIG. 19, the parallel light emitted from the surface emitting illumination 66 provided on the side of the apparatus is refracted by the half mirror 67 toward the semiconductor chip 40. Irradiation of light from the ring illumination 63 is also performed at the same time. The lights of both illuminations are combined, the parallel light rebounds on the surface of the semiconductor chip, is incident on the camera 62 via the lens barrel 61, and an image of the semiconductor chip 40 is taken. When such a type of wafer detector 60B is used, an image with higher resolution can be obtained and the reliability can be improved.

上記のように、本実施の形態の半導体装置の製造方法は、配線基板或いはリードフレームなどの基板41上に複数の半導体チップ40を積層する半導体装置50の一連の製造工程のなかの半導体チップ40のピックアップ工程において、ダイシングテープ等の固定用シートからの半導体チップ40のピックアップに先立ち、半導体チップ40の薄厚化による応力によって反ってしまった半導体チップ40を、透明矯正板によって平坦化させ、この状態で半導体チップ40の撮像を行い、半導体チップの位置・方向および良/不良マークの確認をする。チップ厚が薄く変形量が大きい半導体チップであっても、ウエハ検出器60から照射された光は、半導体チップ40の表面で均一に反射する。これにより、正確に画像取得を行うことができ、半導体チップの位置認識を正確に行うことができる。   As described above, the semiconductor device manufacturing method of the present embodiment is a semiconductor chip 40 in a series of manufacturing steps of a semiconductor device 50 in which a plurality of semiconductor chips 40 are stacked on a substrate 41 such as a wiring board or a lead frame. In this pickup process, prior to picking up the semiconductor chip 40 from a fixing sheet such as a dicing tape, the semiconductor chip 40 warped by the stress due to the thinning of the semiconductor chip 40 is flattened by a transparent straightening plate, and this state Then, the semiconductor chip 40 is imaged and the position / direction of the semiconductor chip and the good / bad mark are confirmed. Even for a semiconductor chip having a small chip thickness and a large amount of deformation, the light emitted from the wafer detector 60 is uniformly reflected on the surface of the semiconductor chip 40. Thereby, image acquisition can be performed accurately and the position of the semiconductor chip can be accurately recognized.

また、半導体チップ40のピックアップ工程において、ダイシングテープ等の固定用シート31から半導体チップ40を引き剥がす前に、反ってしまった半導体チップ40を透明矯正板76によって平坦化させるので、半導体チップ40の応力が開放されるとともに、半導体チップ40が固定用シート31上で形状変化することにより、固定用シート31との固着が解け、より剥がしやすい状態となり、半導体チップ剥離時のクラックの発生が減少する。   Further, in the pick-up process of the semiconductor chip 40, the warped semiconductor chip 40 is flattened by the transparent correction plate 76 before the semiconductor chip 40 is peeled off from the fixing sheet 31 such as a dicing tape. As the stress is released and the shape of the semiconductor chip 40 changes on the fixing sheet 31, the fixing with the fixing sheet 31 is released, and the semiconductor chip 40 is more easily peeled off, and the generation of cracks at the time of peeling the semiconductor chip is reduced. .

実施の形態2.
図20は、実施の形態2のダイボンダ(半導体製造装置)の斜視図である。図21は、本実施の形態のピックアップコレットの下面図である。図22は、図21のピックアップコレットの側断面図である。本実施の形態のダイボンダ装置101においては、ピックアップコレット77は、上記実施の形態1の透明矯正板の機能も兼ね備えている。すなわち、本実施の形態においては、ピックアップコレットと透明矯正板とが兼用となっている。そのため、図20に示すように、本実施の形態のダイボンダ装置101は、図15に示す実施の形態1のダイボンダ装置100と比較して、透明矯正板76と透明矯正板移動用ヘッド(移動手段)75が省略されている。
Embodiment 2. FIG.
FIG. 20 is a perspective view of the die bonder (semiconductor manufacturing apparatus) of the second embodiment. FIG. 21 is a bottom view of the pickup collet of the present embodiment. FIG. 22 is a side sectional view of the pickup collet of FIG. In the die bonder device 101 of the present embodiment, the pickup collet 77 also has the function of the transparent straightening plate of the first embodiment. That is, in the present embodiment, the pickup collet and the transparent correction plate are combined. Therefore, as shown in FIG. 20, the die bonder device 101 of the present embodiment is more transparent than the die bonder device 100 of the first embodiment shown in FIG. ) 75 is omitted.

図21及び図22において、ピックアップコレット77は、アクリル等の透明樹脂で、半導体チップ40のパターンが認識できる透過率の材料で作製された矩形平板状のコレット本体77aを有している。コレット本体77aのXY方向大きさは、対象となる半導体チップ40のXY方向大きさと同じかそれ以上の大きさになっている。また、コレット本体77aのZ方向厚さaは、抗折強度が3N(ニュートン)以上となるような厚さになっている。   21 and 22, the pickup collet 77 has a rectangular flat plate-like collet body 77 a made of a transparent resin such as acrylic and made of a material having a transmittance that allows the pattern of the semiconductor chip 40 to be recognized. The size of the collet body 77a in the XY direction is equal to or larger than the size of the target semiconductor chip 40 in the XY direction. The Z-direction thickness a of the collet body 77a is such that the bending strength is 3N (Newton) or more.

コレット本体77aの下面には、概略中央部に吸着構造として半導体チップ40を吸着把持するための複数の吸引口77bが形成されている。吸引口77bは、中央に1つと90度ずつ等間隔に離れた位置に4つが形成されている。吸引口77bに連通する吸引通路77cは、中央部から各吸引口77bに向かって十字型に延びるが、吸引口77b及び吸引通路77cは、ウエハ検出器60が行う半導体チップ40の位置及び良/不良マークの確認動作に、支障がない位置に形成されている。つまり、ウエハ検出器60Bは、半導体チップ40の位置(向きを含む)を認識する際、例えば半導体チップ40の周囲の輪郭形状を検出して行い、中央部の画像は使わない。また、良/不良マークは、多少位置がズレても吸引口77b及び吸引通路77cと重ならない位置に印されている。   On the lower surface of the collet main body 77a, a plurality of suction ports 77b for sucking and gripping the semiconductor chip 40 as a suction structure are formed in a substantially central portion. Four suction ports 77b are formed in the center and at positions spaced equally by 90 degrees. The suction passages 77c communicating with the suction ports 77b extend in a cross shape from the central portion toward the suction ports 77b. The suction ports 77b and the suction passages 77c are arranged in accordance with the position of the semiconductor chip 40 performed by the wafer detector 60 and It is formed at a position where there is no hindrance to the defect mark confirmation operation. That is, when recognizing the position (including the orientation) of the semiconductor chip 40, the wafer detector 60B detects, for example, the contour shape around the semiconductor chip 40, and does not use the image at the center. The good / bad mark is marked at a position where it does not overlap the suction port 77b and the suction passage 77c even if the position is slightly shifted.

吸着した半導体チップ40の有無を検知する図示しない圧力センサが良好に動作するために、吸引口77bの開口径bは、半導体チップ40を吸着している場合としていない場合とで5kpa以上の差となるような通路径となっている。   In order for a pressure sensor (not shown) that detects the presence or absence of the adsorbed semiconductor chip 40 to operate satisfactorily, the opening diameter b of the suction port 77b is a difference of 5 kpa or more when the semiconductor chip 40 is not adsorbed. The passage diameter is as follows.

図23は、本実施の形態のピックアップコレット及びウエハ検出器の動作を示す模式図である。透明矯正板兼用型のピックアップコレット77の動作は、以下のようになる。まず、ピックアップヘッド70は、これからピックアップしようとする半導体チップ40の上方にピックアップコレット77を移動させ(図23の(a))、その後、所定の高さまでピックアップコレット77を下げる。目標の半導体チップ40は、ピックアップコレット77にて押圧されて押し広げられるように延びて平坦化する。この状態でウエハ検出器60Bにより半導体チップ40の位置および良/不良マークの確認が行われる(図23の(b))。   FIG. 23 is a schematic diagram showing operations of the pickup collet and the wafer detector of the present embodiment. The operation of the pickup collet 77 that is also used as a transparent straightening plate is as follows. First, the pickup head 70 moves the pickup collet 77 above the semiconductor chip 40 to be picked up ((a) in FIG. 23), and then lowers the pickup collet 77 to a predetermined height. The target semiconductor chip 40 is flattened so as to be pushed and spread by the pickup collet 77. In this state, the position of the semiconductor chip 40 and the good / bad mark are confirmed by the wafer detector 60B (FIG. 23B).

その後、多段突き上げジグ35にて裏面より突き上げて(図11)、固定用シート31の伸張性を利用して固定用シート31から半導体チップ40を引き剥がすとともに、ピックアップコレット77の吸引口77bから空気を吸引して半導体チップ40を吸着把持して、位置修正ステージ56に移載する。そして、半導体チップ40の位置や必要に応じて表裏を修正した後、ダイボンディングヘッド53によりリードフレーム上に移送する(図23の(c))。   Thereafter, the multi-stage push-up jig 35 pushes up from the back surface (FIG. 11), peels off the semiconductor chip 40 from the fixing sheet 31 using the stretchability of the fixing sheet 31, and air from the suction port 77b of the pickup collet 77. The semiconductor chip 40 is sucked and held and transferred to the position correction stage 56. Then, after correcting the position of the semiconductor chip 40 and the front and back as required, it is transferred onto the lead frame by the die bonding head 53 ((c) of FIG. 23).

なお、本実施の形態のピックアップコレット77は、アクリル等の透明樹脂で作製されているが、半導体チップ40のパターンが認識できる透過率の材料であればよく、例えばガラスなどにより作製されてもよい。   The pickup collet 77 according to the present embodiment is made of a transparent resin such as acrylic, but may be made of a material having a transmissivity that can recognize the pattern of the semiconductor chip 40, and may be made of, for example, glass. .

このような構成の半導体装置の製造方法によれば、実施の形態1の半導体装置の製造方法と同様の効果が得られることに加えて、半導体製造装置の構成が簡素化されるので、装置のコストダウンを図ることができる。また、製造タクトが短縮されるので、製品である半導体装置のコストダウンを図ることができる。   According to the method of manufacturing a semiconductor device having such a configuration, in addition to obtaining the same effect as the method of manufacturing the semiconductor device of the first embodiment, the configuration of the semiconductor manufacturing device is simplified. Cost can be reduced. In addition, since the manufacturing tact time is shortened, the cost of the semiconductor device as a product can be reduced.

図24は、透明矯正板兼用型のピックアップコレットの他の例を示す下面図である。図25は、図24のピックアップコレットの側断面図である。図24及び図25に示すピックアップコレット78においては、コレット本体78aの下面に、半導体チップ40を吸着把持するための十字型の吸引溝78bが形成されている。吸引溝78bは、幅が0.5mm程度、深さが0.2mm程度である。吸引溝78bに連通する吸引通路78cは、中央部からコレット本体78aの一端に向けて延びている。吸引溝78b及び吸引通路78cは、図21及び図22に示すものと同様に、ウエハ検出器60が行う半導体チップ40の位置及び良/不良マークの確認動作に、支障がない位置に形成されている。   FIG. 24 is a bottom view showing another example of a pickup collet that is also used as a transparent straightening plate. FIG. 25 is a side sectional view of the pickup collet of FIG. In the pickup collet 78 shown in FIGS. 24 and 25, a cross-shaped suction groove 78b for sucking and gripping the semiconductor chip 40 is formed on the lower surface of the collet body 78a. The suction groove 78b has a width of about 0.5 mm and a depth of about 0.2 mm. A suction passage 78c communicating with the suction groove 78b extends from the central portion toward one end of the collet body 78a. The suction grooves 78b and the suction passages 78c are formed at positions that do not hinder the position of the semiconductor chip 40 and the good / bad mark confirmation operation performed by the wafer detector 60, as shown in FIGS. Yes.

また、吸着した半導体チップ40の有無を検知する図示しない圧力センサが良好に動作するために、吸引通路78cの通路径cは、半導体チップ40を吸着している場合としていない場合とで5kpa以上の差となるような通路径となっている。その他の構成は、図21及び図22に示すものと概略同様である。このような形状のピックアップコレット78においても、図21及び図22に示すものと概略同様の動作をさせることができる。   In order for a pressure sensor (not shown) that detects the presence or absence of the adsorbed semiconductor chip 40 to operate satisfactorily, the passage diameter c of the suction passage 78c is 5 kpa or more when the semiconductor chip 40 is not adsorbed. The passage diameter is different. Other configurations are substantially the same as those shown in FIGS. 21 and 22. The pick-up collet 78 having such a shape can be operated in substantially the same manner as that shown in FIGS.

11 ウエハ
12 半導体素子
14 保護テープ
16 接着剤層
22 溝
23 チャックテーブル
24 ダイシング用ブレード
26 ローラー
28 ホイール
28a 砥石
29 回転テーブル
30 フラットリング
31 固定用シート(ダイシングテープ)
33 レーザノズル
34 突き上げ部
35 多段突き上げジグ
40 半導体チップ(チップ)
41 基板
42 ボンディングワイヤ
43 封止樹脂
44 はんだボール
50 半導体装置
51 ウエハ供給部
52 フィーダー
53 ダイボンディングヘッド
55 ウエハリングホルダ
56 位置修正ステージ
60,60B ウエハ検出器
61 鏡筒
62 カメラ
63 リング照明
66 面発光照明
67 ハーフミラー
70 ピックアップヘッド
71,77,78 ピックアップコレット
75 透明矯正板移動用ヘッド
76 透明矯正板
77a コレット本体
77b 吸引口
77c,78c 吸引通路
78a コレット本体
78b 吸引溝
81 モニタ
82 カラータッチパネル
83 ジョイスティック
100,101 ダイボンダ装置
DESCRIPTION OF SYMBOLS 11 Wafer 12 Semiconductor element 14 Protection tape 16 Adhesive layer 22 Groove 23 Chuck table 24 Dicing blade 26 Roller 28 Wheel 28a Grinding wheel 29 Rotary table 30 Flat ring 31 Fixing sheet (dicing tape)
33 Laser nozzle 34 Push-up part 35 Multi-stage push-up jig 40 Semiconductor chip (chip)
DESCRIPTION OF SYMBOLS 41 Board | substrate 42 Bonding wire 43 Sealing resin 44 Solder ball 50 Semiconductor device 51 Wafer supply part 52 Feeder 53 Die bonding head 55 Wafer ring holder 56 Position correction stage 60, 60B Wafer detector 61 Lens barrel 62 Camera 63 Ring illumination 66 Surface light emission Illumination 67 Half mirror 70 Pickup head 71, 77, 78 Pickup collet 75 Transparent correction plate moving head 76 Transparent correction plate 77a Collet body 77b Suction port 77c, 78c Suction passage 78a Collet body 78b Suction groove 81 Monitor 82 Color touch panel 83 Joystick 100 101 Bonder device

Claims (6)

基板上に複数のチップを積層する半導体装置の製造方法において、
半導体素子が形成されたウエハのダイシングラインまたはチップ分割ラインに沿って、前記半導体素子の形成面側から完成時のチップの厚さよりも深い溝を形成し、
前記ウエハの半導体素子の形成面上に表面保護シートを貼り付け、
前記ウエハの裏面を前記完成時のチップの厚さまで研削して、ウエハを個々のチップに分離し、
表面に接着剤層が形成された固定用シートを前記分離されたチップの裏面に貼り付け、 前記表面保護シートを剥離し、
前記分離されたチップに対応して、前記接着剤層を切断し、
前記固定用シートをエキスパンドして、前記チップを剥がれやすい状態にし、
前記チップの半導体素子の形成面を透明矯正板で押圧してチップの反りを矯正し、
前記チップを撮像し得られた画像から前記チップの位置誤差を検出し、
前記チップを前記固定用シートからピックアップし、
ピックアップした前記チップを位置誤差を補正して基板上にダイボンディングする
ことを特徴とする半導体装置の製造方法。
In a manufacturing method of a semiconductor device in which a plurality of chips are stacked on a substrate,
Along the dicing line or chip dividing line of the wafer on which the semiconductor element is formed, a groove deeper than the thickness of the completed chip is formed from the semiconductor element forming surface side,
Affixing a surface protection sheet on the semiconductor element forming surface of the wafer,
Grinding the backside of the wafer to the thickness of the finished chip, separating the wafer into individual chips,
Affixing a fixing sheet having an adhesive layer formed on the surface to the back surface of the separated chip, peeling off the surface protection sheet,
Corresponding to the separated chip, cutting the adhesive layer,
Expand the fixing sheet to make the chip easy to peel off,
Correct the warp of the chip by pressing the semiconductor element forming surface of the chip with a transparent correction plate,
Detecting a position error of the chip from an image obtained by imaging the chip;
Pick up the chip from the fixing sheet,
A method of manufacturing a semiconductor device, wherein the picked-up chip is die-bonded on a substrate while correcting a position error.
前記チップを前記固定用シートからピックアップするコレットと前記透明矯正板とを同一の移動手段にて移動させる
ことを特徴とする請求項1に記載の半導体装置の製造方法。
The method for manufacturing a semiconductor device according to claim 1, wherein a collet that picks up the chip from the fixing sheet and the transparent correction plate are moved by the same moving means.
前記透明矯正板に、前記チップを吸着して保持可能な吸着構造を構成し
前記チップを前記透明矯正板で押圧して前記チップの反りを矯正した状態から、前記透明矯正板にて前記チップをピックアップする
ことを特徴とする請求項2に記載の半導体装置の製造方法。
An adsorption structure that can adsorb and hold the chip on the transparent straightening plate is formed, and the chip is pressed by the transparent straightening plate from a state in which the chip is pressed by the transparent straightening plate to correct the warp of the chip. The semiconductor device manufacturing method according to claim 2, wherein the semiconductor device is picked up.
前記吸着構造を前記透明矯正板の中央部に構成し、
前記チップの外周部の画像を画像処理することにより前記チップの位置誤差を検出する ことを特徴とする請求項3に記載の半導体装置の製造方法。
The adsorption structure is configured at the center of the transparent straightening plate,
The method for manufacturing a semiconductor device according to claim 3, wherein a position error of the chip is detected by performing image processing on an image of an outer peripheral portion of the chip.
前記チップを撮像をする工程の前に、チップの検査を行い、検査結果をチップにマーキングしておき、前記画像からこのマーキングの確認も行う
ことを特徴とする請求項1から4のいずれか1項に記載の半導体装置の製造方法。
The chip is inspected before the step of imaging the chip, the inspection result is marked on the chip, and the marking is also confirmed from the image. A method for manufacturing the semiconductor device according to the item.
個々に切断分離された半導体チップが固定用シート上に整列して担持されている状態から、前記半導体チップをピックアップし、このピックアップされた半導体チップを基板上にダイボンディングする半導体チップのピックアップ方法であって、
前記固定用シートをエキスパンドして、前記チップを剥がれやすい状態にし、
前記チップの半導体素子の形成面を透明矯正板で押圧してチップの反りを矯正し、
前記チップを撮像し得られた画像から前記チップの位置誤差を検出し、
前記チップを前記固定用シートからピックアップし、
ピックアップした前記チップを位置誤差を補正して基板上にダイボンディングする
ことを特徴とする半導体チップのピックアップ方法。
A semiconductor chip pick-up method in which the semiconductor chips are picked up from a state in which the individually cut and separated semiconductor chips are aligned and carried on a fixing sheet, and the picked-up semiconductor chips are die-bonded on a substrate. There,
Expand the fixing sheet to make the chip easy to peel off,
Correct the warp of the chip by pressing the semiconductor element forming surface of the chip with a transparent correction plate,
Detecting a position error of the chip from an image obtained by imaging the chip;
Pick up the chip from the fixing sheet,
A method of picking up a semiconductor chip, wherein the picked-up chip is die-bonded on a substrate while correcting a position error.
JP2009190397A 2009-08-19 2009-08-19 Method of manufacturing semiconductor device Pending JP2011044497A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009190397A JP2011044497A (en) 2009-08-19 2009-08-19 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009190397A JP2011044497A (en) 2009-08-19 2009-08-19 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JP2011044497A true JP2011044497A (en) 2011-03-03

Family

ID=43831722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009190397A Pending JP2011044497A (en) 2009-08-19 2009-08-19 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2011044497A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5158282B1 (en) * 2012-08-23 2013-03-06 富士ゼロックス株式会社 Conveying apparatus, semiconductor element conveying method, and semiconductor element manufacturing method
CN113410170A (en) * 2021-06-16 2021-09-17 武汉新芯集成电路制造有限公司 Method for improving chip picking efficiency, method for manufacturing three-dimensional integrated chip and chip
CN113539984A (en) * 2021-05-28 2021-10-22 日月光半导体制造股份有限公司 Semiconductor structure and forming method thereof
US20220310551A1 (en) * 2021-03-24 2022-09-29 Samsung Electronics Co., Ltd. Semiconductor manufacturing apparatus

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5158282B1 (en) * 2012-08-23 2013-03-06 富士ゼロックス株式会社 Conveying apparatus, semiconductor element conveying method, and semiconductor element manufacturing method
US20220310551A1 (en) * 2021-03-24 2022-09-29 Samsung Electronics Co., Ltd. Semiconductor manufacturing apparatus
US11658147B2 (en) * 2021-03-24 2023-05-23 Samsung Electronics Co., Ltd. Semiconductor manufacturing apparatus
CN113539984A (en) * 2021-05-28 2021-10-22 日月光半导体制造股份有限公司 Semiconductor structure and forming method thereof
CN113410170A (en) * 2021-06-16 2021-09-17 武汉新芯集成电路制造有限公司 Method for improving chip picking efficiency, method for manufacturing three-dimensional integrated chip and chip
CN113410170B (en) * 2021-06-16 2023-12-08 武汉新芯集成电路制造有限公司 Method for improving chip picking efficiency, manufacturing method of three-dimensional integrated chip and chip

Similar Documents

Publication Publication Date Title
KR100506109B1 (en) Separation mechanism for adhesive tape, separation apparatus for adhesive tape, separation method for adhesive tape, pickup apparatus for semiconductor chip, pickup method for semiconductor chip, manufacturing method for semiconductor apparatus, and manufacturing apparatus for semiconductor apparatus
JP4818187B2 (en) Manufacturing method of semiconductor device
CN108364880B (en) Semiconductor manufacturing apparatus and method for manufacturing semiconductor device
JP7102271B2 (en) Semiconductor manufacturing equipment and manufacturing method of semiconductor equipment
TW200539338A (en) A manufacturing method of a semiconductor device
KR102654506B1 (en) Wafer debonding method and wafer debonding apparatus
KR20160131905A (en) Wafer processing method
JP7029900B2 (en) Manufacturing method of die bonding equipment and semiconductor equipment
JP2011044497A (en) Method of manufacturing semiconductor device
TW202107657A (en) Die pickup method
JP6685592B2 (en) Wafer processing method
TWI677047B (en) Semiconductor manufacturing device and method of manufacturing semiconductor device
EP2284863B1 (en) Method and apparatus for inspecting a chip prior to bonding
JP2011181951A (en) Method of manufacturing semiconductor device
TWI803128B (en) Post bond inspection method and system of semiconductor devices for panel packaging
US11552043B2 (en) Post bond inspection of devices for panel packaging
JPH0697215A (en) Small article group attached adhesion sheet and method for picking up small article using thereof
JP2024024567A (en) Semiconductor manufacturing device and method for manufacturing semiconductor device
JP5175610B2 (en) Manufacturing method of semiconductor device
TWI823297B (en) Die bonding device and method for manufacturing semiconductor device
JP6073654B2 (en) Pickup method and pickup device
JP2006237504A (en) Semiconductor chip stripper and process for manufacturing semiconductor device employing it
JP2023002408A (en) Die bonding device, wafer, and semiconductor device manufacturing method
CN118645446A (en) Semiconductor manufacturing apparatus, inspection apparatus, and method for manufacturing semiconductor device
TW202209461A (en) Protective member forming apparatus