CN113539984A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113539984A
CN113539984A CN202110590730.1A CN202110590730A CN113539984A CN 113539984 A CN113539984 A CN 113539984A CN 202110590730 A CN202110590730 A CN 202110590730A CN 113539984 A CN113539984 A CN 113539984A
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China
Prior art keywords
semiconductor structure
trench
silicide
electronic component
equal
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Pending
Application number
CN202110590730.1A
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Chinese (zh)
Inventor
黄文宏
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN202110590730.1A priority Critical patent/CN113539984A/en
Publication of CN113539984A publication Critical patent/CN113539984A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings

Abstract

An embodiment of the present invention provides a semiconductor structure, including: an electronic component having a first surface and a second surface which are oppositely arranged; a circuit layer disposed on the first surface; a groove disposed on the second face; the trenches have at least two different directions of extension. In view of the problems in the related art, the present invention provides a semiconductor structure and a method for forming the same, so as to improve the yield of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the invention relate to semiconductor structures and methods of forming the same.
Background
As the packaging technology has evolved, various packaging structures have also been developed, the overall package size has become smaller and smaller, and the functions have become more and more, so that the functional package is generally required to control various components.
In the current Embedded component, for example, the Semiconductor Embedded in the package SUBstrate is Embedded in the Embedded component technology (SESUB), the warpage problem is mostly occurred, the top surface distance of the dielectric material is not uniform, so that the subsequent opening operation is very difficult, and the conventional method can only be improved by additional process or individual opening, so that the yield and the output per unit time (UPH) are both reduced.
Disclosure of Invention
In view of the problems in the related art, it is an object of the present invention to provide a semiconductor structure and a method for forming the same, so as to improve the yield of the semiconductor structure.
To achieve the above object, an embodiment of the present invention provides a semiconductor structure, including: an electronic component having a first surface and a second surface which are oppositely arranged; a circuit layer disposed on the first surface; a groove disposed on the second face; the trenches have at least two different directions of extension.
In some embodiments, further comprising: and the filling material is arranged in the groove.
In some embodiments, the specific gravity and heat dissipation coefficient of the filler material is greater than the specific gravity and heat dissipation coefficient of the material adjacent to the filler material.
In some embodiments, the depth of the trench is approximately equal to the thickness of the line layer.
In some embodiments, the area ratio of the trench is approximately equal to the area ratio of the line layer.
In some embodiments, the sidewalls of the groove are wavy.
In some embodiments, further comprising: a silicide encapsulating the electronic component, the trench extending from an outer surface of the silicide to a second side of the electronic component.
In some embodiments, further comprising: an insulating material encapsulates the silicide and the electronic elements located in the silicide.
In some embodiments, the width of the trench widens in a direction away from the electronic component from the second face.
In some embodiments, the plurality of grooves are uniform in depth.
An embodiment of the present application provides a semiconductor process, comprising: providing an electronic element covered by a silicide; forming a trench in the silicide that exposes a back side of the electronic component; disposing an electronic component on the adhesive layer; forming an insulating material encapsulating the electronic element and the silicide; a wiring layer is bonded to the adhesive layer and electrically connected to the electronic component.
In some embodiments, the electronic component is disposed on a carrier through the adhesive layer, and the wiring layer is bonded to the adhesive layer after the carrier is removed.
In some embodiments, after the electronic component is disposed on the carrier through the adhesive layer, the adhesive layer is cured.
In some embodiments, the silicide of the wafer is diced to form a pair of singulated said electronic elements prior to forming said trenches.
In some embodiments, after forming the trench, a planarization process is used to thin the silicide at the back of the crystal of the electronic component, the back of the crystal being disposed opposite the trench.
In some embodiments, the planarization process includes grinding.
In some embodiments, disposing the wiring layer includes performing an electroplating process to form the wiring layer.
In some embodiments, forming the trench includes performing a plasma etch process on the silicide.
In some embodiments, the sidewalls of the trench are undulated.
In some embodiments, the plurality of grooves intersect with each other.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1 to 10 are cross-sectional views illustrating a process of forming a semiconductor package structure of the present application.
Detailed Description
In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.
Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.
As used herein, the terms "substantially", "substantially" and "about" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" identical if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.
In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity, and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.
Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.
The semiconductor structure and the method of forming the same of the present application will be described in detail with reference to the accompanying drawings.
Referring to fig. 1, a wafer 14 includes electronic components 10 and a silicide 12, the electronic components 10 being disposed in the silicide 12, in an embodiment, the electronic components 10 are dies or chips.
Referring to fig. 2, the silicide 12 between two electronic components 10 is cut.
Referring to fig. 3, the electronic component 10 and the silicide 12 are inverted on the tape 30, and a planarization process is performed on the backside of the silicide 12. In some embodiments, the planarization process is a grinding process.
Referring to fig. 4A, a plurality of trenches 40 are formed in the silicide 12 on the electronic component 10 and a fill material 42 is disposed in the trenches 40. In some embodiments, the filler material 42 is a metal, such as copper. In some embodiments, the specific gravity and thermal dissipation coefficient of the fill material 42 is that of a silicide.
Fig. 4B shows the grooves 40 in a top view, wherein a plurality of the grooves 40 extend in different directions and intersect each other.
Fig. 4C shows an enlarged view of trench 40, wherein forming trench 40 includes performing a plasma etch process on the insulating material. The side walls of the trench 40 are undulated.
Referring to fig. 5, an adhesive layer 52 is disposed on the first carrier 50, and in some embodiments, the following material may be used for the adhesive layer 52: ABF (Ajinomoto Build-up Film), PBO (Polybenzoxazole), PI (polyimide), or Epoxy (Epoxy resin).
Referring to fig. 6, the filler material 42 is bonded to the adhesive layer 52.
Referring to fig. 7, an insulating material 70 is provided that encapsulates the electronic component 10 and the silicide 12.
Referring to fig. 8, insulating material 70 is perforated to expose the active side of electronic component 10. Wherein the opening can be performed by mechanical or exposure development.
Referring to fig. 9, a via 80 electrically connected to the active side of the electronic component 10 is formed in the opening of the insulating material 70.
Referring to fig. 10, the carrier 50 is removed. And a wiring layer 102 is formed to join the adhesive layer 52, the wiring layer 102 is electrically connected to the electronic component 10, and portions of the wiring layer 102 may be formed by plating. Thus, the semiconductor package structure 100 of the present application is formed.
The groove 40 is formed in the back of the electronic component 10 to release the warping stress of the electronic component, so that the distance of the through hole 80 above the electronic component is as consistent as possible, and subsequent uniform opening is facilitated. The trenches 40 may be filled directly with the insulating material 70 without the filling material 42, thereby improving the bonding force due to the increased contact area. In some embodiments, the filler material 42 in the trenches 40 is a high thermal dissipation material to improve the overall thermal dissipation function.
The function of stress release is improved through the grooves 40 in different directions, and the stress release effect is optimized by using the grid shape formed by the grooves 40. And is balanced by a design that is as symmetrical as possible (e.g., thickness, area ratio, or depth of the trench 40) centered at half the total thickness of the electronic component 10 based on the concept of controlling warpage. In addition, some design rules of grid shape (other diamond shape, wave shape are also possible) are proposed, such as that the depth of the groove 40 is 1/5 to 1/2 of the thickness of the electronic component 10, the number of the grooves 40 is three in the width direction when the width of the electronic component 10 is less than or equal to 10mm, and 10mm < the width of the electronic component 10 <30mm is 5 in the width direction. The distance between two adjacent grooves 40 is 60-100 μm, and the depth of the groove 40 is 5-10 μm. Since the plurality of grooves 40 of the present application extend in different directions, stresses in different directions are released.
After the wafer is diced to form singulated electronic devices, the silicide at the back side is trenched 40 to relieve stress generated by front-end wafer fabrication. The invention constructs the groove for releasing stress behind the electronic element, so the thickness of the electronic element can be thinner, and the thickness of the whole packaging piece can be thinner.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A semiconductor structure, comprising:
an electronic component having a first surface and a second surface which are oppositely arranged;
a circuit layer disposed on the first face;
a groove disposed on the second face;
the grooves have at least two different directions of extension.
2. The semiconductor structure of claim 1, further comprising:
a filler material disposed in the trench.
3. The semiconductor structure of claim 2, wherein the specific gravity and heat dissipation coefficient of the fill material are greater than the specific gravity and heat dissipation coefficient of a material adjacent to the fill material.
4. The semiconductor structure of claim 1, wherein a depth of the trench is approximately equal to a thickness of the line layer.
5. The semiconductor structure of claim 1, wherein an area fraction of the trench is approximately equal to an area fraction of the line layer.
6. The semiconductor structure of claim 1, wherein sidewalls of the trench are wavy.
7. The semiconductor structure of claim 1, further comprising:
a silicide encapsulating the electronic element, the trench extending from an outer surface of the silicide to the second side of the electronic element.
8. The semiconductor structure of claim 7, further comprising: an insulating material encapsulating the silicide and the electronic elements in the silicide.
9. The semiconductor structure of claim 1, wherein a width of the trench widens in a direction away from the electronic component from the second face.
10. The semiconductor structure of claim 1, wherein a plurality of the trenches are of uniform depth.
CN202110590730.1A 2021-05-28 2021-05-28 Semiconductor structure and forming method thereof Pending CN113539984A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110590730.1A CN113539984A (en) 2021-05-28 2021-05-28 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110590730.1A CN113539984A (en) 2021-05-28 2021-05-28 Semiconductor structure and forming method thereof

Publications (1)

Publication Number Publication Date
CN113539984A true CN113539984A (en) 2021-10-22

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002100777A (en) * 2000-09-20 2002-04-05 Denso Corp Semiconductor device
JP2004186651A (en) * 2002-12-06 2004-07-02 Nec Corp Semiconductor device and its manufacture
CN101924058A (en) * 2008-11-12 2010-12-22 台湾积体电路制造股份有限公司 Method for reducing chip warpage
JP2011044497A (en) * 2009-08-19 2011-03-03 Toshiba Corp Method of manufacturing semiconductor device
CN107771352A (en) * 2015-06-26 2018-03-06 英特尔公司 GAN devices on the silicon substrate of design

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002100777A (en) * 2000-09-20 2002-04-05 Denso Corp Semiconductor device
JP2004186651A (en) * 2002-12-06 2004-07-02 Nec Corp Semiconductor device and its manufacture
CN101924058A (en) * 2008-11-12 2010-12-22 台湾积体电路制造股份有限公司 Method for reducing chip warpage
JP2011044497A (en) * 2009-08-19 2011-03-03 Toshiba Corp Method of manufacturing semiconductor device
CN107771352A (en) * 2015-06-26 2018-03-06 英特尔公司 GAN devices on the silicon substrate of design

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