JP2011040632A - Semiconductor optical element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor optical element that can appropriately confine a current and an electric field in an upper clad layer. <P>SOLUTION: The semiconductor optical element 1 includes a semiconductor substrate SB, a semiconductor mesa stripe M provided on the semiconductor substrate SB, a buried layer 30 to embed the semiconductor mesa stripe M, and an intermediate layer 20 that is provided between the semiconductor mesa stripe M and the buried layer 30 and is made of a dielectric material. A lower clad layer C1 shows a first conductive type when it is added with a first dopant, an upper clad layer C2 shows a second conductive type when it is added with a second dopant, and the buried layer 30 shows a semi-insulating property when it is added with a third dopant. The intermediate layer 20 is provided between the side surface F1 of the upper clad layer C2 and the buried layer 30 and is in contact with the side surface F1 of the upper clad layer C2, and the buried layer 30 is in contact with both the side surface F3 of the lower clad layer C1 and the side surface F4 of a core layer 10. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor optical device used for optical communication, optical recording, optical measurement and the like.

  As one of the semiconductor laser structures, there is a buried heterostructure (hereinafter abbreviated as BH) structure. In the BH structure, the side surface of the mesa stripe is buried with a buried layer. For example, in Patent Document 1, a mesa stripe includes a contact layer, a cladding layer (p-type upper cladding layer), an active layer, and a buffer layer (n-type lower cladding layer). For example, Zn-doped p-type InP is used as the clad layer (p-type upper clad layer) constituting the mesa stripe. For example, InP is used as the buried layer.

Japanese Patent Laid-Open No. 9-214045

  A semi-insulating buried layer is used to prevent leakage current from the mesa stripe to the buried layer and favorably confine the current to the mesa stripe region. In order to obtain semi-insulating properties, a dopant such as Fe is added to the buried layer. Deep levels due to Fe dopants are formed in the forbidden band of the Fe-added buried layer. The deep level captures electrons in the buried layer, and therefore has a high resistance to electrons. However, Zn doped in the p-type cladding layer and Fe doped in the buried layer mutually diffuse due to thermal history during the crystal growth of the buried layer and during electrode formation. As a result, since the p-type dopant Zn diffuses in the Fe-doped buried layer, the resistivity of the buried layer decreases, and conversely, the p-type cladding layer into which Fe has diffused increases in resistance. Therefore, since the buried resistance layer having a low resistance next to the p-type cladding layer having a high resistance in the mesa stripe is more susceptible to current flow, the buried layer on the side of the p-type cladding layer in the mesa stripe portion is formed. A leak current flows through the conductor. As another factor, the Fe-doped buried layer can capture electrons but cannot capture holes as described above. That is, it functions as a high resistance layer only for electrons. Therefore, when the p-type cladding layer and the Fe-doped buried layer are in direct contact, holes flow from the p-type cladding layer into the buried layer and recombine with the trapped electrons. End up. These leakage currents are ineffective currents that are not injected into the active layer, and lower the luminous efficiency of the device and cause the oscillation characteristics to deteriorate.

  In Patent Document 1, an Fe diffusion preventing layer is provided between the buried layer and the mesa stripe in order to suppress the leakage current due to the mutual diffusion of the dopant and the injection of holes into the buried layer. Specifically, in Patent Document 1, an Fe diffusion prevention layer made of n-type InP is employed. The material constituting the Fe diffusion prevention layer is a semiconductor material, not a dielectric material. The buffer layer (lower cladding layer) is made of n-type InP, the cladding layer (upper cladding layer) is made of p-type InP, and the contact layer is made of p-type InGaAsP. An Fe diffusion prevention layer made of n-type InP is provided on the side surface of the mesa stripe. Therefore, the junction between the Fe diffusion prevention layer, the contact layer and the cladding layer is a PN junction. However, the formation of such a PN junction causes an increase in device capacitance. In particular, since the Fe diffusion prevention layer is usually highly doped, the PN junction formed thereby causes a significant increase in device capacitance, making high-speed operation difficult. In the structure of Patent Document 1, the n-type Fe diffusion prevention layer is in contact with the mesa stripe portion including the active layer. By introducing this diffusion prevention layer, leakage current from the p-type upper cladding layer to the buried layer is suppressed, but on the other hand, a new leakage current flowing through the main diffusion prevention layer and flowing on the side surface of the mesa stripe is generated. In particular, since the carriers flowing through the main scattering prevention layer are electrons having a high mobility, a large leak current is likely to flow therethrough. As a result, the efficiency of current injection into the active layer is reduced, which may cause deterioration of device characteristics.

  Therefore, the present invention suppresses the diffusion of the dopant added to the upper cladding layer into the buried layer and the diffusion of the dopant added to the buried layer into the upper cladding layer. It is an object of the present invention to provide a semiconductor optical device that prevents the occurrence of leakage current flowing on the side surface of the mesa stripe and does not cause deterioration in high-speed performance due to an increase in device capacity due to the addition of a diffusion prevention layer.

  The semiconductor optical device of the present invention includes a semiconductor substrate, a semiconductor mesa stripe provided on the semiconductor substrate, a buried layer embedding the semiconductor mesa stripe, a gap between the semiconductor mesa stripe and the buried layer, and a dielectric The semiconductor mesa stripe includes a lower cladding layer, a core layer, and an upper cladding layer, and the core layer is provided between the lower cladding layer and the upper cladding layer on the semiconductor substrate. The lower cladding layer exhibits the first conductivity type by the addition of the first dopant, the upper cladding layer exhibits the second conductivity type by the addition of the second dopant, and the buried layer has the half conductivity by the addition of the third dopant. Insulating, the intermediate layer is provided between the side surface of the upper cladding layer and the buried layer, the intermediate layer is in contact with the side surface of the upper cladding layer, and the intermediate layer is above the semiconductor mesa stripe Covers to the lower end of the upper cladding layer from the buried layer is characterized in that in contact with the side surfaces and the core layer of the lower cladding layer.

  According to this semiconductor optical device, the intermediate layer made of a dielectric material is provided between the semiconductor mesa stripe and the buried layer. The intermediate layer covers from the upper end of the semiconductor mesa stripe to the lower end of the upper cladding layer and is in contact with the side surface of the upper cladding layer. Therefore, the junction between the intermediate layer and the upper cladding layer is not a PN junction. Since the intermediate layer is formed of a dielectric material, the second dopant in the upper cladding layer is prevented from interdiffusing into the buried layer, and the third dopant in the buried layer is interdiffused into the upper cladding layer. To prevent that. Therefore, a leak path due to the mutual diffusion of the dopant is not formed between the buried layer and the upper cladding layer. In addition, since the intermediate layer is made of a dielectric material, it is provided between the upper cladding layer and the buried layer, so that diffusion of carriers such as holes from the upper cladding layer to the buried layer can also be prevented. Leakage current due to can also be suppressed. Therefore, this intermediate layer has the same effect as the Fe diffusion preventing layer in the conventional structure of Patent Document 1. Next, advantages of the structure of the present invention over the conventional structure will be described. First, in the structure of the present invention, since the dielectric material constituting the intermediate layer is insulative, no leakage current flows in the intermediate layer. Therefore, it is possible to avoid the occurrence of a leakage current flowing on the side surface of the mesa stripe through the intermediate layer (Fe diffusion preventing layer), which is a problem in the conventional structure. Further, as described above, since the intermediate layer of the dielectric material does not form a PN junction with the upper cladding layer, the element capacitance does not increase even if the intermediate layer is added. Therefore, there is no deterioration in high speed due to an increase in element capacitance, which occurs when the conventional Fe diffusion prevention layer of the n-type semiconductor layer is used as the intermediate layer.

  Moreover, it is preferable that the width | variety of an intermediate | middle layer is 100 nm-1 micrometer. If the intermediate layer has a width of about 100 nm to 1 μm, diffusion that suppresses diffusion of dopants between the buried layer and the upper cladding layer and carriers such as holes from the upper cladding layer to the buried layer is suppressed. As the prevention layer, the intermediate layer can function well.

  The intermediate layer is preferably composed of a dielectric material of any one of BCB (benzocyclobutene), polyimide, silicon nitride, silicon oxide, zirconium oxide, and tantalum oxide. When the intermediate layer is made of any of the materials, the second dopant is effectively prevented from diffusing from the upper cladding layer to the buried layer and the third dopant is diffused from the buried layer to the upper cladding layer. it can.

  The dielectric intermediate layer is preferably made of aluminum nitride or aluminum oxide. Aluminum nitride or aluminum oxide has good thermal conductivity. Therefore, the heat in the semiconductor mesa stripe is released to the outside through the intermediate layer made of aluminum nitride or aluminum oxide. Therefore, it is possible to suppress a decrease in reliability due to heat.

  The third dopant in the buried layer is preferably Fe. The Fe dopant forms a deep level in the forbidden band of the buried layer. Deep levels capture electrons in the buried layer. Therefore, the buried layer can be suitably used as a layer having a function of blocking current caused by electrons.

  The semiconductor substrate is preferably made of InP. Since the semiconductor substrate is made of InP, a semiconductor material necessary for the construction of a long wavelength band optical device for optical communication such as InGaAs or InGaAsP lattice-matched with InP can be epitaxially grown on the substrate with good crystallinity. Therefore, a semiconductor optical element made of the semiconductor material can be suitably used for a light receiving device and a light emitting device for optical communication.

  The buried layer is preferably made of InP. The band gap of InP is higher than the band gap of the semiconductor material used for the core layer. Therefore, by using InP for the buried layer, carriers can be strongly confined in the core layer. The refractive index of InP is lower than the refractive index of the semiconductor material used for the core layer. Therefore, by using InP for the buried layer, light can be strongly confined in the core layer.

  According to the present invention, the dopant added to the upper cladding layer is prevented from diffusing into the buried layer, and the dopant added to the buried layer is prevented from diffusing into the upper cladding layer, via the intermediate layer. It is possible to provide a semiconductor optical device that can avoid the occurrence of a leak current flowing on the side surface of the mesa stripe and that does not deteriorate the high speed due to the addition of the intermediate layer.

FIG. 1 is a cross-sectional view schematically showing the structure of the semiconductor optical device according to the first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. FIG. 3A to FIG. 3C are cross-sectional views showing an example of a method for manufacturing a semiconductor optical device. FIG. 4A to FIG. 4D are cross-sectional views showing an example of a method for manufacturing a semiconductor optical device. FIG. 5A to FIG. 5B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor optical device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals.

(First embodiment)
A preferred first embodiment of the present invention will be described with reference to FIGS. 1 to 5 show an XYZ orthogonal coordinate system S. FIG. 1 is a cross-sectional view schematically showing the structure of the semiconductor optical device 1. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 3-5 is sectional drawing which shows an example of the manufacturing method of a semiconductor optical element. Hereinafter, an example in which the semiconductor optical device 1 is a Fabry-Perot semiconductor laser having a BH structure will be described.

  As shown in FIG. 1, in the semiconductor optical device 1, a semiconductor mesa stripe M is provided on a substrate, and a semiconductor substrate SB can be used for this substrate. The buried layer 30 embeds the semiconductor mesa stripe M. The semiconductor mesa stripe M includes a lower cladding layer C 1, a core layer 10, an upper cladding layer C 2, and a contact layer 17. The lower cladding layer C1 is provided on the semiconductor substrate SB. The core layer 10 is provided between the lower cladding layer C1 and the upper cladding layer C2 on the semiconductor substrate SB. The core layer 10 is provided on the lower cladding layer C1. The upper clad layer C2 is provided on the core layer 10. The contact layer 17 is provided on the upper cladding layer C2. The lower cladding layer C1 exhibits the first conductivity type by the addition of the first dopant. The upper cladding layer C2 exhibits the second conductivity type by the addition of the second dopant. The contact layer 17 exhibits the second conductivity type by the addition of the second dopant. The buried layer 30 exhibits semi-insulating properties due to the addition of the third dopant.

  The intermediate layer 20 made of a dielectric material is provided between the semiconductor mesa stripe M and the buried layer 30. The intermediate layer 20 is provided between the side surface F1 of the upper cladding layer C2 and the buried layer 30. The intermediate layer 20 is in contact with the side surface F1 of the upper cladding layer C2 to form a junction J1. The intermediate layer 20 covers the side surface of the semiconductor mesa stripe M from the upper end Ma of the semiconductor mesa stripe M to the lower end C2b of the upper cladding layer C2. The buried layer 30 is in contact with the side surface F3 of the lower cladding layer C1 and the side surface F4 of the core layer 10. The buried layer 30 is in contact with the side surface F3 of the lower cladding layer C1 to form a junction J3. The buried layer 30 is in contact with the side surface F4 of the core layer 10 to form a junction J4.

  According to the semiconductor optical device 1, the intermediate layer 20 made of a dielectric material is provided between the semiconductor mesa stripe M and the buried layer 30. The intermediate layer 20 covers the side surface of the semiconductor mesa stripe M from the upper end Ma of the semiconductor mesa stripe M to the lower end C2b of the upper cladding layer C2, and is in contact with the side surface F1 of the upper cladding layer C2. Therefore, the junction J1 between the intermediate layer 20 and the upper cladding layer C2 is a junction between a dielectric material and a semiconductor material, and not a PN junction. The intermediate layer 20 prevents the second dopant in the upper cladding layer C2 from interdiffusing into the buried layer 30, and prevents the third dopant in the buried layer 30 from interdiffusing into the upper cladding layer C2. . Therefore, a leakage current path due to dopant interdiffusion is not formed between the side surface F1 of the upper cladding layer C2 and the buried layer 30. Further, since the intermediate layer 20 is formed of a dielectric material, the intermediate layer 20 is provided between the mesa stripe M and the buried layer 30, so that holes such as holes from the upper cladding layer C 2 to the buried layer 30 are formed. Carrier diffusion can also be prevented, and leakage current caused thereby can be suppressed. Therefore, the intermediate layer 20 has the same effect as the Fe diffusion preventing layer in the conventional structure. Further, since the dielectric material constituting the intermediate layer 20 is insulative, no leak current flows through the intermediate layer 20. Therefore, it is possible to avoid the occurrence of a leakage current flowing through the side surface of the mesa stripe M through the intermediate layer 20 which is a problem in the conventional structure. Furthermore, since the intermediate layer 20 of the dielectric material does not form a PN junction with the upper cladding layer C2 as described above, the addition of the intermediate layer does not increase the device capacity, and thus occurs in the conventional structure. Further, there is no deterioration in high speed due to an increase in device capacity when an n-type semiconductor intermediate layer (Fe diffusion preventing layer) is added.

  The intermediate layer 20 is provided between the side surface F2 of the contact layer 17 and the buried layer 30. The intermediate layer 20 is in contact with the side surface F2 of the contact layer 17 to form a junction J2. The junction J2 between the intermediate layer 20 and the contact layer 17 is a junction between a dielectric material and a semiconductor material, and is not a PN junction. The intermediate layer 20 has a first portion 21 and a second portion 22. The width W1 of the first portion 21 and the width W2 of the second portion 22 of the intermediate layer 20 are each several hundred nm or more, for example, 100 nm to 1 μm, respectively. If the intermediate layer 20 has a width of about 100 nm to 1 μm, the mutual diffusion of the dopant between the buried layer 30 and the upper cladding layer C2 and the diffusion of carriers such as holes from the upper cladding layer C2 to the buried layer 30 are performed. The intermediate layer 20 can be made to function satisfactorily as a diffusion preventing layer that suppresses the above.

  The intermediate layer 20 is preferably made of a dielectric material of any one of BCB, polyimide, silicon nitride, silicon oxide, zirconium oxide, and tantalum oxide. When the intermediate layer 20 is made of any of the above materials, the second dopant diffuses from the upper cladding layer C2 to the buried layer 30, or the third dopant diffuses from the buried layer 30 to the upper cladding layer C2. Can be effectively suppressed.

  The intermediate layer 20 is preferably made of aluminum nitride or aluminum oxide. Aluminum nitride or aluminum oxide has good thermal conductivity. Therefore, the heat in the semiconductor mesa stripe M can be released to the outside through the intermediate layer 20 of aluminum nitride or aluminum oxide. Therefore, it is possible to suppress a decrease in reliability due to heat.

  The semiconductor mesa stripe M extends in the predetermined direction Ax. The predetermined direction Ax is, for example, parallel to the Y-axis direction. As shown in FIG. 2, the upper cladding layer C2 extends in the predetermined direction Ax. The intermediate layer 20 extends in the predetermined direction Ax in parallel with the extending direction of the upper cladding layer C2. The side surface F1 of the upper cladding layer C2 includes a first side surface F1a and a second side surface F1b. The first portion 21 of the intermediate layer 20 is in contact with the first side face F1a of the upper cladding layer C2. The second portion 22 of the intermediate layer 20 is in contact with the second side face F1b of the upper cladding layer C2. Similarly, the contact layer 17 extends in the predetermined direction Ax. As shown in FIG. 1, the side surface F2 of the contact layer 17 includes a first side surface F2a and a second side surface F2b. The first portion 21 of the intermediate layer 20 is in contact with the first side surface F2a of the contact layer 17. The second portion 22 of the intermediate layer 20 is in contact with the second side surface F2b of the contact layer 17. Therefore, the upper cladding layer C2 and the contact layer 17 are not in contact with the buried layer 30.

  The buried layer 30 includes a first portion 31 and a second portion 32. The first portion 31 of the buried layer 30 is in contact with the first portion 21 of the intermediate layer 20. The second portion 32 of the buried layer 30 is in contact with the second portion 22 of the intermediate layer 20.

  The semiconductor substrate SB is preferably made of InP. Since the semiconductor substrate SB is made of InP, a semiconductor material necessary for the construction of a long wavelength band optical device for optical communication such as InGaAs or InGaAsP lattice-matched with InP can be epitaxially grown on the substrate with good crystallinity. The semiconductor optical element 1 composed of the semiconductor material can be suitably used for a light receiving device and a light emitting device for optical communication. The semiconductor substrate SB is, for example, n-type.

  As shown in FIG. 1, the core layer 10 can include a lower optical confinement layer 11, an active layer 12, and an upper optical confinement layer 13. In this embodiment, since the semiconductor optical device 1 is a semiconductor laser, the core layer 10 functions as an optical waveguide. For example, a bulk layer is used for the active layer 12. The active layer 12 can use a quantum well structure in which quantum well layers and barrier layers are alternately stacked. Examples of the semiconductor material constituting the active layer 12 include GaInAsP, GaInAs, AlGaInAs, and AlInAs. The refractive index of the lower optical confinement layer 11, the active layer 12, and the upper optical confinement layer 13 constituting the core layer 10 is larger than the refractive index of the upper cladding layer C2 and larger than the refractive index of the lower cladding layer C1. For example, when the semiconductor optical device 1 is an electroabsorption modulator, the active layer 12 functions as a light absorption layer. By making the active layer 12 undoped, light absorption loss can be suppressed.

  Examples of the semiconductor material constituting the lower optical confinement layer 11 and the upper optical confinement layer 13 include GaInAsP, GaInAs, AlGaInAs, and AlInAs. By making the lower optical confinement layer 11 and the upper optical confinement layer 13 undoped, light absorption loss can be suppressed.

  The band gap of the lower optical confinement layer 11 is preferably smaller than the band gap of the lower cladding layer C1 and larger than the band gap of the active layer 12. The band gap of the upper optical confinement layer 13 is preferably smaller than the band gap of the upper cladding layer C2 and larger than the band gap of the active layer 12. Due to the magnitude relationship of the band gap, carriers injected from the lower cladding layer C1 and the upper cladding layer C2 are efficiently injected into the active layer 12.

  When the above-described band gap magnitude relationship is satisfied, the lower optical confinement layer 11 has a refractive index between the refractive index of the lower cladding layer C1 and the refractive index of the active layer 12. The upper optical confinement layer 13 has a refractive index between the refractive index of the upper cladding layer C <b> 2 and the refractive index of the active layer 12. Therefore, light confinement in the active layer 12 is strengthened. Therefore, good oscillation characteristics can be obtained. In particular, when the active layer 12 has a quantum well structure, the lower optical confinement layer 11 and the upper optical confinement layer 13 can significantly increase the optical confinement in the active layer 12. Therefore, better oscillation characteristics can be obtained. However, the lower light confinement layer 11 and the upper light confinement layer 13 are not essential. For example, when the optical confinement necessary for oscillation can be obtained only by the active layer 12 such as when the active layer 12 is bulk, the lower optical confinement layer 11 and the upper optical confinement layer 13 may be omitted.

A semiconductor material is used for the lower clad layer C1 and the upper clad layer C2. Examples of semiconductor materials used for the lower clad layer C1 and the upper clad layer C2 include InP, GaInAsP, GaInAs, AlGaInAs, AlInAs, and the like. In order to efficiently inject carriers into the active layer 12, the lower cladding layer C 1 and the upper cladding layer C 2 have a band gap of the active layer 12, a band gap of the lower optical confinement layer 11, and a band gap of the upper optical confinement layer 13. Are preferably made of materials each having a large band gap. As described above, the first dopant is added to the lower cladding layer C1, and the second dopant is added to the upper cladding layer C2. The first dopant added to the lower cladding layer C1 is, for example, n-type, and the second dopant added to the upper cladding layer C2 is, for example, p-type. The second dopant in the upper cladding layer C2 is preferably Zn. The concentration of the second dopant in the upper cladding layer C2 is preferably 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

A third dopant capable of forming a deep level capable of trapping carriers is added to the buried layer 30 in order to increase the resistance. The buried layer 30 has a high resistance exceeding 108 Ωcm, for example. The third dopant in the buried layer 30 is preferably Fe. The Fe dopant forms a deep level in the forbidden band of the buried layer 30. The deep level captures electrons in the buried layer 30. Therefore, the buried layer 30 can be suitably used as a layer having a function of blocking current (electrons). The concentration of the third dopant in the buried layer 30 is preferably 2 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ .

  The band gap of the buried layer 30 is preferably higher than the band gap of the active layer 12. In this case, a hetero barrier is formed at the interface between the buried layer 30 and the active layer 12 due to the band gap difference between the buried layer 30 and the active layer 12. Therefore, carrier confinement in the active layer 12 is enhanced. When the band gap relationship is established, the refractive index of the buried layer 30 is lower than the refractive index of the active layer 12. Therefore, light confinement in the active layer 12 is strengthened, and as a result, stimulated emission occurs efficiently. Therefore, good oscillation characteristics can be obtained.

  A semiconductor material is used for the buried layer 30. Examples of the semiconductor material used for the buried layer 30 include InP, GaInAsP, GaInAs, AlGaInAs, AlInAs, and the like. In particular, the buried layer 30 is preferably made of InP. InP has the largest band gap among GaInAsP-based materials. Therefore, the band gap of InP is higher than the band gap of the semiconductor material used for the core layer 10. Therefore, carriers can be strongly confined in the core layer 10 by using InP for the buried layer 30. InP has the lowest refractive index among GaInAsP-based materials. Therefore, the refractive index of InP is lower than the refractive index of the semiconductor material used for the core layer 10. Therefore, by using InP for the buried layer 30, light can be confined strongly in the core layer 10. Furthermore, since InP does not contain Al, it is difficult to be oxidized. Further, when the buried layer 30 is InP, since InP is a binary mixed crystal, lattice matching is maintained even if it grows in a stepped region on the side surface of the mesa stripe M. Therefore, if InP is used, the buried layer 30 can be buried and regrown in the mesa stripe M with good crystallinity.

  As the contact layer 17, highly doped GaInAsP or GaInAs is used. The contact layer 17 is, for example, p-type. A lower electrode E1 is formed on the back surface of the semiconductor substrate SB. An upper electrode E <b> 2 is formed on the buried layer 30, the contact layer 17, and the intermediate layer 20. The contact layer 17 forms an ohmic contact with the upper electrode E2.

In an example semiconductor optical device 1,
Semiconductor substrate SB: n-type InP, 100 μm thick lower cladding layer C1: n-type InP, 2 μm thick lower optical confinement layer 11: undoped GaInAsP, 60 nm thick active layer 12: quantum well structure (undoped GaInAsP quantum well layer, 7 nm thick Barrier layer of undoped GaInAsP, 10 nm thick stack)
Upper optical confinement layer 13: undoped GaInAsP, 60 nm thick upper cladding layer C2: p-type InP, 2 μm thick contact layer 17: p-type GaInAs, 0.5 μm thick buried layer 30: Fe-doped InP, 5 μm thick intermediate layer 20: BCB, 2.52μm thickness, width 200nm
It is.

  In the present embodiment, for example, Zn can be used as the p-type dopant. Further, as the n-type dopant, for example, S or Si can be used.

  In the present embodiment, the buried layer 30 made of a semiconductor is buried in the side surface F4 of the active layer 12, and contact between the intermediate layer 20 made of a dielectric and the side surface F4 of the active layer 12 is avoided. Defects are less likely to occur. More specifically, since the dielectric material used for the intermediate layer 20 and the semiconductor material constituting the mesa stripe M are different materials, the interface between them is crystallographically discontinuous. Therefore, when the mesa stripe M and the dielectric intermediate layer 20 are joined, a large number of dangling bonds remain on the side surface of the mesa stripe M in contact with the intermediate layer 20, and as a result, crystals are formed on the side surface of the mesa stripe M. Defects are likely to occur. In particular, in the active layer 12 in which a large amount of carriers (electrons and holes) are injected by current injection, when the injected electrons and holes are non-radiatively recombined through defects caused by the dangling bonds. Since the growth of new defects is promoted by the thermal energy released to the surface, many defects are likely to be generated on the mesa side surface F4 of the active layer 12. This causes a decrease in the light emission efficiency and crystallinity of the active layer 12 and causes a deterioration in the characteristics and reliability of the semiconductor optical device 1. Therefore, in the present invention, as shown in FIG. 1, of the side surface of the mesa stripe M, the side surface portion F1 of the upper cladding layer C2 doped with the second dopant and the contact, which are desired to avoid contact with the buried layer 30 The dielectric intermediate layer 20 is inserted only in the minimum area necessary to cover the side surface F2 of the layer 17. In this case, the active layer 12 is buried with the buried layer 30 which is a semiconductor, and contact between the side surface of the active layer 12 and the intermediate layer 20 can be avoided. Therefore, at the interface between the active layer and the dielectric layer as described above. Deterioration of device characteristics and reliability due to defect generation can be avoided.

  In addition, since the thermal expansion coefficient of the intermediate layer 20 made of a dielectric material and the mesa stripe M made of a semiconductor material are greatly different, when the mesa stripe M and the intermediate layer 20 are joined, the crystal distortion caused by this is present at the interface between them. It is easy to accumulate the stress, which causes deterioration of device characteristics and reliability. Therefore, in the structure of the present embodiment, of the side surfaces of the mesa stripe M, the side surface F1 of the upper cladding layer C2 doped with the second dopant and the side surface F2 of the contact layer 17 that are desired to avoid contact with the buried layer 30 are protected. The dielectric intermediate layer 20 is formed only in the minimum side region necessary for this. In this case, the side surface F4 of the core layer 10 and the side surface F3 of the lower cladding layer C1 are embedded with the embedded layer 30 made of a semiconductor material having the same thermal expansion coefficient as those layers, and therefore, these layers and the embedded layer are embedded. No stress due to the difference in thermal expansion coefficient occurs at the interface of the layers. Therefore, it is possible to minimize deterioration of element characteristics and reliability due to the difference in thermal expansion coefficient between the intermediate layer 20 and the semiconductor mesa stripe M.

  In addition, since the dielectric material has poor thermal conductivity, if the mesa stripe M is embedded in the intermediate layer 20, the heat generated in the active layer 12 during current injection is not easily dissipated outside the mesa stripe M, and the mesa stripe M Excessive heat energy is likely to be accumulated. This also causes deterioration of device characteristics and reliability. Therefore, in order to alleviate this problem, in the structure of the present embodiment, the dielectric intermediate layer 20 is formed in the minimum necessary region as described above, and the other regions are made of a semiconductor material and have thermal conductivity. The buried layer 30 is preferably buried. Thereby, heat dissipation from the mesa stripe M to the outside is improved, and accumulation of excessive thermal energy in the mesa stripe M can be avoided. Accordingly, deterioration of characteristics and reliability due to heat stress can be reduced.

  When the lower cladding layer C1 is n-type, an n-type dopant such as Si or S is added to the lower cladding layer C1. A dopant such as Fe is added to the buried layer 30. However, Si and S hardly diffuse with Fe. The Fe-added buried layer 30 traps many electrons and has a high resistance to electrons. Therefore, unlike the case of the p-type upper clad layer C2, even if the n-type lower clad layer C1 is in direct contact with the buried layer 30, the dopant between the buried layer 30 and the lower clad layer C1. Leakage current due to interdiffusion and electron intrusion into the buried layer 30 does not occur, and therefore device characteristics are not deteriorated by this. Therefore, in the example shown in FIG. 1, the intermediate layer 20 is not provided between the lower cladding layer C <b> 1 and the buried layer 30.

  Further, in order to ensure that the lowermost end portion C2b of the side surface F1 of the upper clad layer C2 is covered with the intermediate layer 20, the intermediate layer 20 includes the upper optical confinement layer 13 as shown in the region R of FIG. It may be in contact with a part of the side surface.

  Below, an example of the manufacturing method of the semiconductor optical element 1 is demonstrated using FIGS. The metal organic vapor phase epitaxy (OMVPE) method is used for crystal growth. A semiconductor substrate SB is prepared. As shown in FIG. 3A, in the first crystal growth step, the lower cladding layer C1, the lower optical confinement layer 11, the active layer 12, the upper optical confinement layer 13, the upper cladding layer C2, and the contact layer 17 are formed. It grows on the semiconductor substrate SB in order.

  Next, a first dielectric mask 50 for forming a semiconductor mesa stripe is formed on a part of the contact layer 17. A dielectric material such as silicon nitride or silicon oxide can be used for the first dielectric mask 50. Etching is performed using dry etching or wet etching. As shown in FIG. 3B, a portion of the semiconductor substrate SB is etched by etching except for the portion directly below the first dielectric mask 50, and a striped semiconductor mesa stripe M is formed. The semiconductor mesa stripe M includes a lower cladding layer C1, a lower optical confinement layer 11, an active layer 12, an upper optical confinement layer 13, an upper cladding layer C2, and a contact layer 17. Note that the etching up to the semiconductor substrate SB is not essential, and in some cases, the etching up to the lower cladding layer C1 may be completed. As shown in FIG. 3C, the side surface of the semiconductor mesa stripe M is buried with the buried layer 30 in the second crystal growth step.

  In order to form the hole for the intermediate layer, another mask 51 is formed on the first dielectric mask 50 and the buried layer 30 as shown in FIG. The mask 51 can be made of a dielectric material such as silicon nitride or silicon oxide. Further, the region of the buried layer 30 other than the region where the hole for the intermediate layer is formed is covered with a resist 52 as shown in FIG. Next, the mask 51 in the region not covered with the resist 52 is etched, and after the etching is completed, the resist 52 that is no longer needed is removed to form a hole for the intermediate layer as shown in FIG. Second dielectric masks 51A and 51B made by etching the mask 51 are formed on the surface of the buried layer 30 other than the region to be formed, and the first dielectric mask 50 is formed on the mesa stripe M. The structure is obtained. The second dielectric masks 51 </ b> A and 51 </ b> B are formed at predetermined intervals from both ends of the first dielectric mask 50. Etching such as dry etching is performed using the first dielectric mask 50 and the second dielectric masks 51A and 51B. By etching, a hole 41 is formed between the buried layer 30 and the side surface F1 of the upper cladding layer C2 and the side surface F2 of the contact layer 17 as shown in FIG. The hole 41 is formed with a depth and a width necessary for forming the intermediate layer. FIG. 4B shows an example in which the hole 41 is formed at such a depth that the side surface F2 of the contact layer 17, the side surface F1 of the upper cladding layer C2, and the side surface of the upper end portion of the upper optical confinement layer 13 are exposed. .

  The first dielectric mask 50 and the second dielectric masks 51A and 51B are removed. As shown in FIG. 4D, a dielectric material 20 a such as BCB is applied in the hole 41 and on the buried layer 30 and the contact layer 17. Excess dielectric material 20a other than the inside of the hole 41 is removed by dry etching to obtain the intermediate layer 20 as shown in FIG. The intermediate layer 20 includes a first portion 21 and a second portion 22.

  Next, first, the upper electrode E <b> 2 is formed on the buried layer 30, the contact layer 17, and the intermediate layer 20. Thereafter, the semiconductor substrate SB is thinned to a thickness capable of cleaving, for example, 100 μm or less by polishing or the like. Finally, as shown in FIG. 5B, the lower electrode E1 is formed on the back surface of the semiconductor substrate SB. As described above, the semiconductor optical device 1 of the present invention is obtained.

  The preferred embodiment of the present invention has been described in detail above, but the present invention is not limited to the above embodiment. In the above-described embodiment, an example in which the semiconductor substrate SB is n-type is shown, but the semiconductor substrate SB may be p-type. When the semiconductor substrate SB is p-type, for example, the lower clad layer C1 can be p-type, and the upper clad layer C2 and the contact layer 17 can be n-type.

  In the above embodiment, the example in which the buried layer 30 doped with Fe as an impurity is used is shown. However, the impurity added to the buried layer 30 does not have to be Fe, for example, Ti, Cr, and A transition metal such as Co may be used.

  In the above embodiment, the semiconductor optical device 1 is a Fabry-Perot semiconductor laser. However, the semiconductor optical device 1 is a distributed feedback (DFB) semiconductor laser, a distributed reflection (DBR) semiconductor laser, or the like. Other semiconductor lasers may be used. The semiconductor optical device 1 can also be applied to an optical device other than a semiconductor laser, such as a light emitting diode (LED), an electroabsorption optical modulator, a Mach-Zehnder optical modulator, and a semiconductor optical amplifier (SOA).

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor optical element, SB ... Semiconductor substrate, M ... Semiconductor mesa stripe, C1 ... Lower clad layer, C2 ... Upper clad layer, 10 ... Core layer, 11 ... Lower light confinement layer, 12 ... Active layer, 13 ... Upper light Confinement layer, 17 ... contact layer, 20 ... intermediate layer, 21 ... first part, 22 ... second part, 30 ... buried layer, 31 ... first part, 32 ... second part, E1 ... lower electrode, E2 ... Upper electrode.

Claims (7)

A semiconductor substrate;
A semiconductor mesa stripe provided on the semiconductor substrate;
A buried layer embedding the semiconductor mesa stripe;
An intermediate layer provided between the semiconductor mesa stripe and the buried layer and made of a dielectric material;
The semiconductor mesa stripe includes a lower cladding layer, a core layer, and an upper cladding layer,
The core layer is provided between the lower clad layer and the upper clad layer on the semiconductor substrate,
The lower cladding layer exhibits a first conductivity type by adding a first dopant,
The upper cladding layer exhibits a second conductivity type by adding a second dopant;
The buried layer exhibits a semi-insulating property by adding a third dopant,
The intermediate layer is provided between a side surface of the upper cladding layer and the buried layer,
The intermediate layer is in contact with the side surface of the upper cladding layer;
The intermediate layer covers from the upper end of the semiconductor mesa stripe to the lower end of the upper cladding layer,
The semiconductor optical device, wherein the buried layer is in contact with a side surface of the lower cladding layer and a side surface of the core layer.   The semiconductor optical device according to claim 1, wherein a width of the intermediate layer is 100 nm to 1 μm.   3. The semiconductor optical device according to claim 1, wherein the intermediate layer is made of any one of BCB, polyimide, silicon nitride, silicon oxide, zirconium oxide, and tantalum oxide.   The semiconductor optical device according to claim 1, wherein the intermediate layer is made of aluminum nitride or aluminum oxide.   The semiconductor optical device according to claim 1, wherein the third dopant added to the buried layer is Fe.   The semiconductor optical device according to claim 1, wherein the semiconductor substrate is made of InP.   The semiconductor optical device according to claim 1, wherein the buried layer is made of InP.

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