JP2011040593A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that when plasma etching with a chlorine gas is performed on an AlNd layer with an Nd addition of 2 at% which has heat resistance of about 400°C against a hillock, a region called a fence is generated where reaction products are deposited, and due to the presence of the fence, there is a possibility that in forming TFT using the AlNd layer as a gate electrode, the electrical property of TFT becomes unstable because an electrically unstable region is formed at the side of the gate electrode. <P>SOLUTION: The AlNd layer 203 is formed with a thickness of not less than 0.45 μm and not more than 0.8 μm, and an Nd content of not less than 0.5 at% and not more than 1.0 at%. In this condition range, the generation of the fence is controlled even when plasma etching is performed mainly using the chlorine gas. Further, since the substrate temperature is raised to 500°C, a silicon oxide layer having high reliability as an interlayer insulating layer 211 is formed without generating the hillock in the AlNd layer 203, and thereby a highly reliable TFT 220 is provided. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  An alloy in which neodymium (hereinafter also referred to as Nd) is added to aluminum (hereinafter also referred to as Al) (hereinafter also referred to as AlNd) has an occurrence of hillocks (fine projection defects) generated during heat treatment. It is suppressed compared to the case where it is used. As shown in Non-Patent Document 1, by adding about 2 at% of Nd, generation of hillocks can be suppressed even for heat treatment at 400 ° C. for 1 hour. When Nd is used, the generation of hillocks can be suppressed even when the addition amount is as low as 2 at%, so that the increase in resistivity due to alloy scattering is minimized as compared with the case where hillocks are suppressed by adding other substances. be able to.

  When an AlNd layer is used to form, for example, a gate electrode or other wiring structure, and an interlayer insulating layer is formed to embed the AlNd layer, it is formed at a low substrate temperature, such as a plasma CVD (chemical vapor deposition) method. However, the substrate temperature of about 300 ° C. is required, and the AlNd layer needs to be able to withstand this substrate temperature.

  The AlNd layer containing about 2 at% Nd has heat resistance that can withstand this process. Therefore, it is suitably used as a wiring material for liquid crystal panels and the like. In the step of etching AlNd containing about 2 at% of Nd, as shown in Patent Document 2, wet etching is mainly used.

  In recent years, in order to cope with the high definition required for display panels, the dimensional accuracy obtained by the wet etching method is insufficient, and a dry etching method with high dimensional accuracy has been studied. Among dry etching methods, a plasma etching method capable of irradiating etching reaction species with a uniform direction with respect to a substrate has been utilized as a suitable method. Practical etching can be performed by dry etching only when the Nd content is about 1 at% or less. Therefore, as shown in Patent Document 1 (particularly, paragraph 0078), a technique for improving heat resistance by suppressing generation of hillocks using a laminated structure using Mo is used.

JP 2004-55842 A JP 2004-356616 A

Kobe Steel Engineering Reports / Vol. 52. No. 2 (Sep. 2002), pp. 2-11

  When plasma etching mainly composed of chlorine gas is performed on AlNd containing about 2 at% of Nd, the selectivity with the resist mask cannot be obtained (for example, 0.2: If AlNd is removed by 1, the resist mask is removed by 5). In this case, the resist mask disappears during etching, and the pattern formation itself cannot be performed. Therefore, as shown in Non-Patent Document 1, a method of adding boron trichloride gas and improving the selection ratio between AlNd and a resist mask has been studied. In this case, a fence is formed on the side surface of the pattern obtained by etching. A region in which a so-called reaction product is deposited results. This frequently occurs when plasma etching is performed using conditions in which the flow ratio of boron trichloride gas is increased.

  FIG. 7 is an SEM photograph showing a state in which the reaction product is attached to the side surface of the AlNd pattern formed on the substrate. Since this is soluble in a hydroxylamine-based solvent, it is presumed that AlNd was not sputtered and reattached, but chlorides and oxides of Al and Nd were deposited. When an AlNd layer is used for a gate electrode or a wiring layer due to the presence of a fence, an electrically unstable region is formed on the side of the gate electrode or on the side of the wiring layer, so that the electrical characteristics of the TFT may be unstable. . In addition, since the fence contains highly active chlorine gas and oxygen, there is a problem that the gate electrode using the AlNd layer and other wiring layers are gradually corroded to reduce reliability.

  Further, by increasing the flow ratio of boron trichloride gas, reaction products (for example, boron oxide) adhere to the plasma etching apparatus. There is a need to frequently clean the plasma etching apparatus, and there is a problem that mass productivity decreases.

  Moreover, in order to make the structure which pinches | interposes an AlNd layer with Mo layer, since a manufacturing process becomes long, there exists a subject that mass productivity falls. Furthermore, the etching of wirings having a multilayer structure has a small process margin, and there is a problem that Mo snow leopard (a phenomenon in which Mo protrudes like a leopard) occurs and the yield is lowered.

  As described above, it is known that it is difficult to obtain a wiring layer that can be dry-etched and can withstand a heat treatment of about 500 ° C. with a single layer structure.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples. “Upper” is defined as the direction from the inside of the substrate toward the aluminum alloy layer to which neodymium is added.

  Application Example 1 A semiconductor device including a metal wiring layer according to this application example, wherein an aluminum alloy layer containing neodymium in a content of 0.5 at% to 1.0 at% in at least a part of the metal wiring layer And the aluminum alloy layer has a thickness of 0.45 μm or more and 0.8 μm or less.

  According to this, it is possible to prevent the generation of a fence by setting the content of neodymium to 1.0 at% or less, and to perform plasma etching with chlorine gas as a main component that can suppress deposits on the inner wall of the etching apparatus. It becomes possible to provide the obtained aluminum alloy layer. In addition, an aluminum alloy layer that suppresses generation of hillocks even when the aluminum alloy layer is heat-treated at 500 ° C. by setting the neodymium content to 0.5 at% or more and the layer thickness to 0.45 μm or more is provided. It becomes possible.

  Although the mechanism that suppresses the generation of hillocks is not clearly understood, the generation of hillocks is suppressed by increasing the total amount of neodymium, or by thickening the aluminum alloy layer, stress relaxation reduces hillocks. It is estimated that the occurrence is suppressed. Further, by providing a thickness of 0.8 μm or less, it becomes possible to perform plasma etching of the aluminum alloy layer in a practical time. Further, since the internal stress generated in the aluminum alloy layer is reduced, the reliability of the aluminum alloy layer can be ensured.

  Application Example 2 A method of manufacturing a semiconductor device including a metal wiring layer according to this application example, including neodymium in a content of 0.5 at% to 1.0 at%, and 0.45 μm to 0.8 μm. And a step of performing plasma etching in an atmosphere containing chlorine and a step of performing a heat treatment at 300 ° C. or more and 500 ° C. or less using an aluminum alloy layer having the thickness of

  According to this, it becomes possible to suppress generation | occurrence | production of the hillock accompanying the heat processing of the aluminum alloy layer to which neodymium was added. Although the mechanism that suppresses the generation of hillocks is not clearly understood, the generation of hillocks is suppressed by increasing the total amount of neodymium, or by thickening the aluminum alloy layer, stress relaxation reduces hillocks. It is estimated that the occurrence is suppressed.

The outline figure which shows the structure of an ICP etching apparatus. (A)-(c) is process sectional drawing which shows the process of forming the gate electrode used as a typical example as a pattern which performs a plasma etching process. The cross-sectional SEM photograph at the time of performing plasma etching using the ICP etching apparatus on the etching conditions of this embodiment. FIG. 3 is a cross-sectional view of a TFT formed using the plasma etching method shown in the first embodiment. Schematic of an ECR plasma etching apparatus. Schematic of the HWP etching apparatus. The SEM photograph which shows the state which the reaction product adhered to the AlNd pattern side surface formed on the board | substrate.

First Embodiment: Manufacturing Method of Semiconductor Device
(Configuration of plasma etching system)
Hereinafter, the configuration of a plasma etching apparatus for forming an AlNd wiring layer as a semiconductor device will be described with reference to the drawings. FIG. 1 is a schematic diagram showing the configuration of an ICP (inductively coupled plasma) etching apparatus that is preferably used as the plasma etching apparatus according to the present embodiment. The ICP etching apparatus 100 includes a transport system 101 for transporting a substrate 200, a gate valve 102, a processing chamber 103, a counter electrode 104, a substrate support unit 105, a coupling capacitor 106, an AC bias power source 107, an antenna 108, a gas supply system 109, and a gas. The substrate 200 is processed including an exhaust system 110, an RF power source 111, a preliminary exhaust system 112, and a preliminary exhaust chamber 113.

  The transport system 101 has a function of transporting the substrate 200 from the atmosphere to the processing chamber 103. The gate valve 102 is hermetically sealed between the atmosphere and the processing chamber 103, and is opened when the substrate 200 is inserted / extracted from the processing chamber 103. The preliminary exhaust chamber 113 has a function of exhausting the atmosphere that is entered when the substrate 200 is transported from the atmosphere from the preliminary exhaust system 112 and suppressing the mixture of the atmosphere into the processing chamber 103.

  The antenna 108 has a function of exciting the etching gas supplied from the gas supply system 109 in the processing chamber 103 and generating plasma by inductive coupling. The gas supply system 109 has a function of introducing an etching gas supplied from a gas flow rate controller (not shown) into the processing chamber 103. The gas exhaust system 110 controls the pressure in the processing chamber 103 by a turbo molecular pump or a pressure control mechanism (not shown).

  The RF power supply 111 supplies energy for generating and maintaining plasma in the processing chamber 103 by supplying high-frequency power of 13.56 MHz to the antenna 108.

  The AC bias power source 107 generates a DC bias between the counter electrode 104 and the substrate 200 via the coupling capacitor 106, and performs etching (ion bombardment) by the aspect ratio of anisotropic etching and ion attraction from plasma. Control). The coupling capacitor 106 has a function of receiving a high-frequency power from the AC bias power source 107 and holding a DC potential generated in the plasma.

  In the figure, an antenna 108 having a two-turn configuration is used, but a one-turn type or a multi-turn type may be used. Although the ICP etching apparatus has been described here, it can handle the plasma excitation energy and the plasma drawing energy independently, such as an ECR (electron cyclotron spin resonance) plasma etching apparatus or an HWP (helicon wave excited plasma) etching apparatus. A plasma etching apparatus may be used. In FIG. 1, the counter electrode 104 can be omitted, and bias power may be supplied between the plasma and the substrate 200.

  Next, an outline of the ECR plasma etching apparatus will be described. FIG. 5 is a schematic view of an ECR plasma etching apparatus. The supply / exhaust system and the transport system are omitted. The plasma excited by the microwave incident from the quartz window causes electron cyclotron resonance in cooperation with the magnetism from the magnet to generate highly efficient plasma. The plasma is supplied with an AC bias to a substrate disposed in the processing chamber via a capacitor inserted between the AC bias power source and blocking a direct current component. This AC bias generates a DC potential in the plasma (generated by the speed difference between electrons and ions) and controls the etching state of the substrate. That is, the power for generating plasma and the power for drawing in plasma are controlled independently.

  Next, an outline of the HWP etching apparatus will be described. FIG. 6 is a schematic view of an HWP etching apparatus. The supply / exhaust system and the transport system are omitted. The high frequency power supplied from the RF power source to the antenna generates a helicon wave in cooperation with the magnet. The plasma excited by the helicon wave is given an AC bias to a substrate disposed in the processing chamber via a capacitor inserted between the AC bias power source and blocking a direct current component. This AC bias generates a DC potential in the plasma (generated by the speed difference between electrons and ions) and controls the etching state of the substrate. That is, the power for generating plasma and the power for drawing in plasma are controlled independently. As described above, when using a plasma etching apparatus in which the power to be generated and the power to draw plasma can be controlled independently, the following plasma etching method can be applied.

(Plasma etching process)
Hereinafter, a plasma etching process using the above-described plasma etching apparatus will be described with reference to the drawings. As an apparatus used for the plasma etching process, for example, an ICP etching apparatus, an ECR plasma etching apparatus, an HWP etching apparatus, or the like described in the first embodiment is used, and plasma etching that can handle plasma excitation energy and plasma drawing energy independently is used. Is preferred. In this embodiment, an example using the above-described ICP plasma etching apparatus will be described. Moreover, the etching conditions shown below show an example and are not limited to these etching conditions.

  FIG. 4 shows one mode of a TFT as a semiconductor device. Hereinafter, a manufacturing process for manufacturing the TFT 220 will be described with reference to a process cross-sectional view shown in FIG. 2A to 2C are process cross-sectional views illustrating a process of forming a typical gate electrode as a pattern for performing a plasma etching process. FIG. 2A shows a process cross-sectional view in a state before performing plasma etching. As shown in FIG. 2A, a polycrystalline silicon layer 201 is formed in an island shape (from the same material formed in the same process) on a substrate 200 using non-alkali glass and having silicon oxide deposited as a buffer layer. In a state separated from each other in plan view). A silicon oxide layer having a thickness of about 100 nm is formed as the gate insulating layer 202 on the polycrystalline silicon layer 201. Since the thickness of the gate insulating layer 202 depends on the breakdown voltage of the TFT described later, this layer thickness is described as a guide for illustrating an example. Note that the polycrystalline silicon layer 201 may be formed by introducing a known impurity in order to form the TFT 220. Alternatively, the TFT 220 may be formed using a process such as an ion implantation method using a gate electrode obtained by processing the AlNd layer 203 as a mask.

  On the gate insulating layer 202, an AlNd layer 203 to which Nd of about 0.8 at% is added is formed. The AlNd layer 203 can be formed using, for example, a sputtering method. Here, the amount of Nd added is preferably 0.5 at% or more and 1.0 at% or less. By making the addition amount 0.5 at% or more, it becomes possible to suppress the generation of hillocks (fine projection defects) even when heat treatment is performed, compared to pure aluminum. In addition, when the addition amount is 1.0 at% or less, it is possible to perform plasma etching while suppressing generation of a fence.

  The layer thickness preferably takes a value of 0.45 μm or more and 0.8 μm or less. By taking a layer thickness of 0.45 μm or more, generation of hillocks can be suppressed even if heat treatment such as annealing or CVD treatment with vacuum heating is performed. In addition, by taking a layer thickness of 0.8 μm or less, it is possible to suppress the time required for plasma etching and ensure mass productivity. Further, it is possible to suppress internal stress generated in the aluminum alloy layer.

  A photoresist layer 230 having a tapered pattern shape is formed on the AlNd layer 203. Then, plasma etching is performed. FIG. 2B is a process cross-sectional view showing a configuration during plasma etching. The photoresist layer 230 is retracted by the plasma irradiation, and accordingly, the taper shape is transferred to the AlNd layer 203 to form the AlNd layer 203 that functions as a gate electrode. Thereafter, the photoresist layer 230 is removed by a process such as ashing. FIG. 2C shows a process cross-sectional view after completing the steps so far.

  Etching conditions are: distance between electrodes (distance between the counter electrode 104 and the substrate support 105 shown in FIG. 1): 150 mm, pressure in the processing chamber 103: 0.6 Pa, plasma excitation output: 2200 W, plasma drawing output: 3300 W Plasma pull-in frequency: 3.0 MHz, chlorine gas flow rate: 250 sccm, plasma excitation frequency: 13.56 MHz, and the substrate 200 is made of alkali-free glass having dimensions of 400 mm × 500 mm. As shown in FIG. 3, there is no fence seen in FIG. 7, and the AlNd layer 203 can be processed by the plasma etching method. FIG. 3 is a SEM photograph after etching the AlNd layer formed on the glass substrate under the etching conditions described above.

  Here, a plasma etching apparatus that can handle plasma excitation energy and plasma drawing energy independently, such as the ECR plasma etching apparatus shown in FIG. 5 and the HWP etching apparatus shown in FIG. Even in such a case, as shown in FIG. 3, it is possible to perform plasma etching in a shape that suppresses the formation of a fence. In addition, when using the apparatus which does not have the counter electrode 104 shown in FIG. 1, the above description of the distance between electrodes becomes invalid. The same applies to the case where another plasma etching apparatus having no counter electrode is used. In this case, plasma drawing energy is applied between the plasma and the substrate 200 instead of the counter electrode 104. That is, the etching proceeds in a state where the average distance between the plasma and the substrate becomes an equivalent inter-electrode distance.

Even if the ECR plasma etching apparatus shown in FIG. 5 or the HWP etching apparatus shown in FIG. 6 is used, the AlNd layer 203 is plasma generated without generating the fence shown in FIG. 7 as shown in FIG. It can be processed by an etching method.
Next, an interlayer insulating layer 211 is deposited using a plasma CVD method or the like. At this time, a substrate temperature of about 400 ° C., preferably about 500 ° C. is required. However, by forming the AlNd layer 203 in the above-described condition range, the AlNd layer 203 can withstand this deposition temperature and suppress the generation of hillocks. It becomes possible. Subsequently, the contact hole 212, the source side electrode 209, the drain side electrode 210, and the like are formed using a known method, so that the TFT 220 shown in FIG. 4 is formed.

(Second Embodiment: Semiconductor Device)
Hereinafter, as a second embodiment, a TFT as a semiconductor device will be described. In the TFT of this embodiment, it is also preferable to use the AlNd layer 203 etched by the plasma etching method exemplified in the first embodiment as a gate electrode. FIG. 4 is a cross-sectional view of a TFT formed by using the plasma etching method exemplified in the first embodiment.

  In addition, as illustrated in the first embodiment, the AlNd layer 203 is etched using a plasma etching apparatus that can handle plasma excitation energy and plasma drawing energy independently, such as an ECR plasma etching apparatus or an HWP etching apparatus. May be used. The TFT 220 includes a substrate 200, a polycrystalline silicon layer 201, a gate insulating layer 202, an AlNd layer 203 as a gate electrode, a source 204, a source side LDD 205, a channel 206, a drain side LDD 207, a drain 208, a source side electrode 209, and a drain side electrode. 210, an interlayer insulating layer 211, and a contact hole 212.

  On the substrate 200, a source 204, a source side LDD 205, a channel 206, a drain side LDD 207, a drain 208, a source side electrode 209, and a drain side electrode 210 using the polycrystalline silicon layer 201 are formed. Here, it is preferable that the Nd concentration of the AlNd layer 203 has a value of 0.5 at% or more and 1.0 at% or less, and plasma etching can be performed in a state where generation of a fence or the like is suppressed. Here, it is 0.8 at%. The layer thickness preferably takes a value of 0.45 μm or more and 0.8 μm or less. By taking a layer thickness of 0.45 μm or more, generation of hillocks can be suppressed even if heat treatment is performed. In addition, by taking a layer thickness of 0.8 μm or less, it is possible to suppress the time required for plasma etching and ensure mass productivity. Further, it is possible to suppress internal stress generated in the aluminum alloy layer.

The source 204 and the drain 208 have a function of supplying carriers transmitted through the channel 206. The source 204 and the drain 208 are given a high impurity concentration of, for example, about 5 × 10 ²⁰ cm ⁻³ so as to enable ohmic contact with the source side electrode 209 and the drain side electrode 210.

  The source side LDD 205 and the drain side LDD 207 are arranged in the vicinity of the end of the channel 206, have an impurity concentration between the source 204, the drain 208, and the channel 206, and are at the end of the AlNd layer 203 (functioning as a gate). It is formed to alleviate the electric field concentration that occurs.

  The channel 206 has a function of inducing carriers according to an electric field applied from the AlNd layer 203 (functioning as a gate) through the gate insulating layer 202 to modulate the conductance of the TFT 220.

  The source side electrode 209 is connected to the source 204 and the drain side electrode 210 is connected to the drain 208 via the contact holes 212, respectively, and has a function of electrically connecting an external circuit (not shown) and the TFT 220.

  As described above, when the Nd concentration of the AlNd layer 203 is set to about 0.5 at% to 1.0 at% and the thickness of the AlNd layer 203 is set to 0.45 μm to 0.8 μm, heat of about 500 ° C. Since the process can be performed without generating hillocks, a silicon oxide layer having higher reliability than an organic layer such as an acrylic resin or a polyimide resin can be used for the interlayer insulating layer 211. The silicon oxide layer can be formed at a temperature of about 400 ° C. to 500 ° C. using plasma CVD or the like. Therefore, it is possible to provide the TFT 220 with high reliability.

  DESCRIPTION OF SYMBOLS 100 ... ICP etching apparatus, 101 ... Transfer system, 102 ... Gate valve, 103 ... Processing chamber, 104 ... Counter electrode, 105 ... Substrate support part, 106 ... Coupling capacitor, 107 ... AC bias power supply, 108 ... Antenna, 109 ... Gas Supply system 110 ... gas exhaust system 111 ... RF power source 112 ... preliminary exhaust system 113 ... preliminary exhaust chamber 200 ... substrate 201 ... polycrystalline silicon layer 202 ... gate insulating layer 203 ... AlNd layer 204 ... Source, 205 ... Source side LDD, 206 ... Channel, 207 ... Drain side LDD, 208 ... Drain, 209 ... Source side electrode, 210 ... Drain side electrode, 211 ... Interlayer insulating layer, 220 ... TFT, 230 ... Photoresist layer.

Claims (2)

A semiconductor device comprising a metal wiring layer,
An aluminum alloy layer containing neodymium in a content of 0.5 at% or more and 1.0 at% or less is used in at least a part of the metal wiring layer, and the thickness of the aluminum alloy layer is 0.45 μm or more and 0.8 μm or less. A semiconductor device comprising a thickness. A method of manufacturing a semiconductor device comprising a metal wiring layer,
A step of performing plasma etching in an atmosphere containing chlorine using an aluminum alloy layer including neodymium in a content of 0.5 at% to 1.0 at% and having a thickness of 0.45 μm to 0.8 μm;
Performing a heat treatment at 300 ° C. or higher and 500 ° C. or lower;
A method for manufacturing a semiconductor device, comprising: