JP2010141082A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an etching method with which deposition of reaction products called a fence can be suppressed when an AlNd layer to which Nd having heat resistance of approximately 400°C is added by 2 atom% is plasma etched. <P>SOLUTION: A chlorine gas is used as an etching gas for plasma etching and supplied so that the etching is carried out at an etching rate of ≤250 nm/minute. A neodymium chloride has lower vapor pressure than an aluminum chloride, but can be vaporized simultaneously with the aluminum chloride by carrying out the plasma etching at an etching rate of ≤250 nm/minute, thereby suppressing production of the fence. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

An alloy (hereinafter referred to as AlNd) in which neodymium (hereinafter referred to as Nd) is added to aluminum (hereinafter referred to as Al) is a hillock (fine protrusion defect) generated during heat treatment.
Can be suppressed as compared with the case of using pure Al. As shown in Non-Patent Document 1, by adding about 2 at% of Nd, it has a characteristic to withstand heat treatment at 400 ° C. for 1 hour. Further, since the generation of hillocks can be suppressed even if the amount of Nd added is small, the increase in resistivity due to alloy scattering can be suppressed to a minimum as compared with the case where hillocks are suppressed by adding other substances.

For example, an AlNd layer is used, and a thin film transistor (hereinafter, referred to as an AlNd layer) is used as a mask.
As a heat treatment for activating the impurities ion-implanted into the TFT), a heat treatment of about 400 ° C. is required, but an AlNd layer containing about 2 at% of Nd has heat resistance that can withstand this step. . Therefore, it is suitably used as a wiring material for liquid crystal panels and the like. 2a
In the process of etching AlNd containing about t% of Nd, as shown in Patent Document 2, wet etching is mainly used.

In recent years, in order to cope with the high definition required for display panels, the dimensional accuracy obtained by the wet etching method is insufficient, and a dry etching method with high dimensional accuracy has been studied. A plasma etching method that can introduce etching reactive species into the substrate in a selective direction has been utilized as a suitable method. For example, the etching method shown in Non-Patent Document 1 is known as a method of etching AlNd containing about 2 at% Nd using a plasma etching method. This is an etching gas
Argon 300 sccm, boron trichloride gas about 160 sccm, chlorine gas about 20 scc
Plasma etching is performed using a boron-rich etching gas supplied at a flow rate of m.

JP 2004-55842 A JP 2004-296297 A Kobe Steel Engineering Reports / Vol. 52. No. 2 (Sep. 2002), pp. 2-11

When plasma etching is performed on AlNd containing about 2 at% of Nd, a region where a reaction product is deposited, called a fence, may be formed on the side surface of the pattern obtained by the etching. This frequently occurs when plasma etching is performed using conditions in which the flow ratio of boron trichloride gas is increased.

FIG. 7 is an SEM photograph showing a state in which the reaction product is attached to the side surface of the AlNd pattern formed on the substrate. Since it is soluble in hydroxylamine-based solvents, AlN
It is estimated that d was not sputtered and reattached, but Al or Nd chloride or oxide was deposited. When a TFT is formed using an AlNd layer as a gate electrode due to the presence of a fence, an electrically unstable region is formed on the side of the gate electrode, so that the electrical characteristics of the TFT may become unstable. In addition, since the fence contains highly active chlorine gas and oxygen, there is a problem that the gate electrode using the AlNd layer and other wiring layers are gradually corroded to cause a decrease in reliability.

In addition, since reaction products (for example, boron oxide) adhere to the plasma etching apparatus,
There is a need to frequently clean the plasma etching apparatus, and there is a problem that mass productivity decreases.

In addition, as described in Non-Patent Document 1, as an atmospheric gas for performing plasma etching, the formation ratio of a fence can be suppressed by reducing the addition ratio of boron trichloride gas added to chlorine gas. Nd greater than 1 at% as described in paragraph 0028)
When performing plasma etching of an AlNd layer to which is added, it is difficult to lower the boron trichloride gas addition ratio within a practical range of conditions.

Further, in Patent Document 1 (paragraph 0067), “chlorine gas / boron chloride gas = 120 sccm”.
/ 60 sccm ”and an example using a gas flow rate ratio in which boron chloride gas accounts for 1/3, but the response when the ratio of boron chloride gas that makes etching more difficult is reduced It is not touched at all.

For this reason, there is no explanation for the case where the ratio of the boron chloride gas is reduced or when only the chlorine gas is used, and the technique for the plasma etching method of the AlNd layer with a small ratio of the boron chloride gas or with pure chlorine gas. Is not disclosed, and there is a problem that plasma etching cannot be performed when the amount of Nd added is high.

In addition, as shown in Non-Patent Document 1, when the amount of Nd added is about 0.7 at%, the heat resistance is about 250 ° C. for about 1 hour, and it can withstand a temperature at which impurities implanted into the TFT can be activated. It becomes impossible. Therefore, in the case of etching an AlNd layer containing about 2 at% of Nd that can withstand a heat treatment at 400 ° C. effective for impurity activation, wet etching is currently used. There is a problem that the dimensional accuracy is low and it is difficult to apply to a high-definition display that has been demanded in recent years.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples. “Upper” is defined as the direction from the inside of the substrate toward the aluminum alloy layer to which neodymium is added.

Application Example 1 A semiconductor device manufacturing method according to this application example is a semiconductor device manufacturing method in which a substrate having a mask pattern formed on an aluminum alloy layer to which neodymium is added is plasma-etched. A chlorine gas is used as an etching gas for performing the etching, and the chlorine gas is supplied so that the etching is performed at an etching rate of 150 nm / min to 250 nm / min.

According to this, it becomes possible to perform etching at a slower rate than the evaporation rate of neodymium chloride. Neodymium chloride has a lower vapor pressure than aluminum chloride, but 250n
Since plasma etching can be performed at an etching rate of m / min or less, it can be evaporated at the same time as aluminum chloride, thereby suppressing the generation of a fence (a reaction product deposited on the side of the wiring layer exposed by etching). It becomes possible. Further, by setting the etching rate to 150 nm / min or more, processing can be performed in a short etching time, and mass productivity can be ensured.

Application Example 2 In the method of manufacturing a semiconductor device according to the application example, a layer made of titanium, titanium nitride, molybdenum, chromium, tantalum, and tungsten is formed in close contact with the substrate side of the aluminum alloy layer. It is characterized by.

According to the application example described above, it is possible to suppress the generation of voids (hollow defects) and hillocks generated in the aluminum alloy layer to which neodymium is added. The mechanism that suppresses the generation of voids and hillocks is not clearly understood, but the metal layer functions as a buffer layer that relieves thermal stress during the manufacturing process that occurs between other layers in close contact with the metal layer. I guess.

Application Example 3 A method of manufacturing a semiconductor device according to the application example, wherein a layer made of titanium, titanium nitride, molybdenum, chromium, tantalum, and tungsten is formed in close contact with the aluminum alloy layer on the side opposite to the substrate. It is characterized by being.

According to the application example described above, it is possible to suppress the generation of voids and hillocks generated in the aluminum alloy layer to which neodymium is added. The mechanism that suppresses the generation of voids and hillocks is not clear, but it is assumed that the metal layer functions as a buffer layer that relieves thermal stress that occurs between other layers in close contact with the manufacturing process. is doing. In addition, in the application example 2 and the application example 3, the above-described metal layer may be formed so as to sandwich the aluminum alloy layer. In this case, generation of voids and hillocks can be more reliably suppressed.

[Application Example 4] A method of manufacturing a semiconductor device according to the above application example, wherein the etching gas is replaced with chlorine gas, and boron chloride gas is converted into a standard state with respect to a flow rate obtained by converting chlorine gas into a standard state. An etching gas added at a rate of 20% or less at a flow rate is used.

According to the application example described above, it is possible to suppress adhesion of reaction products due to boron deposited in the processing chamber in which plasma etching is performed. Boron chloride gas has a function of reducing neodymium oxide caused by residual oxygen and the like, and plasma etching can be performed in a state where the remaining neodymium oxide is suppressed. In the case where 20% or less of boron chloride gas is added at a flow rate converted to the standard state with respect to the flow rate converted to the standard state, the plasma etching mainly proceeds with chlorine ions and chlorine radicals. Neodymium residue accompanying reaction with residual oxygen can be removed. Further, since the flow rate ratio of boron chloride gas in terms of the standard state is less than 20% of chlorine gas, the generation of fences can be suppressed.

Application Example 5 A method of manufacturing a semiconductor device according to the application example, wherein plasma etching is performed by adding a rare gas to the etching gas.

According to the application example described above, the neodymium chloride concentration can be relatively reduced by introducing a rare gas that has a small contribution to plasma etching. Therefore, it becomes possible to suppress the occurrence of a fence.

Application Example 6 A method for manufacturing a semiconductor device according to the application example described above, wherein the amount of neodymium added is 0.5 at% or more and 3.0 at% or less with respect to aluminum.

According to the application example described above, by making the addition amount of neodymium 0.5 at% or more, generation of hillocks (fine protrusion defects) associated with heat treatment can be suppressed as compared with the case where pure aluminum is used. It becomes possible. And by suppressing the addition amount of neodymium to 3.0 at% or less,
It is possible to provide a method of manufacturing a semiconductor device that can suppress the generation of a fence. Furthermore, since the flow rate of boron chloride gas in the standard state is suppressed to 20% or less of the standard state of chlorine gas, the amount of reaction products adhering to the plasma etching apparatus can be suppressed. It is possible to reduce the frequency of cleaning, and to increase the operating rate of the plasma etching apparatus.

Application Example 7 In the method of manufacturing a semiconductor device according to the application example, the amount of neodymium added is more than 1.0 at% and not more than 2.5 at% with respect to aluminum.

According to the application example described above, the addition amount of neodymium is more than 1.0 at%, and 350 ° C.
Even if heat treatment is performed to a certain extent, generation of hillocks (fine protrusion defects) can be suppressed. In particular, by adding neodymium of 1.8 at% or more and 2.2 at% or less,
Even if heat treatment is performed for a long time, generation of hillocks is suppressed, and heat treatment having high impurity activation efficiency becomes possible. Then, by suppressing the amount of neodymium added to 2.5 at% or less, it becomes possible to provide a method for manufacturing a semiconductor device under the conditions that prevent the generation of fences and the decrease in conductivity due to alloy scattering.

Application Example 8 In the method of manufacturing a semiconductor device according to the application example, characterized by a power density to generate plasma 0.4 W / cm ² or more 1.0 W / cm ² or less.

According to the application example described above, plasma etching is performed on the aluminum alloy layer to which neodymium is added at a practical etching rate (chlorine gas flow rate range) by generating plasma at an output of 0.4 W / cm ² or more. Is possible. Further, by generating plasma with an output of 1.0 W / cm ² or less, it becomes possible to perform plasma etching with a forward taper angle of about 60 ° or less. By etching the aluminum alloy layer to which neodymium is added with a forward taper angle, the neodymium reaction product can be released without stagnation. Therefore, it is possible to suppress the generation of a fence due to neodymium.

Application Example 9 In the method of manufacturing a semiconductor device according to the application example, wherein the bias power to draw plasma toward the substrate to 0.75 W / cm ² or more 1.5 W / cm ² or less.

According to the application example described above, a practical etching rate (chlorine gas flow rate range) can be obtained by using a bias power of 0.75 W / cm ² or more. And 1.5W / cm
By using a bias power of ² or less, etching can be performed without hindering the release of neodymium chloride from the substrate due to excessive entrainment of plasma, and the generation of fences due to neodymium can be suppressed. .

[Application Example 10] A semiconductor device manufacturing method according to the above application example, characterized in that a bias frequency for extracting plasma to the substrate side is set to 2.0 MHz or more and 6.0 MHz or less.

According to the application example described above, damage caused by excessive physical ion collision (ion bombardment) can be suppressed by using a frequency of 2.0 MHz or higher. And 6.0MH
By using a frequency equal to or lower than z to remove neodymium chloride having a low vapor pressure by mechanical (ion collision), generation of a fence can be suppressed.

Application Example 11 A semiconductor device formed using the method for manufacturing a semiconductor device according to the application example.

According to this, since it becomes possible to form a semiconductor device using an electrode or wiring processed with an aluminum alloy layer added with neodymium without leaving a fence, the in-plane distribution in the substrate is suppressed, In addition, a highly reliable semiconductor device can be formed.

(First Embodiment: Configuration of Plasma Etching Apparatus)
Hereinafter, the configuration of a plasma etching apparatus will be described as a first embodiment with reference to the drawings. FIG. 1 shows an ICP suitably used as a plasma etching apparatus according to this embodiment.
(Inductively coupled plasma) It is the outline figure which shows the structure of an etching apparatus. The ICP etching apparatus 100 includes a transport system 101 for transporting a substrate 200, a gate valve 102, a processing chamber 103, a counter electrode 104, a substrate support unit 105, a coupling capacitor 106, an AC bias power source 107, an antenna 108, a gas supply system 109, and a gas. Exhaust system 110, RF power supply 111, preliminary exhaust system 11
2. The substrate 200 is processed including the preliminary exhaust chamber 113.

The transport system 101 has a function of transporting the substrate 200 from the atmosphere to the processing chamber 103. The gate valve 102 is hermetically sealed between the atmosphere and the processing chamber 103, and is opened when the substrate 200 is inserted / extracted from the processing chamber 103. The preliminary exhaust chamber 113 has a function of exhausting the atmosphere that is entered when the substrate 200 is transported from the atmosphere from the preliminary exhaust system 112 and suppressing the mixture of the atmosphere into the processing chamber 103.

The antenna 108 has a function of exciting the etching gas supplied from the gas supply system 109 in the processing chamber 103 and generating plasma by inductive coupling. The gas supply system 109 supplies an etching gas supplied from a gas flow rate controller (not shown) to the processing chamber 10.
3 has a function to be introduced. The gas exhaust system 110 controls the pressure in the processing chamber 103 by a turbo molecular pump or a pressure control mechanism (not shown).

The RF power supply 111 supplies energy for generating and maintaining plasma in the processing chamber 103 by supplying high-frequency power of 13.56 MHz to the antenna 108.

The AC bias power source 107 is connected to the counter electrode 104 and the substrate 2 via the coupling capacitor 106.
A DC bias is generated between 0 and 00 to control the aspect ratio of anisotropic etching and the etching (ion bombardment) state by drawing ions from the plasma. The coupling capacitor 106 receives the high frequency power from the AC bias power source 107, and
It has a function of holding a DC potential generated in plasma.

In the figure, an antenna 108 having a two-turn configuration is used, but a one-turn type or a multi-turn type may be used. In addition, although the ICP etching apparatus has been described here, this can handle the plasma excitation energy and the plasma drawing energy independently, such as an ECR (electron cyclotron spin resonance) plasma etching apparatus or an HWP (helicon wave excited plasma) etching apparatus. A plasma etching apparatus may be used. In FIG. 1, the counter electrode 104 can be omitted, and the plasma and the substrate 200 can be omitted.
Bias power may be supplied between the two.

Next, an outline of the ECR plasma etching apparatus will be described. FIG. 5 is a schematic view of an ECR plasma etching apparatus. The supply / exhaust system and the transport system are omitted. The plasma excited by the microwave incident from the quartz window causes electron cyclotron resonance in cooperation with the magnetism from the magnet to generate highly efficient plasma. The plasma is supplied to the substrate disposed in the processing chamber through a capacitor inserted between the AC bias power source and blocking DC components.
A bias is given. This AC bias generates a DC potential in the plasma (generated by the speed difference between electrons and ions) and controls the etching state of the substrate. That is,
Electric power for generating plasma and electric power for drawing in plasma are controlled independently.

Next, an outline of the HWP etching apparatus will be described. FIG. 6 is a schematic view of the HWP etching apparatus. The supply / exhaust system and the transport system are omitted. The high frequency power supplied from the RF power source to the antenna generates a helicon wave in cooperation with the magnet. The plasma excited by the helicon wave is given an AC bias to a substrate placed in the processing chamber through a capacitor inserted between the AC bias power source and blocking a DC component. With this AC bias,
A DC potential is generated in the plasma (generated by the speed difference between electrons and ions) to control the etching state of the substrate. That is, the power for generating plasma and the power for drawing in plasma are controlled independently.

As described above, when using a plasma etching apparatus in which the power to be generated and the power to draw plasma can be controlled independently, the following plasma etching method can be applied.

(Second Embodiment: Plasma Etching Step)
Hereinafter, a plasma etching process will be described as a second embodiment with reference to the drawings. As an apparatus used for the plasma etching process, for example, the ICP etching apparatus described in the first embodiment, the ECR plasma etching apparatus, the HWP etching apparatus, or the like, which uses plasma etching that can independently handle plasma excitation energy and plasma drawing energy, is used. Is preferred. In this embodiment, an example using an ECR plasma etching apparatus will be described as an example.

2A to 2C are process cross-sectional views illustrating a process of forming a typical gate electrode as a pattern for performing a plasma etching process. FIG. 2A shows a process cross-sectional view in a state before performing plasma etching. As shown in FIG. 2A, a polycrystalline silicon layer 201 is arranged in an island shape on a substrate 200 using non-alkali glass and having silicon oxide deposited as a buffer layer. A silicon oxide layer having a thickness of about 100 nm is formed as the gate insulating layer 202 on the polycrystalline silicon layer 201. Since the thickness of the gate insulating layer 202 depends on the breakdown voltage of the TFT described later, this layer thickness is described as a guide for illustrating an example. On the gate insulating layer 202, Al containing about 2 at% of Nd is added.
An Nd layer 203 is formed. The AlNd layer 203 can be formed using, for example, a sputtering method. Here, the addition amount of Nd is preferably more than 0.5 at% and not more than 3.0 at%, and generation of hillocks (fine projection defects) is suppressed even when heat treatment is performed, compared with pure aluminum. The

In addition, by adding Nd of more than 1.0 at% and not more than 2.5 at%, it is possible to suppress the generation of hillocks (fine projection defects) even when heat treatment at about 350 ° C. is performed. Then, by suppressing the amount of Nd added to 2.5 at% or less, it is possible to provide a method for manufacturing a semiconductor device under the conditions that prevent the generation of fences and the decrease in conductivity due to alloy scattering.

In particular, by adding Nd of 1.8 at% or more and 2.2 at% or less, generation of hillocks can be suppressed even when heat treatment is performed at 400 ° C. for 1 hour, and heat treatment having high impurity activation efficiency is possible. And it becomes possible by suppressing the addition amount of Nd to 3.0 at% or less to suppress the generation | occurrence | production of a fence and the electrical conductivity fall by alloy scattering.

A photoresist layer 230 as a mask pattern is formed on the AlNd layer 203. Here, the photoresist layer 230 is preferably formed with a taper angle of about 40 ° or more and less than 90 °. When the taper angle is less than 90 °, the photoresist layer 230 and the AlNd layer are etched when the AlNd layer 203 is plasma etched.
The reaction product gas generated simultaneously with the plasma etching of the layer 203 can be exhausted to the gas exhaust system 110 (see FIG. 1) through the processing chamber 103 (see FIG. 1) without stagnation. In addition, by setting the taper angle to 40 ° or more, the photoresist layer 230 can be easily processed, and the AlNd layer 203 can be processed without reducing the pattern accuracy.

Further, as the plasma etching progresses, a part of the photoresist layer 230 also advances at the same time, and a taper angle is formed in the AlNd layer 203, so that the plasma etching can be performed without hindering the discharge of the reaction product gas. Become. The taper angle of the AlNd layer 203 is preferably about 50 ° to 80 °. By taking a taper angle of 80 ° or less, AlN
The processing chamber 1 without retaining the reaction product gas generated simultaneously with the plasma etching of the photoresist layer 230 and the AlNd layer 203 when the d layer 203 is plasma etched.
The gas can be exhausted to the gas exhaust system 110 (see FIG. 1) via 03 (see FIG. 1). Further, by setting the taper angle to 50 ° or more, the AlNd layer 203 can be easily processed, and the AlNd layer 203 can be processed without reducing the pattern accuracy. FIG. 2B is a process cross-sectional view showing a state in the middle of plasma etching.
After the plasma etching, the photoresist layer 230 is removed by a process such as ashing. FIG. 2C is a process cross-sectional view in a state in which the photoresist layer 230 is removed and the plasma etching process of the AlNd layer 203 functioning as a gate electrode is finished.

As plasma etching conditions, chlorine gas is used as an etching gas and 150 nm is used.
It is preferable to control the chlorine gas flow rate so that etching is performed at an etching rate of at least 250 nm / min. Nd chloride has a lower vapor pressure than Al chloride, but 250 nm
By performing plasma etching so that the etching rate is less than or equal to 1 minute, it is possible to evaporate simultaneously with the Al chloride, so that the generation of a fence can be suppressed. Further, by setting the etching rate to 150 nm / min or more, processing can be performed in a short etching time, and mass productivity can be ensured.

Moreover, when performing the above-mentioned process, you may add the boron chloride gas of the flow volume of 20% or less with respect to the flow volume of chlorine gas in addition to chlorine gas. When boron chloride gas is added to such a degree, the amount of boron-derived reaction product deposited in the processing chamber 103 (see FIG. 1) in which plasma etching is performed is chlorine gas or a gas in which chlorine gas and rare gas are mixed. It can be suppressed to the extent similar to the case where is used. Boron chloride gas has a function of reducing Nd oxide caused by residual oxygen or the like, and plasma etching can be performed under conditions that can remove the residue of Nd oxide.

Further, a rare gas typified by argon, helium, neon, krypton, or xenon may be mixed into chlorine gas or an etching gas obtained by adding boron chloride to chlorine gas. in this case,
It is possible to relatively reduce the Nd chloride concentration by introducing a rare gas that has a small contribution to plasma etching. Therefore, it becomes possible to suppress the occurrence of a fence.

As a condition for exciting the plasma, the power density is 0.4 W / cm ² or more and 1
. It is preferable to use a value of about 0 W / cm ² or less. By generating plasma with an output of 0.4 W / cm ² or more, AlNd can be plasma etched at a practical etching rate. Further, by generating plasma with an output of 1.0 W / cm ² or less, it becomes possible to perform plasma etching with a forward taper angle of about 60 ° or less. By etching the AlNd layer with a forward taper angle, the reaction product containing Nd can be released without stagnation. Therefore, it becomes possible to suppress the generation of a fence due to Nd.

The bias power for drawing the plasma to the substrate side is 0.75 W / cm ² or more and 1.5.
It is preferable that it is W / cm ² or less. A practical etching rate can be obtained by using a bias power of 0.75 W / cm ² or more. By using a bias power of 1.5 W / cm ² or less, etching can be performed without hindering the release of Nd chloride from the substrate due to excessive entrainment of plasma, and the generation of fences due to Nd is suppressed. It becomes possible to do.

In addition, it is preferable that the bias frequency for drawing the plasma to the substrate side is about 2.0 MHz to 6.0 MHz. By using a frequency of 2.0 MHz or higher, damage due to excessive physical ion collision (ion bombardment) can be suppressed. And 6.0
By using a frequency of MHz or lower to remove Nd chloride having a low vapor pressure by mechanical (ion collision), generation of a fence can be suppressed.

As an example of the above condition range, plasma etching was performed under the following conditions.
FIG. 3 is a cross-sectional SEM photograph when plasma etching is performed using the ICP etching apparatus 100 shown in FIG. 1 under the following conditions.

Distance between electrodes (distance between the counter electrode 104 and the substrate support 105 shown in FIG. 1): 150 mm,
Pressure in the processing chamber 103: 0.6 Pa, plasma excitation output: 1500 W, plasma drawing output: 2500 W, plasma drawing frequency: 3.0 MHz, chlorine gas flow rate: 200 sc
cm, plasma excitation frequency: 13.56 MHz, 400 mm × 500 mm for the substrate 200
A non-alkali glass having the following dimensions is used. As shown in FIG. 3, there is no fence seen in FIG. 7, and the AlNd layer 203 having a tapered shape can be processed by the plasma etching method.

Here, by using similar conditions, the ECR plasma etching apparatus shown in FIG.
Even when a plasma etching apparatus capable of independently handling plasma excitation energy and plasma drawing energy such as the HWP etching apparatus shown in FIG. 6 is used, plasma etching is performed in a shape that suppresses fence formation as shown in FIG. Is possible. In addition, when using the apparatus which does not have the counter electrode 104 shown in FIG. 1, the above description of the distance between electrodes becomes invalid. The same applies to the case where another plasma etching apparatus having no counter electrode is used. In this case, instead of the counter electrode 104, the plasma and the substrate 20
Plasma entrapment energy is applied between 0 and 0. That is, etching proceeds on the assumption that the average distance between the plasma and the substrate exists as the distance between the electrodes.

Even if the ECR plasma etching apparatus shown in FIG. 5 or the HWP etching apparatus shown in FIG. 6 is used, as shown in FIG. 3, there is no fence seen in FIG. 7, and the AlNd layer 203 having a tapered shape is formed. It can be processed by plasma etching.

As a feature of the present embodiment, for example, an etching gas in which boron chloride gas is added at a ratio of 20% or less (including 0%) at a standard flow rate with respect to a standard flow rate of chlorine gas is used. Can be mentioned. By using an etching gas with a high proportion of chlorine gas, it is possible to suppress the generation of fences and the amount of reaction products adhering to the inside of the processing chamber 103. In addition, the cleaning frequency in the processing chamber 103 can be reduced.

In the above-described embodiment, the example in which the AlNd layer 203 is used as a single layer has been described.
In this case, a layer containing titanium, titanium nitride, molybdenum, chromium, tantalum, or tungsten may be formed on the substrate 200 side of the AlNd layer 203. In this case, generation of voids (hollow defects) and hillocks generated in the AlNd layer 203 can be suppressed. Although the mechanism to suppress the generation of voids and hillocks is not clearly understood, it is assumed that the metal layer functions as a buffer layer that relieves thermal stress that occurs between the substrate and the manufacturing process. Yes.

In the direction of the AlNd layer 203 facing the substrate 200, titanium, titanium nitride, molybdenum,
A layer containing chromium, tantalum, or tungsten may be formed. Even in this case, generation of voids and hillocks generated in the AlNd layer 203 can be suppressed. The mechanism that suppresses the occurrence of voids and hillocks is not clear, but it is assumed that the metal layer functions as a buffer layer that relieves thermal stress during the manufacturing process that occurs between other layers in close contact with the metal layer. ing.

Alternatively, a layer containing titanium, titanium nitride, molybdenum, chromium, tantalum, or tungsten may be formed on both sides of the AlNd layer 203. In this case, generation of voids and hillocks can be suppressed more reliably.

(Third Embodiment: Semiconductor Device)
Hereinafter, a TFT as a semiconductor device will be described as a third embodiment. The TFT of this embodiment is an Al film etched using the plasma etching method exemplified in the second embodiment.
The Nd layer 203 is used as a gate electrode. FIG. 4 is a cross-sectional view of a TFT formed using the plasma etching method exemplified in the second embodiment.

In addition, as illustrated in the second embodiment, an AlNd layer 203 is etched using a plasma etching apparatus that can handle plasma excitation energy and plasma drawing energy independently, such as an ECR plasma etching apparatus or an HWP etching apparatus. It may be used. The TFT 220 includes a substrate 200, a polycrystalline silicon layer 201, a gate insulating layer 202, an AlNd layer 203 as a gate electrode, a source 204, a source side LDD 205, a channel 20.
6, a drain side LDD 207 and a drain 208.

On the substrate 200, a source 204 using a polycrystalline silicon layer 201, a source side LDD 2
05, channel 206, drain side LDD 207, drain 208, source side electrode 209
The drain side electrode 210 is formed. Here, the Nd concentration of the AlNd layer 203 is 2 at%.
It is about.

The source 204 and the drain 208 have a function of supplying carriers transmitted through the channel 206. The source 204 and the drain 208 are given a high impurity concentration so as to enable ohmic contact with an electrode (not shown).

The source-side LDD 205 and the drain-side LDD 207 are disposed in the vicinity of the end of the channel 206, and have an impurity concentration between the source 204, the drain 208, and the channel 206.
It is formed to alleviate electric field concentration occurring at the end of the lNd layer 203 (functioning as a gate).

The channel 206 extends from the AlNd layer 203 (functioning as a gate) to the gate insulating layer 20.
2 has a function of inducing carriers according to the electric field applied through 2 and modulating the conductance of the TFT 220.

The source side electrode 209 is connected to the source 204, and the drain side electrode 210 is connected to the drain 208, and has a function of electrically connecting an external circuit (not shown) and the TFT 220.

As described above, by setting the Nd concentration of the AlNd layer 203 to about 2 at%, 400 ° C.
Since annealing for one hour can be performed without generating hillocks, it is possible to activate the impurities in the source 204 and the drain 208 to which high-concentration impurities are added. Therefore, the contact resistance between the source side electrode 209 and the source 204 and the drain side electrode 2
10 and the drain 208 can be electrically connected with a low value while suppressing in-plane distribution.

The outline figure which shows the structure of an ICP etching apparatus. (A)-(c) is process sectional drawing which shows the process of forming the gate electrode used as a typical example as a pattern which performs a plasma etching process. The cross-sectional SEM photograph at the time of performing plasma etching using the ICP etching apparatus on the etching conditions of this embodiment. Sectional drawing of TFT formed using the plasma etching method shown in 2nd Embodiment. FIG. 3 is a schematic view of an ECR plasma etching apparatus. FIG. 3 is a schematic view of an HWP etching apparatus. The SEM photograph which shows the state which the reaction product adhered to the AlNd pattern side surface formed on the board | substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... ICP etching apparatus, 101 ... Conveyance system, 102 ... Gate valve, 103 ... Processing chamber, 104 ... Counter electrode, 105 ... Substrate support part, 106 ... Coupling capacitor, 107 ... AC
Bias power supply, 108 ... antenna, 109 ... gas supply system, 110 ... gas exhaust system, 111 ...
RF power source, 112 ... preliminary exhaust system, 113 ... preliminary exhaust chamber, 200 ... substrate, 201 ... polycrystalline silicon layer, 202 ... gate insulating layer, 203 ... AlNd layer, 204 ... source, 205 ... source side LDD, 206 ... channel 207: drain side LDD 208: drain 209
... Source side electrode, 210 ... Drain side electrode, 220 ... TFT, 230 ... Photoresist layer.

Claims (11)

A method for manufacturing a semiconductor device in which a substrate on which a mask pattern is formed is plasma-etched on an aluminum alloy layer to which neodymium is added, wherein chlorine gas is used as an etching gas for performing plasma etching, and an etching rate is 150 nm / min or more. A method for manufacturing a semiconductor device, comprising supplying chlorine gas so that etching is performed in a range of 250 nm / min or less. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a layer made of titanium, titanium nitride, molybdenum, chromium, tantalum, and tungsten is formed in close contact with the substrate side of the aluminum alloy layer. A method for manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a layer made of titanium, titanium nitride, molybdenum, chromium, tantalum, and tungsten is formed in close contact with the side of the aluminum alloy layer opposite to the substrate. A method of manufacturing a semiconductor device. It is a manufacturing method of the semiconductor device as described in any one of Claims 1-3, Comprising: It replaces with chlorine gas as said etching gas, Boron chloride gas is a standard state with respect to the flow volume which converted chlorine gas into the standard state A method for manufacturing a semiconductor device, wherein an etching gas added at a rate of 20% or less at a flow rate converted to is used. 5. The method of manufacturing a semiconductor device according to claim 1, wherein plasma etching is performed by adding a rare gas to the etching gas. 6. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the amount of neodymium added is 0.5 at% or more and 3.0 at% or less with respect to aluminum. Device manufacturing method. The semiconductor device manufacturing method according to claim 1, wherein the amount of neodymium added is more than 1.0 at% and not more than 2.5 at% with respect to aluminum. Device manufacturing method. A method of manufacturing a semiconductor device according to any one of claims 1 to 7, characterized in that the power density to generate plasma 0.4 W / cm ² or more 1.0 W / cm ² or less A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 1-8, characterized in that the bias power to draw plasma toward the substrate 0.75 W / cm ² or more 1.5 W / cm ² or less A method for manufacturing a semiconductor device. 10. The method for manufacturing a semiconductor device according to claim 1, wherein a bias frequency for drawing plasma to the substrate side is set to 2.0 MHz or more and 6.0 MHz or less. 11. Method. It forms using the manufacturing method of the semiconductor device as described in any one of Claims 1-10, The semiconductor device characterized by the above-mentioned.