JP2011035725A - Pulse generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse generation circuit which generates a PWM pulse with circuit configuration which does not perform classification to reduce the number of gates, and whose operation speed is raised by reducing a circuit area. <P>SOLUTION: The pulse generation circuit is constituted by being provided with: a circuit which receives the input of a rising timing signal and a falling timing signal to generate non-adjusted pulse data having logic values of a period of each unit time from 0 to n-1 obtained by dividing the inside of one period of a clock signal by n; and a circuit which receives the input of a delay time signal DELAY within a range from 0 to n-1 for specifying delay time using the unit time as a unit to generate delay pulse data having a logic value of a period from n-DELAY to n-1 of the non-adjusted pulse data in the last period in a period from 0 to DELAY-1, and a logic value from 0 to (n-1)-DELAY of the non-adjusted pulse data in the present period in a period from DELAY to n-1 within each period of the clock signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a pulse generation circuit, and more particularly to a PWM (Pulse Width Modulation) pulse generation circuit having an output position delay function.

  The digital PWM pulse generation circuit refers to the value of the signal ST indicating the rising position (timing) of the pulse and the signal EN indicating the falling position of the pulse, which are input in synchronization with the clock signal. A rising position and a falling position in one cycle are determined, and a PWM pulse is generated. For example, as shown in FIG. 6, one period of the clock signal is divided into 64, and should be set to H (high level) or L (low level) in each of 64 locations from the values of the referenced signals ST and EN. The PWM pulse corresponding to one cycle of the clock signal is generated.

  Also, it has an output position delay function for generating a PWM pulse whose output position is delayed by referring to the values of signals ST and EN delayed in accordance with the signal DELAY, which are also input in synchronization with the clock signal. A pulse generation circuit is known.

  However, depending on the value of the signal DELAY, the PWM pulse may be delayed for a maximum of one period. In this case, in order to generate a correct PWM pulse, it is necessary to divide the case to determine where the positions of the signals ST and EN are located in 64 locations within one cycle of the clock signal.

  FIGS. 7A to 7D show respective patterns (types 0 to 3) obtained by dividing the cases of the signals ST and EN according to the signal DELAY.

First, FIG. 7A shows a case of type 0, where both the signals ADD_ST and ADD_EN, which are values obtained by adding the value of the signal DELAY to the values of the signals ST and EN, are within the current cycle. In this case, an H PWM pulse is generated with reference to both values of the signals ADD_ST and ADD_EN in the current cycle.
On the other hand, FIG. 7B shows type 1 where the signal ADD_ST is in the current cycle, but the signal ADD_EN is shifted to the next cycle. In this case, only the rising edge of the PWM pulse is generated with reference to the value of the signal ADD_ST in the current cycle. That is, the PWM pulse remains H at the end of the current cycle.

  Further, it may be necessary to refer to the values of the signals ADD_Pre_ST and ADD_Pre_EN, which are values obtained by adding the value of the signal DELAY to the signals ST and EN (hereinafter referred to as signals Pre_ST and Pre_EN) in the previous cycle in the current cycle. is there.

FIG. 7C shows type 2 when the signal ADD_Pre_ST in the previous cycle is in the previous cycle, but the value of the signal ADD_Pre_EN in the previous cycle is shifted to the current cycle. In this case, only the falling edge of the PWM pulse is generated with reference to the value of the signal ADD_Pre_EN in the current cycle. That is, the PWM pulse remains H at the start of the current cycle.
FIG. 7D is type 3, where the value of the signal DELAY in the previous cycle is large and both the signals ADD_Pre_ST and ADD_Pre_EN in the previous cycle are shifted to the current cycle. In this case, rising and falling edges of the PWM pulse are generated with reference to the values of the signals ADD_Pre_ST and ADD_Pre_EN in the current cycle.

  FIG. 8 shows a block diagram of the PWM pulse generation circuit 100 in the case where four cases of types 0 to 3 are necessary for the signals ST and EN. The PWM pulse generation circuit 100 includes a DELAY addition unit 102, a case classification / 64-bit generation unit 104, and a current cycle / previous cycle synthesis unit 106.

  Here, the signals Pre_ST [5: 0] and Pre_EN [5: 0] are the signals ST [5: 0] and EN [5: 0] of the previous period. The signal DELAY [5: 0] is a signal that delays the output position of the signal PWMout [63: 0], and is 1/64 of one cycle from 0 to 63 obtained by dividing one cycle of the clock signal into 64. The amount of delay can be specified using the period as a unit time.

The DELAY adder 102 receives 6-bit signals ST [5: 0], EN [5: 0], and DELAY [5: 0] in synchronization with the clock signal. The signals ST [5: 0] and EN [5: 0] are delayed by one cycle of the clock signal by a flip-flop that operates in synchronization with the clock signal, and are output as signals Pre_ST and Pre_EN.
Further, the signals DELAY [5: 0] are added to the signals Pre_ST [5: 0], Pre_EN [5: 0] and the signals ST [5: 0], EN [5: 0] by the adders, respectively. 7-bit signals ADD_Pre_ST [6: 0], ADD_Pre_EN [6: 0], and signals ADD_ST [6: 0], ADD_EN [6: 0]. That is, the DELAY adder 102 adds the value of the signal DELAY to each signal and outputs a signal whose output position is delayed.

Subsequently, the 7-bit signals output from the DELAY adder 102 are input to the case classification / 64-bit generator 104. The signals ADD_ST [6: 0] and ADD_EN [6: 0] are input to the generation / 104 bit generation circuit 104a that performs the classification of types 0 and 1.
In the case-by-case / 64-bit generation circuit 104a, based on the values of these signals ADD_ST [6: 0] and ADD_EN [6: 0], the case of type 0, 1 described above corresponds to the PWM pulse of the current cycle. A 64-bit signal PWMc [63: 0] is output. That is, the PWMc [63: 0] is a logic of the signal PWM_type0 [N] corresponding to the PWM pulse in the case of type0 and the signal PWM_type1 [N] (N is 0 to 63) corresponding to the PWM pulse in the case of type1. This corresponds to the summed data (corresponding to the logical sum of conditional expressions (1) and (2) described later).

Similarly, the signals ADD_Pre_ST [6: 0] and ADD_Pre_EN [6: 0] are input to the case-by-case / 64-bit generation circuit 104b in which cases 2 and 3 are divided.
In the case-by-case / 64-bit generation circuit 104b, based on the values of these signals ADD_Pre_ST [6: 0] and ADD_Pre_EN [6: 0], the case of type 2 and 3 described above corresponds to the PWM pulse of the previous period. A 64-bit signal PWMp [63: 0] is output. That is, the PWMp [63: 0] is a logic between the signal PWM_type2 [N] corresponding to the PWM pulse in the case of type2 and the signal PWM_type3 [N] (N is 0 to 63) corresponding to the PWM pulse in the case of type3. This corresponds to the summed data (corresponding to the logical sum of conditional expressions (3) and (4) described later).

  The current cycle / previous cycle combining unit 106 receives the current cycle data PWMc [63: 0] and the previous cycle data PWMp [63: 0]. The current cycle data PWMc [63: 0] and the previous cycle data PWMp [63: 0] are combined (for example, logical sum) by the current cycle / previous cycle combining unit 106, thereby causing the delayed pulse data PWMout [63]. : 0] (corresponding to conditional expression (5) described later).

Here, the PWM pulse generation circuit 100 is represented by the following conditional expressions as [1] to [4].
[1] DELAY addition
ADD_ST = ST + DELAY
ADD_EN = EN + DELAY
ADD_Pre_ST = Pre_ST + DELAY
ADD_Pre_EN = Pre_EN + DELAY

[2] Case classification (a) Current cycle (2 types)
type0 = (ADD_ST <= 63) & (ADD_EN <= 63)
type1 = (ADD_ST <= 63) &(ADD_EN> = 63)
(B) Previous period (2 types)
type2 = (ADD_Pre_ST <= 63) &(ADD_Pre_EN> = 63)
type3 = (ADD_Pre_ST> = 63) &(ADD_Pre_EN> = 63)

[3] 64 bits generation (N is 64 ways from 0 to 63)
(A) Current cycle
PWM_type0 [N] = (type0) & (ADD_ST <= N &ADD_EN> = N) (1)
PWM_type1 [N] = (type1) & (ADD_ST <= N) (2)
(B) Previous period
PWM_type2 [N] = (type2) &(ADD_Pre_EN> = 64 + N) (3)
PWM_type3 [N] = (type3) & (ADD_Pre_ST <= 64 + N &ADD_Pre_EN> = 64 + N) (4)

[4] Current cycle, previous cycle 64-bit data composition (N is 64 ways from 0 to 63)
PWMout [N] = PWM_type0 [N] | PWM_type1 [N] | PWM_type2 [N] | PWM_type3 [N] (5)
('|' Represents a logical sum)
Expression (5) becomes H when any of Expressions (1) to (4) is established.

As described above, there are five conditional expressions for generating 64 bits and combining data and combining the number of cases and data combining. Since one period is divided into 64, 320 (5 × 64) conditions An expression is required.
Thus, as the number of cases is increased, the number of gates and the circuit area increase, resulting in a complicated circuit configuration, and the timing becomes stricter. Therefore, the improvement in the operation speed of the circuit cannot be expected. was there.

Here, there is Patent Document 1 as a prior art document relevant to the present invention.
Patent Document 1 discloses a digital PWM signal generation circuit that generates a PWM signal by sequentially setting the register bits from the lower level and the upper level, and from the center and the middle, to the H level using a counter. ing.

JP 2004-345280 A

  An object of the present invention is to provide a pulse generation circuit in which the operation speed is improved by reducing the number of gates and reducing the circuit area.

  In order to solve the above-described problem, the present invention receives a rising timing signal specifying a rising timing and a falling timing signal specifying a falling timing within each period of the clock signal, and receives one of the clock signals. An unadjusted pulse data generation circuit for generating unadjusted pulse data having a logical value of each unit time period from 0 to n−1 obtained by dividing the period by n (n is an integer of 2 or more), and the unit time The delay time signal DELAY in the range from 0 to n−1 that designates the delay time in units is received, and within each period of the clock signal, the period from 0 to DELAY-1 is within the immediately preceding period. The logical value of the non-adjusted pulse data in the period from n-DELAY to n−1 is the current period. Wherein providing a pulse generating circuit, characterized in that a delay pulse data generating circuit for generating a delay pulse data having a logical value of from 0 unregulated pulse data to (n-1) -DELAY of.

  According to the present invention, PWM pulses can be generated with a circuit having a smaller number of gates by combining unadjusted pulse data and unadjusted pulse data in the immediately preceding cycle (hereinafter referred to as immediately preceding unadjusted pulse data). it can. As a result, the circuit area can be reduced, and as a result, PWM pulses can be generated at high speed.

It is a block diagram which shows an example of the pulse generation circuit which concerns on this invention. It is explanatory drawing which shows the non-adjustment pulse for 1 period which does not consider DELAY based on this invention. It is a circuit diagram which shows an example for 1 bit of a delay pulse data generation circuit. It is a circuit diagram which shows another example for 1 bit of a delay pulse data generation circuit. It is explanatory drawing by the timing chart which shows an example of the relationship of each pulse data based on this invention. It is explanatory drawing showing the example of a division | segmentation of a PWM pulse. (A)-(d) is explanatory drawing which shows the case division of the conventional PWM pulse generation circuit. It is a block diagram which shows an example of the conventional PWM pulse generation circuit.

  A pulse generation circuit according to the present invention will be described in detail below based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a pulse generation circuit of the present invention.
The pulse generation circuit 10 shown in FIG. 1 includes an unadjusted pulse data generation circuit 12, a previous unadjusted pulse data generation circuit 14, and a delayed pulse data generation circuit 16.
The pulse generation circuit 10 receives a 6-bit rising timing signal ST [5: 0], a falling timing signal EN [5: 0], and a delay time signal DELAY [5, which are externally input in synchronization with a clock signal. : 0], data corresponding to the high level PWM pulse from the rising position specified by the signal ST [5: 0] to the falling position specified by the signal EN [5: 0] is generated, This is delayed for a predetermined time specified by the signal DELAY [5: 0], and the delayed pulse data PWMout [63: 0] is output.

  Here, the signal ST [5: 0] and the signal EN [5: 0] specify the rising timing and falling timing within each period of the clock signal in the generated PWM pulse, respectively. It is a signal in the range up to. Further, the delay time signal DELAY [5: 0] designates a delay time in units of 1 / 64th unit time of one cycle of the clock signal obtained by dividing 64 within one cycle of the clock signal. It is a signal of the range.

  That is, in the pulse generation circuit 10, based on the 6-bit signals ST [5: 0], EN [5: 0], and DELAY, the PWM pulse delay pulse data PWMout in which one cycle is represented by 64-bit bit data. [63: 0] is generated.

  The non-adjustment pulse data generation circuit 12 receives the signals ST [5: 0] and EN [5: 0] and based on the values of these signals ST [5: 0] and EN [5: 0] ( 64 bits corresponding to each unit time period from 0 to 63 divided into 64 within one cycle of the clock signal, that is, one cycle of the generated PWM pulse) The 64-bit unadjusted pulse data [63: 0] having each logical value (H or L) of the data is generated.

  In the non-adjustment pulse data generation circuit 12, the non-adjustment pulse data in which the delay time designated by the signal DELAY [5: 0] is not considered based only on the signals ST [5: 0] and EN [5: 0]. [63: 0] is generated. Thereby, as shown in FIG. 2, since the signals ST [5: 0] and EN [5: 0] are both included in the current period, it is not necessary to consider the previous period and the next period, and only the current period is considered. I will do better. As a result, the number of conditional expressions that have been a problem in the prior art can be greatly reduced.

  The immediately preceding unadjusted pulse data generation circuit 14 is configured by a flip-flop. Unadjusted pulse data [63: 0] output from the unadjusted pulse data generation circuit 12 is input to the immediately preceding unadjusted pulse data generation circuit 14. The immediately preceding unadjusted pulse data generation circuit 14 latches the unadjusted pulse data [63: 0] output from the unadjusted pulse data generation circuit 12 in a flip-flop in synchronization with the clock signal, and this is latched by the immediately preceding unadjusted pulse data. Output as data [63: 0].

The delayed pulse data generation circuit 16 includes unadjusted pulse data [63: 0] output from the unadjusted pulse data generation circuit 12 and previous unadjusted pulse data [63] output from the previous unadjusted pulse data generation circuit 14. : 0] and the signal DELAY [5: 0].
If the value of the signal DELAY [5: 0] is DELAY, the delay pulse data generation circuit 16 has a period from 0 to DELAY-1 within the period of each clock signal, and the immediately preceding unadjusted pulse data [63: 0]. ] In the period from 64-DELAY to 63, and the period from DELAY to 63 is a delay having a logic value from 0 to 63-DELAY of unadjusted pulse data [63: 0] in the current cycle. Pulse data PWMout [63: 0] is generated.

Here, FIG. 3 shows a generation circuit of the delayed pulse data PWMout [31] among the delayed pulse data generation circuit 16 that generates the delayed pulse data PWMout [63: 0].
The PWMout [31] generation circuit is configured by connecting six-stage multiplexers in a tree shape. The first-stage multiplexer receives respective bits of the immediately preceding unadjusted pulse data [63: 0] and unadjusted pulse data [63: 0] corresponding to the logical value of PWMout [31], which are determined according to DELAY. Is done. Each bit of the signal DELAY [5: 0] is input as a selection signal for the first to sixth stages of multiplexers.

  For example, when DELAY = 3, since the signal DELAY [5: 0] = ‘000001’ (binary number), unadjusted pulse data [28] is output as PWMout [31]. When DELAY = 60, since the signal DELAY [5: 0] = “111100” (binary number), the immediately preceding unadjusted pulse data [35] is output as PWMout [31].

  FIG. 4 shows a circuit for obtaining delayed pulse data PWMout [63] as another example. The operation of the circuit is the same as that for obtaining the delayed pulse data PWMout [31], but the unadjusted pulse data [63: 0] is input to each multiplexer in the first stage.

Next, the operation of the pulse generation circuit according to this embodiment will be described.
First, a signal ST [5: 0] indicating the rising position of the pulse and a signal EN [5: 0] indicating the falling position of the pulse are input to the unadjusted pulse data generation circuit 12.
The non-adjustment pulse data generation circuit 12 is generated within one cycle of the clock signal, that is, based on the values of these signals ST [5: 0] and EN [5: 0] (for example, the values are decoded). Unadjusted pulse data [63] having each logical value (H or L) of 64-bit bit data corresponding to each unit time period from 0 to 63 obtained by dividing 64 within one cycle of the PWM pulse. : 0] is generated and output.

  The unadjusted pulse data [63: 0] output from the unadjusted pulse data generation circuit 12 is input to the immediately previous unadjusted pulse data generation circuit 14. In the immediately preceding unadjusted pulse data generation circuit 14, the unadjusted pulse data [63: 0] output from the unadjusted pulse data generation circuit 12 is latched by a flip-flop in synchronization with the clock signal, and immediately before one cycle. It is output as unadjusted pulse data [63: 0]. That is, the immediately preceding unadjusted pulse data [63: 0] is output with a delay of one cycle from the unadjusted pulse data [63: 0].

  The delayed pulse data generation circuit 16 includes unadjusted pulse data [63: 0] output from the unadjusted pulse data generation circuit 12 and previous unadjusted pulse data [63] output from the previous unadjusted pulse data generation circuit 14. : 0] and the signal DELAY [5: 0].

  In the delay pulse data generation circuit 16, assuming that the value of the signal DELAY is DELAY, when DELAY> = 1, the period from 0 to DELAY−1 is the last unadjusted pulse data [ The logical value of the period from 64-DELAY to 63 of 63: 0] is the logical value of 0 to 63-DELAY of the non-adjustment pulse data [63: 0] in the current cycle during the period from DELAY to 63. The delayed pulse data PWMout [63: 0] having the following is generated and output by the following equation (6). When DELAY = 0, it is generated and output by the following equation (7).

PWMout [DELAY-1: 0] = Previous unadjusted pulse data [63: 64-DELAY]
PWMout [63: DELAY] = Unadjusted pulse data [63-DELAY: 0]
That is,
PWMout [63: 0] = {Unadjusted pulse data [63-DELAY: 0],
Previously unadjusted pulse data [63: 64-DELAY]} (DELAY> = 1) (6)
PWMout [63: 0] = unadjusted pulse data [63: 0] (DELAY = 0) (7)

  That is, in the pulse generation circuit 10, the unadjusted pulse data [63: 0] generated based on the signals ST and EN in the current cycle and the previous unadjusted data obtained by delaying this by one cycle of the clock signal. The pulse data [63: 0], in other words, the immediately preceding unadjusted pulse data [63: 0] generated based on the signals Pre_ST and Pre_EN in the previous period is appropriately set according to the value of the signal DELAY [5: 0]. By combining these, delayed pulse data PWMout [63: 0] is generated.

  In the present embodiment, the value of the signal DELAY is a value from 0 to 63 with the unit time as a unit. Therefore, the time that the PWM pulse is delayed according to the signal DELAY [5: 0] It is shorter than the time for one cycle. Therefore, as described above, the unadjusted pulse data [63: 0] and the immediately preceding unadjusted pulse data [63: 0] are appropriately combined in accordance with the value of the signal DELAY [5: 0], so that FIG. The same delayed pulse data PWMout [63: 0] as the conventional pulse generation circuit shown can be generated.

  In the pulse generation circuit 10, the timing of the signals ST [5: 0] and EN [5: 0] in the current cycle is delayed according to the value of the signal DELAY [5: 0] as in the conventional pulse generation circuit. Signals ADD_ST [6: 0], ADD_EN [6: 0], and signals ADD_Pre_ST [6: 0], ADD_Pre_EN [, in which the timing of the signals Pre_ST [5: 0] and Pre_EN [5: 0] in the previous cycle is delayed. 6: 0] is not obtained, and PWMout [63: 0] is not generated based on these signals. Therefore, the circuit scale can be significantly reduced, and the generation of PWMout [63: 0] can be greatly speeded up.

Here, FIG. 5 is a timing chart showing the relationship between the unadjusted pulse data, the immediately preceding unadjusted pulse data, and the delayed pulse data PWMout.
The timing chart of FIG. 5 shows the unadjusted pulse and the immediately preceding unadjusted corresponding to the unadjusted pulse data [63: 0], the immediately preceding unadjusted pulse data [63: 0], and the delayed pulse data PWMout [63: 0]. The waveform of a pulse and a delay pulse is displayed. In the figure, the vertical axis represents the logical value (H or L) of each pulse, and the horizontal axis represents the time flow of each pulse.

  In this timing chart, the waveform of each pulse is shown over a plurality of periods. When one period of each pulse is divided into 64 along the time axis direction, the left end becomes a logical value corresponding to 0 and the right end corresponds to 63 data. Further, in the figure, the period corresponding to the delay time specified by DELAY is indicated by a vertical line range, and other periods within one cycle are indicated by horizontal line ranges.

  As shown in FIG. 5, when the value of DELAY is 1 or more, it corresponds to the vertical line range of the previous unadjusted pulse data corresponding to the delay time specified by DELAY and the other period within one cycle. The delayed pulse data PWMout [63: 0] can be generated by combining the horizontal line range of the non-adjustment pulse data. When the DELAY value is 0, the non-adjustment pulse data [63: 0] may be used as the delayed pulse data PWMout [63: 0] as it is.

  Here, when the equations (6) and (7) are combined with the bit arrangement of FIG. 5, the following equations (8) and (9) are obtained.

PWMout [0:63] = {no adjustment pulse data just before [64-DELAY: 63],
Unadjusted pulse data [0: 63-DELAY]} (DELAY> = 1) (8)
PWMout [0:63] = Unadjusted pulse data [0:63] (DELAY = 0) (9)

  That is, the delay pulse data PWMout [0:63] has a bit (logical value: corresponding to the value of DELAY) of the previous unadjusted pulse data [64-DELAY: 63] when the DELAY value is 1 or more. The bits of the delayed pulse data PWMout [0: DELAY-1] are combined with the bits of the non-adjusted pulse data [0: 63-DELAY] as the bits of the delayed pulse data PWMout [DELAY: 63]. Is done.

When the pulse generation circuit 10 according to the present invention is expressed by conditional expressions, the following [5] to [7] are obtained.
[5] Case classification None [6] 64 bits are generated (N is 64 ways from 0 to 63)
Unadjusted pulse data [N] = (ST <= N &EN> = N) (10)
[7] DELAY value reflection PWMout [63: 0] = {no adjustment pulse data [63-DELAY: 0],
Previously unadjusted pulse data [63: 64-DELAY]} (DELAY> = 1) (6)
PWMout [63: 0] = unadjusted pulse data [63: 0] (DELAY = 0) (7)

As shown in the above embodiment, the pulse generation circuit 10 according to the present invention does not need to be divided into cases, and does not need to synthesize data in each case. Therefore, the conditional expression for generating the pulse data for 64 bits is the above expression (10), which may be the conditional expression of 64, and the expressions (6) and (7) that reflect the DELAY value. Even if is added, the delayed pulse data PWMout can be generated with fewer conditional expressions than in the prior art.
Further, by greatly reducing the conditional expressions, the circuit complexity can be suppressed, the number of gates can be reduced, the circuit area can be reduced, and the operation speed of the circuit can be improved.

The number of bits m (m is an integer of 1 or more) of the signals ST, EN, DELAY, that is, the number of divisions n (= 2 ^m ) (n is an integer of 2 or more) within one cycle of the clock signal is not limited. However, it can be changed as needed.
Further, the specific configurations of the non-adjustment pulse data generation circuit, the immediately previous non-adjustment pulse data generation circuit, and the delay pulse data generation circuit are not limited in any way, and it is possible to employ various configurations of circuits that realize the same function. it can.

  Although the pulse generation circuit of the present invention has been described in detail above, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the scope of the present invention. .

DESCRIPTION OF SYMBOLS 10 Pulse generation circuit 12 Unadjusted pulse data generation circuit 14 Unadjusted pulse data (immediately previous unadjusted pulse data) generation circuit in the immediately preceding period 16 Delay pulse data generation circuit

Claims (1)

Receiving a rising timing signal for specifying a rising timing within each cycle of the clock signal and a falling timing signal for specifying a falling timing, n is received within one cycle of the clock signal (n is an integer of 2 or more). An unadjusted pulse data generation circuit for generating unadjusted pulse data having a logical value of each divided unit time period from 0 to n−1;
The delay time signal DELAY in the range from 0 to n−1 that specifies the delay time in units of the unit time is received, and the period from 0 to DELAY−1 is the immediately preceding period within each period of the clock signal. The logical value of a period from n-DELAY to n-1 of the non-adjusted pulse data in the period is represented by 0 to (n-1) of the unadjusted pulse data in the current period in the period from DELAY to n-1. And a delay pulse data generation circuit for generating delay pulse data having a logical value up to -DELAY.

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