JP2011034371A - Logic verification apparatus and logic verification method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic verification apparatus and a logic verification method capable of accelerating an execution speed of logic verification and outputting uncompressed original waveform data. <P>SOLUTION: The logic verification apparatus for performing logic verification of a plurality of circuit blocks to be driven by a plurality of clock signals having respectively different frequencies by switching the clock signals includes: an operation control means for controlling the circuit blocks so that the second circuit block is driven by a first clock signal of the first circuit block during the period of no operation of the first circuit block and outputting switching information including the period and a frequency division ratio of the first clock signal and a second clock signal of the second circuit block; and output means for outputting waveform data including the switching information and a compressed waveform data obtained by restoring the first clock signal driving the second circuit block to a frequency of the second clock signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a logic verification device and a logic verification method for logically verifying a plurality of circuit blocks operating with a plurality of clock signals having different frequencies by switching the clock signals.

  A system LSI (Large Scale Integration) in which a microprocessor, a memory, and the like are combined is verified using a logic verification device such as an emulator. An emulator is a device that implements logic simulation with hardware. In a general emulator, only one clock signal is supplied to the test bench. Therefore, when a verification target circuit has a plurality of clock inputs, a clock signal to be supplied to the test bench is divided in the test bench to generate a plurality of clock signals and supplied to the verification target circuit.

  For example, if the verification target circuit has a high-speed operation circuit block that operates with a high-speed clock signal and a low-speed operation circuit block that operates with a low-speed clock signal, the clock signal supplied to the test bench is supplied to the high-speed operation circuit. Is done. A clock signal generated by dividing the clock signal supplied to the test bench is supplied to the low-speed operation circuit.

  In this case, a low-speed clock signal is supplied to the low-speed operation circuit even when the high-speed operation circuit is stopped. Therefore, when performing logic verification of a circuit using a plurality of systems of clock signals, there is a problem that the time required for logic verification when the high-speed operation circuit is stopped increases.

  As a method for solving this problem, when the high-speed operation circuit is not operating, the clock signal (high-speed) given to the test bench is generated from the clock signal (low-speed) generated by dividing the clock signal supplied to the low-speed operation circuit. There is a way to switch to).

  This method is effective when it is not necessary to consider an exact circuit delay in the logic verification item and it is sufficient if verification can be performed within the clock synchronization range. This is because the verification of the clock synchronous operation does not affect the logic verification result even when the operation clock is changed.

  In this method, the verification execution time can be shortened by switching the clock signal supplied to the low-speed operation circuit to the high-speed clock signal when the high-speed operation circuit is not operating.

JP 2000-222238 A

  In the conventional technique as described above, the execution speed of logic verification can be increased. However, the waveform data indicating the logic verification result is partially compressed, and correct waveform data cannot be observed. For this reason, for example, there is a problem that it is difficult to determine whether or not the circuit to be verified has completed the target operation within a predetermined time.

  The present invention has been made in view of the above points, and provides a logic verification device and a logic verification method capable of increasing the execution speed of logic verification and outputting original uncompressed waveform data. With the goal.

  In order to solve the above-described problem, a logic verification device that performs logic verification on a plurality of circuit blocks that operate with a plurality of clock signals having different frequencies by switching the clock signals, wherein the first circuit block is not operating. The second circuit block is controlled to operate with the first clock signal of the first circuit block, and the period and the frequency division ratio between the first clock signal and the second clock signal of the second circuit block are Operation control means for outputting switching information, including the switching information, waveform data including compressed waveform data in which the first clock signal for operating the second circuit block is restored to the frequency of the second clock signal, Output means.

  Since the execution speed of logic verification can be increased and the compressed waveform data can be restored based on the switching information, the original uncompressed waveform data can be output.

It is a figure which shows the hardware structural example of a logic verification system. It is a figure explaining the logic verification apparatus and waveform display apparatus of a 1st Example. It is a figure which shows an example of the waveform data when not switching a clock signal in a 1st Example. It is a figure which shows an example of the waveform data at the time of switching a clock signal in a 1st Example. It is a figure which shows an example of the waveform data containing the decompression | restoration waveform data in a 1st Example. It is a figure explaining the logic verification apparatus and waveform display apparatus of 2nd Example. It is a figure for demonstrating operation | movement of an operation control part. It is a figure which shows an example of the waveform data when not switching a clock signal in 2nd Example. It is a figure which shows an example of the waveform data at the time of switching a clock signal in 2nd Example. It is a figure which shows an example of the waveform data containing decompression | restoration waveform data in 2nd Example. It is a figure explaining the logic verification apparatus of 3rd Example. It is a figure explaining the logic verification apparatus of 4th Example. It is a figure explaining the logic verification apparatus of 5th Example. It is a figure which shows an example of a clock switching table. It is a figure which shows an example of the waveform data at the time of switching a clock signal in 5th Example. It is a figure which shows the other example of the waveform data at the time of switching a clock signal in 5th Example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating a hardware configuration example of a logic verification system. The logic verification system 100 includes a logic verification device 200 and a waveform display device 300.

  The logic verification device 200 includes an MPU (microprocessor) 21, a memory device 22, and a verification model device 23 that are mutually connected by a bus B 1. The MPU 21 controls various processes executed by the logic verification device 200. The memory device 22 stores a program or the like that realizes processing executed by the logic verification device 200. In the verification model device 23, a verification target circuit to be described later is arranged and logic verification is performed.

  The waveform display device 300 includes a CPU (Central Processing Unit) 31, an auxiliary storage device 32, an input device 33, a display device 34, and a driver 35 that are connected to each other via a bus B 2. The CPU 31 controls various processes executed by the waveform display device 300. The auxiliary storage device 32 stores a program for realizing the processing executed by the waveform display device 300, data necessary for executing the program, and the like. The input device 33 includes a keyboard and a mouse, and is used for inputting various signals. The display device 33 includes a display device and the like, and is used to display various windows and data.

  When the recording medium 36 that records the waveform display program that is a part of the program for operating the waveform display device 300 is set in the driver 35, the waveform display program is transferred from the recording medium 36 to the auxiliary storage device 32 via the driver 35. Installed. The recording medium 36 on which the waveform display program is recorded is information such as a CD-ROM, a flexible disk, a magneto-optical disk, etc., a recording medium for recording information optically, electrically or magnetically, a ROM, a flash memory, etc. Various types of recording media, such as a semiconductor memory that electrically records data, can be used.

(First Example)
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram for explaining the logic verification device and the waveform display device of the first embodiment.

  The logic verification device 200 according to the present embodiment includes a verification model device 23. The logic verification device 200 according to the present exemplary embodiment includes a clock signal supply unit 210, a switching information acquisition unit 220, and an output unit 230. The clock signal supply unit 210 supplies the clock signal A to the verification model device 23. The switching information acquisition unit 220 acquires the switching information 290 output from the operation control unit 270. Details of the operation control unit 270 and the switching information 290 will be described later. The output unit 230 outputs the waveform data 280 as the verification result of the verification target circuit 240 arranged in the verification model device 23 and the switching information 290 acquired by the switching information acquisition unit 220 to the waveform display device 300.

  The verification model device 23 is provided with a verification target circuit 240. The verification target circuit 240 includes a circuit block 241 and a circuit block 242. Further, the verification model device 23 includes a frequency dividing circuit 250, a clock switching unit 260, and an operation control unit 270.

  The frequency dividing circuit 250 divides the clock signal A supplied from the clock signal supply unit 210 to the verification model device 23 to generate the clock signal B. The clock switching unit 260 switches the clock signal supplied to the circuit block 242 to either the clock signal A or the clock signal B. The operation control unit 270 selects a clock signal supplied to the circuit block 242 based on the operation of the circuit block 241 and controls switching of the clock signal by the clock switching unit 260. Further, the operation control unit 270 outputs switching information 290 described later to the switching information acquisition unit 220.

  In the verification model device 23 of the present embodiment, the operation clock of the circuit block 241 is the clock signal A. The operation clock of the circuit block 242 is a clock signal B.

  In this embodiment, for example, the clock signal A is a high frequency, the clock signal B is a low frequency, and the clock signal B is a signal obtained by dividing the clock signal A. Therefore, the circuit block 241 that uses the clock signal A as an operation clock is a circuit block that operates faster than the circuit block 242 that uses the clock signal B as an operation clock.

  In the verification model device 23 of this embodiment, the operation control unit 270 determines whether or not the circuit block 241 is operating. When the circuit block 241 is not operating, the verification model device 23 switches the clock signal supplied to the circuit block 242 from the clock signal B to the clock signal A by the clock switching unit 260. When the circuit block 241 resumes operation, the operation control unit 270 switches the clock signal supplied to the circuit block 242 from the clock signal A to the clock signal B.

  Further, the operation control unit 270 outputs switching information 290. The switching information 290 will be described below.

  The switching information 290 of this embodiment includes period information indicating a period during which the circuit block 242 operates with the clock signal A, block identification information for identifying the circuit block 242, and the division between the clock signal A and the clock signal B. The ratio is included. The block identification information and the frequency division ratio may be set in the verification model device 23 in advance, for example. The period information is information including the start time and end time of the operation of the circuit block 242 by the clock signal A.

  When the clock signal A is supplied to the circuit block 242 and the operation is performed, the waveform data of the verification result is compressed waveform data as compared with the case where the clock signal B is used as the operation clock. For example, when the clock signal B is a signal obtained by dividing the clock signal A by 4, the waveform data obtained as a result of verifying the circuit block 242 with the clock signal A is 4 waveform data obtained as the result of verifying the circuit block 242 with the clock signal B. The waveform data is double-compressed.

  The verification result waveform data will be described below with reference to FIGS. FIG. 3 is a diagram illustrating an example of waveform data when the clock signal is not switched in the first embodiment.

  In the example of FIG. 3, the circuit block 241 that uses the clock signal A as the operation clock is not operating, and only the circuit block 242 that uses the clock signal B as the operation clock is operating. In this case, if the operation clock of the circuit block 242 is switched from the clock signal B to the clock signal A during the period H from the time point T1 to the time point T2 when the operation of the circuit block 241 is stopped, the waveform data of the period H (hereinafter, compressed) The previous waveform data 281) can be compressed, and the logic verification can be speeded up.

  Therefore, in this embodiment, when the operation control unit 270 determines that the circuit block 241 is not operating, the clock signal supplied to the circuit block 242 by the clock switching unit 260 is switched from the clock signal B to the clock signal A.

  FIG. 4 is a diagram showing an example of waveform data when the clock signal is switched in the first embodiment. In the example of FIG. 4, the clock signal supplied to the circuit block 242 is switched to the clock signal A at the time T1 when the operation of the circuit block 241 stops. Therefore, the period H in FIG. 3 is a compressed period H1. The waveform data as the verification result of the circuit block 242 becomes compressed waveform data 282 compressed in the period H1. Therefore, the waveform data 280 output from the output unit 230 of the logic verification device 200 to the waveform display device 300 is waveform data including the compressed waveform data 282 shown in FIG.

  Returning to FIG. 2, the switching information acquisition unit 220 included in the logic verification device 200 acquires the switching information 290. The switching information 290 includes period information indicating a period during which the clock signal A is supplied to the circuit block 242 under control of the operation control unit 270, block identification information for identifying the circuit block 242, and the division of the clock signal A and the clock signal B. The ratio is included.

  The output unit 230 of the logic verification device 200 outputs the waveform data 280 indicating the verification result by the verification model device 23 and the switching information 290 acquired by the switching information acquisition unit 220 to the waveform display device 300. The waveform data 280 output from the output unit 230 includes compressed waveform data 282.

  The waveform display device 300 according to the present embodiment restores the compressed waveform data 282 included in the waveform data 280 so as to have the same time axis as the pre-compression waveform data 281. Then, the waveform display device 300 causes the display device 34 to display the restored waveform data.

  The waveform display device 300 includes a waveform data acquisition unit 310, a switching information acquisition unit 320, a restoration unit 330, and a display control unit 340. The waveform data acquisition unit 310 acquires the waveform data 280 output from the logic verification device 200. The switching information acquisition unit 320 acquires the switching information 290 output from the logic verification device 200.

  The restoration unit 330 identifies waveform data that includes the compressed waveform data 282 in the waveform data 280 from the acquired waveform data 280 and the block identification information included in the switching information 290. In this case, waveform data as a result of logic verification of the circuit block 242 is specified. The restoration unit 330 specifies the compressed waveform data 282 included in the specified waveform data based on the period information included in the switching information 290. Then, the compressed waveform data 282 is restored so as to have the same time axis as the pre-compressed waveform data 281 by using the frequency division ratio included in the switching information 290. The restored waveform data is referred to as restored waveform data 283 (see FIG. 5).

  For example, when the clock signal B is a signal obtained by dividing the clock signal A by ¼, the restoration unit 330 can restore the compressed waveform data 282 to the same time axis as the pre-compression waveform data 281 by extending the compressed waveform data 282 by four times. .

  The display control unit 340 causes the display device 34 to display the waveform data 280 including the restored waveform data 283 that has been restored.

  FIG. 5 is a diagram illustrating an example of waveform data including restored waveform data in the first embodiment. As shown in FIG. 5, the compressed waveform data 282 is restored to the restored waveform data 283 by the restoration unit 330. The restored waveform data 283 is restored so as to have the same time axis as the pre-compression waveform data 281 shown in FIG.

  As described above, according to this embodiment, the waveform data once compressed is restored to the waveform data before compression and displayed, so that the execution speed of logic verification is increased and the original waveform data which is not compressed is output. be able to. Therefore, for example, it can be determined whether or not the verification target circuit 240 has completed the target operation within a predetermined time.

(Second embodiment)
A second embodiment of the present invention will be described below with reference to the drawings. FIG. 6 is a diagram for explaining the logic verification device and the waveform display device of the second embodiment. The verification target circuit 240A arranged in the verification model device 23A of the logic verification device 200A of the present embodiment has an external terminal EN. The circuit block 241A included in the verification target circuit 240A includes a control register 243, a status register 242, an OR circuit 245, a clock control unit 246, and a circuit block operation unit 247.

  The external terminal EN of this embodiment is connected to the circuit block 241A, and the input value is controlled by a test pattern (not shown). In the control register 243, one bit in the control register 243 is an ENABLE bit. In the status register 244, one bit in the status register 244 is a RUN bit, and the value of the RUN bit indicates the state of the circuit block 241A. The ENABLE bit of the control register 243 is input to one input of the OR circuit 245, and the input value of the external terminal EN is input to the other input. The value of the RUN bit of the status register 244 is a value obtained by ORing the output value of the OR circuit 245, that is, the ENABLE bit of the control register 243 and the input value of the external terminal EN.

  Based on the value of the RUN bit of the status register 246, the clock control unit 246 controls the supply of the clock signal A to the circuit block operation unit 247 that is the operation unit of the circuit block 241A. When the RUN bit of the status register 244 is 1, the clock control unit 246 of this embodiment supplies the clock signal A to the circuit block operation unit 247 to operate the circuit block 241A. When the RUN bit of the status register 244 is 0, the clock control unit 246 stops the supply of the clock signal A to the circuit block operation unit 277 and stops the operation of the circuit block 241A.

  The operation control unit 270 according to the present embodiment refers to the RUN bit of the status register 244 included in the circuit block 241A, determines whether or not the circuit block 241A is operating, and selects a clock signal to be supplied to the circuit block 242. . The operation of the operation control unit 270 of this embodiment will be described with reference to FIG. FIG. 7 is a diagram for explaining the operation of the operation control unit.

  The operation control unit 270 of this embodiment determines that the circuit block 241A is operating when the RUN bit of the status register 244 is 1. When the circuit block 241A is operating, since the clock signal A is supplied to the circuit block 241A, the operation control unit 270 selects the clock signal B as the clock signal supplied to the circuit block 242.

  The operation control unit 270 determines that the circuit block 241A is not operating when the RUN bit of the status register 244 is 0. When the circuit block 241A is not operating, the operation control unit 270 selects the clock signal A as a clock signal to be supplied to the circuit block 242. When the clock signal A is selected, the clock switching unit 260 switches the clock signal supplied to the circuit block 242 from the clock signal B to the clock signal A. At this time, the operation control unit 270 obtains information on the time when the selection of the clock signal A is started, that is, the time when the clock switching unit 260 switches from the clock signal B to the clock signal A (hereinafter, start time information).

  Next, when the RUN bit of the status register 244 changes from 0 to 1, the operation control unit 270 determines that the operation of the circuit block 241A has been resumed, and selects the clock signal B as a clock signal to be supplied to the circuit block 242. When the clock signal B is selected, the clock switching unit 260 switches the clock signal supplied to the circuit block 242 from the clock signal A to the clock signal B. At this time, the operation control unit 270 acquires information on the time when the selection of the clock signal A is completed, that is, information on the time when the clock switching unit 260 switches from the clock signal A to the clock signal B (hereinafter referred to as end time information).

  The operation control unit 270 uses the start time information and the end time information as period information. The operation control unit 270 outputs the period information, the block identification information for identifying the circuit block 242 and the frequency division ratio to the switching information acquisition unit 220 as switching information.

  Therefore, the switching information acquisition unit 220 according to the present embodiment can obtain period information indicating a period in which the clock signal A is supplied to the circuit block 242, that is, a period in which the operation of the circuit block 241 A is stopped.

  The output unit 230 outputs the switching information 290 acquired by the switching information acquisition unit 220 and the waveform data 280 that is the result of logic verification to the waveform display device 300. The waveform display device 300 of this embodiment is as described in the first embodiment.

  Hereinafter, waveform data as a result of logic verification will be described with reference to FIGS. FIG. 8 is a diagram illustrating an example of waveform data when the clock signal is not switched in the second embodiment. In the example of FIG. 8, the circuit block 242 is operated with the clock signal B during the period T3 during which the operation of the moving circuit block 241A is stopped. In this case, the pre-compression waveform data 281A that is the waveform data of the verification result of the circuit block 242 is the same as the waveform data of the circuit block 242 when the circuit block 241A is operating.

  FIG. 9 is a diagram illustrating an example of waveform data when the clock signal is switched in the second embodiment. In the example of FIG. 9, the circuit block 242 operates with the clock signal A during a period T4 from the time T10 when the operation of the circuit block 241A stops to the time T11 when the operation of the circuit block 241A resumes. Therefore, the waveform data in the period T4 is compressed waveform data 282A that is compressed.

  From the output unit 230 of the logic verification device 200A, the waveform data 280A including the compressed waveform data 282A and the switching information 290 are output to the waveform display device 300.

  In the waveform display device 300, as described in the first embodiment, the compressed waveform data 282A included in the waveform data 280A is identified from the waveform data 280A and the switching information 290, and the waveform is the same as that of the waveform data 281A before compression. Restore.

  FIG. 10 is a diagram illustrating an example of waveform data including restored waveform data in the second embodiment. The waveform data 280A shown in FIG. 10 includes restored waveform data 283A obtained by restoring the compressed waveform data 282A. In the example of FIG. 10, the period T4 shown in FIG. 9 is restored to the same period as the period T3 shown in FIG. 8, and the compressed waveform data 282A becomes the same waveform data as the pre-compression waveform data 281A. Has been restored.

  As described above, according to this embodiment, the waveform data once compressed is restored to the waveform data before compression and displayed, so that the execution speed of logic verification is increased and the original waveform data which is not compressed is output. be able to. Therefore, for example, it can be determined whether or not the verification target circuit 240 has completed the target operation within a predetermined time.

(Third embodiment)
A third embodiment of the present invention will be described below with reference to the drawings. FIG. 11 is a diagram for explaining a logic verification apparatus according to the third embodiment. The logic verification device 200B according to the present exemplary embodiment includes a restoration unit 290 that restores the waveform data 280 including the compressed waveform data 282.

  In the logic verification apparatus 200B of the present embodiment, the waveform verification apparatus 200B performs up to the restoration of the waveform data 280, thereby eliminating the need for a waveform display apparatus having a function for restoring the waveform data 280. Therefore, in this embodiment, for example, waveform data including the restored waveform data 283 can be displayed only by connecting the logic verification device 200B to a general display device or the like.

  The restoration unit 290 of the logic verification device 200B according to the present embodiment includes a waveform data acquisition unit 291 and a switching information acquisition unit 220. The waveform data acquisition unit 291 acquires waveform data as a result of verification by the verification model device 23B. The waveform data acquired by the waveform data acquisition unit 291 is waveform data before restoration, and is waveform data including the compressed waveform data 282.

  The switching information acquisition unit 220 is as described in the first embodiment and the second embodiment, and acquires switching information.

  The restoration unit 290 identifies and restores the compressed waveform data included in the waveform data based on the waveform data acquired by the waveform data acquisition unit 291 and the switching information acquired by the switching information acquisition unit 220. That is, the restoration unit 290 specifies waveform data including the compressed waveform data 282 from the block identification information included in the switching information, and specifies the compressed waveform data 282 in the waveform data specified based on the period information. Then, the compressed waveform data 282 is restored to the restored waveform data using the frequency division ratio.

  Therefore, in this embodiment, the waveform data once compressed is restored to the waveform data before compression and displayed, so that the execution speed of logic verification can be increased and the original waveform data that is not compressed can be output. Therefore, for example, it can be determined whether or not the verification target circuit 240 has completed the target operation within a predetermined time. Further, in this embodiment, since the waveform data restored from the logic verification device 200B can be output, a waveform display device having a waveform data restoration function becomes unnecessary.

(Fourth embodiment)
A fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 12 is a diagram for explaining a logic verification apparatus according to the fourth embodiment. The logic verification device 200C of this embodiment is an example in which a verification model device 23A is arranged in the logic verification device 200C of the third embodiment. The operation control unit 270 of the verification model device 23A of the logic verification device 200C of this embodiment refers to the RUN bit of the status register 244 of the circuit block 241A and selects the operation clock signal of the circuit block 242. In addition, the logic verification device 200 </ b> C of this embodiment includes a restoration unit 290 that restores the compressed waveform data 282.

  Therefore, in this embodiment, the same effects as in the third embodiment can be obtained.

(Fifth embodiment)
A fifth embodiment of the present invention will be described below with reference to the drawings. In the fifth embodiment of the present invention, a case where there are three circuit blocks included in the circuit to be verified and three clock signals are used will be described. FIG. 13 is a diagram for explaining a logic verification apparatus according to the fifth embodiment.

  The logic verification device 200D of this embodiment includes a verification model device 23B. Further, the logic verification device 200D of this embodiment includes a clock supply unit 210, a switching information acquisition unit 220, and an output unit 230.

  A verification target circuit 240B is arranged in the verification model device 23B of the present embodiment, and logic verification is performed. The verification target circuit 240B of this embodiment includes circuit blocks 241, 242, and 249.

  The verification model device 23B according to the present embodiment includes frequency dividing circuits 250, 251, and 252, clock switching units 260 and 261, and operation control units 270 and 271. The frequency dividing circuit 250 divides the clock signal A supplied from the clock supply unit 210 to the verification model device 23B to generate the clock signal B. The frequency dividing circuit 251 divides the clock signal A to generate the clock signal C, and the frequency dividing circuit 252 divides the clock signal A to generate the clock signal D.

  The clock switching unit 260 switches between the clock signal A and the clock signal B. The clock switching unit 251 switches between the clock signal A, the clock signal C, and the clock signal D.

  The operation control unit 270 selects a clock signal supplied to the circuit block 242 based on the operation of the circuit block 241 and controls the clock switching unit 260 to switch the clock signal. The circuit block 241 of this embodiment has a status register (not shown), and the value of the RUN-1 bit of the status register is 1 when the circuit block 241 is operating. When the circuit block 241 is not operating, the value of the RUN-1 bit of the status register is 0. The operation control unit 270 according to the present embodiment refers to the value of the status register of the circuit block 241 to determine whether or not the circuit block 241 is operating, and selects a clock signal supplied to the circuit block 242.

  The operation control unit 271 selects a clock signal supplied to the circuit block 249 based on the operation of the circuit block 241 and the operation of the circuit block 242, and controls the clock switching unit 261 to switch the clock signal. The circuit block 242 of this embodiment has a status register (not shown). When the circuit block 242 is operating, the value of the RUN-2 bit of the status register is 1. When the circuit block 242 is not operating, the value of the RUN-2 bit of the status register is 0. The operation control unit 271 of this embodiment refers to the value of the status register of the circuit block 242 to determine whether the circuit block 242 is operating and selects a clock signal supplied to the circuit block 249.

  In this embodiment, the operation clock of the circuit block 241 is the clock signal A, the operation clock of the circuit block 242 is the clock signal B, and the operation clock of the circuit block 249 is the clock signal C. In this embodiment, the frequency of the clock signal C is smaller than the frequency of the clock signal B.

  Therefore, in this embodiment, it can be seen that the circuit block 241 operates at the highest speed and the circuit block 249 operates at the lowest speed.

  In this embodiment, a clock signal supplied to each circuit block is selected based on the operation of the circuit block 241 and the operation of the circuit block 242, and the clock signal is switched under the control of the clock switching units 260 and 261.

  The logic verification device 200D of the present embodiment includes a clock switching table 40 that associates the operation of the circuit block 241, the operation of the circuit block 242, and the selected clock signal. The operation control units 270 and 271 control the clock switching units 260 and 261 with reference to the clock switching table 40. The clock switching table 40 is stored in, for example, the memory device 22 of the logic verification device 200D.

  FIG. 14 is a diagram illustrating an example of the clock switching table. According to the clock switching table 40 of this embodiment, when the circuit blocks 241 and 242 are operating, the clock switching unit 260 uses the clock signal B as the clock signal supplied to the circuit block 242. The clock switching unit 261 uses the clock signal C as a clock signal supplied to the circuit block 249.

  When the circuit block 241 is operating and the circuit block 242 is not operating, the clock signal A is supplied to the circuit block 241 and the clock signal C is supplied to the circuit block 249.

  When the operation of the circuit block 241 is stopped and the circuit block 242 is operating, the clock switching unit 260 switches the clock signal supplied to the circuit block 242 from the clock signal B to the clock signal A. The clock switching unit 261 switches the clock signal supplied to the circuit block 249 from the clock signal C to the clock signal D.

  Here, the clock signal D will be described.

  In this embodiment, when the clock signal of the circuit block 242 is switched, it is necessary to keep the ratio between the operation clock of the circuit block 242 and the operation clock of the circuit block 249 constant. For example, when the clock signal B is a signal obtained by dividing the clock signal A by 4, and the clock signal C is a signal obtained by dividing the clock signal A by 8, the ratio of the clock signal B to the clock signal C is 1: 2. .

  That is, when the operation clock of the circuit block 242 is switched from the clock signal B to the clock signal A, the ratio of the clock signal A and the operation clock signal of the circuit block 249 needs to be 1: 2. The clock signal D of this embodiment is the ratio of the clock signal supplied to the circuit block 242 and the clock signal supplied to the circuit block 249 when the clock signal supplied to the circuit block 242 is switched to the clock signal A. Is a signal set to be the same as before switching.

  Therefore, as shown in FIG. 14, when the operation of the circuit block 241 is stopped and the circuit block 242 is operating, the clock signal B is supplied to the circuit block 242 and the clock signal D is supplied to the circuit block 249. Supplied.

  When the operations of both the circuit block 241 and the circuit block 242 are stopped, the clock switching unit 261 switches the operation clock of the circuit block 249 to the clock signal A.

  FIG. 15 is a diagram showing an example of waveform data when the clock signal is switched in the fifth embodiment.

  In the example illustrated in FIG. 15, the operation of the circuit block 241 is stopped in a period T5 from time T21 to time T22.

  Therefore, the operation control unit 270 controls the clock switching unit 260 with reference to the clock switching table 40, and switches the operation clock of the circuit block 242 from the clock signal B to the clock signal A during the period T5. The operation control unit 271 controls the clock switching unit 261 with reference to the clock switching table 40, and switches the operation clock of the circuit block 249 from the clock signal C to the clock signal D during the period T5.

  The waveform data in the period T5 is compressed compressed waveform data 232B. Further, the logic verification device 200D acquires the switching information 290 including the period information having the time T21 and the time T22 as the start time information and the end time information of the period T5 by the switching information acquisition unit 220 and passes the switching information 290 to the output unit 230. The output unit 230 outputs the waveform data 280B including the compressed waveform data 282B, the switching information 290, and the identification information of the circuit block to the waveform display device 300 having a compressed waveform data restoration function.

  In the waveform display device 300, it is possible to display wave example data including decompressed waveform data obtained by restoring compressed waveform data.

  FIG. 16 is a diagram showing another example of waveform data when the clock signal is switched in the fifth embodiment.

  In the example illustrated in FIG. 16, the operation of the circuit block 241 and the circuit block 242 is stopped in a period T6 from time T31 to time T32.

  Therefore, the operation control unit 271 controls the clock switching unit 261 with reference to the clock switching table 40, and switches the operation clock of the circuit block 249 from the clock signal C to the clock signal A during the period T6.

  Therefore, the waveform data in the period T6 becomes compressed compressed waveform data 282C. The logic verification device 200D of the present embodiment outputs the waveform data 280C including the compressed waveform data 282C from the output unit 230 to the waveform display device 300, and includes the restored waveform data obtained by restoring the compressed waveform data 282C in the waveform display device 300. Display waveform data.

  Therefore, according to the present embodiment, since the waveform data once compressed is restored to the waveform data before compression and displayed, the execution speed of logic verification can be increased, and the original waveform data that is not compressed can be output. it can. Therefore, for example, it can be determined whether the verification target circuit 240B has completed the target operation within a predetermined time.

The present invention may have the following configurations as described below.
(Appendix 1)
A logic verification device that performs logic verification on a plurality of circuit blocks that operate with a plurality of clock signals having different frequencies by switching the clock signals,
The second circuit block is controlled to operate with the first clock signal of the first circuit block during a period when the first circuit block is not operating, and the period, the first clock signal, and the second circuit block Operation control means for outputting switching information including a frequency division ratio with respect to two clock signals;
And output means for outputting the switching information and waveform data including compressed waveform data in which the first clock signal for operating the second circuit block is restored to the frequency of the second clock signal. A logic verification device.
(Appendix 2)
Switching information acquisition means for acquiring the switching information;
Waveform data acquisition means for acquiring the waveform data;
Restoring means for restoring the compressed waveform data in the waveform data based on the period included in the switching information to restored waveform data that is waveform data of the frequency of the previous second clock signal using the division ratio;
2. The logic verification apparatus according to claim 1, wherein a waveform display device having display means for displaying the waveform data including the restored waveform data is connected.
(Appendix 3)
The first circuit block has a register to which a value indicating whether or not the first circuit block is operating is written;
The operation control means includes
The logic verification device according to appendix 1 or 2, characterized in that it is determined that the first circuit block is not operating with reference to a value written in the register.
(Appendix 4)
The logic verification device according to claim 3, further comprising switching means for switching the second clock signal to the first clock signal when the operation control means determines that the first circuit block is not operating. .
(Appendix 5)
The operation control means includes
Information indicating a time when it is determined that the first circuit block is not operating, and information indicating a time when the operation control means determines that the first circuit block has started to operate. The logic verification device according to appendix 3 or 4, characterized in that it is period information indicating the period included in the switching information.
(Appendix 6)
Having a third circuit block;
Based on the operation of the first circuit block and the operation of the second circuit block, the third circuit block is connected to the first clock signal, the third clock signal of the third circuit block, or a preset clock signal. 6. The logic verification device according to any one of appendices 1 to 5, further comprising third circuit block operation control means that is operated by any one of the clock signals.
(Appendix 7)
A clock switching table in which the operation of the first circuit block and the operation of the second circuit block are associated with the third clock signal;
The operation control means and the third circuit block operation control means select a clock signal for operating the second circuit block and the third circuit block with reference to the clock switching table. The logic verification device according to appendix 6.
(Appendix 8)
The third circuit block operation control means includes:
Supplementary note 6 or 7 wherein when the operation of the first circuit block is stopped and the second circuit block is operating, the third circuit block is operated by the preset clock signal. The logic verification device described.
(Appendix 9)
The ratio between the first clock signal and the preset clock signal is:
9. The logic verification device according to appendix 8, wherein a ratio of the first clock signal and the second clock signal when the first circuit block is operating is equal to the ratio.
(Appendix 10)
A logic verification device that performs logic verification on a plurality of circuit blocks that operate with a plurality of clock signals having different frequencies by switching the clock signals,
The second circuit block is controlled to operate with the clock signal of the first circuit block during a period when the first circuit block is not operating, and the second period of the period, the first clock signal, and the second circuit block is controlled. An operation control means for outputting switching information including a frequency division ratio with the clock signal;
Output means for outputting the switching information and waveform data including compressed waveform data in which the first clock signal for operating the second circuit block is restored to the frequency of the second clock signal;
Restoring means for restoring the compressed waveform data in the waveform data based on the period included in the switching information to restored waveform data that is waveform data of the frequency of the second clock signal using the division ratio; A logic verification device comprising:
(Appendix 11)
A waveform display device for displaying a plurality of circuit blocks operating with a plurality of clock signals having different frequencies, and displaying waveform data as a result of logical verification by switching the clock signals,
The second circuit block is controlled to operate with the clock signal of the first circuit block during a period when the first circuit block is not operating, and the second period of the period, the first clock signal, and the second circuit block is controlled. Operation control means for outputting switching information including a frequency division ratio with a clock signal and block identification information for identifying the second circuit block;
An output means for outputting the switching information and waveform data including compressed waveform data in which the first clock signal for operating the second circuit block is restored to the frequency of the second clock signal; Connected with
Switching information acquisition means for acquiring the switching information from the logic verification device;
Waveform data acquisition means for acquiring the waveform data from the logic verification device;
The waveform data to be restored is specified based on the block identification information included in the switching information, the compressed waveform data included in the waveform data to be restored is specified from the period included in the switching information, and the compressed waveform Restoring means for restoring the compressed waveform data to restored waveform data that is waveform data of the frequency of the second clock signal using the frequency division ratio included in the switching information;
And a display means for displaying the waveform data including the restored waveform data.
(Appendix 12)
A logic verification device that performs logic verification on a plurality of circuit blocks that operate with a plurality of clock signals having different frequencies by switching the clock signal, and a waveform display device that displays waveform data as a result of logic verification by the logic verification device. A logic verification system comprising:
The logic verification device includes:
The second circuit block is controlled to operate with the clock signal of the first circuit block during a period when the first circuit block is not operating, and the second period of the period, the first clock signal, and the second circuit block is controlled. An operation control means for outputting switching information including a frequency division ratio with a clock signal and block identification information for identifying the second circuit block;
Output means for outputting the switching information and waveform data including compressed waveform data in which the first clock signal that operates the second circuit block is restored to the frequency of the second clock signal;
The waveform display device
Switching information acquisition means for acquiring the switching information;
Waveform data acquisition means for acquiring the waveform data;
The waveform data to be restored is specified based on the block identification information included in the switching information, the compressed waveform data included in the waveform data to be restored is specified from the period included in the switching information, and the compressed waveform Restoring means for restoring the compressed waveform data to restored waveform data that is waveform data of the frequency of the second clock signal using the frequency division ratio included in the switching information;
And a display unit for displaying the waveform data including the restored waveform data.
(Appendix 13)
A logic verification device that performs logic verification on a plurality of circuit blocks that operate with a plurality of clock signals having different frequencies by switching the clock signal, and a waveform display device that displays waveform data as a result of logic verification by the logic verification device. A logic verification method using a logic verification system comprising:
The logic verification device controls the second circuit block to operate with the clock signal of the first circuit block during a period when the first circuit block is not operating, the period, the first clock signal, and the second An operation control procedure for outputting switching information including a frequency division ratio of the circuit block to the second clock signal and block identification information for identifying the second circuit block;
An output procedure for outputting the switching information and waveform data including compressed waveform data in which the first clock signal for operating the second circuit block is restored to the frequency of the second clock signal;
A switching information acquisition procedure for acquiring the switching information by the waveform display device;
A waveform data acquisition procedure for acquiring the waveform data;
The waveform data to be restored is specified based on the block identification information included in the switching information, the compressed waveform data included in the waveform data to be restored is specified from the period included in the switching information, and the compressed waveform A restoration procedure for restoring the compressed waveform data to restored waveform data to be waveform data of the frequency of the second clock signal using the frequency division ratio included in the switching information;
And a display procedure for displaying the waveform data including the restored waveform data.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

DESCRIPTION OF SYMBOLS 100 Logic verification system 200, 200A, 200B, 200C, 200D Logic verification apparatus 210 Clock supply part 220 Period information acquisition part 230 Output part 240, 240A, 240B Verification object circuit 250, 251, 252 Frequency division circuit 260, 261 Clock switching part 270, 271 Operation control unit 300 Waveform display device 310 Waveform data acquisition unit 320 Period information acquisition unit 330 Decoding unit

Claims (5)

A logic verification device that performs logic verification on a plurality of circuit blocks that operate with a plurality of clock signals having different frequencies by switching the clock signals,
The second circuit block is controlled to operate with the first clock signal of the first circuit block during a period when the first circuit block is not operating, and the period, the first clock signal, and the second circuit block Operation control means for outputting switching information including a frequency division ratio with respect to two clock signals;
And output means for outputting the switching information and waveform data including compressed waveform data in which the first clock signal for operating the second circuit block is restored to the frequency of the second clock signal. A logic verification device. Switching information acquisition means for acquiring the switching information;
Waveform data acquisition means for acquiring the waveform data;
Restoring means for restoring the compressed waveform data in the waveform data based on the period included in the switching information to restored waveform data that is waveform data of the frequency of the second clock signal using the division ratio;
The logic verification apparatus according to claim 1, further comprising: a waveform display device having display means for displaying the waveform data including the restored waveform data. Having a third circuit block;
Based on the operation of the first circuit block and the operation of the second circuit block, the third circuit block is connected to the first clock signal, the third clock signal of the third circuit block, or a preset clock signal. 3. The logic verification apparatus according to claim 1, further comprising a third circuit block operation control unit that is operated by any one of the clock signals. A clock switching table in which the operation of the first circuit block and the operation of the second circuit block are associated with the third clock signal;
The operation control means and the third circuit block operation control means select a clock signal for operating the second circuit block and the third circuit block with reference to the clock switching table. The logic verification device according to claim 3. A logic verification device that performs logic verification on a plurality of circuit blocks that operate with a plurality of clock signals having different frequencies by switching the clock signal, and a waveform display device that displays waveform data as a result of logic verification by the logic verification device. A logic verification method using a logic verification system comprising:
The logic verification device controls the second circuit block to operate with the clock signal of the first circuit block during a period when the first circuit block is not operating, the period, the first clock signal, and the second An operation control procedure for outputting switching information including a frequency division ratio of the circuit block to the second clock signal and block identification information for identifying the second circuit block;
An output procedure for outputting the switching information and waveform data including compressed waveform data in which the first clock signal for operating the second circuit block is restored to the frequency of the second clock signal;
A switching information acquisition procedure for acquiring the switching information by the waveform display device;
A waveform data acquisition procedure for acquiring the waveform data;
The waveform data to be restored is specified based on the block identification information included in the switching information, the compressed waveform data included in the waveform data to be restored is specified from the period included in the switching information, and the compressed waveform A restoration procedure for restoring the compressed waveform data to restored waveform data to be waveform data of the frequency of the second clock signal using the frequency division ratio included in the switching information;
And a display procedure for displaying the waveform data including the restored waveform data.

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