JP2011034109A - Luminescence device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a luminescence device capable of stable display. <P>SOLUTION: The luminescence device 10 includes a plurality of pixels 30 arranged in a row direction and a column direction. Each pixel 30 includes a luminescence driving transistor, a pixel electrode, a luminescence layer formed above the pixel electrode, and an opposing electrode formed above the luminescence layer. Current supply lines La connect the pixels 30 in the row direction and are arranged to extend in the same direction. Adjoining current supply lines La are electrically connected to each other by a drain electrode of the luminescence driving transistor of the pixel 30 positioned between the current supply lines La. Thus, adjoining current supply lines La are made to be at the same potential. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a light emitting device using an organic EL (electroluminescence) element.

  In recent years, as a next-generation display device following a liquid crystal display (LCD), a light-emitting element type display panel in which self-light-emitting elements such as organic electroluminescence elements (hereinafter abbreviated as “organic EL elements”) are two-dimensionally arranged. Research and development for full-scale practical application and dissemination of display devices are actively underway.

  The organic EL element includes an anode electrode, a cathode electrode, and an electron injection layer, a light emitting layer, a hole injection layer, and the like formed between these electrodes. In the organic EL element, light is emitted by energy generated by recombination of holes supplied from the hole injection layer and electrons supplied from the electron injection layer in the light emitting layer. Such an organic EL element is used as a display device as disclosed in Patent Document 1, and is driven by, for example, a TFT (Thin Film Transistor) provided in each pixel.

JP 2001-195012 A

  By the way, in such a display device, a plurality of pixels including an organic EL element are generally arranged in a matrix in a row direction and a column direction. For example, a TFT in a pixel for each row is selected by a selection scanning line. In this case, the plurality of pixels arranged in the same row are connected to a voltage source that supplies current to each organic EL element via one current supply line (feed line). For this reason, when a plurality of pixels emit light at the same time, a current flows simultaneously from a single current supply line to a plurality of pixels in the same row.

  In an active matrix display device with voltage gradation designation or current gradation designation drive, when writing a display signal defining the light emission amount of an organic EL element to an element that drives each pixel, each pixel is in accordance with the display signal. Since writing is performed with current flowing, the potential of the current supply line is likely to be displaced from the reference value when the sum of the write currents of the pixels arranged in the same row is large or when the resistance of the current supply line is not sufficiently low. There's a problem. As a result, the potential varies depending on the length of the current supply line between the voltage source and each pixel, that is, the position of each pixel, the voltage written to the capacitor changes, and a desired luminance display cannot be obtained. There is a problem. This problem is more prominent as the display device has a larger area. In particular, in an image that is modulated like a moving image, the total amount of writing to a plurality of pixels of each current supply line varies greatly from frame to frame, and therefore unstable display tends to occur.

  For this reason, there is a demand for a light emitting device capable of stable display.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a light-emitting device capable of stable display.

In a light emitting device including a light emitting element having a light emitting layer between a pixel electrode and a counter electrode,
A first select transistor having a gate electrode connected to the gate line;
A second selection transistor having a gate electrode connected to the gate line and a source electrode connected to the data line;
A light emission driving transistor having a drain electrode connected to the drain electrode of the first selection transistor and a source electrode connected to the drain electrode of the second selection transistor and the pixel electrode;
A capacitor connected to the gate electrode of the light emission drive transistor and the source electrode of the light emission drive transistor;
Have
The gate electrode of the light emission driving transistor and the source electrode of the first selection transistor are separated from each other and connected to each other through a capacitor electrode of the capacitor.

  The pixel electrode and the capacitor electrode may be transparent.

  The capacitor electrode of the capacitor may be disposed below the pixel electrode through an insulating film.

  The source electrode and the capacitor electrode of the first selection transistor may be connected via a contact hole provided in the insulating film.

  According to the present invention, a light emitting device capable of stable display can be provided.

3 is a plan view illustrating a configuration example of the light emitting device according to Embodiment 1. FIG. It is an equivalent circuit diagram showing a pixel drive circuit. It is a top view of a pixel. It is the IV-IV sectional view taken on the line shown in FIG. It is the VV sectional view taken on the line shown in FIG. 2 is an equivalent circuit diagram showing a circuit configuration and a driving principle of a pixel. FIG. 4A shows a current flow during a scanning period _TSC , and FIG. 4B shows a current flow during a group emission voltage period. The flow is shown. It is a timing chart figure in which operation was shown. 5 is a diagram illustrating a method for manufacturing the light emitting device according to Embodiment 1. FIG. 5 is a diagram illustrating a method for manufacturing the light emitting device according to Embodiment 1. FIG. 5 is a diagram illustrating a method for manufacturing the light emitting device according to Embodiment 1. FIG. It is the figure which calculated the grade of the voltage drop with the case where it provided with the column direction connection wiring, and the case where it does not provide. 6 is a plan view illustrating a configuration example of a light emitting device according to Embodiment 2. FIG. 6 is a plan view of a pixel according to Embodiment 2. FIG. It is a top view of the pixel which abbreviate | omitted column direction connection wiring. It is the XV-XV sectional view taken on the line shown in FIG. It is the XVI-XVI sectional view taken on the line shown in FIG. It is a figure which shows the manufacturing method of the light-emitting device which concerns on Embodiment 2. FIG. It is a figure which shows the manufacturing method of the light-emitting device which concerns on Embodiment 2. FIG. 6 is a plan view illustrating a configuration example of a light emitting device according to Embodiment 3. FIG. 10 is a plan view of a pixel according to Embodiment 3. FIG. (A) is the XXIA-XXIA sectional view taken on the line shown in FIG. 20, (b) is the XXIB-XXIB sectional view taken on the line shown in FIG. It is a figure which shows a modification. It is a figure which shows a modification. 6 is a plan view illustrating a configuration example of a light-emitting device according to Embodiment 4. FIG. It is an equivalent circuit diagram showing a pixel drive circuit. It is a timing chart figure in which operation was shown. FIG. 10 is a plan view illustrating a configuration example of a light emitting device according to Embodiment 5. It is an equivalent circuit diagram showing a pixel drive circuit. It is a timing chart figure in which operation was shown. It is a figure which shows a modification.

  A light-emitting device and a method for manufacturing the light-emitting device according to each embodiment of the present invention will be described with reference to the drawings. In the present embodiment, an active driving type light emitting device using a bottom emission type organic EL (electroluminescence) element that emits light of an organic EL element to the outside through a substrate on which the organic EL element is formed is taken as an example. explain.

(Embodiment 1)
A light-emitting device and a method for manufacturing the light-emitting device according to Embodiment 1 will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration example of a display device as a light emitting device according to the first embodiment. FIG. 2 is an equivalent circuit of a pixel driving circuit of the light emitting device. 3 is a plan view of the pixel, FIG. 4 is a sectional view taken along line IV-IV shown in FIG. 3, and FIG. 5 is a sectional view taken along line VV shown in FIG. FIG. 6 is a diagram showing pixel writing and light emission operations, and FIG. 7 is a timing chart.

  In the light emitting device 10, as shown in FIG. 1, a set of three pixels 30 that emit red (R), green (G), and blue (B) on a pixel substrate 31 (see FIG. 4), respectively, A plurality of, for example, m arrays are repeatedly arranged in the row direction (left and right direction in FIG. 1), and a plurality of, for example, n pixels of the same color are arranged in the column direction (up and down direction in FIG. 1). .

  In this manner, m × n pixels that emit RGB colors are arranged in a matrix. Each pixel 30 includes an organic EL element (light emitting element) 21 that emits RGB light and a pixel circuit DS that actively operates the organic EL element 21. The three pixels 30 of red (R), green (G), and blue (B) may be in a delta arrangement.

  As shown in FIG. 2, the pixel circuit DS includes a first selection transistor Tr11, a second selection transistor Tr12, a light emission drive transistor Tr13, a capacitor Cs, and an organic EL element 21. The first selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 are inverted staggered n-channel TFTs (Thin Film Transistors) each including a semiconductor layer having amorphous silicon.

  In the light emitting device 10, as shown in FIGS. 1 and 2, a plurality of current supply lines (anode lines) La connected to a plurality of pixel circuits DS arranged in a predetermined row, and a voltage Vss such as a ground potential are provided. A data line Ld connected to the counter electrode (second electrode) 40, which is a cathode formed by a single electrode layer for all the pixels, and a plurality of pixel circuits DS arranged in a predetermined column. A plurality of gate lines Lg for selecting the first selection transistor Tr11 and the second selection transistor Tr12 of the plurality of pixel circuits DS arranged in a predetermined row and a plurality of current supply lines La are electrically connected to each other between the pixels. Are connected to each other in the column direction connection line Lc.

The current supply line La is connected to a power supply or current supply driver (not shown), and the power supply or current supply driver scans a plurality of groups of current supply lines La for each unit, as will be described in detail in FIG. The applied voltage is modulated to a low level L and a high level H during the period T _{SC and} during the light emission period _TEM , respectively. Further, as will be described in detail later, the current supply line La and the column-direction connecting wiring Lc are formed together with the source electrode and the drain electrode using source-drain conductive layers that become the source and drain electrodes of the transistors Tr11 to Tr13. Is done. The data line Ld is formed together with these gate electrodes by a gate conductive layer that becomes the gate electrode of each of the transistors Tr11 to Tr13, and the gate line Lg is formed using a third metal layer provided above the source-drain conductive layer. Is done. The wirings provided in these different layers and the respective electrodes of the transistor are connected via contact portions 41 to 44 provided in the insulating film 32.

  As shown in FIGS. 1 to 5, the gate electrode 11 g of the first selection transistor Tr <b> 11 is gated through the contact portion 42 that is a contact hole provided in the insulating film 32 and the gate electrode 12 g of the second selection transistor Tr <b> 12. The current supply line La is connected to the line Lg, and is connected to the drain electrode 11d by being stacked on the drain electrode 11d of the first selection transistor Tr11. Further, the source electrode 11s of the first selection transistor Tr11 is connected to the capacitor electrode Cs1 through a contact portion 43 that is a contact hole provided in the insulating film 32.

  The drain electrode 12d of the second selection transistor Tr12 is connected to the source electrode 13s of the light emission drive transistor Tr13 via the pixel electrode (first electrode) 34, and the source electrode 12s is provided on the insulating film 32. It is connected to the data line Ld through a contact portion 41 which is a contact hole. The gate electrode 12g of the second selection transistor Tr12 is connected to the gate line Lg through the contact portion.

  The drain electrode 13d of the light emission drive transistor Tr13 is connected to the current supply line La, the gate electrode 13g of the light emission drive transistor Tr13 is connected to the capacitor electrode Cs1 via the contact portion 44, and further via the capacitor electrode Cs1. Are connected to the source electrode 11s of the first selection transistor Tr11. Further, the source electrode 13s of the light emission drive transistor Tr13 is connected by partially overlapping the pixel electrode 34 in the contact portion 45.

  The capacitor Cs includes a capacitor electrode Cs1, a pixel electrode 34 that functions as the other capacitor electrode, and an insulating film 32 such as silicon nitride that is a derivative interposed between the capacitor electrode Cs1 and the pixel electrode 34.

  In the present embodiment, as shown in FIGS. 1 and 2, the column-direction connecting wiring Lc that electrically connects a plurality of current supply lines La to each other is arranged in a column of each pixel orthogonal to the arrangement direction of the current supply lines La. Formed in the direction. In the present embodiment, for example, as shown in FIG. 1, one column-direction connecting line Lc is formed in each column for every four current supply line La units. For example, in the case of the light-emitting device 10 in which m × n pixels are arranged, m column-direction connection lines Lc are formed for four current supply lines La, and the column-direction connection provided in the light-emitting device 10. The total number of wirings Lc is m × n / 4 (n is an integer multiple of 4). In this way, the current supply lines La adjacent to each other are electrically connected to each other in the unit of the predetermined number of current supply lines La by the column-direction connection wiring Lc, so that the wiring resistance is lowered as a whole. Suppresses the voltage drop caused by a single resistor. Therefore, each pixel 30 is connected to each unit from the current supply line La without largely depending on the resistance of the current supply line La between the power supply or the current supply driver (not shown), that is, the position in the light emitting device 10. A uniform voltage is applied every time, and a current corresponding to the display signal can be passed through the organic EL element 21. If the voltage drop of the current supply line La can be suppressed to a desired degree, the number of the plurality of current supply lines La connected to each other is not limited to four as long as it is an integer of 2 or more. Further, the number of column-direction connecting lines Lc provided for a plurality of current supply lines La connected to each other is arbitrary, and may be one or more, for example, every two or six. A connection wiring Lc may be provided.

  Further, in the present embodiment, as shown in FIG. 3, a conductive layer 48 is provided on the upper surface of the current supply line La of each row and the upper surface of each light emitting drive transistor Tr13 of each of the plurality of pixels 30 of the row. ing. The conductive layer 48 is formed wider on the upper surface of the current supply line La than the current supply line La. The conductive layer 48 is made of a conductive material. By providing the conductive layer 48, the resistance of the current supply line La can be further reduced, and the voltage drop can be suppressed. In particular, in this embodiment, as will be described in detail later, by forming the conductive layer 48 simultaneously with the formation of the gate line Lg using the third metal layer, the current can be increased without increasing the number of manufacturing steps. The resistance of the supply line La can be reduced.

  Next, the organic EL element 21 includes a pixel electrode 34, a hole injection layer 36, an interlayer 37, a light emitting layer 38, and a counter electrode 40. The hole injection layer 36, the interlayer 37, and the light emitting layer 38 are carrier transport layers in which electrons and holes are transported as carriers. The carrier transport layer is disposed between the interlayer insulating film 33, the insulating layer 35, and the partition wall 39 arranged in the column direction.

  On the pixel substrate 31 of each pixel, gate electrodes 11g, 12g, and 13g of a first selection transistor Tr11, a second selection transistor Tr12, and a light emission driving transistor Tr13 formed by patterning a gate conductive layer are formed. Further, one electrode Cs1 of the capacitor Cs is formed on the pixel substrate 31 of each pixel, and a gate conductive layer is patterned on the pixel substrate 31 adjacent to each pixel and extends along the column direction. A data line Ld is formed, and an insulating film 32 functioning as a dielectric of the gate insulating film and the capacitor Cs is further formed so as to cover them.

  When the organic EL element 21 is a bottom emission type that emits display light from the pixel substrate 31 side, the capacitor electrode Cs1 and the pixel electrode 34 are doped with indium oxide (ITO) doped with tin oxide or zinc oxide. In addition, a transparent electrode such as indium oxide (Indium Zinc Oxide) is formed, and the gate electrode 13g of the light emission drive transistor Tr13 is formed so as to overlap the capacitor electrode Cs1 in the contact portion 44. If the gate conductive layer contains aluminum and the capacitor electrode Cs1 is made of ITO, the cell electrode can be prevented from being induced by patterning the gate conductive layer after the capacitor electrode Cs1 is first patterned. When the organic EL element 21 is a top emission type that emits display light from the counter electrode 40 side, the counter electrode 40 is a transparent electrode such as ITO, but the capacitor electrode Cs1 does not need to be transparent. Cs1 can be formed together and integrally with the gate electrode 13g of the light emission drive transistor Tr13 by patterning the gate conductive layer. Since the gate conductive layer can be patterned at once by photolithography, if it is a top emission type, the manufacturing process of these members can be simplified.

  The insulating film 32 is formed of an insulating material such as a silicon oxide film or a silicon nitride film, and is formed on the pixel substrate 31 so as to cover the data line Ld, the gate electrodes 12g and 13g, and the capacitor electrode Cs1. The A contact portion as a contact hole is formed in the insulating film 32 to contact the gate conductive layer and the source / drain layer.

  Each of the first selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 is an n-channel thin film transistor (TFT). Each transistor is formed on the pixel substrate 31 as shown in FIG. As shown in FIG. 4, the second selection transistor Tr12 includes a semiconductor layer 121 having a-Si or microcrystalline silicon, a protective insulating film 122, a drain electrode 12d, a source electrode 12s, and an a containing n-type impurities. -Ohmic contact layers 124 and 125 having microcrystalline silicon containing Si or n-type impurities, and a gate electrode 12g. The light-emitting drive transistor Tr13 includes a semiconductor layer 131 including a-Si or microcrystalline silicon, a protective insulating film 132, a drain electrode 13d, a source electrode 13s, and a-Si or n-type impurities including n-type impurities. And ohmic contact layers 134 and 135 having microcrystalline silicon, and a gate electrode 13g. Although not shown, the first selection transistor Tr11 has the same configuration as the second selection transistor Tr12. The light emission drive transistor Tr13 is larger in size than the first selection transistor Tr11 and larger in size than the second selection transistor Tr12 in order to supply current to the organic EL element 21 to emit light. That is, in the light emission drive transistor Tr13, the channel width of the semiconductor layer 131 is longer than the channel width of the semiconductor layer of the first selection transistor Tr11 and longer than the channel width of the semiconductor layer 121 of the second selection transistor Tr12. Therefore, the source and drain electrodes 13s and 13d of the light emission drive transistor Tr13 are longer than the source and drain electrodes 11s and 11d of the first selection transistor Tr11 and longer than the source and drain electrodes 12s and 12d of the second selection transistor Tr12. . The channel widths of the source and drain electrodes 13s and 13d and the semiconductor layer 131 of the light emitting drive transistor Tr13 extend along the column direction.

  In each of the transistors Tr11, Tr12, and Tr13, the gate electrode is selected from at least one of, for example, a Mo film, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, an AlNdTi alloy film, a MoNb alloy film, and the like. It is formed from an opaque gate conductive layer. Since the first selection transistor Tr11, the second selection transistor Tr12, and the gate electrodes 11g, 12g, and 13g of the light emission drive transistor Tr13 formed by the gate conductive layer are opaque to the light emitted from the organic EL element 21, Light entering from the lower side of the selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 toward each semiconductor layer can be shielded. The drain electrode and the source electrode are each formed of a source-drain conductive layer such as aluminum-titanium (AlTi) / Cr, AlNdTi / Cr, or Cr. In addition, an ohmic contact layer is formed between the drain electrode and the source electrode and the semiconductor layer for low resistance contact.

  In the present embodiment, as shown in FIGS. 1 and 3, in the light emission drive transistor Tr13, the drain electrode 13d is connected to each column, and the drain electrode 13d also functions as a part of the column-direction connecting line Lc. . As a result, the four current supply lines La and the column-direction connecting lines Lc arranged in the row direction are connected in a mesh shape in the row direction and the column direction, thereby reducing the overall resistance and suppressing the voltage drop. it can. Since the drain electrode 13d also serves as a wiring for connecting the current supply line La in this way, there is no need to separately provide a region for forming a wiring for connecting the current supply line La on the pixel substrate. The voltage drop of the current supply line La can be suppressed without reducing the aperture ratio (the ratio of the area of the light emitting layer 38 interposed between the pixel electrode 34 and the counter electrode 40). Note that the gate line Lg running in the same direction as the current supply line La is formed using a third metal layer different from the source-drain conductive layer forming the source electrode and the drain electrode of the transistor. Since the gate line Lg extending in the row direction intersects the column-direction connecting line Lc (drain electrode 13d) via the interlayer insulating film 33 positioned below the gate line Lg, the gate line Lg is a current supply line. It is electrically insulated from La and the column direction connection wiring Lc. Further, a contact portion 49 that is a contact hole is provided in the interlayer insulating film 33 on the drain electrode 13d and the current supply line La, and the conductive layer 48 is placed on the drain electrode 13d and the current supply line La via the contact portion 49. Since they are connected to each other by being deposited, the current supply line La, the column-direction connecting line Lc, and the conductive layer 48 are connected to each other, so that the resistance of the entire line can be further lowered and the voltage drop is suppressed. Can do. Note that since the conductive layer 48 is formed using the third metal layer that is the same layer as the gate line Lg, the conductive layer 48 can be formed without increasing the number of steps for forming the conductive layer 48.

  The pixel electrode (anode electrode) 34 is made of a light-transmitting conductive material, for example, indium thin oxide (ITO) doped with tin oxide, indium oxide doped with zinc oxide (Indium Zinc Oxide), or the like. The Each pixel electrode 34 is separated from the pixel electrode 34 of another adjacent pixel 30.

  The interlayer insulating film 33 is formed of an insulating material, for example, a silicon nitride film, has a substantially rectangular opening 33 a that opens the center of each pixel electrode 34, and is adjacent to the pixel electrode 34 so as to surround the periphery of the pixel electrode 34. 34. The interlayer insulating film 33 is formed so as to cover the transistors Tr11, Tr12, Tr13, the current supply line La, and the like. As shown in FIG. 5, a gate line Lg and a conductive layer 48 are formed on the interlayer insulating film 33. Further, an insulating layer having an insulating material, for example, a silicon nitride film so as to cover the gate line Lg and the conductive layer 48 is formed. 35 is formed. The insulating layer 35 is formed with an opening 35a whose shape substantially coincides with the opening 33a, and the opening 33a and the light emitting layer 38 interposed between the pixel electrode 34 and the counter electrode 40 by the opening 35a, that is, A light emitting area of the pixel 30 is drawn. Further, a groove-like opening 39 b extending in the column direction (vertical direction in FIG. 3) is formed in the partition wall 39 across the plurality of pixels 30.

  The partition 39 is formed by curing an insulating material, for example, a photosensitive resin such as polyimide, and is formed on the interlayer insulating film 33 and the insulating layer 35. The partition 39 is formed in a stripe shape as shown in FIG. 3, and includes an opening 39b. The partition wall 39 is a liquid containing a material that becomes the light emitting layer 38 of the R (red) pixel 30 formed on the pixel electrode 34 during the manufacturing process, and a material that becomes the light emitting layer 38 of the G (green) pixel 30. And a liquid containing a material that will become the light emitting layer 38 of the B (blue) pixel 30, when applied to the pixel electrode 34, it flows out to the pixels 30 emitting different colors adjacent to each other in the row direction. The light-emitting layer 38 is prevented from being mixed. The planar shape of the partition wall 39 is not limited to this and may be a lattice shape.

  The hole injection layer 36 is formed on the pixel electrode 34 and has a function of supplying holes to the light emitting layer 38. The hole injection layer 36 includes an organic polymer material, a low molecular material, or an inorganic compound that can inject and transport holes. As an organic compound-containing liquid containing an organic polymer hole injection / transport material, for example, polyethylenedioxythiophene (PEDOT) which is a conductive polymer and polystyrene sulfonic acid (PSS) which is a dopant are dispersed in an aqueous solvent. The hole injection layer 36 is formed by applying and drying the PEDOT / PSS aqueous solution that is the dispersion. As the inorganic compound, the hole injection layer 36 is formed by continuously forming high resistance molybdenum oxide on the pixel electrode 34 and the surface of the partition wall 39.

  The interlayer 37 is formed on the hole injection layer 36. The interlayer 37 has a function of suppressing the hole injection property of the hole injection layer 36 to facilitate recombination of electrons and holes in the light emitting layer 38, in order to increase the light emission efficiency of the light emitting layer 38. It is an organic compound layer provided.

  The light emitting layer 38 is formed on the interlayer 37. The light emitting layer 38 has a function of generating light by applying a voltage between the anode electrode and the cathode electrode. The light emitting layer 38 is a known polymer light emitting material capable of emitting fluorescence or phosphorescence, for example, red (R) or green (G) containing a conjugated double bond polymer such as polyparaphenylene vinylene or polyfluorene. And a blue (B) light emitting material. In addition, these luminescent materials are suitably used in a nozzle coating method in which a solution (dispersion) dissolved (or dispersed) in an aqueous solvent or an organic solvent such as tetralin, tetramethylbenzene, mesitylene, and xylene is discharged as a continuous liquid flow. It forms by apply | coating by the inkjet method etc. which are discharged as a isolate | separated several droplet, and volatilizing a solvent.

  Further, in the case of the bottom emission type, the counter electrode (cathode electrode) 40 is provided on the light emitting layer 38 side, and a layer having a conductive material, for example, a material having a low work function such as Li, Mg, Ca, Ba, and the like. A laminated structure having a light-reflective conductive layer such as Al laminated thereon. In the case of the top emission type, it is provided on the light emitting layer 38 side and is extremely thin with a thickness of about 10 nm, for example, Li, Mg, Ca, Ba A transparent laminated structure having a light transmissive low work function layer having a low work function material such as ITO and a light transmissive conductive layer such as ITO having a thickness of about 100 nm to 200 nm. In the present embodiment, the counter electrode 40 is composed of a single electrode layer formed across a plurality of pixels 30, and for example, a common voltage Vss that is a ground potential is applied.

Next, the operation of the light emitting device 10 and the operation of the pixel 30 according to the present embodiment will be described with reference to FIGS. When the current supply lines La are connected to each other in units of d rows (d is an integer of 2 or more), the first row gate line Lg to the nth row (n = c × d is satisfied; however, c is 2 or more) Of the gate lines Lg in the scanning period T _SC of the gate lines Lg connected to each other in the d-th scanning period, that is, a group of the i-th row to (i + d−1) -th row (where i = d × k− (d−1) = d (k−1) +1, where k is a natural number and is equal to or less than n / d). The group write voltage period T _WR (= d × T _SC ) of each group is assumed. In each group of d rows, groups emission voltage period T _EM as a group writing voltage period T _WR after the light emission period is followed, then the group writing voltage period T _WR, Groups emission voltage period T _EM is repeated again.

  In accordance with the control signal group output from the control circuit, the gate driver sequentially outputs high level (on level ON) pulses from the first row gate line Lg to the n th gate line Lg. Further, in this embodiment, the current supply lines La are connected to each other in units of four by the column-direction connecting wiring Lc, so that the power supply or the current supply driver is “d = 4” according to the control signal group output from the control circuit. ", A low level L pulse is sequentially output every four rows from the current supply line La of the first row.

Here, as shown in FIG. 7, in each gate line Lg of the group of i to (i + d−1) rows, one scanning period T _{SC in} which the ON level ON pulse of the gate line Lg is output is shifted from each other. However, each one scanning period T _SC is set within the group write voltage period T _WR in which a low level L pulse is output to the current supply line La of i to (i + d−1) rows. In the present embodiment, since the current supply lines La of i to (i + d−1) rows are connected to each other by the column-direction connecting wiring Lc, the low level to the current supply lines La of i to (i + d−1) rows is low. The time length of the pulse of L is the sum of one scanning period T _SC for sequentially outputting on-level ON pulses from the i-th to (i + d−1) -th gate lines Lg, that is, the group write voltage period T _WR Become. In other words, the i-th (i + d−1) -th group current supply lines La are output to the i-th gate line Lg from the off-level OFF to on-level ON pulse, and then the (i + d−1) -th row. A low level L pulse is output until a pulse for switching from the ON level ON to the OFF level OFF is output to the gate line Lg. In addition, during the period when the ON level ON pulse is output to the gate line Lg of each row, the data driver syncs the data lines Ld in all columns according to the emission luminance gradation according to the control signal group output from the control circuit. A display signal that is a current (ie, a current toward the data driver) is generated. Here, the data driver applies a current driver that passes a gray-scale current that has a current value according to the image data received by the control circuit, or a gray-scale voltage that flows a current having a current value according to the image data. The display driver outputs a display signal to the data line Ld of each column and causes a sink current to flow.

The current flow and voltage application of each pixel 30 will be described in detail.
At the start time t _{i of the i-th} scanning period T _SC , a high level (on-level ON) pulse is output from the scanning driver to the i-th gate line Lg, and from time t _i to time t _{(i + 1).} During the scanning period T _SC until immediately before, the i-th gate line Lg has an on-level ON scanning signal voltage that turns on the first selection transistor Tr11 and the second selection transistor Tr12. Applied to line Lg. Subsequently, at the start time t _{(i + 1)} of the scanning period T _{SC in} the (i + 1) th row, a high level (on level ON) pulse is output from the scanning driver to the gate line Lg in the (i + 1) th row, On-level ON scanning signal voltage that turns on the first selection transistor Tr11 and the second selection transistor Tr12 on the gate line Lg of the (i + 1) th row from t _{(i + 1)} to immediately before time t _{(i + 2).} Is applied to the gate line Lg of the (i + 1) th row. Similarly, from time t _{(i + 2),} which is the scanning period T _SC of the (i + 2) th row, to immediately before time t _{(i + 3)} , the gate line Lg of the (i + 2) th row has the first selection transistor Tr11 and the second selection transistor Tr11. An on-level ON scanning signal voltage that turns on the selection transistor Tr12 is applied to the gate line Lg of the (i + 2) -th row, and the time from the time t _{(i + 3)} that is the scanning period T _SC of the (i + 3) -th row. Until just before t _{(i + 4)} , the (i + 3) -th row gate line Lg has an on-level ON scanning signal voltage that turns on the first selection transistor Tr11 and the second selection transistor Tr12. Applied to the gate line Lg of the eye.

Furthermore, at the start time t _i of the group write voltage period T _{WR for} the d-th group of the i- (i + d−1) th row, the current of the i- (i + d−1) -th group from the power supply or current supply driver. A low level L pulse signal is output to the supply line La. The low level L is equal to or lower than the reference potential Vss. Furthermore, each row of the scanning period T _SC, the data driver in accordance with image data received by the control circuit, supplying a sink current of a predetermined current value.

First, in the scanning period T _SC of the i-th gate line Lg, the first selection transistor Tr11 and the second selection transistor Tr12 are turned on, and the data driver performs a sink current for current control whose voltage value is equal to or lower than the reference voltage Vss. To the data line Ld of each column. Therefore, a voltage corresponding to the current value of the sink current is applied to one end of the gate and source of the light emission drive transistor Tr13, and as shown in FIG. 6A, the data line Ld and the second selection transistor Tr12 are used. A sink current flows through the light emission drive transistor Tr13.

Since the potential of the gate electrode 13g of the light emission drive transistor Tr13 is equal to the potential of the drain electrode 13d, a potential difference is generated between the gate and the source of the light emission drive transistor Tr13, and the data line Ld follows the voltage specified by the data driver. The sink current I having the current value (that is, the current value according to the image data) flows in the direction indicated by the arrow K shown in FIG. In the scanning period T _SC , since the power supply signal voltage of the current supply line La is equal to or lower than the reference voltage H, the anode potential of the organic EL element 21 is lower than the cathode potential, and the reverse bias voltage is applied to the organic EL element 21. Is applied. Therefore, no current from the current supply line La flows through the organic EL element 21.

  At this time, both ends of the capacitor 13 of each pixel 30 become a voltage according to the current value of the current flowing through the drain electrode 13d-source electrode 13s of the light emission drive transistor Tr13 based on the display signal controlled by the data driver. That is, the capacitor 13 of each pixel 30 has a charge that causes a potential difference between the gate and the source of each light emission drive transistor Tr13 that causes the current I according to the display signal to flow through the light emission drive transistor Tr13 of each pixel 30. Charged.

Such an operation is performed for each scanning period T _SC for i to (i + d−1) rows. The group writing voltage period T _WR end time t _{(i + d),} pulses output from the scan driver (i + d-1) to the gate line Lg of row switches off level OFF from ON level ON, and power or current A signal output from the supply driver to the i to (i + d−1) rows of current supply lines La is switched from the low level L to the high level H. Therefore, in the group of i to (i + d−1) rows, _{i to (i + d)} during the group light emission voltage period T _EM from the end time t _{(i + d)} to the start time t _i of the next group write voltage period T _WR. -1) An off level OFF (low level) scanning signal voltage is applied to the gate of the first selection transistor Tr11 and the gate of the second selection transistor Tr12 to the gate line Lg of the row, and also applied to the current supply line La. The power supply signal voltage is a high-level power supply voltage H that is sufficiently higher than the potential low level L output during the reference potential Vss and the group write voltage period _TWR .

Therefore, as shown in FIG. 6B, in the group light emission voltage period _TEM , the second selection transistor Tr12 in the non-selected row is turned off, and no current flows through the second selection transistor Tr12. Furthermore, the group emission voltage period T _EM, the first selection transistor Tr11 is turned off, capacitor 13, continues to hold the electric charge stored by the first and second ends, the light emission drive transistor Tr13 is maintained in the on state Keep doing. That is, the gate-source voltage value V _GS of the light emission drive transistor Tr13 is equal in the group light emission voltage period T _EM and the group write voltage period T _WR immediately before the group light emission voltage period T _EM . Therefore, even a group emission voltage period T _EM, since the light emission drive transistor Tr13 continues flowing a current having a current value according to the image data, the current value of the current I of the group emission voltage period T _EM is the group emission voltage period T _EM It is equal to the current value of the current K in the previous group write voltage period _TWR . During the group emission voltage period T _EM, current K flowing through the light emission drive transistor Tr13 is flow through the organic EL element 21 emits light at a luminance according to the current value of the current I in which the organic EL element 21 flows. In this way, the organic EL element 21 emits light at a luminance gradation according to the display signal.

Further, when i~ (i + d-1) a group writing voltage period T _WR of th gate line Lg is completed, continue (i + d) th ~ (i + 2d-1) gate line Lg of row groups are sequentially selected at a group writing voltage period T _WR that, during this time, the signal output from the power source or current supply driver (i + d) ~ (i + 2d-1) row of the current supply line La is switched from the low level L to high level H. As described above, when the writing of all the rows is completed by switching the voltage of the current supply line La so that the writing is performed in a group of d rows connected to each other, the current supply line La is completed. One scanning period T _SC starts from Lg, and writing is repeated.

  Next, a manufacturing method of the bottom emission type light emitting device according to the present embodiment will be described with reference to FIGS. The first selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13 have the same basic structure except for the channel width, and the first selection transistor Tr11 is the same as the second selection transistor Tr12. Since it is formed by the same process, the description thereof is omitted below.

  First, a pixel substrate 31 having a glass substrate or the like is prepared. A transparent conductive film such as ITO is deposited on the pixel substrate 31 by sputtering, vacuum evaporation, or the like, and then a capacitor electrode Cs1 is patterned by photolithography.

  Next, on the pixel substrate 31, for example, at least one of a Mo film, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, an AlNdTi alloy film, and a MoNb alloy film is formed by sputtering, vacuum deposition, or the like. A gate conductive film is formed and patterned into the shapes of the gate electrodes 12g and 13g of the transistors Tr12 and Tr13 and the data line Ld as shown in FIG. At this time, the gate electrode 13g of the light emission drive transistor Tr13 is formed so as to overlap with a part of the capacitor electrode Cs1 in the contact portion 44, but the transparent metal oxide such as ITO which becomes the capacitor electrode Cs1 has a contact resistance with Al. Therefore, the gate conductive film is preferably a Mo film or MoNb alloy film having a relatively low contact resistance with a transparent metal oxide such as ITO. In the case of the top emission type, the capacitor electrode Cs1 does not need to be transparent, so that the gate conductive film is patterned to integrally form the gate electrode 13g of the light emission drive transistor Tr13 and the source electrode 11s of the first selection transistor Tr11. Since it is formed, there is no restriction on the material of the transparent conductive film described above.

  Subsequently, an insulating film 32, an amorphous silicon film, and a silicon nitride film are successively deposited on the gate electrodes 12g and 13g, the capacitor electrode Cs1, and the data line Ld by a CVD (Chemical Vapor Deposition) method or the like, and a silicon nitride film is formed. The protective insulating films 122 and 132 are formed by patterning.

  Next, after depositing an amorphous silicon film containing an n-type impurity by a CVD method or the like, patterning is performed to form ohmic contact layers 124, 125, 134, 135 as shown in FIG. The semiconductor layers 121 and 131 of the transistors Tr12 and Tr13 are formed by patterning.

  Next, a transparent conductive film such as ITO is used on the insulating film 32 by sputtering, vacuum deposition, or the like in the case of the bottom emission type, and a light reflective conductive film and a transparent conductive film such as ITO in the case of the top emission type. After coating, the pixel electrode 34 is formed by patterning by photolithography.

  Subsequently, after forming contact portions 41 and 43 which are through holes in the insulating film 32, for example, Mo film, Cr film, Al film, Cr / Al laminated film, AlTi alloy film, AlNdTi alloy film, MoNb alloy film A source-drain conductive film containing at least one of the above and the like is coated by a sputtering method, a vacuum deposition method, or the like, and patterned by photolithography to form drain electrodes 12d and 13d and a source as shown in FIGS. The electrodes 12s and 13s, the current supply line La, and the column direction connection wiring Lc are formed. At this time, the source electrode 13s of the light emission drive transistor Tr13 and the drain electrode 12d of the second selection transistor Tr12 are formed so as to overlap with part of the pixel electrode 34, respectively. Thus, since the source electrode 13s of the light emission drive transistor Tr13 and the drain electrode 12d of the second selection transistor Tr12 are connected via the pixel electrode 34, the second selection transistor Tr12 and the light emission drive transistor Tr13 are mutually connected. A lead-out wiring for connection becomes unnecessary, and the aperture ratio of the pixel can be increased. The contact holes 41 and 43 together with the contact holes exposing the connection terminal portions of the gate lines Lg for connection to the gate driver and the connection terminal portions of the data lines Ld for connection to the data driver are respectively formed in the insulating film 32. You may form in. If the conductive film to be the pixel electrode 34 is deposited after forming the contact holes and the contact portions 41 and 43 and then patterned by photolithography, the pixel electrode 34 is formed and the contact portions 41 and 43 are formed. A connection portion having a three-layer structure in which a conductive film to be the pixel electrode 34 is interposed between the gate conductive film and the source-drain conductive film can be formed.

  Subsequently, as shown in FIG. 8C, an interlayer insulating film 33 having a silicon nitride film is formed by CVD or the like so as to cover the transistors Tr12, Tr13 and the like.

  In the interlayer insulating film 33, openings that become the contact portion 49 and the contact portion 42 are formed by photolithography or the like. Subsequently, for example, a metal film including a Mo film, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, an AlNdTi alloy film, a MoNb alloy film, or the like is formed by a vacuum evaporation method or a sputtering method. Next, by patterning by photolithography, as shown in FIGS. 3 and 9A, the conductive layer 48 connected to the column-direction connecting wiring Lc and the current supply line La via the contact portion 49, and the contact portion 42 are formed. Thus, the gate electrode 12g of the second selection transistor Tr12 and the gate line Lg connected to the gate electrode 11g of the first selection transistor Tr11 are formed. Subsequently, an insulating layer 35 having a silicon nitride film or the like is formed so as to cover the conductive layer 48 and the gate line Lg. Next, as shown in FIG. 9B, an opening 35 a that exposes the pixel electrode 34 is formed in the insulating layer 35 and the interlayer insulating film 33.

  Next, photosensitive polyimide is applied so as to cover the interlayer insulating film 33 and the insulating layer 35, and is patterned by exposure, development, and baking through a mask corresponding to the shape of the partition wall 39, as shown in FIG. As shown in FIG.

  Subsequently, the organic compound-containing liquid containing the hole injection material was surrounded by the opening 35a by a nozzle printing apparatus that continuously flows, an inkjet apparatus that discharges the liquid as a plurality of individual droplets, or a roll-type printing apparatus. It is selectively applied onto the pixel electrode 34. Subsequently, the pixel substrate 31 is heated in an air atmosphere to volatilize the solvent of the organic compound-containing liquid, thereby forming the hole injection layer 36. The organic compound-containing liquid may be applied in a heated atmosphere. In addition to the wet film formation, the hole injection layer 36 may be formed by vapor deposition.

  Subsequently, an organic compound-containing liquid containing a material that becomes the interlayer 37 is applied onto the hole injection layer 36 using a nozzle printing apparatus, an inkjet apparatus, or a roll printing apparatus. The interlayer 37 is formed by performing heat drying in a nitrogen atmosphere or heat drying in a vacuum to remove the residual solvent. The organic compound-containing liquid may be applied in a heated atmosphere.

  Next, an organic compound-containing liquid containing the light emitting polymer material (R, G, B) is similarly applied by a nozzle printing apparatus, an ink jet apparatus, or a roll type printing apparatus and heated in a nitrogen atmosphere to remove residual solvent. Removal is performed to form the light emitting layer 38. The organic compound-containing liquid may be applied in a heated atmosphere.

  In the case of the bottom emission type, a layer having a low work function material such as Li, Mg, Ca, Ba and a light reflective conductive layer such as Al are formed on the pixel substrate 31 formed up to the light emitting layer 38 by vacuum deposition or sputtering. A counter electrode 40 having a two-layer structure is formed. In the case of the top emission type, the counter electrode 40 is formed on a light transmissive low work function layer having an extremely thin material having a low work function such as Li, Mg, Ca, Ba, and the like having a thickness of about 10 nm. In addition, a transparent laminated structure having a light-reflective conductive layer such as ITO having a thickness of about 100 nm to 200 nm is obtained.

Next, outside the display area where the plurality of pixels 30 are formed, a sealing resin having an ultraviolet curable resin or a thermosetting resin is applied onto the pixel substrate 31, and the pixel substrate 31 and the sealing substrate are bonded together. . Next, the sealing resin is cured by ultraviolet rays or heat to bond the pixel substrate 31 and the sealing substrate.
Through the above steps, the light emitting device 10 is manufactured as shown in FIG.

  In the present embodiment, a plurality of current supply lines La formed in the row direction are formed by forming the column-direction connecting lines Lc so that the drain electrodes 13d of the light emission drive transistors Tr13 are connected to each other in units of a plurality of rows. Are tied in a mesh. Accordingly, it is possible to suppress a drop due to the wiring resistance of the voltage applied to the current supply line La, and it is possible to cause a plurality of organic EL elements to emit light satisfactorily. In particular, in the present embodiment, since the drain electrode 13d is extended in the column direction of the pixel to form the column direction connection wiring Lc, a wiring for connecting the current supply line La is formed separately from the drain electrode 13d. There is no need to provide a region to be formed on the pixel substrate 31. Thereby, the voltage drop of the current supply line La can be suppressed without reducing the aperture ratio of the pixel 30.

  In the present embodiment, since the drain electrode 13d is extended, the gate line Lg intersecting the drain electrode 13d is formed of a third metal layer different from the gate conductive layer and the source-drain conductive layer. is doing. When forming the gate line Lg, the thickness of the current supply line La can be increased without particularly increasing the number of steps by forming the third metal layer on the current supply line La and the drain electrode 13d. Thus, the resistance of the current supply line La can be reduced.

  FIG. 11 shows the simulation result. FIG. 11 shows an example in which a data line, a current supply line, and a pixel are arranged as shown in FIG. 1, in which the current supply lines in each row are electrically independent, and the current supply lines in two rows. The degree of voltage drop was calculated for the case where the current supply lines are connected to each other and the case where the current supply lines of the four rows are connected to each other. In addition, the wiring resistance of the current supply line having a length corresponding to one pixel (corresponding to the length between adjacent data lines) is set to R1, and the corresponding length of one pixel (the length between adjacent current supply lines) is set. R2 is the resistance of the column direction connection wiring. In the example shown in FIG. 11, R1 is 5Ω, R2 is 100Ω, and the potential in each pixel when a current of 1 μA is drawn from each data line is shown. Note that 320 pixels are set in the horizontal direction (row direction), and pixels closer to the power supply or current supply driver (lower wiring resistance) are set to have a smaller number of stages. The simulation was performed assuming that the power supply or the current supply driver is supplied only from the direction in which the first pixel is installed.

  As is clear from FIG. 11, when the current supply line is not connected, the voltage drop is about 0.25 V at the 320th pixel compared to the first pixel. On the other hand, in each of the examples in which the current supply lines are connected to each other in the column direction, the voltage drop can be suppressed. When two lines are connected, about 0.12V, which is about half, and four lines each. When connected, it was a drop of about 0.06V. Thus, it can be said from FIG. 11 that the voltage drop can be suppressed by connecting the current supply lines with the column-direction connecting wires. In particular, when the data driver is a voltage driver that applies a gradation voltage for flowing a current value according to image data to the data line Ld, the current value of the current flowing between the drain and source of the light emission drive transistor Tr13 is: The greater the variation in voltage on the current supply line La in each pixel 30, the greater the variation. Thus, the structure as in this embodiment has a remarkable effect.

(Embodiment 2)
A light-emitting device and a method for manufacturing the light-emitting device according to Embodiment 2 will be described with reference to the drawings. The light emitting device of this embodiment is different from that of the first embodiment described above in the first embodiment, in which the gate line Lg is formed from the third metal layer on the source-drain conductive layer. Then, the column-direction connecting wiring is formed from the third metal layer. Portions common to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 12 is a diagram illustrating a configuration example of the light emitting device 50 according to the second embodiment. FIG. 13 is a plan view showing the pixel 51 of the light emitting device according to the second embodiment, and FIG. 14 is a plan view showing the pixel 51 with the column-direction connecting line Lc omitted. 15 is a cross-sectional view taken along line XV-XV shown in FIG. 13, and FIG. 16 is a cross-sectional view taken along line XVI-XVI shown in FIG.

  As shown in FIG. 12, the light emitting device 50 of the present embodiment is a set of pixels 51 of three colors of red (R), green (G), and blue (B) on the pixel substrate 31 as in the first embodiment. This set is repeatedly arranged in the row direction (left and right direction in FIG. 12), and a plurality of pixels of the same color are arranged in the column direction (up and down direction in FIG. 12). Each pixel 51 includes an organic EL element 21 that emits RGB light, and a pixel circuit DS that actively operates the organic EL element 21, as in the first embodiment. Similarly to the first embodiment, the pixel circuit DS includes a first selection transistor Tr11, a second selection transistor Tr12, a light emission drive transistor Tr13, a capacitor Cs, and an organic EL element 21. The organic EL element 21 is opposite to the pixel electrode 34, the partition 39, the interlayer insulating film 33, the insulating layer 35, the hole injection layer 36, the interlayer 37, and the light emitting layer 38 as in the first embodiment. An electrode 40.

  In the pixel 51 of the present embodiment, as shown in FIGS. 12 and 13, the column direction connection line Lc connects the current supply lines La of the pixels 51 adjacent in the column direction. Further, as shown in FIGS. 15 and 16, the column-direction connecting line Lc is formed of a third metal layer formed on the source-drain conductive layer. The gate line Lg, the current supply line La, and the drain electrode 13d of the light emission drive transistor Tr13 are formed using the same source-drain conductive layer. For this reason, the column-direction connecting line Lc is formed along the drain electrode 13d of the light emission drive transistor Tr13 as shown in FIG. 13, and between the drain electrode 13d and the current supply line La as shown in FIG. It is formed so as to be in contact with the drain electrode 13d and the current supply line La through a contact portion 47 which is a contact hole provided in the insulating film 33. Further, the region where the column-direction connecting line Lc and the gate line Lg intersect is insulated by the interlayer insulating film 33. In the present embodiment, the column-direction connecting wiring Lc is exemplified as a configuration that is linearly formed along the drain electrode 13d. However, since the current supply line La and the drain electrode 13d have the same potential, As in the first embodiment, the current supply line La can be formed in the row direction along the current supply line La to reduce the resistance of the current supply line La.

  In the present embodiment, the gate line Lg and the gate electrode 12g of the second selection transistor Tr12 are connected via a contact portion 55, which is a contact hole provided in the insulating film 32, as shown in FIG. .

  Next, a method for manufacturing the light emitting device 50 according to the present embodiment will be described with reference to FIGS. The capacitor electrode Cs1 is patterned. Next, on the pixel substrate 31, for example, at least one of Mo film, Cr film, Al film, Cr / Al laminated film, AlTi alloy film, AlNdTi alloy film, MoNb alloy film, etc. As shown in FIG. 17A, this is patterned into the shape of the gate electrodes 12g and 13g of the transistors Tr12 and Tr13 and the data line Ld. An insulating film 32, an amorphous silicon film, and a silicon nitride film are successively deposited on the gate electrodes 12g and 13g, the capacitor electrode Cs1, and the data line Ld by a CVD method or the like, and the protective film 122, 132 is formed.

  Next, after depositing an amorphous silicon film containing an n-type impurity by a CVD method or the like, patterning is performed to form ohmic contact layers 124, 125, 134, 135, and the amorphous silicon film is patterned to form semiconductors of the transistors Tr12 and Tr13. Layers 121 and 131 are formed. Next, a transparent conductive film such as ITO is used on the insulating film 32 by sputtering, vacuum deposition, or the like in the case of the bottom emission type, and a light reflective conductive film and a transparent conductive film such as ITO in the case of the top emission type. After coating, the pixel electrode 34 is formed by patterning by photolithography.

  Subsequently, after forming contact portions 41 and 43 which are through holes in the insulating film 32, for example, Mo film, Cr film, Al film, Cr / Al laminated film, AlTi alloy film or AlNdTi alloy film, MoNb alloy film A source-drain conductive film having the same structure is coated by sputtering, vacuum deposition or the like, and patterned by photolithography to form drain electrodes 12d, 13d and source electrodes 12s, 13s, current supply line La, and gate line Lg. . At this time, the source electrode 13s of the light emission drive transistor Tr13 and the drain electrode 12d of the second selection transistor Tr12 are formed so as to overlap with part of the pixel electrode 34, respectively.

  Subsequently, as shown in FIG. 17A, an interlayer insulating film 33 having a silicon nitride film is formed by CVD or the like so as to cover the transistors Tr12, Tr13 and the like.

  In the interlayer insulating film 33, an opening corresponding to the column direction connection wiring Lc except for the gate line Lg is formed by photolithography or the like. Subsequently, for example, a third metal layer selected from at least one of a Mo film, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, an AlNdTi alloy film, a MoNb alloy film, and the like, It is formed by sputtering. Next, patterning is performed by photolithography to form the column direction connection wiring Lc as shown in FIG. Note that the column-direction connecting line Lc is formed so as to be in contact with the drain electrode 13d and the current supply line La but insulated from the gate line Lg by the interlayer insulating film 33.

  Subsequently, an insulating layer 35 having a silicon nitride film or the like is formed so as to cover the column direction connection wiring Lc. Next, an opening 35 a that exposes the pixel electrode 34 is formed in the insulating layer 35 and the interlayer insulating film 33.

  Next, photosensitive polyimide is applied so as to cover the interlayer insulating film 33 and the insulating layer 35, and is patterned by exposure, development, and baking through a mask corresponding to the shape of the partition wall 39, as shown in FIG. As shown in FIG.

  Subsequently, as in the first embodiment, the hole injection layer 36 is formed on the pixel electrode 34 surrounded by the opening 35a by a nozzle printing apparatus, an inkjet apparatus, or a roll printing apparatus. In addition to the wet film formation, the hole injection layer 36 may be formed by vapor deposition. Next, an interlayer 37 is formed on the hole injection layer 36, and a light emitting layer 38 is formed on the interlayer 37.

  In the case of the bottom emission type, a layer having a low work function material such as Li, Mg, Ca, Ba and a light reflective conductive layer such as Al are formed on the pixel substrate 31 formed up to the light emitting layer 38 by vacuum deposition or sputtering. A counter electrode 40 having a two-layer structure is formed. In the case of the top emission type, the counter electrode 40 is formed on a light transmissive low work function layer having an extremely thin material having a low work function such as Li, Mg, Ca, Ba, and the like having a thickness of about 10 nm. In addition, a transparent laminated structure having a light-reflective conductive layer such as ITO having a thickness of about 100 nm to 200 nm is obtained.

Next, outside the display area where the plurality of pixels 51 are formed, a sealing resin having an ultraviolet curable resin or a thermosetting resin is applied onto the pixel substrate 31, and the pixel substrate 31 and the sealing substrate are bonded together. . Next, the sealing resin is cured by ultraviolet rays or heat to bond the pixel substrate 31 and the sealing substrate.
Through the above steps, the light emitting device 50 is manufactured as shown in FIG.

  As described above, in the present embodiment, the column direction connection line Lc is connected so as to connect the drain electrode 13d of the light emission drive transistor Tr13 of the pixel 51 and the drain electrode 13d of the light emission drive transistor Tr13 of the pixel 51 adjacent in the column direction. Form. Thereby, a plurality of current supply lines La can be connected, and the voltage drop of the current supply line La can be suppressed satisfactorily.

(Embodiment 3)
A light emitting device 60 according to Embodiment 3 will be described with reference to the drawings. In the first and second embodiments described above, the current supply line La, the data line Ld, and the gate line Lg are formed by the gate conductive layer, the source-drain conductive layer, and the third metal layer. The third embodiment is different in that these wirings are formed by only two layers of a gate conductive layer and a source-drain conductive layer. Portions common to the above-described embodiments are assigned the same reference numerals, and detailed descriptions thereof are omitted.

  FIG. 19 is a diagram illustrating a configuration example of the light emitting device 60 according to the third embodiment. 20 is a plan view showing a pixel 61 of the light emitting device according to the third embodiment, FIG. 21A is a sectional view taken along line XXIA-XXIA shown in FIG. 20, and FIG. 20B is shown in FIG. It is XXIB-XXIB sectional view.

  As in the first embodiment, the light emitting device 60 according to the present embodiment is a set of pixels 61 of three colors of red (R), green (G), and blue (B) on the pixel substrate 31, and this set is arranged in the row direction. A plurality of pixels are repeatedly arranged in the horizontal direction (FIG. 20), and a plurality of pixels of the same color are arranged in the column direction (vertical direction in FIG. 20). Each pixel 61 includes an organic EL element 21 that emits RGB light and a pixel circuit DS that actively operates the organic EL element. Similarly to the first embodiment, the pixel circuit DS includes a first selection transistor Tr11, a second selection transistor Tr12, a light emission drive transistor Tr13, a capacitor Cs, and an organic EL element 21. As in the first embodiment, the organic EL element 21 includes a pixel electrode 34, an interlayer insulating film 33, a hole injection layer 36, an interlayer 37, a light emitting layer 38, a partition wall 39, and a counter electrode 40. Prepare.

  In this embodiment, as shown in FIG. 20, the drain electrode 13d of the light emission drive transistor Tr13 is extended in the column direction and connected to the drain electrode 13d of the adjacent pixel 61, and the drain electrode 13d functions as the column-direction connecting line Lc. Let Since the drain electrode 13d is formed so as to extend over a plurality of pixels in this way, in this embodiment, the gate line Lg is used as the data so that the column direction connection wiring Lc (drain electrode 13d) and the gate line Lg do not intersect. The gate conductive layer is formed in the same layer as the line Ld and is formed under the insulating film 32. When the gate line Lg is formed using a gate conductive layer, a region where the gate line Lg and the data line Ld intersect as shown in the lower left of FIG. 20 is generated. For this reason, as shown in FIG. 21B, the gate lines Lg are insulated from each other by using the contact portions 66 and 67 provided in the insulating film 32 and the detour wiring 65 formed from the source-drain conductive layer. The gate line Lg and the data line Ld are insulated from each other.

Next, a method for manufacturing the light emitting device 60 of this embodiment will be described.
First, the capacitor electrode Cs1 is patterned. Next, on the pixel substrate 31, for example, at least one of Mo film, Cr film, Al film, Cr / Al laminated film, AlTi alloy film, AlNdTi alloy film, MoNb alloy film, etc. Is formed and patterned into the shapes of the gate electrodes 12g and 13g of the transistors Tr12 and Tr13, the data line Ld, and the gate line Lg. Next, an insulating film 32, an amorphous silicon film, and a silicon nitride film are successively deposited on the gate electrodes 12g and 13g, the capacitor electrode Cs1, the data line Ld, and the gate line Lg by CVD or the like, and the silicon nitride film is patterned. Thus, protective insulating films 122 and 132 are formed.

  Next, after depositing an amorphous silicon film containing an n-type impurity by a CVD method or the like, patterning is performed to form ohmic contact layers 124, 125, 134, 135, and the amorphous silicon film is patterned to form semiconductors of the transistors Tr12 and Tr13. Layers 121 and 131 are formed. Next, a transparent conductive film such as ITO is used on the insulating film 32 by sputtering, vacuum deposition, or the like in the case of the bottom emission type, and a light reflective conductive film and a transparent conductive film such as ITO in the case of the top emission type. After coating, the pixel electrode 34 is formed by patterning by photolithography.

  Subsequently, through holes corresponding to the contact portions 66 and 67 are formed in a predetermined region of the insulating film 32. For example, a Mo film, a Cr film, an Al film, a Cr / Al laminated film, an AlTi alloy film, or an AlNdTi A source-drain conductive layer having an alloy film, a MoNb alloy film, or the like is coated by a sputtering method, a vacuum deposition method, or the like, and patterned by photolithography. Thereby, the contact portions 66 and 67, the bypass wiring 65, the drain electrodes 12d and 13d, the source electrodes 12s and 13s, and the current supply line La are formed. At this time, the source electrode 13s of the light emission drive transistor Tr13 and the drain electrode 12d of the second selection transistor Tr12 are formed so as to overlap with part of the pixel electrode 34, respectively.

  Subsequently, an interlayer insulating film 33 having a silicon nitride film is formed by a CVD method or the like so as to cover the transistors Tr12, Tr13 and the like. Next, an opening 35a is formed in the interlayer insulating film 33 by photolithography or the like, and the pixel electrode 34 is exposed.

  Next, photosensitive polyimide is applied so as to cover the interlayer insulating film 33, and patterned by exposure, development, and baking through a mask corresponding to the shape of the partition 39, thereby forming the partition 39. Subsequently, as in the first embodiment, the hole injection layer 36 is formed on the pixel electrode 34 surrounded by the opening 35a. Next, an interlayer 37 is formed on the hole injection layer 36, and a light emitting layer 38 is formed on the interlayer 37.

  In the case of the bottom emission type, a layer having a low work function material such as Li, Mg, Ca, Ba and a light reflective conductive layer such as Al are formed on the pixel substrate 31 formed up to the light emitting layer 38 by vacuum deposition or sputtering. A counter electrode 40 having a two-layer structure is formed. In the case of the top emission type, the counter electrode 40 is formed on a light transmissive low work function layer having an extremely thin material having a low work function such as Li, Mg, Ca, Ba, and the like having a thickness of about 10 nm. In addition, a transparent laminated structure having a light-reflective conductive layer such as ITO having a thickness of about 100 nm to 200 nm is obtained.

Next, outside the display area where the plurality of pixels 61 are formed, a sealing resin having an ultraviolet curable resin or a thermosetting resin is applied onto the pixel substrate 31, and the pixel substrate 31 and the sealing substrate are bonded together. . Next, the sealing resin is cured by ultraviolet rays or heat to bond the pixel substrate 31 and the sealing substrate.
The light emitting device 60 is manufactured through the above steps.

  As described above, in this embodiment, the drain electrode 13d of the light emission drive transistor Tr13 of the pixel 61 is formed to extend, and is connected to the drain electrode 13d of the light emission drive transistor Tr13 of the pixel 61 adjacent in the column direction. It functions as the direction connection wiring Lc. Thereby, the voltage drop of the electric current supply line La can be suppressed favorably. Furthermore, in the present embodiment, the gate line Lg is formed using a gate conductive layer that forms the data line Ld, and the region where the gate line Lg and the data line Ld intersect is formed using the source-drain conductive layer. The bypass line 65 bypasses the gate line Lg. In this way, by bypassing the gate line Lg, the current supply line La can be connected by the column-direction connecting wiring Lc only with the two metal layers of the gate conductive layer and the source-drain conductive layer. The voltage drop of the line La can be suppressed satisfactorily.

  In the above-described third embodiment, the case where the gate line Lg is formed using the gate conductive layer has been described as an example. However, the present invention is not limited to this. For example, as illustrated in FIG. Similarly to 2, the source-drain conductive layer may be used, and the column-direction connecting wiring Lc and the current supply line La may be formed using the source-drain conductive layer. In this case, since the column direction connection wiring Lc and the gate line Lg intersect in the region corresponding to the lower right of FIG. 20, the gate line Lg is disconnected near the column direction connection wiring Lc, and the column direction connection A detour wiring in which the ends of the gate lines Lg located on the left and right sides of the wiring Lc are patterned using the gate conductive layer in the same manner as in the third embodiment through the contact portions that are contact holes provided in the insulating film 32. 71 may be connected.

  Further, the data line Ld and the column direction connection wiring Lc are directly related to transmission of a display signal for controlling the light emission of the organic EL element, and it is preferable that no voltage drop occurs. In the case where the influence on light emission is small, for example, in Embodiment 3, it is possible to bypass the data line Ld instead of the gate line Lg, and it is formed using a source-drain conductive layer as shown in FIG. The column-direction connecting wiring Lc can be bypassed by the bypass wiring 72 formed by using the gate conductive layer through the contact portion that is a contact hole provided in the insulating film 32.

(Embodiment 4)
A light emitting device 70 according to a fourth embodiment will be described with reference to FIGS. The fourth embodiment is different from the first to third embodiments in that a switch transistor Tr14 is provided as a switching element in the column-direction connection line Lc between adjacent rows. Further, the current supply line La is not divided in units of d rows (d is an integer of 2 or more), and all rows are connected via the column-direction connection wiring Lc between the rows and the switch transistor Tr14. Portions common to the above-described embodiments are assigned the same reference numerals, and detailed descriptions thereof are omitted.

  The switch transistor Tr14 in the i-th row has a drain electrode connected to the column-direction connection line Lc connected to the i-th current supply line La, and a source electrode connected to the (i + 1) -th current supply line La. The gate electrode is connected to the control wiring Ls in the i-th row, connected to the column-direction connecting wiring Lc. That is, when the number of control lines Ls is n, (n−1) lines are arranged. For this reason, when an ON level ON switch signal voltage is applied to the i-th control wiring Ls, the i-th current supply line La and the (i + 1) -th current supply line La become conductive, and the off-level When an OFF switch signal voltage is applied, the i-th current supply line La and the (i + 1) -th current supply line La do not conduct. Here, in order to connect the current supply lines La to each other in units of d rows (d is an integer of 2 or more), as shown in FIG. 26, the gate line Lg of the i-th row is turned on. When the signal voltage is applied, the switch signal voltage at the OFF level OFF is applied to the control wiring Ls in the i-th row, and the current supply line La in the i-th row is connected to the current supply line La in the (i + 1) -th row. The switch signal voltage of OFF level OFF is applied to the control wiring Ls in the (id) row, and the current supply line La in the (id) row becomes the (id-1) row. A switch signal voltage with an ON level ON is applied to all the control wirings Ls other than the i-th row and the (id) -th row, which are not electrically connected to the current supply line La.

  When an on-level ON scanning signal voltage is applied to the i-th gate line Lg, the voltage applied to the i-th current supply line La is switched from the high level H to the low level L, and then ( The power supply or current supply driver is set so that the low level L voltage is continuously applied until the scanning signal voltage applied to the gate line Lg of the (i + d-1) -th row is switched from the ON level ON to the OFF level OFF. Yes. When the scanning signal voltage applied to the (i + d) -th gate line Lg is switched from the OFF level OFF to the ON level ON, the voltage applied to the i-th current supply line La is changed from the low level L to the high level. The power supply or current supply driver is set to switch to H.

  In other words, when the on-level ON scanning signal voltage is applied to the i-th gate line Lg, the on-level ON switch is applied to the control wiring Ls in the (i−d + 1) th to (i−1) th rows. Since the signal voltage is applied and (d−1) switch transistors Tr14 between the (i−d + 1) th row and the ith row are turned on, the column direction between the (i−d + 1) th row and the ith row Since the connection wiring Lc is conductive, the current supply lines La of the (i−d + 1) -th to i-th rows are mutually conductive and a low level L potential is applied. When the on-level ON scanning signal voltage is applied to the i-th gate line Lg, the off-level OFF switch signal voltage is applied to the (id) and i-th control wiring Ls, Since the switch transistors Tr14 in the (id) and i-th rows are turned off, the current supply lines La in the (i-d + 1) -th to i-th rows are electrically connected to the current supply lines La in the other rows. do not do. Further, when a scanning signal voltage with an ON level ON is applied to the i-th gate line Lg, the control wiring Ls in the first to (id-1) th rows and the (i + 1) th to (n-) rows. 1) On-level ON switch signal voltage is applied to the control wiring Ls in the row, and the control wiring Ls in the first to (id-1) th rows and (i + 1) th to (n-1). Since the switch transistor Tr14 in the row is turned on, the current supply lines La in the first row to the (id) row are electrically connected to each other, and a high level H potential is applied, and the (i + 1) th row to the nth row. The current supply lines La of the eyes are electrically connected to each other, and a high level H potential is applied.

In this way, while the ON-level ON scanning signal voltage is applied to the i-th gate line Lg, the d (i−d + 1) -th to i-th current supply lines La are connected to each other. Runode, group writing voltage period T _WR can suppress the voltage drop of the potential of the low level L applied to further first row ~ (i-d) th current supply line La is high level electrically connected to each other The voltage drop of the H potential can be suppressed, and (i + 1) the current supply lines La of the sixth to nth rows can be connected to each other to suppress the voltage drop of the high level H potential.

(Embodiment 5)
A light emitting device 80 according to Embodiment 5 will be described with reference to FIGS. In the fifth embodiment, one switch transistor Tr14 is provided as a switching element for every d rows (d is an integer equal to or larger than 2) in the column-direction connecting line Lc. The column-direction connecting line Lc between the pixel 30 in the (p × d) row (p is a positive integer) and the pixel 30 in the (p × d + 1) row, specifically, the pixel 30 in the d row ( (d + 1) column-direction connection line Lc between the pixels 30 in the row, the pixel-direction connection line Lc between the pixels 30 in the 2d-th row and the pixels 30 in the (2d + 1) -th row, Switch transistors Tr14 are provided in the column direction connection lines Lc,... Between the pixels 30 in the (3d + 1) th row, and the source and drain electrodes of each switch transistor Tr14 are connected to the upper and lower column direction connection lines Lc, respectively. Yes. Therefore, each switch transistor Tr14 controls conduction and non-conduction between the (p × d) -th current supply line La and the {p × (d + 1)}-th current supply line La (p is a positive value). integer). 27 to 29 are diagrams of examples in which d is 4. Further, the current supply line La is connected in the column direction via the column direction connection line Lc and the switch transistor Tr14. Portions common to the above-described embodiments are assigned the same reference numerals, and detailed descriptions thereof are omitted.

As shown in FIG. 29, the current supply driver connected to the current supply line La applies the same voltage in units of d current supply lines La. That is, the current supply driver outputs a low level voltage L in the group write voltage period _TWR for each d current supply lines La, and then outputs a high level voltage H in the group light emission voltage period _TEM . The group write voltage period T _WR is the {(p−1) × d + 1} row to the p × d row, that is, the first row to the d row, the (d + 1) row to the 2d row, and the (2d + 1) row. The first to third rows,..., (N−d + 1) to every nth row are sequentially shifted.
Each control wiring Ls is connected to a power supply or a control wiring driver, and the power supply or control wiring driver includes a current supply line La in the (p × d) row and a current supply line La in the {p × (d + 1)} row. Current supply line La of {(p−1) × d + 1} -th to (p × d) -th row with respect to the control wiring Ls connected to the gate electrode of the switch transistor Tr14 of the column-direction connection wiring Lc between Switch signal voltage of OFF level OFF during the group write voltage period _TWR of the current supply line La of the group write voltage period _TWR of the next group and the (p × d + 1) th row to the {(p + 1) × d} row of the next group Is output, and the switch signal voltage of the ON level ON is output during other periods.

When an ON level ON switch signal voltage is applied to the control wiring Ls in the (p × d) row, the current supply line La in the (p × d) row and the current supply line in the (p × d + 1) row When La is conducted and a switch signal voltage of OFF level OFF is applied, the current supply line La of the (p × d) row and the current supply line La of the (p × d + 1) row are not conducted.
For this reason, the current supply lines La of the {(p−1) × d + 1} th row to the (p × d) th row are the currents of the {(p−1) × d + 1} th row to the (p × d) th row. group writing voltage period of the supply line La T _WR and the next group (p × d + 1) th ~ {(p + 1) × d} in the group writing voltage period T _WR of th current supply lines La, (p × d + 1 ) The current supply line La of the row to the {(p + 1) × d} row is turned off. Therefore, the current supply line La of the {(p−1) × d + 1} th to (p × d) rows and the current supply line La of the (p × d + 1) th to {(p + 1) × d} rows are , During the group write voltage period _TWR of the current supply line La in the {(p−1) × d + 1} row to the (p × d) row, the voltage can be maintained at the low level L and the high level H, respectively. , During the group write voltage period _TWR of the current supply line La of the (p × d + 1) th row to the {(p + 1) × d} row, the voltage can be maintained at the high level H and the low level L, respectively.

When viewed in the current supply line La of the (p × d + 1) th row to the {(p + 1) × d} row, the currents in the (p−1) × d + 1th row to the (p × d) th row of the group above it. With respect to the supply line La, the group write voltage period _TWR of the current supply line La of the (p−1) × d + 1th to (p × d) th rows and the (p × d + 1) th to {(p + 1) th rows During the group write voltage period _TWR of the current supply line La of the × d} row, the transistor Tr14 in the (p × d) row is turned off so that the applied voltage is different, and the {(p + 1) × d + 1 of the lower group is turned off. } The group write voltage period of the current supply line La of the (p × d + 1) th row to {(p + 1) × d} row with respect to the current supply line La of the row # to {(p + 2) × d}. T _WR and {(p + 1) × d + 1} th ~ {(p + 2) × d} th current supply In the group writing voltage period in La T _WR, the applied voltage is different, turns off the {(p + 1) × d } row of the switch transistor Tr14. In other words, if the current supply line La of a certain group has a different potential with respect to the current supply line La of the adjacent group, the switch transistor Tr14 between the adjacent groups is turned off to be non-conductive with each other. If so, the switch transistor Tr14 between adjacent groups can be turned on to conduct to each other to reduce resistance.

The present invention is not limited to the above-described embodiments, and various modifications and applications are possible.
For example, in Embodiment 1 described above, the conductive layer 48 is formed so as to cover the entire current supply line La and is formed on the drain electrode 13d of the light emission drive transistor Tr13. Without being limited thereto, the conductive layer 48 may be formed so as to be separated for each pixel on the current supply line La. Further, it may be formed so as to cover only the drain electrode 13d.

  Further, in the above-described second embodiment, the example in which the column-direction connecting wiring Lc is formed in the column direction so as to overlap the drain electrode 13d of the light emission driving transistor Tr13 has been described. However, the conductive layer 48 of the above-described first embodiment As described above, the column-direction connecting line Lc may also be formed on the current supply line La.

  In each of the above-described embodiments, the pixel circuit DS has been described as an example including a total of three transistors, ie, the first selection transistor Tr11, the second selection transistor Tr12, and the light emission drive transistor Tr13. Like the pixel circuit DS <b> 2 illustrated, the pixel circuit DS <b> 2 may include two transistors, a selection transistor Tr <b> 21 and a light emission drive transistor Tr <b> 22.

  In the above-described embodiments, the bottom emission type organic EL element has been mainly described. However, the present invention is not limited to this, and the top emission type organic EL that emits display light of the organic EL element 21 to the outside through the counter electrode 40 is not limited thereto. It can also be used for an element.

  In each of the embodiments described above, the light emitting device is a display device. However, the light emitting device can also be applied to a printer head that emits light to a photosensitive drum of a printer.

In each of the embodiments described above, the organic EL element includes the hole injection layer 36, the interlayer 37, and the light emitting layer 38. However, the combination of the carrier transport layers is not limited to this, and for example, the hole injection layer A double-layer structure such as only 36 and the light-emitting layer 38, a single-layer structure in which the light-emitting layer also serves as a hole injection layer, or a layer structure having four or more carrier transport layers including the light-emitting layer may be used. .
In each of the embodiments described above, the organic EL element 21 is applied, but other light emitting elements such as LEDs may be applied.

  Each embodiment described above may be arbitrarily combined with each other as long as there is consistency.

  10, 50, 60, 70, 80 ... light emitting device, 30, 51, 61 ... pixel, 21 ... organic EL element, 31 ... pixel substrate, 32 ... insulating film, 33 ... Interlayer insulating film 34... Pixel electrode 35. Insulating layer 36. Hole injection layer 37. Interlayer 38. Light emitting layer 39. ..Counter electrode, 41, 42, 43, 44, 49, 55, 66, 67 ... contact part, 48 ... conductive layer, Cs ... capacitor, Cs1 ... capacitor electrode, La ... Current supply line, Lc... Column connection wiring, Ld... Data line, Lg... Gate line, Tr11... First selection transistor, Tr12. Driving transistor

Claims (4)

In a light emitting device including a light emitting element having a light emitting layer between a pixel electrode and a counter electrode,
A first select transistor having a gate electrode connected to the gate line;
A second selection transistor having a gate electrode connected to the gate line and a source electrode connected to the data line;
A light emission driving transistor having a drain electrode connected to the drain electrode of the first selection transistor and a source electrode connected to the drain electrode of the second selection transistor and the pixel electrode;
A capacitor connected to the gate electrode of the light emission drive transistor and the source electrode of the light emission drive transistor;
Have
The light emitting device, wherein the gate electrode of the light emission driving transistor and the source electrode of the first selection transistor are separated from each other and connected to each other through a capacitor electrode of the capacitor.   The light emitting device according to claim 1, wherein the pixel electrode and the capacitor electrode are transparent.   3. The light emitting device according to claim 1, wherein the capacitor electrode of the capacitor is disposed below the pixel electrode through an insulating film.   4. The light emitting device according to claim 3, wherein the source electrode and the capacitor electrode of the first selection transistor are connected via a contact hole provided in the insulating film.

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