JP2011033906A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a multiple gray scale by lowering a frequency of a clock rate of a gray scale counter, and further by using a set of ramp signals. <P>SOLUTION: The gray scale counter 104 can make a frequency of a clock Count-CK of the gray scale counter 104 be lower than a clock used in the gray scale counter to output a counter value of 10 bits, because it is constructed so as to obtain a counter value output of 9 bits compared to higher-order 9 bits of pixel data. Further, a gray scale of 10 bits more than 9 bits compared with a comparator 103 is obtained by changing an electric potential corresponding to pixel data of higher-order 9 bits sampled by using a set of ramp signals (reference ramp voltage Ref_Ramp(+) and Ref_Ramp(-)) and held on data lines D1(+)-Dm(+), D1(-)-Dm(-) in accordance with a value of lower-order 1 bit of pixel data by mounting least significant bit switches 107a and 107b. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device of a plurality of projection type liquid crystal display devices.

  In the active matrix liquid crystal display device, the image of the analog video signal is displayed by controlling the liquid crystal display element to a transmittance corresponding to the gradation of the analog video signal. On the other hand, with the advancement of digital signal processing technology, the digitization of external circuits of liquid crystal elements is progressing. Accordingly, it is becoming more convenient for the entire system to input a digital signal as a video signal to the liquid crystal element. Therefore, a drive circuit for a liquid crystal display device that drives a liquid crystal element by converting a digital video signal into an analog video signal pixel by pixel using a ramp signal has been proposed (see, for example, Patent Document 1).

  The driving circuit of the liquid crystal display device of Patent Document 1 is a driving circuit of an active matrix type liquid crystal panel, and a simple ramp reference for one horizontal scanning period having gradation levels of all video signals from black to white. A signal (ramp signal) is supplied to the video switch, and a so-called gradation counter is counted up by a clock synchronized with the ramp signal. The count value of the gradation counter and each pixel value of the horizontal digital video signal latched in the line buffer are compared in pixel units in the comparator, and the count value is latched in the line buffer. The video switch corresponding to the pixel is turned off, and the voltage of the ramp signal at this time is held in the pixel connected to the video switch that is turned off, so that the analog video signal of the input digital video signal Conversion to

  The video switches are turned on all at once by the latch clock signal and start the sampling operation for the parasitic capacitance or the holding capacitance. When the signal when the counter value matches with the counter value is output from the comparator, the video switch is turned off and the ramp signal voltage holding operation immediately before is entered, and this voltage value is also stored in the storage capacitor in the pixel. The written liquid crystal element is driven. This operation is performed in parallel with respect to pixels for one line. Usually, since the video signal is different for each pixel, the ON time of the video switch and the held voltage value are different for each pixel.

  In the liquid crystal display device having such a configuration, for example, when a full high-definition video signal having a scanning line number of 1125 lines is displayed in 10-bit gradation at 60 Hz, which is used for a general television video signal, data is displayed. The sampling rate is 74.25 MHz, and in progressive display, the data sampling rate is about 150 MHz. At this time, the clock frequency of the gradation counter in progressive display is 150 MHz, and a high frequency clock rate is required. In frame N double speed processing of frame double speed, triple speed, quadruple speed, etc., if the data sampling rate is handled in parallel with 2-phase, 3-phase, 4-phase, etc., it is possible to avoid increasing the sampling rate. However, since the clock rate of the gradation counter increases to 2 times, 3 times, 4 times,... 150 MHz, the frequency increases. In addition, when performing stereoscopic display, display for the right eye and the left eye is necessary. Further, when the number of gradations is increased, it is necessary to further increase the clock rate. Therefore, it is a big problem to reduce the clock rate of the gradation counter.

  Therefore, a drive circuit for a liquid crystal display device that prepares a plurality of the ramp signals and selects the ramp signals according to pixel data has been proposed in the past (see, for example, Patent Document 2). In Patent Document 2, a plurality of ramp signals (reference ramp voltages) are prepared, and a reference ramp voltage is selected according to pixel data, thereby preventing an increase in the clock rate of the gradation counter associated with multi-gradation. .

Japanese Patent Publication No. 7-50389 JP 2005-148733 A

However, in the method of preparing a plurality of reference lamp voltages described in Patent Document 2, it is difficult to obtain an accurate gradation due to a difference in each reference lamp voltage. For example, assuming that the amplitude from the white level to the black level of the reference lamp voltage is 4VP-P, when displaying a 10-bit gradation, the potential difference for one gradation is about 4 mV (≈4V / 2 ¹⁰ ). In this case, when two reference ramp voltages are prepared to obtain a 10-bit gradation, the potential difference for one gradation is about 8 mV. However, it is very difficult to connect two kinds of lamp voltages having a small potential difference of about 8 mV without error, and it is a problem that a gradation disturbance occurs in a switching portion between the two lamp voltages.

  The present invention has been made in view of the above points, and provides a liquid crystal display device capable of reducing the clock rate of a grayscale counter and obtaining multiple grayscales using a set of ramp signals. Objective.

  In order to achieve the above object, the liquid crystal display device of the present invention is provided with liquid crystal provided at intersections where a plurality of sets of data lines and a plurality of gate lines intersect each other. Provided for each of a plurality of pixels including an element and a plurality of sets of data lines, a positive video signal is supplied to one of a set of two data lines, and a negative polarity is applied to the other data line A plurality of analog switches for sequentially supplying video signals to a plurality of sets of data lines in units of sets within one horizontal scanning period, and a vertical drive for selecting a plurality of gate lines for each horizontal scanning period. Vertical driving means for performing, latch means for latching a digital video signal composed of a series of pixel data of x bits (x is a natural number of 2 or more) in units of one line, and one horizontal scanning continuously from black level to white level Varies with period And a positive polarity ramp signal and a negative polarity ramp signal that are set in opposite directions of level change are generated, and the positive polarity ramp signal and the negative polarity ramp signal are in the ON state. Ramp signal generating means for supplying a plurality of sets of data lines as a positive video signal and a negative video signal through a plurality of analog switches, and (xy) bits (y is 1 or more x in one horizontal scanning period) Counter means for generating a counter value of a natural number less than), the value of pixel data of upper (xy) bits among the x-bit pixel data of each pixel of one line latched by the latch means, and the counter means Compared with the counter value from the pixel unit, outputs a coincidence pulse when they coincide with each other, turns off the corresponding analog switch among a plurality of analog switches, The comparator means for sampling and holding the potential of the positive polarity ramp signal and the negative polarity ramp signal immediately before the analog switch is turned off and latched by a set of data lines connected to the analog switch and the latch means Of the x-bit pixel data of each pixel in one line, according to the value of the lower y-bit pixel data, sampling is performed on a plurality of sets of data lines after the comparison unit finishes comparing the pixel data of all pixels in one line. Lower-order bit data for changing the potential of each pixel held in this way and writing a video signal of x-bit gradation to each pixel of one line connected to a plurality of sets of data lines in units of sets. And a supply means.

Here, each of the plurality of pixels is
A liquid crystal element in which a liquid crystal layer is sandwiched between a pixel electrode and a common electrode facing each other, and one data line to which a positive polarity ramp signal is supplied out of a set of two data lines. A potential is supplied as a positive video signal, a first sampling and holding means that samples and holds the positive video signal for a certain period, and a negative ramp signal is supplied from a set of two data lines. A second sampling and holding means for supplying a potential held in the other data line as a negative video signal, sampling the negative video signal and holding it for a certain period, and a first sampling and holding means The positive polarity video signal voltage held in the second sampling and the negative polarity video signal voltage held in the second sampling and holding means is switched at a predetermined cycle shorter than the vertical scanning period to thereby form a pixel electrode Characterized in that it comprises a switching means for applying alternately.

  The lower bit data supply means includes a first switch means for selecting lower y bit pixel data among the x bit pixel data latched by the latch means, and a set of two data lines. Among these, a first potential that changes the potential held in one data line to which the positive polarity ramp signal is supplied in the positive direction in accordance with the value of the lower y-bit pixel data input through the first switch means. A first signal output means including a capacitor; a second switch means for selecting the lower y-bit pixel data from among the x-bit pixel data latched by the latch means; and a set of two The potential held in the other data line to which the negative ramp signal is supplied is inverted from the lower y-bit pixel data inputted through the second switch means. And having a second signal output means including a second capacitance that changes in the negative direction in accordance with.

  Here, the first signal output means includes two or more first capacitance adjustment switches that can be switched independently of each other, and two or more first capacitance adjustment switches provided corresponding to the first capacitance adjustment switches. The second signal output means corresponds to two or more second capacitance adjustment switches that can be switched independently of each other and a second capacitance adjustment switch. The structure which consists of two or more provided 2nd capacity | capacitances and 2nd resistance may be sufficient.

  According to the present invention, the clock rate of the gradation counter can be reduced, and (x + y) bits are used by using a set of ramp signals used to obtain an analog conversion value of x-bit pixel data. Can be obtained.

It is a block diagram of one embodiment of the liquid crystal display device of the present invention. FIG. 2 is a circuit diagram illustrating a configuration of a horizontal driver circuit of the liquid crystal display device of FIG. 1. FIG. 2 is an equivalent circuit diagram of an example of the pixel in FIG. 1. 4 is a timing chart for explaining an outline of AC drive control of a liquid crystal display device having the pixel circuit shown in FIG. 3. It is a figure which shows the relationship from the black level of a positive polarity video signal written in a pixel, and a negative polarity video signal to a white level. 3 is a timing chart for explaining the operation of the horizontal driver circuit of FIG. 2. FIG. 3 is a diagram showing an example of written gradations of adjacent pixels a to a + 4 after an analog switch connected to a positive polarity data line D + according to the embodiment of FIGS. 1 and 2; FIG. 3 is a diagram showing an example of written gradations of adjacent pixels a to a + 4 after the analog switch connected to the negative polarity data line D− according to the embodiment of FIG. 1 and FIG. 2. It is a figure which shows the 1st connection structural example of the data line D + for positive polarity, and the least significant bit switch. It is a figure which shows the 1st connection structural example of the data line D- for negative polarity, and the least significant bit switch. It is a figure which shows an example of the gradation written in the adjacent pixel a to a + 4 after the least significant bit switch connected to the data line D + for positive polarity was turned on. It is a figure which shows an example of the gradation written in the adjacent pixel a to a + 4 after the least significant bit switch connected to the data line D- for negative polarity was turned on. It is a figure which shows the 2nd connection structural example of the data line D + for positive polarity, and a least significant bit switch. It is a figure which shows the 2nd connection structural example of the data line D- for negative polarity, and a least significant bit switch. It is a figure which shows the example of a connection structure of the data line D + for positive polarity, and a lower 2 bits switch. It is a figure which shows the example of a connection structure of the data line D- for negative polarity, and a switch of lower 2 bits.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a configuration diagram of an embodiment of a liquid crystal display device according to the present invention, and FIG. 2 is a circuit diagram of a horizontal driver circuit in FIG. In both drawings, the same components are denoted by the same reference numerals.

  As shown in FIG. 1, the liquid crystal display device 100 includes shift register circuits 101a and 101b, a one-line latch circuit 102, a comparator 103, a gradation counter 104, an inverter 105, an analog switch 106, and a least significant bit. The switch 107 includes m pixels in the horizontal direction and n pixels arranged in a matrix in the vertical direction, a timing generator 109, a polarity switching control circuit 110, and a vertical shift register and level shifter 111. .

  The shift register circuits 101a and 101b, the one-line latch circuit 102, the comparator 103, and the gradation counter 104 constitute a horizontal driver circuit. This horizontal driver circuit constitutes a data line driving circuit together with the inverter 105, the analog switch 106, and the least significant bit switch 107. The data line driving circuit is also shown in FIG. The comparator 103 is shown as one block in FIG. 1 for the sake of simplicity, but actually, it is provided for each pixel column as shown in FIG.

  The analog switch 106 shown in FIGS. 1 and 2 has a configuration in which a pair of sampling analog switches for positive polarity and negative polarity are arranged for each pixel column. 1 includes a total of m data lines (D1 + and D1-),..., (Dm + and Dm-) and n gate lines (row scanning). Lines) are arranged at intersections with G1, ..., Gn.

  Here, the circuit configuration and operation of one of the n · m pixels 108 will be described with reference to FIGS. FIG. 3 shows an equivalent circuit diagram of an example of the pixel 108. As shown in FIG. 3, the pixel circuit, which is an equivalent circuit of the pixel 108, connects pixel selection switching transistors Q1 and Q2 for writing positive and negative video signals, and video signal voltages of respective polarities in parallel. Two independent holding capacitors Cs1 and Cs2 that are held in the memory, transistors Q3 and Q4 whose gates are connected to the signal storage nodes of the holding capacitors Cs1 and Cs2, and drains that are connected to the sources of the transistors Q3 and Q4. Transistors Q5 and Q6, transistor Q7, and liquid crystal element LC.

  The transistor Q3 forms a first impedance conversion buffer (source follower) circuit. Similarly, the transistor Q4 constitutes a second impedance conversion buffer (source follower) circuit. The output terminals (the sources of Q5 and Q6) of the first and second impedance conversion buffer circuits are connected to the drains of the transistors Q5 and Q6. The transistors Q5 and Q6 are polarity switching switching transistors that can individually control conduction / non-conduction of the impedance conversion buffer circuit output with respect to the pixel electrode PE.

  The drain of the constant current load transistor Q7 of the source follower circuit is connected to a connection point between the sources of the transistors Q5 and Q6 and the pixel electrode PE of the liquid crystal element LC. The transistor Q7 is configured to function in common as a constant current load element of both the source follower circuits (Q3, Q4). Like the conventional liquid crystal element, the liquid crystal element LC has a configuration in which a display body (liquid crystal layer) LCM is sandwiched between the pixel electrode PE and the common electrode CE facing each other.

  The data line of the pixel portion is composed of a set of two positive polarity data lines Di + and negative polarity data lines Di− for each pixel circuit, and video signals having different polarities sampled by a data line driving circuit (not shown). Is supplied. The input drain terminals of the write switching transistors Q1 and Q2 are connected to the data lines Di + and Di-, respectively, and the gate terminals are connected to the gate line (row scanning line) Gj for the same row. When a scanning pulse is supplied from a vertical scanning circuit (not shown), the writing switching transistors Q1 and Q2 are simultaneously turned on, and positive and negative video signal voltages are accumulated in the holding capacitors Cs1 and Cs2, respectively.

  The gate of the constant current source load transistor Q7 is commonly wired as the wiring B in the row direction for the same row pixel, and the bias control of the constant current load is possible. The input resistance of each source follower circuit of the MOS transistors Q3 and Q4 is almost infinite, and the charge accumulated in the storage capacitor terminal does not leak as in the conventional active matrix liquid crystal display device, and the signal is output after one vertical scanning period. Is held until it is newly written.

  The switching transistors Q5 and Q6 switch and send the output signal of the source follower circuit to the liquid crystal element LC including the pixel electrode PE, the liquid crystal display LCM, and the common electrode CE. The gate terminals of the transistor Q5 for switching the positive video signal and the transistor Q6 for switching the negative video signal are independent of each other, and each of them is wired as wirings S + and S− in the row direction for the same row pixel. Has been. By alternately sending on / off control pulses to the wirings S + and S-, the switching transistors Q5 and Q6 are alternately turned on to give a liquid crystal drive signal that is inverted to positive and negative polarity to the pixel drive unit. it can. The pixel circuit shown in FIG. 3 has a polarity inversion function in the circuit itself, and can be driven at a high frequency without restriction of the vertical scanning frequency by controlling the switching transistors Q5 and Q6 at high speed. .

  Next, an outline of AC drive control of the liquid crystal display device of the present embodiment will be described with reference to the timing chart of FIG. 4A is a vertical synchronizing signal which is a reference for vertical scanning of the video signal, and FIG. 4B is a control of load characteristics supplied to the gate of the constant current load transistor Q7 of the source follower buffer in the pixel circuit of FIG. FIG. 4C shows the gate control signal of the switching transistor Q5 shown in FIG. 3 that transfers the positive video signal through the wiring S +, and FIG. 4D shows the transmission of the negative video signal through the wiring S−. 3 is a gate control signal of the switching transistor Q6 shown in FIG.

  FIG. 5 shows the relationship from the black level to the white level of the positive video signal I and the negative video signal II written to the pixel. The positive video signal I has a black level when the level is minimum and a white level when the level is maximum, whereas the negative video signal II has a white level when the level is minimum and a black level when the level is maximum. The inversion center of the positive video signal I and the negative video signal II is indicated by III.

  In FIG. 5, the positive video signal I has a black level when the level is minimum and a white level when the level is maximum, whereas the negative video signal II has a white level and maximum when the level is minimum. Although the case of the black level is shown, in the pixel circuit of the liquid crystal display device of the present invention, the positive video signal is the white level when the level is minimum, the black level when the level is maximum, and the negative video signal is the level. The black level may be at the minimum, and the white level at the maximum.

  In the pixel circuit shown in FIG. 3, the positive polarity side switching transistor Q5 is turned on while the gate control signal of the wiring S + shown in FIG. When the signal is set to the high level as shown in FIG. 4B, the source follower buffer circuit becomes active, and the pixel electrode PE node is charged to the positive video signal level. When the potential of the pixel electrode PE is fully charged, the load characteristic control signal of the wiring B is set to a low level, and at that time, the gate control signal of the wiring S + is also switched to a low level. PE becomes floating, and a positive drive voltage is held in the liquid crystal capacitor.

  On the other hand, the negative polarity side switching transistor Q6 is turned on while the gate control signal of the wiring S− shown in FIG. 4D is at a high level, and the load characteristic control signal supplied to the wiring B during this period is shown in FIG. ), The source follower buffer circuit becomes active and the pixel electrode PE node is charged to a negative video signal level. When the potential of the pixel electrode PE is fully charged, the load characteristic control signal of the wiring B is set to low level, and the gate control signal of the wiring S- is also switched to low level at that time, the pixel electrode PE becomes floating, and the negative drive voltage is held in the liquid crystal capacitor.

  In the following, the pixel electrode PE of the liquid crystal element has a positive polarity and a negative polarity by repeating the operation of intermittently activating the constant current load transistor Q7 in synchronization with the switching in which the switching transistors Q5 and Q6 are alternately turned on. A drive voltage VPE converted into an alternating current by each video signal is applied as shown in FIG.

  The pixel circuit of FIG. 3 is configured to supply a voltage via the source follower buffer circuit, instead of transferring the held charge directly to the pixel driving unit, so that even if charge / discharge is repeatedly performed with positive and negative polarity, There is no problem of neutralization, and driving without attenuation of the voltage level can be realized even if the polarity is switched many times.

  Further, Vcom shown in FIG. 4F represents a voltage applied to the common electrode CE formed on the counter substrate of the liquid crystal display device. The substantial AC drive voltage of the liquid crystal display LCM is a difference voltage between the applied voltage Vcom of the common electrode CE and the applied voltage VPE of the pixel electrode PE. In the present embodiment, as shown in FIG. 4F, the applied voltage Vcom of the common electrode CE is synchronized with the pixel polarity switching with respect to a reference level substantially equal to the inversion reference level Vc of the pixel electrode voltage VPE. Inverted. As a result, the absolute value of the potential difference between the applied voltage Vcom of the common electrode CE and the applied voltage VPE of the pixel electrode PE is always the same, and the liquid crystal display LCM has an AC voltage having no DC component as shown in FIG. VLC is applied.

  As described above, in the present embodiment in which the driving shown in the timing chart of FIG. 4 is performed with respect to the pixel circuit of FIG. 3, the application voltage Vcom of the common electrode CE is switched in the opposite phase to the pixel electrode voltage VPE. The amplitude of the drive voltage VPE on the (PE) side can be reduced to about 1/2 or less. As a result, the required breakdown voltage of the transistors constituting the pixel circuit and the peripheral scanning circuit is greatly reduced, the application of a special high breakdown voltage structure and process is not required, and a normal logic process can be applied, thereby reducing the manufacturing cost. . In addition, in the pixel driving method of the present embodiment, since a driving unit such as a pixel circuit can be configured with a low breakdown voltage and small transistor as described above, a liquid crystal display device with a higher pixel density can be realized, and the transistor breakdown voltage can be reduced. Since it is possible to employ a transistor having a high driving capability per unit channel width, it is possible to easily cope with a high-speed driving operation.

  In consideration of the reduction in current consumption in the liquid crystal display device, as shown in FIG. 4B, the load characteristic control signal of the wiring B is used as a pulse train, and the constant current load transistor Q7 of the source follower buffer circuit is always active. Instead, control is performed so that the polarity switching switching transistors Q5 and Q6 become active only during a limited period of the conduction period. For example, even if the current of the steady source follower buffer circuit per pixel circuit is a very small current of 1 μA, a large current is consumed under the condition that all the pixels of the liquid crystal display device constantly consume the current. There is a problem that. For example, in a full high-definition (2 million pixels) liquid crystal display device, the current consumption reaches 2 A.

  Therefore, in the present embodiment, as shown in FIGS. 4B to 4D, the polarity switching switching transistor in which the gate control signal supplied through the polarity switching wirings S + and S− is at a high level. Only during the conduction period of Q5 and Q6, the load characteristic control signal supplied via the wiring B is set to the high level to limit the driving period of the constant current load transistor Q7 of the source follower buffer circuit. As a result, immediately after the pixel electrode voltage VPE of the liquid crystal element is charged and discharged to the target level as shown in FIG. 4D, the load characteristic control signal immediately becomes low level as shown in FIG. Then, the constant current load transistor Q7 is turned off, and the current of the source follower buffer circuit is stopped. Therefore, according to the present embodiment, it is possible to suppress a substantial current consumption while having a configuration in which a buffer is provided for all pixels.

  By the way, in the liquid crystal display device 100 having such a feature, in the present embodiment, the clock rate of the gradation counter is lowered, so that multiple gradations are obtained using one ramp signal. Returning to FIG. 1 and FIG.

  The polarity switching control circuit 110 shown in FIG. 1 is based on the timing signal from the timing generator 109, and has the positive polarity switch control signal for the wiring S +, the negative polarity switch control signal for the wiring S−, and the load characteristic for the wiring B. Control signals are output respectively. The vertical shift register and level shifter 111 shown in FIG. 1 sequentially outputs gate signals to the gate lines (row scanning lines) G1 to Gn in one horizontal scanning period (1H period), and outputs the gate lines G1 to Gn by one horizontal. Select sequentially in the scan cycle.

  Next, the operation of the horizontal driver circuit in FIGS. 1 and 2 will be described with reference to the timing chart of FIG. 1 and 2, a digital video signal in which, for example, 10-bit pixel data (DATA) shown in FIG. 6B, which is synchronized with the horizontal synchronizing signal HD shown in FIG. The data is sequentially developed as data for one line by the shift register circuits 101a and 101b, and is latched by the one-line latch circuit 102 when the development for one line is completed.

  Of the pixel data (DATA) shown in FIG. 6B, horizontal even-numbered column pixel data DATA (even) shown every other white background is supplied to the shift register circuit 101a, and the remaining hatched lines are shown. Every other odd-numbered pixel data DATA (odd) in the horizontal direction is supplied to the shift register circuit 101b. This is because it is easy to cope with high-speed operation on a high-resolution panel.

  The one-line latch circuit 102 is a one-line period of the same line composed of odd-numbered column pixel data DATA (odd) output from the shift register circuit 101a and even-numbered column pixel data DATA (even) output from the shift register circuit 101b. This pixel data DATA is held as schematically shown in FIG.

  Also, as shown in FIGS. 1 and 2, the 1-line latch circuit 102 outputs only the upper 9 bits of the 10-bit pixel data of one line period held, and the comparator 103 of each pixel column The first data input unit is supplied. Also, the 1-line latch circuit 102 does not pass through the comparator 103 and outputs the least significant bit output to the least significant bit data line Dlsb among the pixel data DATA of one line period held therein. The data is output to the data line D + via the switch 107a, and the value of the least significant bit output to the least significant bit data line Dlsb is inverted by the inverter 105, and then output to the data line D- via the least significant bit switch 107b. To do. That is, the least significant bit switch 107 is composed of a pair of a switch 107a for the data line D + and a switch 107b for the data line D-.

  The gradation counter 104 is a counter that outputs a 9-bit counter value. The gradation counter 104 counts the clock Count-CK shown in FIG. 6E, and a plurality of gradation values are horizontally displayed as shown in FIG. The reference gradation data C-out, which is a counter value that sequentially changes from the minimum value to the maximum value within the scanning period, is output and supplied to the second data input unit of the comparator 103 of each pixel column. That is, the reference gradation data C-out is a counter value that makes a round from the minimum gradation value to the maximum gradation value in one horizontal scanning period.

  The comparator 103 compares the value of the input pixel data DATA of the first data input unit with the value of the input reference gradation data C-out (gradation value) of the second data input unit, and the two values match. A coincidence pulse is generated and output at the same timing.

  In each pixel column, a pair of sampling analog switches 106 for positive polarity and negative polarity are arranged. Among the analog switches 106, the sampling analog switch for positive polarity has a reference ramp voltage (ramp signal) Ref_Ramp (+) applied to the input side common wiring. On the other hand, in the negative sampling analog switch, the reference ramp voltage (ramp signal) Ref_Ramp (−) is applied to the input-side common wiring.

  Of the reference ramp voltages Ref_Ramp (+) and Ref_Ramp (−) generated by a reference voltage generation circuit (not shown), Ref_Ramp (+) is the black level of the video in the horizontal scanning period as shown in FIG. This is a periodic sweep signal that changes from white level to white level. On the other hand, the reference ramp voltage Ref_Ramp (−) is a periodic sweep signal that changes in a direction in which the level decreases from the black level to the white level of the image in the horizontal scanning period as shown in FIG. 6 (J). . Therefore, the reference lamp voltages Ref_Ramp (+) and Ref_Ramp (−) have an inversion relationship with respect to a predetermined reference potential.

  The analog switch 106 receives the SW-Start signal shown in FIG. 6 (G), turns on at the same time at the start of the horizontal scanning period, and then turns off when the coincidence pulse is received from the comparator 103. Open / close controlled. Corresponding to the analog switch 106 which is turned off in response to the coincidence pulse from the comparator 103 among the m pixels on the same line selected by supplying the scanning pulse output from the vertical shift register / level shifter 111 in the 1H cycle. The positive reference lamp voltage Ref_Ramp (+) and the negative reference lamp voltage Ref_Ramp (-) immediately before the analog switch 106 is turned off are written in the signal holding capacitors Cs1 and Cs2 provided in the pixel. Retained.

  In the timing chart of FIG. 6, as an example, the opening / closing timing of the analog switch 106 in the pixel column corresponding to the pixel data DATA of the upper 9-bit gradation level kk is shown as a waveform SPk shown in FIG. As a result, the reference ramp voltage Ref_Ramp (+) at the time when the pair of sampling analog switches for positive polarity and negative polarity constituting the analog switch 106 of the pixel column are simultaneously turned off in response to the coincidence pulse. And Ref_Ramp (−) corresponding levels (point PP and point QQ in FIGS. 6 (I) and (J)) are simultaneously sampled on the data lines D + and D− of the pixel column. The data line D + corresponds to Di + in FIG. 3, and is one or more of m positive data lines D1 (+) to Dm (+) shown in FIGS. Data lines are shown generically. Similarly, the data line D- corresponds to Di- in FIG. 3, and one or two of the m negative polarity data lines D1 (-) to Dm (-) shown in FIGS. The above data lines are shown generically.

  FIG. 7 shows gradations written from adjacent pixels a to a + 4 after the analog switch 106 connected to the positive data line D + according to the embodiment of FIGS. 1 and 2 is turned off according to this embodiment. It is a figure which shows an example. However, the least significant bit switch 107a is off. FIG. 7 shows a case where data that is increased by one gradation in 10-bit gradation is written from the adjacent five pixels a to a + 4 of the pixels 108 via the positive data line D +. ing. As shown in FIG. 7, even if the input pixel data is 10 bits, the gradation written in the pixel corresponds to the value of the upper 9-bit pixel data after the analog switch 106 is turned off in this embodiment. The reference ramp voltage Ref_Ramp (+) is obtained and only the upper 9 bits of gradation of the pixel data can be obtained, so that the gradations of two adjacent pixels (pixel a and pixel a + 1, pixel a + 2 and a + 3) have the same value. It becomes brightness.

  Further, in FIG. 8, writing is performed from adjacent pixels a to a + 4 after the analog switch 106 connected to the negative polarity data line D− according to the embodiment of FIGS. 1 and 2 is turned off according to this embodiment. It is a figure which shows an example of a gradation. However, the least significant bit switch 107b is off. FIG. 8 shows a case where data that has been increased by one gradation in the 10-bit gradation is written from the adjacent five pixels a to a + 4 of the pixels 108 via the negative polarity data line D−. ing. As shown in FIG. 8, even if the input pixel data is 10 bits, in this embodiment, the gradation written in the pixel corresponds to the value of the upper 9-bit pixel data after the analog switch 106 is turned off. The reference ramp voltage Ref_Ramp (−) is obtained, and only the upper 9 bits of gradation of the pixel data can be obtained. Therefore, as shown in FIG. 8, two adjacent pixels (pixel a and pixel a + 1, pixel a + 2 and a + 3) The gradation has the same luminance value.

  When the reference ramp voltages Ref_Ramp (+) and Ref_Ramp (-) reach the white level, all the pixel data should have finished matching the count value of the gradation counter 104, so all the analog switches 106 are off. In this state, sampling of all the data lines D + and D- is completed, and the voltage of the upper 9 bits of pixel data is held by the data line capacity.

  In this embodiment, the least significant bit switch 107 (107a, 107b) is turned on by the switch control signal LSBSW at this time. As a result, the least significant bit switch 107 (107a, 107b) directly compares the least significant bit pixel data latched in the one-line latch circuit 102 with the least significant bit data without comparing with the gradation counter 104. The data is output to the line Dlsb and through the inverter 105 to the least significant bit data line Dlsb.

  FIG. 9 shows a first connection configuration example between the data line D + for sampling the reference ramp voltage Ref_Ramp (+) and the least significant bit switch 107a. As shown in FIG. 9, the least significant bit switch 107a connected to the least significant bit data line Dlsb is grounded to the GND via the resistor Ra and disposed via the data line D + and the least significant bit capacitor 120a. Has been. The data line D + has a data line capacitance 121a.

  FIG. 10 shows a first connection configuration example between the data line D− for sampling the reference ramp voltage Ref_Ramp (−) and the least significant bit switch 107b. As shown in FIG. 10, the least significant bit switch 107b connected to the least significant bit data line Dlsb is connected to VDD via the resistor Rb and arranged via the data line D− and the least significant bit capacitance 120b. Has been. Note that the data line D- has a data line capacitance 121b. The bit switch 107b receives the data of the least significant bit of the negative pixel data whose logic value is inverted by the inverter 105 connected to the least significant bit data line Dlsb.

  In the present embodiment, when the reference lamp voltage Ref_Ramp (+) reaches the white level, the least significant bit switch 107a is turned on by the switch control signal LSBSW. As a result, the voltage of the least significant bit data is applied to the data line D + via the least significant bit switch 107a and the least significant bit capacitor 120a. Here, the value of the resistor Ra is set so that the voltage is correctly applied to the data line D + when the least significant bit data is output, and is set to 100 kΩ, for example.

  Therefore, when the least significant bit data is “0”, a low level is output to the data line D +, and the potential of the data line D + remains as it is (the potential based on the upper 9 bits of pixel data). On the other hand, when the least significant bit data is “1”, the least significant bit switch 107a outputs a high level to the least significant bit data line Dlsb, and raises the potential of the data line D + by 4 mV in the white level direction. Control the tone (brightness) to increase.

  Similarly to the above, in this embodiment, when the reference lamp voltage Ref_Ramp (−) reaches the white level, the least significant bit switch 107b shown in FIG. 10 is turned on by the switch control signal LSBSW. As a result, the voltage of the least significant bit data is applied to the data line D− via the least significant bit switch 107b and the least significant bit capacitor 120b. Here, the value of the resistor Rb is set so that the voltage is correctly applied to the data line D− when the least significant bit data is output, and is set to 100 kΩ, for example.

  Therefore, when the least significant bit data is “0”, the logic value is inverted by the inverter 105 and a high level is output to the data line D−, and the potential of the data line D− remains as it is (the upper 9 bit pixel). Data potential). On the other hand, when the least significant bit data is “1”, the least significant bit switch 107b inverts the logical value by the inverter 105 and outputs a low level to the least significant bit data line Dlsb, and the potential of the data line D− is set to white. Control is performed so that the gradation (luminance) increases by 1 mV in the level direction by 1 mV.

  The data lines D + and D- are formed such that the voltage crosstalks with the least significant bit data from the least significant bit switches 107a and 107b, thereby obtaining the gradation potential for the least significant bits.

  As a result, when data that is increased by one gradation in the 10-bit gradation is written to the adjacent five pixels a to a + 4 of the pixels 108 via the positive data line D +, the writing is performed. 7 is turned on by turning on the least significant bit switch 107a from the state shown in FIG. 7, the potentials of the positive polarity data line of the pixel a + 1 and the positive polarity data line of the pixel a + 3 as shown in FIG. Since the luminance increases by one gradation according to the bit data, the original 10-bit gradation can be obtained.

  Similarly, when data that has been increased by one gradation in the 10-bit gradation is written to the adjacent five pixels a to a + 4 of the pixels 108 via the negative-polarity data line D−. As shown in FIG. 12, when the least significant bit switch 107b is turned on from the state shown in FIG. 8, the gradation of the negative polarity data line of the pixel a + 1 and the negative polarity data line of the pixel a + 3 is the highest. The lower 10-bit data is reduced by one gradation and the brightness is increased, so that the original 10-bit gradation is obtained.

  While the least significant bit switches 107a and 107b are kept on, the transistors in the pixels connected to the gate lines (row scanning lines) are turned off, whereby the 10-bit gradation pixels held in the signal holding capacitors The potential is determined.

  Note that in order to actually change the potential by 4 mV for one gradation, it is necessary to estimate how much the capacity for crosstalking the data lines D + and D− should be estimated. It is assumed that the capacitance of the data lines D + and D− is 1 pF, for example. It is created by forming certain least significant bit capacitors 120a, 120b between the least significant bit data line Dlsb and the data line. The least significant bit capacitors 120a and 120b are preferably formed between the wirings.

  If it is desired to form an accurate capacitance, a gate oxide film between the polysilicon and the silicon substrate may be used. The least significant bit data output may be logic, and if the power supply voltage of the transistor in the one-line latch circuit 102 that drives the data output line of the least significant bit of the positive polarity pixel data is 5 V, the data lines D + and D- The least significant bit capacitances 120a and 120b necessary for changing the potential of 4 mV are 0.8 fF.

  As a result, when the least significant bit data is “1”, the luminance of the pixel data is increased by a half gradation in a 9-bit gradation, and a 10-bit gradation can be achieved as a whole.

  As described above, according to the liquid crystal display device 100 of the present embodiment, the gradation counter 104 obtains a 9-bit counter value output to be compared with the value of the upper 9 bits of the pixel data instead of all 10 bits of the pixel data. Since the configuration is adopted, the clock Count-CK of the gradation counter 104 can be made to have a lower frequency than the clock used in the conventional gradation counter that outputs a 10-bit counter value.

  Further, according to the liquid crystal display device 100 of the present embodiment, the data lines D + (D1 (+) to Dm (+) are generated using a set of ramp signals (reference ramp voltages Ref_Ramp (+) and Ref_Ramp (-)). )), D- (D1 (-) to Dm (-)), the potential corresponding to the value of the upper 9 bits of the 10-bit pixel data sampled and held, and the least significant bit switches 107a and 107b. Since it is provided and changed in accordance with the value of the lower 1 bit of the pixel data, it is possible to obtain 10-bit gradation more than 9 bits compared by the comparator 103.

  Further, in the liquid crystal display device 100 of the above embodiment, the least significant bit capacitances 120a and 120b may be as small as 0.8 fF in the above example, so that a large area capacitance is not particularly required. Therefore, a 10-bit gradation can be obtained by using a set of ramp signals used to obtain an analog conversion value of 9-bit pixel data without affecting the increase in chip area.

  Next, another connection configuration example between the data lines D + and D− and the least significant bit switch will be described.

FIG. 13 shows a second connection configuration example between the data line D + for sampling the reference ramp voltage Ref_Ramp (+) and the least significant bit switch 107a. As shown in FIG. 13, the least significant bit switch 107a connected to the least significant bit data line Dlsb is connected to GND via _four capacitance adjusting switches 131 _{1 to} 131 ₄ and via resistors R1 to R4 separately. And the four least significant bit capacitors 132 _{1 to} 132 ₄ are separately arranged on the data line D +. The data line D + has a data line capacitance 121a.

FIG. 14 shows a second connection configuration example between the data line D− for sampling the reference ramp voltage Ref_Ramp (−) and the least significant bit switch 107b. As shown in FIG. 14, the least significant bit switch 107b connected to the least significant bit data line Dlsb is connected to VDD via _four capacitance adjustment switches 133 _{1 to} 133 ₄ in parallel and further via resistors R5 to R8 separately. And the _four least significant bit capacitors 134 _{1 to} 1344 are separately arranged on the data line D−. Note that the data line D- has a data line capacitance 121b. The bit switch 107b receives the data of the least significant bit of the negative polarity pixel data whose logic value is inverted by the inverter 105 connected to the least significant bit data line Dlsb.

In the first connection configuration example of the data lines D +, D− and the least significant bit switches 107a, 107b shown in FIG. 9 and FIG. 10, the lowest necessary for changing the data lines D +, D− by 4 mV potential. Since the lower bit capacities 120a and 120b are as small as 0.8 fF, it may be difficult to obtain 0.8 fF accurately. On the other hand, in the second connection configuration example of the data lines D + and D− and the least significant bit switches 107a and 107b shown in FIGS. 13 and 14, the capacity adjustment switches 131 _{1 to} 131 ₄ and 133 _{1 to} 133 _{4 are used.} Is appropriately turned on or off, and the parallel combined capacitance value obtained by appropriately selecting the least significant bit capacitors 132 _{1 to} 132 ₄ and 134 _{1 to} 1344 can be adjusted to accurately change to ₄ mV luminance.

  The gradation can be further improved by preparing a plurality of capacity changeover switches and changing the least significant bit capacity. Next, a method in which the gradation counter 104 realizes an 11-bit gradation using a 9-bit clock rate will be described.

  FIG. 15 shows a connection configuration example of the data line D + for sampling the reference ramp voltage Ref_Ramp (+) and the lower 2-bit switch corresponding to 2 bits from the least significant bit. As shown in FIG. 15, the bit switches 107a1 and 107a2 connected to the lowest-order bit data line Dlsb and the lower-order 2-bit data line D12b that outputs the lower-order second bit data, which is one bit higher than the lowest-order bit, 141.

Further, the decoder 141 is connected to _three capacitance adjustment switches 143 _{1 to} 143 3 via _three buffers 142 _{1 to} 142 ₃ in parallel. Further, the capacity adjustment switches 143 _{1 to} 143 ₃ are grounded to GND via the resistors R11 to R13 separately, and are arranged on the data line D + via the _three least significant bit capacitors 144 _{1 to} 144 ₃ separately. ing. The data line D + has a data line capacitance 121a. The bit switches 107a1 and 107a2 are switches to which positive two-bit pixel data is input.

  FIG. 16 shows a connection configuration example of the data line D− for sampling the reference ramp voltage Ref_Ramp (−) and the lower 2-bit switch corresponding to 2 bits from the least significant bit. As shown in FIG. 16, the bit switches 107b1 and 107b2 are connected to the decoder 151 to the lowest-order bit data line Dlsb and the lower-order 2-bit data line Dl2b that outputs the lower-order second bit data that is one bit higher than the lowest-order bit. Has been.

Further, the decoder 151 is connected to _three capacity adjustment switches 153 _{1 to} 153 3 via _three buffers 152 _{1 to} 152 ₃ in parallel. Further, the capacitance adjustment switches 153 _{1 to} 153 ₃ are connected to the VDD via the resistors R21 to R23 separately, and are disposed on the data line D− via the _three least significant bit capacitors 154 _{1 to} 154 ₃ separately. Has been. Note that the data line D- has a data line capacitance 121b. The bit switches 107b1 and 107b2 are input with lower two bits of negative polarity pixel data whose logical values are inverted by the inverters 105 ₁ and 105 ₂ .

15 and 16, the capacitance values of the least significant bit capacities 144 _{1 to} 144 ₃ and 154 _{1 to} 154 ₃ are selected to be 0.4 fF. The decoders 141 and 151 decode the lower 2 bits of the pixel data. When the lower 2 bits are “0” (00), all the _three capacitance adjustment switches 143 _{1 to} 143 ₃ and 153 _{1 to} 153 ₃ are turned off. When the lower two bits of data are “1” (01), one capacitance adjustment switch is turned on and the luminance of the lower bit data output line for 0.4 fF is changed by 2 mV.

  When the lower 2 bits of data are “2” (10), the two capacitance adjustment switches are turned on, and the luminance is changed by 4 mV by the lower bit data output line for 0.8 fF. When the lower 2 bits of data are “3” (11), all three capacitance adjustment switches are turned on and the luminance of the lower bit data output line for 1.2 fF is changed by 6 mV. Thereby, all the 11-bit gradation is obtained by changing the potential of the gradation voltage of the higher-order 9-bit data written in the data line using the lower-order 2-bit data.

  If this method is used, the number of gradations can be further increased by using one ramp signal and the low clock rate of the gradation counter 104.

  The circuit configuration and operation of the preferred embodiment of the present invention have been described above. According to the liquid crystal display device 100 of the present embodiment, it is possible to supply each pixel with a gray scale higher than the clock rate of the gray scale counter 104 from one ramp signal (reference ramp voltage) with a simple configuration.

  The present invention is not limited to the above embodiment. For example, in the above embodiment, the potential of the upper 9 bits of 10-bit pixel data sampled on the data lines D + and D− is set. The 10-bit gradation is obtained by changing the value according to the value of the lower 1 bit of the pixel data, but the number of lower bits is not limited to 1 bit. That is, according to the present invention, when the total number of bits of pixel data is x bits, the potential of upper (xy) bits sampled on the data line is a value of lower y bits (y is 1 or more and less than x). What is necessary is just to change according to.

  Further, the pixel 108 is not limited to the equivalent circuit (pixel circuit) shown in FIG. 3. For example, instead of the transistor Q 7, a constant current load transistor is separately provided on each source side of the transistors Q 3 and Q 4. It is good.

DESCRIPTION OF SYMBOLS 100 Liquid crystal display device 101a, 101b Shift register circuit 102 1 line latch circuit 103 Comparator 104 Gradation counter 105 Inverter 106 Analog switch 107, 107a, 107b Least significant bit switch 107a1, 107a2, 107b1, 107b2 Lower 2 bit switch 108 Pixel 109 The timing generator 110 polarity switching control circuit 111 the vertical shift register / shifter _{120a, 120b, 132 1 ~132 4} , 134 1 ~134 4, 144 1 ~144 3, 154 1 ~154 3 least significant bit capacity 121a, 121b data lines Capacity 131 _{1 to} 131 ₄ , 133 _{1 to} 133 ₄ Capacity adjustment switch 141, 151 Decoder 143 _{1 to} 143 ₃ , 153 _{1 to} 153 ₃ Capacity changeover switch D +, D i +, D1 (+) to Dm (+) Positive polarity data line D-, Di-, D1 (-) to Dm (-) Negative polarity data line Dlsb Least significant bit data line Dls2 Lower order 2 bit data line Gj, G1 to Gn gate lines (row scanning lines)
S +, S- Gate control signal wiring B Load characteristics control signal wiring
Ref_Ramp (+) and Ref_Ramp (-) Reference ramp voltage (ramp signal)
Q1, Q2 Pixel selection switching transistor Q3, Q4 Source follower transistor Q5, Q6 Switching transistor Q7 Constant current load transistor Cs1 and Cs2 Retention capacitance LC Liquid crystal element PE Pixel electrode CE Common electrode LCM Display (Liquid crystal layer)

Claims (4)

A plurality of pixels each having a liquid crystal element provided at an intersection where a plurality of sets of data lines and a plurality of gate lines intersect each other, each of which includes two data lines;
Provided for each of the plurality of sets of data lines, supplying a positive video signal to one of the two data lines and supplying a negative video signal to the other data line A plurality of analog switches that sequentially perform a group unit within one horizontal scanning period with respect to the plurality of data lines;
Vertical driving means for performing vertical driving for selecting a plurality of the gate lines for each horizontal scanning period;
Latch means for latching a digital video signal composed of a series of x-bit (x is a natural number of 2 or more) pixel data in units of one line;
A positive polarity ramp signal and a negative polarity ramp signal that are continuously changed from a black level to a white level in one horizontal scanning period and whose level change directions are opposite to each other are generated. A ramp signal generating means for supplying the positive video signal and the negative video signal to the plurality of sets of data lines through the plurality of analog switches when the signal and the negative ramp signal are in an ON state;
Counter means for generating a counter value of (x−y) bits (y is a natural number greater than or equal to 1 and less than x) in one horizontal scanning period;
Of the x-bit pixel data of each pixel of one line latched by the latch means, the value of the upper (xy) bit pixel data and the counter value from the counter means are compared in pixel units. The coincidence pulse is output when they coincide with each other, the corresponding analog switch among the plurality of analog switches is turned off, and the set of data lines connected to the analog switch that is turned off, Comparison means for sampling and holding the potential of the positive polarity ramp signal and the negative polarity ramp signal immediately before the analog switch is turned off;
Of the x-bit pixel data of each pixel in one line latched by the latch means, the comparison means finishes comparing pixel data of all pixels in one line according to the value of lower y-bit pixel data. By changing the potential of each pixel sampled and held in the plurality of sets of data lines, the x bit of each pixel is connected to the plurality of sets of data lines in a set unit. A liquid crystal display device comprising: lower bit data supply means for writing a gradation video signal. Each of the plurality of pixels is
The liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode;
The potential held in one data line to which the positive polarity ramp signal is supplied is supplied as the positive polarity video signal, and the positive polarity video signal is sampled. First sampling and holding means for holding for a certain period,
The potential held in the other data line to which the negative ramp signal is supplied is supplied as the negative video signal, and the negative video signal is sampled. Second sampling and holding means for holding for a certain period of time;
Switching between the positive video signal voltage held in the first sampling and holding means and the negative video signal voltage held in the second sampling and holding means at a predetermined cycle shorter than the vertical scanning period. The liquid crystal display device according to claim 1, further comprising: a switching unit that alternately applies to the pixel electrode. The lower bit data supply means includes
First switch means for selecting lower y-bit pixel data among the x-bit pixel data latched by the latch means;
The lower y-bit pixel data inputted through the first switch means, the potential held in one data line to which the positive polarity ramp signal is supplied out of a set of the two data lines. First signal output means including a first capacitor that changes in the positive direction according to the value of
Second switch means for selecting the lower y-bit pixel data from the x-bit pixel data latched by the latch means by logical inversion;
The lower y-bit pixel data inputted through the second switch means, the potential held in the other data line to which the negative polarity ramp signal is supplied out of the set of the two data lines. 3. The liquid crystal display device according to claim 1, further comprising: a second signal output unit including a second capacitor that changes in a negative direction in accordance with a logically inverted value of. The first signal output means includes two or more first capacitance adjustment switches that can be switched independently of each other, and two or more first capacitances provided corresponding to the first capacitance adjustment switches. And a first resistor,
The second signal output means includes two or more second capacitance adjustment switches that can be switched independently of each other, and two or more second capacitances provided corresponding to the second capacitance adjustment switches. 4. The liquid crystal display device according to claim 3, further comprising: a second resistor.

Images