JP2011197353A - Display device and driving method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a device constitution by reducing the number of output signal lines from a timing controller, for a liquid crystal display device in which an auxiliary capacitance bus line is driven by signals of a plurality of phases.SOLUTION: In the display device, one display pixel is divided into a plurality of sub pixels having an auxiliary capacitance, and the luminance of each sub pixel is made to be different by applying an auxiliary capacitance driving signal of different voltage to the auxiliary capacitance of the sub pixels. A timing controller LSI1 of the display device outputs an auxiliary capacitance data signal for generating the auxiliary capacitance driving signal. This auxiliary capacitance data signal is a signal switched by the horizontal period unit of a video signal, and in this auxiliary capacitance data signal, data for generating the auxiliary capacitance driving signals of a plurality of phases is multiplex-serialized. Thereby, only two signal lines of data and a clock are required for the signal lines from the timing controller LSI1 to a CS driver IC3.

Description

  The present invention relates to a display device and a display device driving method, and more specifically, a display in which an auxiliary capacitance voltage is applied to an auxiliary capacitance bus line from a plurality of auxiliary capacitance trunk lines and a pixel is driven by a multi-pixel driving method. The present invention relates to an apparatus and a driving method thereof.

  As a technique for improving the viewing angle dependency of the γ characteristic in a liquid crystal display device, there is a multi-picture element driving method. The multi-picture element driving method improves the viewing angle dependency of the viewing angle characteristic, that is, the γ characteristic by forming one picture element by two or more sub-picture elements having different luminances.

  FIG. 4 is a diagram illustrating a configuration example of a multi-pixel drive type liquid crystal display device. Each picture element P included in the liquid crystal panel of the liquid crystal display device is divided into two sub picture elements sp1 and sp2. The sub-picture element sp1 includes a TFT 10a and an auxiliary capacitor 11a. Similarly, the sub-picture element sp2 includes a TFT 10b and an auxiliary capacitor 11b.

  The gate electrodes of the TFTs 10a and 10b are connected to a common gate bus line GL, and the source electrodes are connected to a common source bus line SL. The auxiliary capacitor 11a is formed between the sub-picture element electrode of the sub-picture element sp1 and the auxiliary capacity bus line CsL1. Similarly, the auxiliary capacitor 11b is formed between the sub picture element electrode of the sub picture element sp2 and the auxiliary capacity bus line CsL2.

  The storage capacitor bus line CsL1 is provided so as to extend in parallel with the gate bus line GL with the region of the sub-picture element sp1 interposed between the storage bus line CsL1 and the gate bus line GL. Similarly, the storage capacitor bus line CsL2 is provided so as to extend in parallel with the gate bus line GL with the area of the sub-picture element sp2 interposed between the storage capacitor bus line CsL2 and the gate bus line GL.

  Further, the auxiliary capacity bus line CsL1 of the picture element P is an auxiliary capacity for the sub picture element sp2 of another picture element P adjacent to the picture element P to form the auxiliary capacity 11b across the auxiliary capacity bus line CsL1. Also serves as the bus line CsL2. Similarly, the auxiliary capacitance bus line CsL2 of the picture element P is used for the sub-picture element sp1 of another picture element P adjacent to the picture element P across the auxiliary capacitance bus line CsL2 to form the auxiliary capacitance 11a. It also serves as the auxiliary capacity bus line CsL1.

  A separate auxiliary capacitance voltage is applied to each of the n auxiliary capacitance bus lines CsL1, CsL2,. The auxiliary capacitance voltage Vcs in the auxiliary capacitance bus lines CsL1 and CsL2 corresponding to the sub-picture elements Sp1 and Sp2 in the same picture element P has a waveform composed of binary levels that vibrate at the same level change timing and the same cycle. Yes. The paired auxiliary capacitance voltages Vcs are set so that the phases are gradually shifted between the odd lines. The number of pairs is n / 2. A signal for applying the auxiliary capacitance voltage is an auxiliary capacitance (CS) drive signal.

The gate pulse Vg applied to the odd-numbered gate bus lines GL has a pulse period in a certain period of the auxiliary capacitance voltage Vcs, and has an end timing of the pulse period at the rise or fall timing of the auxiliary capacitance voltage Vcs.
As a result, first, a data signal is written to the odd-numbered picture element P, and the two sub-picture elements sp1 and sp2 of the picture element P to which the same data signal is written by a change in the auxiliary capacitance voltage Vcs after the data signal is written. Different potential displacements ΔV are added to the pixel electrode potential due to the feed through phenomenon through the capacitance between the gate bus line GL and the pixel electrode. Accordingly, the luminances of the sub-pixels sp1 and sp2 are different from each other, and the average luminance based on the effective value of the liquid crystal applied voltage through one frame period of the auxiliary capacitance voltage Vcs is a wide viewing angle. Appropriate in scope.

  The scan of the even line is performed after the scan of the odd line, and the auxiliary capacitance voltage Vcs applied to the sub-picture elements sp1 and sp2 belonging to the same picture element P at that time has the same level change timing as the odd line. Although the pair is not formed as described above, since the same potential change of the first pixel electrode after the end of the gate pulse as that of the odd-numbered line is obtained, the γ characteristic is also improved.

  The waveform of the auxiliary capacitance voltage Vcs and the scanning method are merely examples, and the γ characteristic of the entire picture element P is improved by changing the luminance depending on the voltage change of the different auxiliary capacitance voltage Vcs between the sub-picture elements sp1 and sp2. This is the main technology of the multi-picture element method.

  For example, Patent Document 1 discloses a technique for improving the viewing angle dependency of the γ characteristic of a liquid crystal display device by a multi-picture element driving method. Here, each of the pixels has a first sub-pixel and a second sub-pixel that can apply different voltages to the respective liquid crystal layers. If the effective voltages applied to the liquid crystal layers of the first subpixel and the second subpixel are V1 and V2, and the effective voltage difference ΔV12 = V1−V2, at least in the range of 0 <gk ≦ n−1, ΔV12 (gk)> 0 (volts) and ΔV12 (gk) ≧ ΔV12 (gk + 1) is satisfied.

  Further, in the liquid crystal display device disclosed in Patent Document 2, in the horizontal scanning period correction value setting circuit, the video signal Da1 indicating the display image of the pixel forming portion of the polarity inversion line and the display image of the pixel forming portion of the next row are displayed. And a signal width correction value α for correcting the length of the horizontal scanning period is generated. At this time, the signal is set so that the charging rate of the pixel forming portion is constant regardless of the difference between the target voltage of the driving video signal when the polarity is inverted and the target voltage of the driving video signal when the polarity is maintained. A width correction value α is set. A source output control signal Cs and a gate output control signal Cg are generated based on the signal width correction value α, and a scanning signal and a driving video signal are generated based on the source output control signal Cs and the gate output control signal Cg. Generated. This prevents a reduction in display quality due to a difference in charging rate between the pixel forming portions.

  Patent Document 3 discloses a technique for reducing block ghosts when phase expansion driving is performed in which a plurality of data lines are blocked and image signals are sampled together. Here, the average value of the gradation level changed from the previous block when the target block is selected, and the average value of the gradation level changed from the block two blocks before the target block when the previous block is selected. Are added to obtain correction data Db. At this time, the former average value is weighted larger than the latter average value. Then, the correction data Db is added to the video data Vd1d to Vd6d of each pixel belonging to the block of interest to obtain corrected video data Vd1e to Vd6e, and analog conversion and polarity inversion are performed to obtain an image signal of the electro-optical panel. The line is supplied.

  Further, the liquid crystal display device described in Patent Document 4 aims to reduce flicker with a relatively simple configuration while adopting a line inversion driving method. The control circuit 1 of the liquid crystal display device receives n-bit input data of a digital signal, and controls the horizontal driver so that a voltage corresponding to this input data is supplied to the liquid crystal panel based on the reference voltage during a certain 1H period. Further, the control circuit inverts each bit of the input data to generate a polarity-inverted gradation value. In the next 1H period, the voltage corresponding to the generated gradation value is set to the reference voltage. Originally supplied to the LCD panel. In this case, the gradation-γ correction voltage characteristic used by the control circuit for gradation display has a point-symmetric relationship between the central gradation of the highest gradation and the lowest gradation.

JP 2004-62146 A JP 2005-156661 A International Publication WO2005 / 073953 JP 2002-236474 A

  FIG. 5 is a diagram for explaining a configuration example of an auxiliary capacitance wiring using a plurality of voltage conversion circuits. In the multi-pixel drive type liquid crystal display device as described above, a gate driver substrate (not shown) is generally used to drive the display area of the liquid crystal panel 2. The auxiliary capacity bus line of the pixel of the liquid crystal panel 2 is connected to a plurality of auxiliary capacity (CS) trunk lines 41, and the auxiliary capacity voltage Vcs is supplied via the CS trunk lines.

  FIG. 6 is a diagram for explaining a configuration example of the CS trunk wiring and each auxiliary capacity bus line. In this example, twelve CS trunk lines (1-12) are connected to an auxiliary capacity bus line (CS line). In this example, one pixel consists of three RGB picture elements, and one picture element consists of two sub-picture elements.

  Since the auxiliary capacitance voltage Vcs is supplied via the trunk line, different auxiliary capacitance voltages Vcs are applied to different CS lines among the plurality of CS trunk lines. In this case, in the CS trunk line group composed of twelve CS trunk lines, a plurality of (in this case, twelve) auxiliary capacitor voltages Vcs having the number of phases corresponding to the number of CS trunk lines are connected to the liquid crystal panel 2. Supplied to the source substrate. Here, since the gate driver ON timing is different for each gate bus line, different Vcs are applied to different CS trunk lines in order to match each ON timing. As for the CS trunk wiring, the larger the number, the more suitable timing can be set. However, as the number increases, the area other than the active area of the screen called the frame increases. The number of phases is as follows.

  FIG. 7 is a diagram for explaining an example of a waveform when a binary auxiliary capacitor (CS) drive signal is used, and shows a CS drive signal input from the power supply conversion circuit 6 to the liquid crystal panel 2. As shown in FIG. 7, individual auxiliary capacitance voltages are applied to each of the n auxiliary capacitance bus lines CsL1, CsL2,. The auxiliary capacitance voltage Vcs in the auxiliary capacitance bus lines CsL1 and CsL2 corresponding to the sub-picture elements Sp1 and Sp2 in the same picture element P is a binary level (in this example, 5V, 7V) that vibrates at the same level change timing and the same cycle. ). This is because a bright picture element and a dark picture element are configured by sub-picture elements arranged on both sides of one gate line GL. Since the polarities of the picture elements arranged on the left and right of one picture element are reversed by the dot inversion driving, the left and right of the dark picture element become bright picture elements, and the right and left of the bright picture element become dark picture elements. The paired auxiliary capacitance voltage Vcs is set so that the phase is gradually shifted for each odd-numbered gate line GL.

  As described above, in the conventional multi-pixel drive type liquid crystal display device using the CS trunk wiring, the CS trunk is output at the stage of outputting the analog signal of the auxiliary capacitance voltage from the voltage conversion circuit 6 to the source substrate of the liquid crystal panel 2. A large number of wirings 41 are required. In addition, a large number of CS trunk lines 41 for sending digital signals from the timing controller LSI 1 to the voltage conversion circuit 6 are also required. Specifically, as many CS signal lines as there are CS signal lines are required.

  FIG. 8 is a diagram illustrating a configuration example for generating a CS drive signal using a CS driver IC. Here, a digital signal is sent from the timing controller LSI 1 to the CS driver IC 3 that outputs an analog signal. This digital signal is a signal for generating a CS drive signal by the CS driver IC 3. In order to improve the transient response characteristics at this stage, overdrive driving using, for example, a quaternary signal is performed.

  One line of auxiliary capacitance is connected to the source bus line SL. For example, in an FHD (full high-definition) liquid crystal panel, if it is changed to 1920 dots and picture elements (sub-pixels), an auxiliary capacity of 5760 dots is connected, the load is large, and the waveform becomes dull even if a rectangular wave is input. In recent years, the frame frequency displayed on the liquid crystal panel 2 has also increased from 60 Hz to 120 Hz, and further to 240 Hz. The pulse period at the same value of the CS drive signal waveform is shortened and the signal becomes dull. This is equivalent to a shortage of charging and a substantial reduction in the time to charge the auxiliary capacity.

In order to minimize such waveform dullness, a higher voltage is applied to the rising part of the waveform than when it is binary, and a lower voltage is applied to the falling part of the waveform than when it is binary. An overdrive drive that improves the transient response characteristic is used.
FIG. 9 shows an example of an input waveform of a CS drive signal with a normal binary value and a dull waveform, and FIG. 10 shows an example of an input waveform of a CS drive signal with a 4-value overdrive drive and a dull waveform.

  FIG. 11 is a diagram illustrating an example of an interface waveform when driving with a four-value signal using a CS driver IC, and illustrates a waveform of a digital signal output from the timing controller LSI1 to the CS driver IC3. Here, the binary signal is assumed to be conventional, and a signal indicating an overshoot portion is further assigned. For example, a quaternary signal CSD1 ′ indicating an overshoot portion is assigned to the binary signal CSD1.

  FIG. 12 is a diagram for explaining an example of a CS drive signal when a quaternary signal is used. Similarly, in the case of a quaternary signal, the auxiliary capacitance voltage Vcs in the auxiliary capacitance bus lines CsL1 and CsL2 corresponding to the sub-picture elements Sp1 and Sp2 in the same picture element P oscillates at the same level change timing and the same cycle. It has a waveform consisting of four levels. The paired auxiliary capacitance voltages Vcs are set in a state in which phases are gradually shifted for each odd-numbered gate line.

  For example, if the quaternary voltage is 4V, 5V, 7V, 8V and the VCOM (center value) is 6V, the bit representing the binary value is “0” and the bit in the overshoot portion is “ If it is 0, the bit representing 5V and the binary value is “0” and the bit in the overshoot part is “1”. If the bit representing the binary value is “1” and the bit representing the binary value is “1”, the bit in the overshoot part is “1”. When the bit is “0”, the signal is 7V, and when the binary bit is “1” and the bit of the overshoot is “1”, the signal is 8V.

  Considering a liquid crystal panel that requires twelve phases of CS drive signals, when performing overdrive driving, the signal input to the liquid crystal panel 2 is an analog signal in the interface to the liquid crystal panel 2. The signal lines may be twelve. However, when a digital signal is sent between the timing controller LSI1 and the CS driver IC3, a quaternary signal is required. Therefore, in the case of overdrive driving, a total of 24 signal lines between the timing controller LSI 1 and the CS driver IC 3 are required. In this case, 12 binary signal lines and 12 signal lines for overdrive driving are required.

  However, since the 24 signals to be transmitted include signals having different polarities, two signals having different polarities can be combined into one signal by providing the CS driver IC 3 with a polarity inversion circuit. In the example of FIG. 11, the binary signals CSD1 and CSD2 are signals having different polarities only, and it is only necessary to reverse the polarity in the circuit of the CS driver IC3. Therefore, when the signal is sent from the timing controller LSI1 to the CS driver IC3, one of them is omitted. can do.

  Also, the quaternary signals CSD1 'and CSD2' indicating overdrive have the same waveform if the pulse width at the rise and the pulse width at the fall of the binary waveform are exactly the same. One can be omitted. However, in this case as well, the signal lines from the timing controller LSI1 to the CS driver IC3 are 12 signal lines in total including 6 signal lines for transmitting binary signals and 6 signal lines for transmitting quaternary signals. Digital signal lines are required.

As described above, a large number of signal lines for transmitting drive signals are required even when binary CS drive is performed or when quaternary drive is performed by overdrive.
The cost of the digital LSI is determined by the chip area, and the chip area is determined by the number of logic gates and the number of buffers placed around the LSI. That is, the number of PINs greatly affects. When the number of PINs of a digital LSI is large, there is a problem that the chip area is limited and hinders cost reduction.

  The present invention has been made in view of the above-described conventional problems, and is a liquid crystal display device in which an auxiliary capacity bus line is driven by signals of a plurality of phases, and the number of output signal lines from a timing controller is reduced. Thus, it is an object of the present invention to provide a liquid crystal display device and a driving method of the liquid crystal display device in which the device configuration is simplified.

  In order to solve the above problems, the first technical means of the present invention includes a plurality of display picture elements, and one display picture element is divided into a plurality of sub-picture elements each having an auxiliary capacity. The auxiliary capacitor drive signal is generated in a display device in which the luminance of each of the multiple picture elements is made different by applying an auxiliary capacitor drive signal having a different voltage to each of the auxiliary capacitors included in the sub-picture element. The auxiliary capacity data signal is a signal that is switched in units of horizontal periods of the video signal, and the data for generating the auxiliary capacity drive signal of a plurality of phases is multiplexed. This is a signal that is serialized and output.

  According to a second technical means, in the first technical means, the auxiliary capacitance data signal includes a delay control signal for performing delay control of each phase of the plurality of auxiliary capacitance drive signals. It is.

  The third technical means includes a plurality of display picture elements, and one display picture element is divided into a plurality of sub picture elements each having an auxiliary capacity, and is different from each of the auxiliary capacity provided in the sub picture element. In a display device driving method in which the luminance of each multi-picture element is made different by applying a voltage auxiliary capacitor driving signal, an auxiliary capacitor for generating the auxiliary capacitor driving signal from a timing controller of the display device When the data signal is output, the timing controller uses the auxiliary capacitor data signal as a signal for switching the horizontal period unit of the video signal, and data for generating a plurality of auxiliary capacitor driving signals as the auxiliary capacitor data signal Are serialized and output.

  According to a fourth technical means, in the third technical means, the auxiliary capacitance data signal includes a delay control signal for performing delay control of each phase of the auxiliary capacitance drive signal of a plurality of phases. It is.

  According to the present invention, an auxiliary capacity bus line is driven by a plurality of phase signals, and the number of output signal lines from the timing controller is reduced to simplify the device configuration. A liquid crystal display device and a driving method of the liquid crystal display device can be provided.

It is a figure for demonstrating one Embodiment of the liquid crystal display device based on this invention. It is a figure which shows the structural example when CS driver IC is arrange | positioned on a source substrate. It is a figure for demonstrating the structural example of a packet required when serializing data and a clock. It is a figure which shows the structural example of the liquid crystal display device of a multi picture element drive system. It is a figure for demonstrating the structural example of the auxiliary capacity wiring which used the several voltage conversion circuit. It is a figure for demonstrating the structural example of CS trunk wiring and each auxiliary capacity bus line. It is a figure for demonstrating an example of the waveform in the case of using a binary CS drive signal. It is a figure explaining the structural example for producing | generating a CS drive signal using CS driver IC. It is a figure which shows the input waveform of the CS drive signal by a normal binary value, and a dull waveform example. It is a figure which shows the input waveform and dull waveform example of CS drive signal by quaternary overdrive drive. It is a figure which shows an example of the interface waveform in the case of driving with a 4-value signal using CS driver IC. It is a figure for demonstrating an example of CS drive signal in the case of using a quaternary signal.

  In a multi-pixel drive type liquid crystal display device, a CS drive signal for driving a storage capacitor (CS) is a signal that switches in units of horizontal periods, and is not faster than an image signal. In the embodiment, the data signal (auxiliary capacitance data signal) output from the timing controller LSI in order to generate this CS drive signal by the CS driver IC is serialized in multiple, thereby reducing the number of signals from the timing controller LSI to the CS driver IC. It became possible to reduce significantly. At this time, as a means for transmitting the auxiliary capacity data signal, a method of dividing into packets (also referred to as frames) is used. At the same time, when the auxiliary capacity data signal is multiplexed and serialized, it is possible to finely adjust the timing by sending a delay control signal of each phase as a packet.

  According to the embodiment of the present invention, the number of signal lines connected between the timing controller LSI and the CS driver IC can be greatly reduced, and the cost of the timing controller LSI and the entire board can be reduced by reducing the number of PINs. Can be realized. Further, the timing of the CS drive signal can be finely adjusted in each phase, and a display device with uniform and good image quality can be obtained.

FIG. 1 is a diagram for explaining an embodiment of a liquid crystal display device according to the present invention, in which a CS drive signal is transmitted between a liquid crystal panel and a timing controller for driving the liquid crystal panel of the liquid crystal display device. 2 shows a configuration example of the signal line.
The timing controller LSI (T-CON) 1 creates a desired timing signal from a horizontal synchronization signal and a vertical synchronization signal of a signal such as LVDS sent from a signal processing LSI (not shown) placed in the preceding stage, and generates CS It is sent to the driver IC (CS-IC) 3 and the source substrate 21 of the liquid crystal panel 2. Conventionally, data for generating a CS drive signal (auxiliary capacitance data signal) is sent from the timing controller LSI 1 to the CS driver IC 3 through 12 signal lines. However, in the embodiment according to the present invention, the timing controller LSI 1 Two signal lines, a signal line 4a for sending a clock and a signal line 4b for sending data, are connected to the CS driver IC3.

  Twelve CS drive signals are output as analog voltage signals from the CS driver IC 3 to the source substrate 21 on one side of the liquid crystal panel 2. At this time, the pair of signals output to the left and right source substrates 21 are the same signal in order to drive one liquid crystal panel 2 from the left and right. Here, it is assumed that there are two source substrates 21. However, if the source substrate 21 can be driven only on one side according to the panel size of the liquid crystal panel 2, the source substrate 21 is provided only on one side. . Further, although the gate driver 23 is disposed on both sides of the liquid crystal panel 2, it may be provided on only one side depending on the panel size of the liquid crystal panel 2.

The CS driver IC 3 can also be arranged on either the substrate of the timing controller LSI 1 or the source substrate 21. FIG. 2 shows a configuration example when the CS driver IC 3 is arranged on the source substrate 21.
In any of the configurations shown in FIGS. 1 and 2, serialized data and a clock are transmitted from the timing controller LSI 1 to the CS driver IC 3. The data in this case is data for generating a CS drive signal by the CS driver IC3.

FIG. 3 is a diagram for explaining a configuration example of a packet necessary for serializing data and a clock.
When data and a clock are serialized, a protocol is required that determines the number of packets that represent the start and end points of data and which data is shown. Both the timing controller LSI1 and the CS driver IC3 need to be circuits that comply with this protocol.

  In order to serialize the data and the clock, a unique start flag and a packet for setting how many packets of each data are required. Therefore, serialized data includes a packet for sending a start flag, a packet for which the number of packets for each data is set, a packet for controlling the delay of each phase, a packet for sending data for each phase, and a unique end It consists of a packet consisting of flags. This packet group is transmitted during one horizontal period of the video signal. The data of each phase is data that is converted into an analog CS drive signal by the CS driver IC 3 and output to the source substrate.

At this time, for example, 8B10B, which is generally used for serializing 8-bit parallel data, can be used as an encoding method for serialized data. Also, an original encoding method can be applied.
In the case of 8B10B, a code is selected so that the same data is not continuously output, and a clock can be embedded in the data. For example, a 10-bit code is assigned to 8-bit data and transmitted. When 8B10B is used, the number of signal lines for transmitting data and clock can be reduced to one.

However, in this case, since it is necessary to separately provide a circuit for regenerating the clock, in the embodiment according to the present invention, two signal lines for transmitting the clock and data are used for circuit reduction. ing.
Further, even when a unique encoding method is used without using 8B10B as a data encoding method, data is transmitted in units of 8 bits. Here, if the start flag and the end flag are not unique code strings different from other data, they will malfunction, so it is necessary to increase the number of bits compared to the input data. Here, since the data transmission unit is 8 bits, it is necessary to assign unique signals such as 9 bits or 10 bits to the start flag and the end flag. For example, 10 bits are assigned to the start flag and the end flag.

In this embodiment, the CS drive signal to be transmitted has 12 phases. In this case, the CS drive signal to be transmitted by one signal line includes positive polarity and negative polarity. Therefore, the auxiliary capacity data signal output from the timing controller LSI 1 to the CS driver IC 3 only needs to have six phases.
At this time, in order to prevent the signal from becoming dull due to the influence of the load on the CS trunk line and the CS bus line, overdrive driving for speeding up the change of the signal can be used. In this case, it is necessary to add at least 6 phases, and data transmission of a total of 12 phases is required in one line period. This number of phases depends on the design of the CS trunk wiring. In the embodiment according to the present invention, any number of phases can be handled.

  As shown in FIG. 3, the serialized data and clock signal includes a packet for sending a start flag, a packet in which the number of packets of each data is set, a packet for controlling the delay of each phase, It is composed of a packet for transmitting CS data of each phase and a packet consisting of a unique end flag, and this packet group is transmitted during one horizontal period. The circuit on the receiving side, that is, the CD driver IC 3 monitors the start flag, and after detecting the start flag, receives a packet indicating the number of data packets to be transmitted thereafter. And the packet of setting data, such as a delay of each CS data, is received. The CS data is binary, quaternary, or both digital data for generating an analog voltage signal for CS driving.

  Thereafter, the CS driver IC 3 receives the binary CS data of the number of transmitted packets, receives the 4-value CS data of the number of packets transmitted in the next packet, and finally receives the packet consisting of the end flag. Receive. The reason why binary CS data and quaternary CS data exist is that only binary CS data is used in some cases. Data structure.

  The CS driver IC 3 uses the received end flag packet as a reference, delays by the delay specified by the delay setting data using the clock signal, and outputs an analog voltage obtained by converting the CS data of each phase as the auxiliary capacitance voltage. . With this analog voltage, multi-picture element driving can be performed by the feedthrough effect, and the viewing angle of the liquid crystal panel 2 can be improved.

  With the configuration as described above, in the embodiment according to the present invention, the number of signal lines connected between the timing controller LSI 1 and the CS driver IC 3 can be greatly reduced, and the timing controller LSI and the entire substrate can be reduced by reducing the number of PINs. The cost can be reduced. Also, when sending a serialized signal, by sending a delay control signal for each phase, it is possible to finely adjust the CS drive timing in each phase, thereby obtaining uniform and good image quality. .

  The present invention can be applied to a liquid crystal television device.

DESCRIPTION OF SYMBOLS 1 ... Control circuit, 2 ... Liquid crystal panel, 3 ... CS driver IC, 4a ... Signal line, 4b ... Signal line, 5a ... Auxiliary capacity, 5b ... Auxiliary capacity, 6 ... Voltage conversion circuit, 10a ... TFT, 10b ... TFT, 11a ... auxiliary capacitor, 11b ... auxiliary capacitor, 21 ... source substrate, 23 ... gate driver, 41 ... CS trunk wiring.

Claims (4)

A plurality of display picture elements are provided, and one display picture element is divided into a plurality of sub picture elements each having an auxiliary capacity, and an auxiliary capacity drive signal having a different voltage is supplied to each of the auxiliary capacity provided in the sub picture element. In the display device in which the luminance of each double picture element is made different by applying,
A timing controller that outputs an auxiliary capacitance data signal for generating the auxiliary capacitance driving signal, wherein the auxiliary capacitance data signal is a signal that is switched in units of a horizontal period of a video signal, The display device is characterized in that the data for generating the data is a signal that is output after being serialized multiple times.   2. The display device according to claim 1, wherein the storage capacitor data signal includes a delay control signal for performing delay control of each phase of the plurality of storage capacitor drive signals of the plurality of phases. A plurality of display picture elements are provided, and one display picture element is divided into a plurality of sub picture elements each having an auxiliary capacity, and an auxiliary capacity drive signal having a different voltage is supplied to each of the auxiliary capacity provided in the sub picture element. In the driving method of the display device in which the luminance of each double picture element is made different by applying,
When outputting the storage capacitor data signal for generating the storage capacitor drive signal from the timing controller included in the display device, the timing controller uses the storage capacitor data signal as a signal for switching the horizontal period of the video signal, A display device driving method, wherein data for generating a storage capacitor driving signal of a plurality of phases is multiplexed and serialized and output as an auxiliary capacitor data signal.   4. The display device driving method according to claim 3, wherein the auxiliary capacitance data signal includes a delay control signal for performing delay control of each phase of the plurality of auxiliary capacitance driving signals. Device driving method.

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