JP2011029859A - Pulse width modulation circuit and switching amplifier thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output a pulse width modulation signal corresponding to an input signal correctly even if current values of a DC bias current Ic and a discharge current Id are varied by a temperature coefficient. <P>SOLUTION: A current generation circuit 14 is equipped with a constant current circuit 31 which generates a constant current I1, a differential circuit 32 which generates a current I2+Δi which is the sum of a current I2 having the current value equal to 1/2 of the constant current I1 and a current Δi obtained by converting an AC voltage es into a current, a current voltage conversion means 33 for converting the constant current I1 into a voltage Vb2, a voltage current conversion means 34 for converting the voltage Vb2 supplied from the current voltage conversion means 33 into a current, thus generating the discharge current Id, a current voltage conversion means 35 for converting the current I2+Δi into a voltage Vb1, and a voltage current conversion means 36 for converting the voltage Vb1 supplied from the current voltage conversion means 35 into a current, thus generating a charging current Ic+Δi. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a pulse width modulation circuit that converts an audio signal into a pulse width modulation signal having a constant period and a duty ratio that changes in accordance with the amplitude of the audio signal, and a switching amplifier (for example, an audio amplifier) using the same. ).

  2. Description of the Related Art Conventionally, a pulse width modulation circuit that converts an AC voltage signal such as an audio signal into a pulse width modulation signal whose duty ratio changes according to its amplitude has been proposed. For example, Patent Document 1 below proposes a pulse width modulation circuit using a monostable multivibrator. The applicant has proposed a pulse width modulation circuit that does not use a monostable multivibrator (for example, Patent Documents 2 and 3 below).

  FIG. 8 is a circuit diagram showing a schematic configuration of a pulse width modulation circuit proposed by the applicant. 9 and 10 are timing charts showing voltage waveforms of signals in the pulse width modulation circuit shown in FIG. 9 and 10 mainly show waveforms in the charge / discharge operation of the first capacitor C11.

  8 includes a reference clock generation circuit 54, a dead time generation circuit 55, a falling edge detection circuit 56, a charge current generation circuit 57, a discharge current generation circuit 58, and a current bypass circuit. 59, first to fourth switches SW11 to SW14, first and second capacitors C11 and C12, first and second RS flip-flop circuits 60 and 61, and a signal output circuit 62 including a NAND circuit. ing.

  In the pulse width modulation circuit 51 shown in FIG. 8, a current signal Ij (hereinafter referred to as “charging current Ij”) for charging the first and second capacitors C11 and C12 from the audio signal eS by the charging current generation circuit 57. The discharge current generation circuit 58 generates a current Id (hereinafter referred to as “discharge current Id”) for discharging the first and second capacitors C11 and C12, and the reference clock generation circuit 54 generates the reference clock MCLK. Generated.

  The charging current Ij is expressed by Ij = Ic ± Δi. The bias voltage at the output terminal of the operational amplifier 63 is determined by −Vcc and the resistance elements R11 and R12, and the DC bias current Ic (> 0) is determined by the bias voltage, the resistance element R14, the transistor Q11, and the voltage source 64. Is done. Further, ± Δi is a current component obtained by voltage-current conversion of the audio signal eS (AC voltage signal).

  Based on the reference clock MCLK, the dead time generating circuit 55 generates a first switching signal φ1 for controlling the charging operation of the first capacitor C11 and a second switching signal φ2 for controlling the charging operation of the second capacitor C12 (FIG. 9 (b) and (c)). The first RS flip-flop circuit 60 generates a third switching signal φ3 that controls the discharge operation of the first capacitor C11 (see FIG. 9F), and the second RS flip-flop circuit 61 controls the discharge operation of the second capacitor C12. A fourth switching signal φ4 is generated.

  The first capacitor C11 is charged by supplying the charging current Ij (= Ic ± Δi) from the charging current generation circuit 57 only during the ON period (high level period) of the first switching signal φ1 by the first switch SW11. Is done. By this charging, the first capacitor C11 rises from the voltage Vth to a voltage corresponding to the amplitude E of the audio signal eS during the high level period of the first switching signal φ1 (see the solid line L1 in FIGS. 9B and 9E). ).

  In the off period (low level period) of the first switching signal φ1, the first set signal set1 (falling to the low level for a moment) is detected when the falling edge detection circuit 56 detects the falling (low level inversion) of the first switching signal φ1. Signal) is input to the set terminal of the first RS flip-flop circuit 60, the third switching signal φ3 output from one output terminal of the first RS flip-flop circuit 60 is inverted to a high level, and the third switch SW13 The discharge current Id from the discharge current generation circuit 58 is supplied to the first capacitor C11, thereby starting the discharge of the first capacitor C11 (see solid lines L1 and (f) in FIGS. 9D and 9E). .

  When the voltage of the first capacitor C11 decreases from the charge end voltage to the threshold voltage Vth (threshold voltage that divides the high level and the low level in the first RS flip-flop circuit 60) after the discharge starts, the voltage becomes the first reset signal res1 as the first RS. Input to the flip-flop circuit 60, the third switching signal φ3 is inverted to a low level, and the discharge current generating circuit 58 is electrically disconnected by the third switch SW13.

  The output rsout1 output from the other output terminal of the first RS flip-flop circuit 60 is inverted to a low level when the first set signal set1 is input, and then high when the first reset signal res1 is input. Invert to level. That is, from the other output terminal of the first RS flip-flop circuit 60, a pulse having the same pulse width as the discharge time of the first capacitor C11 (the time from when the charge end voltage is lowered to the threshold voltage Vth) for each discharge period. An output rsout1 composed of a signal is output (see FIG. 9G).

  The second capacitor C12 is charged and discharged in the same manner as the first capacitor C11, and the second capacitor C12 is discharged from the other output terminal of the second RS flip-flop circuit 61 every discharge period (from the charging end voltage to the threshold value). An output rsout2 composed of a pulse signal having the same pulse width as the time until the voltage Vth is lowered is output.

  Since the charging / discharging operation of the second capacitor C12 is controlled based on the second switching signal φ2, the charging / discharging period is shifted from the charging / discharging period of the first capacitor C11 by a half cycle of the reference clock MCLK. Therefore, the pulse signal of the output rsout1 and the pulse signal of the output rsout2 are alternately generated every half cycle of the reference clock MCLK.

  Then, a pulse width modulation signal PWMout obtained by synthesizing the output rsout1 and the output rsout2 is output from the signal output circuit 62 (see FIG. 9 (h)).

  A solid line L1 shown in FIG. 9 (e) shows the waveform when the audio signal eS is no signal (Δi = 0), which is the charge / discharge waveform of the first capacitor C11. When the audio signal eS is no signal (Δi = 0), the first capacitor C11 is charged with the DC bias current Ic. The DC bias current Ic is charged with the power supply voltage of the first RS flip-flop circuit 60. It is set to be a potential Vm (≈ (Vcc−Vth) / 2) at the midpoint between Vcc and the threshold voltage Vth.

  When the amplitude E of the audio signal eS is positive (in the case of Ij = Ic + Δi), the slope of the charging waveform becomes steeper than the solid line L1 according to the magnitude of the amplitude E. On the other hand, when the amplitude E of the audio signal eS is negative (Ij = Ic−Δi), the charging waveform has a gentler slope than the solid line L1 depending on the magnitude of the amplitude E. Therefore, a pulse width modulation signal whose high level period changes according to the audio signal is output.

JP 2007-89122 A JP 2008-206128 A JP 2009-141408 A

  As described above, the pulse width modulation circuit 51 discharges the charging current generation circuit 57 for generating the charging current Ij for charging the first and second capacitors C11 and C12, and the first and second capacitors C11 and C12. Discharge current generation circuits 58 for generating the discharge current Id to be generated are independently provided. The pulse width modulation circuit 51 sets the case where the current value of the DC bias current Ic and the discharge current Id is Ic: Id = 1: 2 when the amplitude value of the audio signal eS is 0, and the pulse width The modulation degree of the modulation signal PWMout becomes 0 (duty ratio 50%, the period between the high level and the low level coincides). However, since the constant voltage sources 64 and 65 included in the charging current generation circuit 57 and the discharge current generation circuit 58 include semiconductor elements and resistors, the constant voltage sources 64 and 65 depend on the temperature coefficient of the semiconductor elements and resistors. The output voltage value varies according to the temperature. As a result, the current values of the DC bias current Ic and the discharge current Id vary depending on the temperature due to the influence of the temperature coefficient. Even if the current value of each current fluctuates, if the ratio of the DC bias current Ic and the discharge current Id maintains the relationship of Ic: Id = 1: 2, a normal pulse width modulation signal PWMout is output. be able to. However, when the ratio of the DC bias current Ic and the discharge current Id does not maintain the relationship of Ic: Id = 1: 2, a DC offset occurs in the pulse width modulation signal PWMout.

  Details will be described by taking as an example a case where the amplitude of the audio signal eS is zero. First, when the discharge current Id does not vary depending on the temperature and only the DC bias current Ic increases due to the temperature coefficient, the slope of the charging waveform of the capacitor C11 is a solid line as shown by the broken line L2 in FIG. It becomes steeper than L1, and the charge end voltage charged in the capacitor C11 increases during the high level period of the first switching signal φ1. Since the discharge current Id does not fluctuate, the time until the charging voltage of the capacitor C11 reaches the threshold voltage Vth is longer than that of the solid line L1, and the output pulse width modulation signal PWMout has a high level period during the solid line L1. As a result, it becomes longer than that at the time, and the modulation degree changes. On the other hand, when only the DC bias current Ic is decreased by the temperature coefficient without changing the discharge current Id according to the temperature, the slope of the charging waveform of the capacitor C11 is a solid line as shown by the broken line L3 in FIG. Compared to L1, the charge end voltage charged in the capacitor C11 is reduced during the high level period of the first switching signal φ1. Since the discharge current Id has not changed, the time until the charging voltage of the capacitor C11 reaches the threshold voltage Vth is shorter than that of the solid line L1, and the high level period of the output pulse width modulation signal PWMout is shortened. The modulation degree changes.

  Next, when the DC bias current Ic does not vary according to the temperature and only the discharge current Id increases due to the temperature coefficient, the high level of the first switching signal φ1 is shown as indicated by the broken line L4 in FIG. The charging end voltage charged in the capacitor C11 during the period is the same as that of the solid line L1, but since the slope of the discharge waveform becomes steep, the time until the charging voltage of the capacitor C11 reaches the threshold voltage Vth is indicated by the solid line L1. , The high level period of the output pulse width modulation signal PWMout is shortened, and the modulation degree changes. On the other hand, when the DC bias current Ic does not fluctuate and only the discharge current Id decreases due to the temperature coefficient, as shown by a broken line L5 in FIG. The charging end voltage to be charged is the same as that of the solid line L1, but since the slope of the discharge waveform becomes gentle, the time until the charging voltage of the capacitor C11 reaches the threshold voltage Vth becomes longer than that of the solid line L1. The high level period of the output pulse width modulation signal PWMout becomes longer, and the modulation degree changes.

  Even when both the DC bias current Ic and the discharge current Id fluctuate depending on the temperature coefficient, and the ratio of the DC bias current Ic and the discharge current Id deviates from the relationship of 1: 2, either of the above states occurs. End up.

  The present invention has been conceived under the circumstances described above, and in the pulse modulation circuit having the above-described configuration, the current values of the DC bias current Ic and the discharge current Id vary depending on the temperature coefficient. Another object of the present invention is to provide a pulse width modulation circuit that outputs a pulse width modulation signal accurately corresponding to an input signal, and a switching amplifier to which the pulse width modulation circuit is applied.

  A pulse width modulation circuit according to a preferred embodiment of the present invention includes a first charge accumulation unit that accumulates charges, a second charge accumulation unit that accumulates charges, and a current corresponding to an amplitude of the AC voltage from an input AC voltage. Current generating means for generating a first current whose value changes and generating a second current; and a first period in a first period which is a half cycle of a predetermined clock signal based on the first current. The voltage in the charge storage means is changed, and the voltage in the first charge storage means is changed in the first period in a second period following the first period that is shifted from the first period by a half cycle based on the second current. The voltage in the second charge storage means is changed based on the first current, and is shifted by a half cycle from the second period based on the second current. Second Voltage control means for changing the voltage in the second charge storage means in the opposite direction to the increase / decrease direction in the second period in a third period, and in the first charge storage means after the start of the second period. A first detecting means for detecting a time until the voltage reaches a threshold voltage; and a first detecting means for detecting a time from when the third period starts until the voltage at the second charge storage means reaches the threshold voltage. 2 detection means, and a pulse signal generation that generates a pulse signal having a pulse width of the time based on a time alternately output from the first detection means and the second detection means every half cycle of the clock signal And the current generation means includes constant current generation means for generating a third current which is a constant current, and the first current is obtained from the third current and the AC voltage. Form, to generate the second current from the third current.

  Since the first current and the second current are generated from the constant current generated by the common constant current generating means, the constant current varies depending on the temperature coefficient of the constant current generating means, and the direct current of the first current is changed. Even when the bias current and the second current fluctuate, the ratio between the DC bias current of the first current and the second current can be made constant. This is because when the current value of the DC bias current of the first current varies due to the variation of the constant current, the current value of the second current also varies at the same ratio. Therefore, even if the DC bias current of the first current and the second current fluctuate due to the temperature coefficient, it is possible to output a pulse width modulation signal that accurately corresponds to the input signal.

  In a preferred embodiment, the current generating means generates a fourth current obtained by adding a current having a current value ½ of the third current and a current obtained by converting the AC voltage into a current. A first current-voltage conversion means for converting the third current into a first voltage, the first voltage supplied from the first current-voltage conversion means into a current, and the second The first voltage-current conversion means for generating the current, the second current-voltage conversion means for converting the fourth current into the second voltage, and the second voltage supplied from the second current-voltage conversion means And a second voltage / current conversion means for generating the first current.

  In a preferred embodiment, the first voltage-current conversion means and the second voltage-current conversion means each have transistors, and these transistors have the same temperature coefficient and base-emitter voltage (conduction start voltage). is there.

  A switching amplifier according to a preferred embodiment of the present invention includes a pulse width modulation circuit, a voltage source that outputs a predetermined reference power supply voltage, and a modulation signal output from the pulse width modulation circuit. And a switching circuit for switching the supplied reference power supply voltage.

  In the case where the first current and the second current are generated by a common constant current, the direct current bias current and the second current of the first current fluctuate due to the temperature coefficient of each element. However, the ratio between the DC bias current of the first current and the second current can be made constant. Therefore, even if the DC bias current of the first current and the second current fluctuate due to the temperature coefficient, it is possible to output a pulse width modulation signal that accurately corresponds to the input signal.

It is a block diagram showing a switching amplifier to which a pulse width modulation circuit according to the present invention is applied. 1 is a block circuit diagram showing a first embodiment of a pulse width modulation circuit according to the present invention. FIG. 3 is a circuit diagram showing a current generation circuit 14. FIG. It is a circuit diagram which shows another electric current generation circuit 14 '. It is a figure which shows the time chart which shows operation | movement when the amplitude of an audio signal is 0. It is a figure which shows the time chart which shows operation | movement when the amplitude of an audio signal is positive. It is a block circuit diagram which shows the pulse width modulation circuit of another embodiment. It is a circuit diagram which shows the pulse width modulation circuit which the applicant has proposed. FIG. 9 is a timing chart showing voltage waveforms of signals in the pulse width modulation circuit shown in FIG. 8. FIG. 9 is a timing chart showing voltage waveforms of signals in the pulse width modulation circuit shown in FIG. 8.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a switching amplifier to which a pulse width modulation (PWM) circuit according to the present invention is applied. FIG. 2 is a block circuit diagram showing the pulse width modulation circuit shown in FIG.

[Configuration of switching amplifier]
This switching amplifier includes a pulse width modulation circuit 1 connected to an audio signal generation source AU, a switching circuit 2, a low-pass filter circuit 3, a first power supply 4 that supplies positive and negative power supply voltages + EB and -EB, and a second power supply. And a power source 5. A speaker (not shown) as a load RL is connected to the output of the low-pass filter circuit 3.

  The pulse width modulation circuit 1 converts the audio signal eS as an input signal output from the audio signal generation source AU into a pulse width modulation signal PWMout and outputs it. The pulse width modulation signal PWMout output from the pulse width modulation circuit 1 is input to the switching circuit 2.

  The switching circuit 2 includes a switch element SW-A whose on / off operation is controlled by the pulse width modulation signal PWMout, an inverter 2a for inverting the phase of the pulse width modulation signal PWMout output from the pulse width modulation circuit 1, and The switch element SW-B whose on / off operation is controlled by the pulse width modulation signal PWMout ′ whose phase is inverted output from the inverter 2a is connected to both ends of the switch elements SW-A and SW-B. Reverse-current preventing diodes DA and DB are provided.

  In the switching circuit 2, positive and negative power supply voltages + EB and -EB are supplied from the first power supply 4 and the second power supply 5 to the load RL via the switch element SW-A and the switch element SW-B, respectively. Since the SW-A and the switch element SW-B are alternately turned on and off by the pulse width modulation signal PWMout and the pulse width modulation signal PWMout ′, respectively, the power supply voltage + EB is applied to the low-pass filter circuit 3 and the load RL. The power supply voltage -EB is supplied alternately. That is, the load RL is supplied with a rectangular wave voltage having the same duty ratio as that of the pulse width modulation signal PWMout through the low-pass filter circuit 3 while the level changes between + EB and -EB.

  The low-pass filter circuit 3 is configured by an LC circuit including a coil L0 and a capacitor C0. The low-pass filter circuit 3 is a circuit that removes a high-frequency component of the rectangular wave voltage input from the switching circuit 2 and has a cutoff frequency of 60 kHz, for example. The low-pass filter circuit 3 outputs an AC voltage signal (AC voltage signal having substantially the same waveform as that of the audio signal eS) obtained by demodulating the pulse width modulation signal PWMout, and the AC signal is supplied to the load RL. Is output as audio.

[Configuration of pulse width modulation circuit]
As shown in FIG. 2, the pulse width modulation circuit 1 includes a reference clock generation circuit 11, a dead time generation circuit 12, a falling edge detection circuit 13, a charging current / discharge current generation circuit (hereinafter referred to as a current generation circuit). .) 14, first to fourth switches SW1 to SW4, first and second capacitors C1 and C2 (integrators), a current bypass circuit 16, first and second RS flip-flop circuits 17 and 18, And a signal output circuit 19.

The pulse width modulation circuit 1
(1) A charging current Ij for charging the first and second capacitors C1 and C2 is generated by the current generation circuit 14 from the audio signal eS input from the outside.
(2) Of the one cycle of the reference clock MCLK, for example, the first half cycle of the first capacitor C1 is a charging period, the latter half cycle is a discharging period, and the first half cycle of the second capacitor C2 is a discharging period. When the second half cycle is a charging period, the first and second capacitors C1 and C2 are charged with the charging current Ij in each charging period, and the accumulated charges of the first and second capacitors C1 and C2 are discharged in each discharging period. Discharge with current Id.
(3) Every discharge period of the first and second capacitors C1 and C2, from the start of discharge (at the end of charging) until the voltage of the first and second capacitors C1 and C2 changes to a predetermined threshold voltage Vth Pulse signals having the same pulse width as the discharge time are generated.
(4) A pulse width modulation signal PWMout is generated by synthesizing pulse signals generated alternately every half cycle of the reference clock MCLK.
The audio signal eS is converted into the pulse width modulation signal PWMout by the operation principle described above.

  The reference clock generation circuit 11 is a circuit that generates the reference clock MCLK. The reference clock MCLK is a clock signal having a constant cycle and a duty ratio of approximately 50%, and first and second switching signals φ1 and φ2 for controlling on / off operations of the first and second switches SW1 and SW2. This is the reference signal. The reference clock MCLK is also a reference signal that defines the period of the pulse width modulation signal PWMout. The reference clock generation circuit 11 outputs the reference clock MCLK to the dead time generation circuit 12. The reference clock generation circuit 11 may be provided outside the pulse width modulation circuit 1 and configured to supply the reference clock MCLK to the pulse width modulation circuit 1 as an external clock signal.

  The dead time generation circuit 12 is a circuit that generates the first switching signal φ1 and the second switching signal φ2 based on the reference clock MCLK from the reference clock generation circuit 11. The second switching signal φ2 has an opposite phase relationship to the first switching signal φ1, but the falling timing and rising timing of the second switching signal φ2 coincide with the rising timing and falling timing of the first switching signal φ1, respectively. As a result, the level inversion timing of the second switching signal φ2 is shifted by a predetermined time ΔT (dead time) with respect to the level inversion timing of the first switching signal φ1.

  That is, as shown in FIGS. 5A and 5B, the first switching signal φ1 changes from the low level to the high level after a predetermined period ΔT from the time when the reference clock MCLK is inverted from the low level to the high level. The signal is inverted, and the reference clock MCLK is inverted from the high level to the low level, and at the same time is inverted from the high level to the low level. On the other hand, as shown in FIGS. 5A and 5C, the second switching signal φ2 is inverted from the high level to the low level at the same time as the reference clock MCLK is inverted from the low level to the high level. This signal is inverted from the low level to the high level after a predetermined period ΔT from when the high level is inverted to the low level.

  By providing a dead time between the first switching signal φ1 and the second switching signal φ2, as shown in FIGS. 5B and 5C, the high level inversion and the second switching of the first switching signal φ1 are performed. Since the low level inversion of the signal φ2 does not occur at the same time and the low level inversion of the first switching signal φ1 and the high level inversion of the second switching signal φ2 do not occur at the same time, the first switch SW1 is turned on by the first switching signal φ1. When switching from the off state to the on state (when the node supplying the charging current Ij of the current generation circuit 14 is connected to the first capacitor C1), the second switch SW2 is already switched to the off state by the second switching signal φ2. (The node supplying the charging current Ij of the current generation circuit 14 is already disconnected from the second capacitor C2) and supplies the charging current Ij of the current generation circuit 14 Are not simultaneously connected to the first and second capacitors C1 and C2. Also, when the second switch SW2 is switched from the off state to the on state by the second switching signal φ2 (when the node supplying the charging current Ij of the current generation circuit 14 is connected to the second capacitor C2), the first switch SW1 has already been switched to the OFF state by the first switching signal φ1 (the node supplying the charging current Ij of the current generation circuit 14 has already been disconnected from the first capacitor C1), and the charging current Ij of the current generation circuit 14 Are not simultaneously connected to the first and second capacitors C1 and C2.

  As a result, the charging current Ij supplied from the current generation circuit 14 to the first capacitor C1 during the charging of the first capacitor C1 is also supplied to the second capacitor C2, and conversely the current during the charging of the second capacitor C2. Since the charging current Ij supplied from the generation circuit 14 to the second capacitor C2 is not supplied to the first capacitor C1, the pulse signals output from the first and second RS flip-flop circuits 17 and 18, respectively. It is possible to prevent an inconvenience that an error occurs in the pulse width of the signal and as a result an error occurs in the pulse width of the pulse width modulation signal PWMout. The first and second switching signals φ1 and φ2 are output to the first and second switches SW1 and SW2, respectively, and also output to the falling edge detection circuit 13.

  Note that the dead time provided in the dead time generation circuit 12 is extremely small, and the first switch SW1 is substantially controlled to be turned on and off by the reference clock MCLK, and the second switch SW2 inverts the phase of the reference clock MCLK. It can be said that ON / OFF is controlled by the clock.

  The falling edge detection circuit 13 is a circuit that outputs first and second set signals set1 and set2 supplied to first and second RS flip-flop circuits 17 and 18, which will be described later. That is, the falling edge detection circuit 13 detects the timing at which the first switching signal φ1 falls from the high level to the low level, and as shown in FIG. 5D, the signal that falls to the low level for a moment at the detection timing. Is output to the first RS flip-flop circuit 17 as the first set signal set1. Further, the falling edge detection circuit 13 detects the timing at which the second switching signal φ2 falls from the high level to the low level, and as shown in FIG. 5 (e), the signal that falls to the low level for a moment at the detection timing. Is output to the second RS flip-flop circuit 18 as the second set signal set2.

  The current generation circuit 14 performs voltage-current conversion on the audio signal eS supplied from the audio signal generation source AU to the pulse width modulation circuit 1, and generates a charging current Ij obtained by adding the DC bias current Ic to the converted current Δi. Circuit. The node that outputs the charging current Ij of the current generation circuit 14 is connected to the first and second capacitors C1 and C2 via the first and second switches SW1 and SW2, respectively. When the first switch SW1 is in the on state, The first capacitor C1 is connected to the first capacitor C1 and charged with the charging current Ij. When the second switch SW2 is in the ON state, the second capacitor C2 is connected to charge the second capacitor C2 with the charging current Ij.

  The current generation circuit 14 generates a discharge current Id, and discharges the accumulated charges of the first and second capacitors C1 and C2 with the discharge current Id. That is, the node from which the discharge current Id of the current generation circuit 14 is output is connected to the first and second capacitors C1 and C2 via the third and fourth switches SW3 and SW4, respectively, and the third switch SW3 is When the first capacitor C1 is turned on and connected to the first capacitor C1, the charge accumulated in the first capacitor C1 is discharged by the discharge current Id. When the fourth switch SW4 is turned on and connected to the second capacitor C2, the second capacitor C2 is turned on. The accumulated charge in the capacitor C2 is discharged with the discharge current Id. Details of the current generation circuit 14 will be described later.

  The current bypass circuit 16 includes a diode D2 and a voltage source 23. The current bypass circuit 16 discharges even when the node that outputs the discharge current Id of the current generation circuit 14 is not electrically connected to the first and second capacitors C1 and C2 by the third and fourth switches SW3 and SW4. This is for flowing the current Id. That is, when the node that outputs the discharge current Id of the current generation circuit 14 is not electrically connected to the first and second capacitors C1 and C2 by the third and fourth switches SW3 and SW4, the diode D2 is turned on. The voltage source 23 is connected to the node that outputs the discharge current Id of the current generation circuit 14.

  In this state, for example, when the third switch SW3 is turned on and the first capacitor C1 is connected to the node that outputs the discharge current Id of the current generation circuit 14, the voltage of the first capacitor C1 is the cathode side of the diode D2. Therefore, the diode D2 is turned off, and the path through which the discharge current Id flows is switched from the voltage source 23 to the first capacitor C1. That is, at the same time as the third switch SW3 is turned on, the discharge operation with the discharge current Id of the charge accumulated in the first capacitor C1 is started. The same operation is performed when the fourth switch SW4 is turned on, and at the same time when the fourth switch SW4 is turned on, the discharge operation with the discharge current Id of the charge accumulated in the second capacitor C2 is started.

  The first and second switches SW1 and SW2 are switches for controlling the charging operation by the charging current Ij from the current generation circuit 14 of the first and second capacitors C1 and C2. One end of the first switch SW1 is connected to a node that outputs the charging current Ij of the current generation circuit 14, and the other end of the first switch SW1 is connected to one end of the first capacitor C1 (see point A in FIG. 2). Yes. When the first switch SW1 is turned on (closed), a charging path for the first capacitor C1 is formed. Further, one end of the second switch SW2 is also connected to a node that outputs the charging current Ij of the current generation circuit 14, and the other end of the second switch SW2 is connected to one end of the second capacitor C2 (see point A ′ in FIG. 2). It is connected. When the second switch SW2 is turned on (closed), a charging path for the second capacitor C2 is formed.

  The first and second switches SW1 and SW2 are turned on and off by first and second switching signals φ1 and φ2 output from the dead time generation circuit 12. That is, as shown in FIG. 5B, the first switch SW1 is turned on when the first switching signal φ1 is at a high level, and is turned off when the first switching signal φ1 is at a low level. Further, as shown in FIG. 5C, the second switch SW2 is turned on when the second switching signal φ2 is at a high level, and is turned off when the second switching signal φ2 is at a low level.

  The third and fourth switches SW3 and SW4 are switches for controlling the discharge operation by the discharge current Id from the current generation circuit 14 of the first and second capacitors C1 and C2. One end of the third switch SW3 is connected to a node that outputs the discharge current Id of the current generation circuit 14, and the other end of the third switch SW3 is connected to one end of the first capacitor C1 (see point A in FIG. 2). Yes. When the third switch SW3 is turned on (becomes closed), a discharge path for the first capacitor C1 is formed. Further, one end of the fourth switch SW4 is also connected to a node that outputs the discharge current Id of the current generation circuit 14, and the other end of the fourth switch SW4 is connected to one end of the second capacitor C2 (see point A ′ in FIG. 2). It is connected. When the fourth switch SW4 is turned on (becomes closed), a discharge path for the second capacitor C2 is formed.

  The third and fourth switches SW3 and SW4 are turned on and off by third and fourth switching signals φ3 and φ4 from first and second RS flip-flop circuits 17 and 18, which will be described later. That is, as shown in FIG. 5H, the third switch SW3 is turned on when the third switching signal φ3 is at a high level, and is turned off when it is at a low level. Further, as shown in FIG. 5I, the fourth switch SW4 is turned on when the fourth switching signal φ4 is at a high level, and is turned off when it is at a low level.

  The first and second capacitors C1 and C2 are for generating time according to the amplitude (instantaneous voltage value) of the audio signal eS. Specifically, the first capacitor C1 generates a current when the first switch SW1 is turned on (the third switch SW3 is turned off at this time) during the on period (a certain period) of the first switching signal φ1. By charging with the charging current Ij (= Ic ± Δi, current corresponding to the amplitude (instantaneous voltage value) of the audio signal eS) from the circuit 14, the voltage corresponding to the amplitude of the audio signal eS from the threshold voltage Vth (charging end) Voltage). After the charging operation is completed, the third switch SW3 is turned on (at this time, the first switch SW1 is turned off), so that the accumulated charge is discharged with a constant discharge current Id. In this discharge operation, the discharge time until the voltage of the first capacitor C1 drops from the charge end voltage to the predetermined threshold voltage Vth is generated as a time corresponding to the amplitude (instantaneous voltage value) of the audio signal eS.

  The predetermined threshold voltage Vth is a logic level threshold voltage in the first and second RS flip-flop circuits 17 and 18, and is approximately 1 / V of the power supply voltage + Vcc supplied to the first and second RS flip-flop circuits 17 and 18. 2 voltage. For example, if the drive voltage of the first and second RS flip-flop circuits 17 and 18 is +5 [v], the threshold voltage Vth is approximately +2.5 [v].

  The second capacitor C2 is charged from the current generation circuit 14 when the second switch SW2 is turned on (the fourth switch SW4 is turned off at this time) during the on period (a certain period) of the third switching signal φ3. By charging with the current Ij, the charge start voltage Vth is raised to a voltage (charge end voltage) corresponding to the amplitude of the audio signal eS. After the charging operation is completed, the fourth switch SW4 is turned on (at this time, the second switch SW2 is turned off), so that the accumulated charge is discharged with a constant discharge current Id. In this discharge operation, a discharge time until the voltage of the second capacitor C2 drops from the charge end voltage to the predetermined threshold voltage Vth is generated as a time corresponding to the amplitude (instantaneous voltage value) of the audio signal eS.

  The first RS flip-flop circuit 17 generates a pulse signal having the same pulse width as the discharge time of the first capacitor C1 during each discharge period of the first capacitor C1, and also generates a third switching signal φ3. is there.

  The first RS flip-flop circuit 17 is an RS flip-flop circuit configured by two NAND gates (first NAND circuit NA1 and second NAND circuit NA2). The voltage of the first capacitor C1 is input to the first NAND circuit NA1 as the first reset signal res1, and the output rsout1 is output from the first NAND circuit NA1. Further, the first set signal set1 (a signal that instantaneously falls to a level lower than the threshold voltage Vth) output from the falling edge detection circuit 13 is input to the second NAND circuit NA2, and the third NAND circuit NA2 to the third A switching signal φ3 is output.

  When the first set signal set1 is input, the first RS flip-flop circuit 17 inverts the output rsout1 to low level and the third switching signal φ3 to high level, and the voltage of the first capacitor C1 is low level (threshold voltage Vth or less) In other words, when the first reset signal res1 is input, the output rsout1 is inverted to the high level and the third switching signal φ3 is inverted to the low level. Since the input timing of the first set signal set1 corresponds to the discharge start timing of the first capacitor C1, and the input timing of the first reset signal res1 is the timing when the voltage of the first capacitor C1 drops to the threshold voltage vth, the output rsout1 The low level period corresponds to the discharge time of the first capacitor C1.

  Therefore, from the output terminal of the first NAND circuit NA1 of the first RS flip-flop circuit 17, a pulse signal having the same pulse width as the discharge time of the first capacitor C1 is output as an output rsout1 during each discharge period of the first capacitor C1. Is done.

  The second RS flip-flop circuit 18 generates a pulse signal having the same pulse width as the discharge time of the second capacitor C2 during each discharge period of the second capacitor C2, and generates a fourth switching signal φ4. is there.

  Similarly to the first RS flip-flop circuit 17, the second RS flip-flop circuit 18 is also an RS flip-flop circuit configured by two NAND gates (a third NAND circuit NA3 and a fourth NAND circuit NA4). The voltage of the second capacitor C2 is input to the third NAND circuit NA3 as the second reset signal res2, and the output rsout2 is output from the third NAND circuit NA3. Further, the second set signal set2 (a signal that instantaneously falls to a level lower than the threshold voltage Vth) output from the falling edge detection circuit 13 is input to the fourth NAND circuit NA4, and the fourth NAND circuit NA4 to the fourth NAND circuit NA4. A switching signal φ4 is output.

  When the second set signal set2 is input, the second RS flip-flop circuit 18 inverts the output rsout2 to the low level and the fourth switching signal φ4 to the high level, and the voltage of the second capacitor C2 is low level (threshold voltage Vth or less) In other words, when the second reset signal res2 is input, the output rsout2 is inverted to the high level and the fourth switching signal φ4 is inverted to the low level. Since the input timing of the second set signal set2 corresponds to the discharge start timing of the second capacitor C2, and the input timing of the second reset signal res2 is the timing when the voltage of the second capacitor C2 drops to the threshold voltage vth, the output rsout2 The low level period corresponds to the discharge time of the second capacitor C2.

  Accordingly, a pulse signal having the same pulse width as the discharge time of the second capacitor C2 is output as an output rsout2 during each discharge period of the second capacitor C2 from the output terminal of the third NAND circuit NA3 of the second RS flip-flop circuit 18. Is done.

  The signal output circuit 19 is a circuit that combines the output rsout1 output from the first RS flip-flop circuit 17 and the output rsout2 output from the second RS flip-flop circuit 18. The signal output circuit 19 includes a NAND gate (fifth NAND circuit NA5). The output rsout1 is a signal that generates a pulse signal (a pulse signal having the same pulse width as the discharge time of the first capacitor C1) only during the low level period of the reference clock MCLK, while the output rsout2 is the high level of the reference clock MCLK. Since the pulse signal (the pulse signal having the same pulse width as the discharge time of the second capacitor C2) is generated only during the period, the signal output circuit 19 outputs the pulse signal of the output rsout1 and the pulse signal of the output rsout2. A pulse signal (a pulse train signal having a pulse width corresponding to the eS amplitude (instantaneous voltage value) of the audio signal in the same cycle as the half cycle of the reference clock MCLK) is output as a pulse width modulation PMWout. Is done.

[Configuration of Current Generation Circuit 14]
FIG. 3 is a circuit diagram of the current generation circuit 14. The current generation circuit 14 includes a constant current generation means 31, a differential circuit 32, current-voltage conversion means (hereinafter referred to as IV conversion circuit) 33 and 35, and voltage-current conversion means (hereinafter referred to as VI conversion circuit). 34, 36. The current generation circuit 14 further includes addition means (a configuration in which the audio signal generation source AU is connected to the base of the transistor Q1) for adding the current Δi corresponding to the audio signal eS to the DC bias current Ic. Yes.

  The current generation circuit 14 generates a DC bias current Ic of the charging current Ij and a discharge current Id from the constant current generated by the common constant current generation unit 31. Therefore, even if the DC bias current Ic and the discharge current Id fluctuate due to a temperature change due to the temperature coefficient of the constant current generating means 31, there is a fluctuation error between the DC bias current Ic and the discharge current Id. By canceling each other, the ratio of the DC bias current Ic and the discharge current Id can be maintained at a constant ratio (for example, Ic: Id = 1: 2).

  The constant current generating means 31 employs a general constant current circuit (hereinafter referred to as a constant current circuit 31). For example, the constant current circuit 31 employs a circuit composed of a JFET and a resistor, or a circuit composed of a voltage source, a resistor, and a bipolar transistor. The constant current circuit 31 generates a constant current I1 and supplies it to the differential circuit 32 and the IV conversion circuit 33.

  The differential circuit 32 is connected to the constant current circuit 31, and generates a current I2 having a magnitude that is 1/2 of the current I1 supplied from the constant current circuit 31. Specifically, the differential circuit 32 generates a current I2 ± Δi obtained by adding the current ± Δi obtained by voltage-current conversion of the audio signal eS from the audio signal source AU to the current I2. Differential circuit 32 includes npn transistors Q1, Q2 and resistors R1, R2, R6, R7. The transistor Q1 has an emitter connected to the constant current circuit 31 via the resistor R6, a collector connected to the power supply voltage VCC via the resistor R1, and a base connected to the audio signal source AU. The transistor Q2 has an emitter connected to the constant current circuit 31 via the resistor R7, a collector connected to the power supply voltage VCC via the resistor R2, and a base connected to the ground potential (however, on the actual circuit, The base may give negative feedback). Resistors R1 and R2 have the same resistance value (R1 = R2), and transistors Q1 and Q2 have characteristics (for example, conduction start voltage (base-emitter voltage), internal resistance, temperature coefficient) Etc.) are used, and resistance elements having the same resistance value and temperature coefficient are used for the resistors R6 and R7.

  In differential circuit 32, current I2 + Δi flows from the collector of transistor Q1 to the emitter, and current I2-Δi flows from the collector of transistor Q2 to the emitter. When the amplitude value of the audio signal eS is 0 (no signal), Δi is 0, so that the current I2 flows from the collector of the transistor Q1 toward the emitter, and the current flows from the collector of the transistor Q2 toward the emitter. I2 flows.

  The IV conversion circuit 33 is supplied with the current I1 from the constant current circuit 31, and generates a voltage Vb2 by performing current-voltage conversion on the current I1. The IV conversion circuit 33 includes a resistor R3. One end of the resistor R3 is connected to the constant current circuit 31 and the base of the transistor Q4, and the other end is connected to the power supply voltage -VCC. A voltage Vb2 is generated across the resistor R3, and the voltage Vb2 is supplied to the VI conversion circuit 34.

  The VI conversion circuit 34 is supplied with the voltage Vb2 from the IV conversion circuit 33, and generates a discharge current Id by converting the voltage Vb2 into voltage-current. The VI conversion circuit 34 includes an npn transistor Q4 and a resistor R5. The transistor Q4 has a base connected to a connection point between the constant current circuit 31 and the resistor R3, an emitter connected to the power supply voltage -VCC through the resistor R5, and a collector serving as a node that outputs the discharge current Id. In other words, the collector of the transistor Q4 is connected to the first capacitor C1 through the third switch SW3, and is connected to the second capacitor C2 through the fourth switch SW4.

  The IV conversion circuit 35 generates a voltage Vb1 by current-voltage conversion of the current I2 + Δi generated by the differential circuit 32. The IV conversion circuit 35 includes a resistor R <b> 1 that is a part of the differential circuit 32. One end of the resistor R1 is connected to the collector of the transistor Q1 and the base of the transistor Q3, and the other end is connected to the power supply voltage VCC. A voltage Vb1 is generated across the resistor R1, and the voltage Vb1 is supplied to the VI conversion circuit 36.

  The VI conversion circuit 36 is supplied with the voltage Vb1 from the IV conversion circuit 35, and generates a charging current Ic + Δi by performing voltage-current conversion on the voltage Vb1. The VI conversion circuit 36 includes a pnp transistor Q3 and a resistor R4. The transistor Q3 has a base connected to a connection point between the transistor Q1 and the resistor R1, an emitter connected to the power supply voltage VCC via the resistor R4, and a collector serving as a node that outputs the charging current Ic + Δi. That is, the collector of the transistor Q3 is connected to the first capacitor C1 via the first switch SW1, and is connected to the second capacitor C2 via the second switch SW2. Transistors Q3 and Q4 have the same characteristics (for example, conduction start voltage, internal resistance, temperature coefficient, etc.). As for the relationship between the resistor R4 and the resistor R5, the resistance value is R4 = 2R5.

Hereinafter, it will be described that the current generation circuit 14 can maintain the relationship of Ic: Id = 1: 2 without being affected by the temperature coefficient of each element. In the following, it is assumed that the audio signal is no signal (Δi = 0).
Due to the relationship between the constant current circuit 31 and the differential circuit 32, as described above, the relationship between the currents I1 and I2 is as follows.
I1 = 2I2 (Formula 1)

The voltages Vb1 and Vb2 generated by the IV conversion circuits 35 and 33 are as follows.
Vb1 = R1 · I2 (Formula 2)
Vb2 = R3 · I1 (Formula 3)

The current Ic flowing from the emitter to the collector of the transistor Q3 and the current Id flowing from the collector to the emitter of the transistor Q4 are as follows. However, Vbe is a conduction start voltage of the transistors Q3 and Q4.
Ic = (Vb1-Vbe) / R4 (Formula 4)
Id = (Vb2-Vbe) / R5 (Formula 5)

Here, when R1 = 2R3 is set, Vb2 is expanded into the following equation by Equations 1 to 3, and becomes equal to Vb1.
Vb2 = R3 · I1 = (R1 / 2) · 2I2 = R1 · I2 = Vb1 (Formula 6)

Since R4 = 2R5 as described above, the relationship of DC bias current Ic: discharge current Id = 1: 2 is obtained from Equations 4 to 6. Here, assuming that the change in Vbe based on the temperature coefficient of the transistors Q3 and Q4 is ΔVbe, Equations 1 to 5 are developed, and the DC bias current Ic and the discharge current Id are as follows.
Ic = (R1 · I2- (Vb2 + ΔVbe)) / R4
= (R1 · I1-2 (Vb2 + ΔVbe)) / 2R4 (Formula 7)
Id = (R3 · I1- (Vbe + ΔVbe)) / R5
= (R1 · I1-2 (Vbe + ΔVbe) / R4
= 2 (R1 · I1-2 (Vb2 + ΔVbe)) / 2R4 (Formula 8)
Therefore, even when the change ΔVbe in Vbe based on the temperature coefficients of the transistors Q3 and Q4 is included in the DC bias current Ic and the discharge current Id, the relationship of Ic: Id = 1: 2 is maintained.

  As described above, even if the DC bias current Ic and the discharge current Id vary depending on the temperature coefficient, the ratio of the current values of the DC bias current Ic and the discharge current Id is maintained in the relationship of Ic: Id = 1: 2. be able to. That is, even if the DC bias current Ic increases and the charging end voltage of the first and second capacitors C1 and C2 increases, the discharge current Id also increases at the same rate. The time until the voltage of C2 reaches the threshold voltage does not vary with temperature. Even if the discharge current Id increases and the discharge speed of the first and second capacitors C1 and C2 increases, the DC bias current Ic also increases at the same rate, so that the charging of the first and second capacitors C1 and C2 is performed. The time until the end voltage increases and the voltage of the first and second capacitors C1, C2 reaches the threshold voltage due to discharge by the discharge current Id does not vary with temperature. As a result, even if the discharge current Id and the DC bias current Ic fluctuate due to the temperature coefficient, the pulse width modulation signal PWMout that accurately corresponds to the audio signal eS can be output.

  FIG. 4 is a circuit diagram showing a current generation circuit 14 ′ according to another embodiment. In the current generation circuit 14 ′, a resistor R 8 is employed as the constant current generation means 31 instead of the constant current circuit 31. Other configurations are the same as those of the current generation circuit 14 of FIG.

  In FIGS. 3 and 4, an inverted configuration in which the transistors Q1 and Q2, Q3 and Q4 are joined by an npn transistor and a pnp transistor may be employed.

[Operation of pulse width modulation circuit]
Next, the operation of the pulse width modulation circuit 1 will be described with reference to the time charts of FIGS.

  FIG. 5 is a time chart when the amplitude of the audio signal is 0 (that is, charging current Ij = DC bias current Ic). 5F and 5G, the solid line N1 is the voltage waveform of the capacitors C1 and C2 when the current values of the discharge current Id and the DC bias current Ic do not vary with temperature, and the broken line N2 The voltage waveforms of the capacitors C1 and C2 when the discharge current Id and the DC bias current Ic increase according to the temperature, and the broken line N3 indicates the capacitors C1 and C1 when the discharge current Id and the DC bias current Ic decrease according to the temperature. It is a voltage waveform of C2. First, the basic operation of the pulse width modulation circuit 1 in the case where the discharge current Id and the DC bias current Ic do not vary with temperature will be described.

  A high level period and a low level period of the first switching signal φ1 are a charging period and a discharging period of the first capacitor C1, respectively. When the first switching signal φ1 is inverted to the high level, the first switch SW1 connects the output node of the charging current Ij of the current generation circuit 14 to the first capacitor C1, and the first capacitor by the charging current Ij from the current generation circuit 14 is connected. Charging of C1 is started. The charging operation is continued until the first switching signal φ1 is inverted to the low level and the first switch SW1 disconnects the current generation circuit 14 (see FIGS. 5B and 5F).

  When the first switching signal φ1 is inverted to a low level and shifts to the discharge period, the third switching signal φ3 output from the first RS flip-flop circuit 17 is set to a high level by the first set signal set1 that detects the low level inversion. As a result, the third switch SW3 connects the output node of the discharge current Id of the current generation circuit 14 to the first capacitor C1, and the discharge of the first capacitor C1 by the discharge current Id from the current generation circuit 14 is started. . The discharging operation continues until the voltage of the first capacitor C1 drops to the threshold voltage Vth, whereby the third switching signal φ3 is inverted to a low level, and the third switch SW3 disconnects the current generating circuit 14 (FIG. 5). (See (b), (d), (f)).

  During the discharge period, the first set signal set1 is input from the first RS flip-flop circuit 17 and at the same time the level is inverted to a low level, and the voltage of the first capacitor C1 input as the first reset signal res1 decreases to the threshold voltage Vth. At the same time, a pulse signal that is inverted to a high level is output as an output rsout1. That is, a pulse signal having a pulse width corresponding to the amplitude of the audio signal eS is generated (see (j) in FIG. 5).

  Further, the high-level period and the low-level period of the second switching signal φ2 are a charging period and a discharging period of the second capacitor C2, respectively. If the dead time is ignored, the second switching signal φ2 is a signal obtained by inverting the phase of the first switching signal φ1, so that the second capacitor C2 is similar to the charge / discharge operation in the first capacitor C1 described above. The charging / discharging operation is performed while being shifted by a half cycle of the first switching signal φ1 (see (c), (e), (g), (i) in FIG. 5).

  Therefore, during the discharge period of the second capacitor C2, the second set signal set2 is input from the second RS flip-flop circuit 18 and at the same time inverted to a low level, and the second capacitor C2 input as the second reset signal res2 A pulse signal that is inverted to a high level at the same time that the voltage drops to the threshold voltage Vth is output as an output rsout2. That is, a pulse signal having a pulse width corresponding to the amplitude of the audio signal eS is generated (see (k) in FIG. 5).

  The output rsout1 and the output rsout2 output from the first and second flip-flop circuits 17 and 18 are synthesized by the signal output circuit 19 to be a pulse width modulation signal PWMout (a signal obtained by synthesizing the waveform of the output rsout1 and the waveform of the output rsout2). (See (l) of FIG. 5).

  As shown in FIG. 6, when the amplitude of the audio signal eS is positive, the magnitude of the charging current Ij = Ic + Δi is large, and the slope of the charging voltage waveform at one end of the first and second capacitors C1 and C2 is increased. Also, the amplitude of the audio signal eS becomes larger than when the amplitude is zero. Therefore, the terminal voltage of the first and second capacitors C1 and C2 at the time when the level of the first or second switching signal φ1 or φ2 is inverted from the high level to the low level is higher than that when the audio signal eS is no signal. When these are discharged by the discharge current Id, the time to reach the threshold voltage Vth after the discharge is started is longer than when the audio signal eS is no signal. Therefore, as shown in FIG. 6 (l), the pulse width modulation signal PWMout having a long high level time is output compared to the case where the audio signal eS shown in FIG. Thus, the pulse width modulation signal PWMout corresponding to the amplitude of the audio signal eS is output.

  Although not shown, similarly, when the audio signal eS is negative, the magnitude of the charging current Ij = Ic + Δi is small, and the slope of the charging voltage waveform at one end of the first and second capacitors C1, C2 is also small. . Therefore, the terminal voltage of the first and second capacitors C1 and C2 at the time when the level of the first or second switching signal φ1 or φ2 is inverted from the high level to the low level is higher than that when the audio signal eS is no signal. When these are discharged by the discharge current Id, the time to reach the threshold voltage Vth after the start of discharge is shorter than when the audio signal eS is no signal. Accordingly, the pulse width modulation signal PWMout is output with a shorter high level time than when the audio signal eS is not a signal.

  Next, a case where the amplitude of the audio signal is 0 and both the discharge current Id and the DC bias current Ic increase with temperature will be described with reference to the broken line N2 in FIG. As described above, the discharge current Id and the DC bias current Ic both increase due to temperature, but the relationship of Ic: Id = 1: 2 is maintained. Accordingly, when the first capacitor C1 is charged by the DC bias current Ic and the first switching signal φ1 is inverted from the high level to the low level, the charging end voltage of the first capacitor C1 depends on the temperature depending on the DC bias current Ic and the discharge current. Although Id is higher than that in the case of the solid line N1 that does not fluctuate, the discharge current Id also increases at the same ratio as the DC bias current Ic, so the first capacitor C1 is discharged by the discharge current Id, and the threshold value The time until the voltage Vth is reached is the same as in the case of the solid line N1. Note that, as indicated by a broken line N2 in FIG. 5G, the second capacitor C2 is similarly discharged by the discharge current Id, and the time until it reaches the threshold voltage Vth is the same as in the case of the solid line N1. As a result, although both the discharge current Id and the DC bias current Ic increase according to the temperature, a normal pulse width modulation signal PWMout can be output as in the case of the solid line N1.

  Next, a case where the amplitude of the audio signal eS is 0 and both the discharge current Id and the DC bias current Ic decrease according to the temperature will be described with reference to the broken line N3 in FIG. As described above, the discharge current Id and the DC bias current Ic both decrease due to temperature, but the relationship of Ic: Id = 1: 2 is maintained. Accordingly, when the first capacitor C1 is charged by the DC bias current Ic and the first switching signal φ1 is inverted from the high level to the low level, the charging completion voltage of the first capacitor C1 is the DC bias current Ic and the voltage depending on the temperature. Although the discharge current Id is lower than that in the case of the solid line N1 that does not fluctuate, the discharge current Id also decreases at the same rate as the DC bias current Ic, so the first capacitor C1 is discharged by the discharge current Id. The time to reach the threshold voltage Vth is the same as in the case of the solid line N1. Note that, as indicated by the broken line N3 in FIG. 5G, the second capacitor C2 is similarly discharged by the discharge current Id, and the time until the threshold voltage Vth is reached is the same as in the case of the solid line N1. As a result, although the discharge current Id and the DC bias current Ic both decrease according to the temperature, a normal pulse width modulation signal PWMout can be output as in the case of the solid line N1.

[Another embodiment]
Next, a pulse width modulation circuit 1 ′ according to another embodiment of the present invention will be described. FIG. 7 is a block circuit diagram showing the main part of the pulse width modulation circuit 1 ′. In FIG. 7, only the parts different from FIG. 2 are described, and the reference clock generation circuit 11, the dead time generation circuit 12, the falling edge circuit 13, the first RS flip-flop circuit 17, the second RS flip-flop circuit 18, and The signal output circuit 19 is omitted. The pulse width modulation circuit 1 ′ is obtained by reversing the direction of voltage change of the first and second capacitors C1 and C2 during the charge / discharge period. That is, the directions of the charging current Ij (= Ic + Δi) and the discharging current Id are opposite to those of the pulse width modulation circuit 1 in FIG. 2, and the first capacitor C1 is applied by the charging current Ij during the period when the first switching signal φ1 is at the high level. Is discharged (that is, charged in the negative direction with respect to the ground potential), and the first capacitor C1 is charged with the discharge current Id while the first switching signal φ1 is at the low level (that is, discharged in the positive direction with respect to the ground potential). ) The pulse width modulation circuit 1 ′ is provided with comparison circuits 27 and 28 for comparing the charging voltages of the first and second capacitors C1 and C2 with the reference voltage Vref instead of the threshold voltage. The details of the pulse width modulation circuit 1 ′ are disclosed in Patent Document 2 above.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment. The constant ratio between the DC bias current Ic and the discharge current Id is not limited to 1: 2, but may be 1: 1 or 2: 3 depending on the circuit configuration.

  The present invention can be suitably applied to a pulse width modulation circuit of an audio switching amplifier.

1, 1 'pulse width modulation circuit 2 switching circuit 3 low-pass filter circuit 4 first power supply 5 second power supply 11 reference clock generation circuit 12 dead time generation circuit 13 falling edge detection circuit 14 current generation circuit 16 current bypass circuit 17 first RS Flip-flop circuit 18 second RS flip-flop circuit 19 signal output circuit 23 voltage source C1 first capacitor C2 second capacitor eS audio signal Ic DC bias current Id discharge current res1 first reset signal res2 second reset signal set1 first set signal set2 Second set signal SW1 First switch SW2 Second switch SW3 Third switch SW4 Fourth switch Vth Threshold voltage φ1 First switching signal φ2 Second switching signal φ3 Third switching signal φ4 Fourth switching signal

Claims (4)

First charge storage means for storing charge;
Second charge storage means for storing charge;
Current generating means for generating a first current whose current value changes according to the amplitude of the AC voltage from the input AC voltage, and generating a second current;
The voltage in the first charge storage means is changed in a first period which is a half cycle of a predetermined clock signal based on the first current, and a half cycle shift from the first period based on the second current. In the second period following the first period, the voltage in the first charge storage means is changed in the direction opposite to the increase / decrease direction in the first period, and the second charge storage means is changed based on the first current. The voltage in the second charge storage means is changed in the second period in the third period following the second period shifted by a half cycle from the second period based on the second current. Voltage control means for changing in the opposite direction;
First detection means for detecting a time from when the second period starts until the voltage in the first charge storage means reaches a threshold voltage;
Second detection means for detecting a time from when the third period starts until the voltage in the second charge storage means reaches the threshold voltage;
A pulse signal generation unit that generates a pulse signal having a pulse width of the time based on a time alternately output from the first detection unit and the second detection unit every half cycle of the clock signal;
The current generation means includes constant current generation means for generating a third current that is a constant current, generates the first current from the third current and the AC voltage, and generates the first current from the third current. A pulse width modulation circuit for generating the second current. The current generating means is
A differential circuit that generates a fourth current obtained by adding a current having a current value that is ½ of the third current and a current obtained by converting the alternating voltage into a current;
First current-voltage conversion means for converting the third current into a first voltage;
First voltage-current conversion means for converting the first voltage supplied from the first current-voltage conversion means into a current and generating the second current;
Second current-voltage conversion means for converting the fourth current into a second voltage;
2. The pulse width modulation according to claim 1, further comprising: a second voltage-current conversion unit configured to convert the second voltage supplied from the second current-voltage conversion unit into a current and generate the first current. circuit.   3. The pulse width modulation according to claim 2, wherein each of the first voltage-current conversion unit and the second voltage-current conversion unit includes transistors, and the transistors have the same temperature coefficient and base-emitter voltage. circuit. The pulse width modulation circuit according to any one of claims 1 to 3,
A voltage source that outputs a predetermined reference power supply voltage;
A switching amplifier comprising: a switching circuit that switches the reference power supply voltage supplied from the voltage source based on a modulation signal output from the pulse width modulation circuit.

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