JP2011021987A - Semiconductor test device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor test device which can intuitively obtain position information of a pin of a pin electronics card allocated to each pin of a DUT with a simple operation procedure. <P>SOLUTION: In the semiconductor test device having an operation display screen and constituted so that a prescribed pin of a DUT is allocated to each pin of a plurality of pin electronics cards accommodated in a test head in accordance with a test item, the operation display screen includes a DUT pin designation area for inputting a pin number of the DUT to be retrieved, a slot layout screen display area displaying a slot layout screen representing the arrangement relation of the slot in the test head accommodating the plurality of pin electronics cards, and a list display area displaying the retrieval result corresponding to the pin number of the DUT in a list display screen format. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus, and more particularly to a visualization display of allocation between pins of a pin electronics card housed in a test head and pins of a test object (hereinafter referred to as DUT).

  FIG. 5 is a block diagram showing a conceptual configuration example of a conventional semiconductor test apparatus. In the test head 10, a plurality of n pin electronics cards 20 on which a plurality of measurement circuits are mounted are modularized and stored.

  In testing a plurality of m DUTs 30, predetermined pins of the DUT 30 are assigned to the respective pins of the pin electronics card 20 according to the test items, and the test items are set between the respective pins of the pin electronics card 20 and the predetermined pins of the DUT 30. Various input / output signals such as a DC signal, an AC signal, a high-frequency signal, and a digital signal related to the measurement are transmitted and received.

  By the way, the user of the semiconductor test apparatus performs the test of the DUT 30 efficiently in the test of the DUT 30, and in order to correctly judge and analyze the result, each pin of the pin electronics card 20 in each test item and a predetermined pin of the DUT 30 It is necessary to accurately grasp the correct allocation relationship.

  FIG. 6 is an explanatory diagram showing an example of the flow of processing for grasping the allocation relationship of each pin in a conventional semiconductor test apparatus.

  When the user grasps the position of the pin number HWP # of the pin electronics card 20 from the pin number DUTP # of the DUT 30, first, as a first step, the device definition shown in (A) stored in advance in the semiconductor test apparatus Based on the file, the pin number DUTP # of the DUT 30 is associated with the pin number ATEP # of the semiconductor test equipment.

  Subsequently, as a second stage, based on the system configuration file (B) stored in advance in the semiconductor test apparatus, the pin number ATEP # of the semiconductor test apparatus is changed to the slot number SLOT # and the pin number of the pin electronics card 20. Associate with HWP #. Thus, the slot number SLOT # corresponding to the pin number DUTP # of the DUT 30 and the pin number HWP # of the pin electronics card 20 are determined.

  Then, as a third stage, the test head 10 is referred to by referring to the slot layout diagram of the test head 10 shown in (C) created based on the arrangement relationship of the pin electronics card 20 actually stored in the test head 10. The pin electronics card 20 corresponding to the pin electronics card 20 stored in the card is identified, and the corresponding pin number HWP # is identified. In (C), the positional relationship between the test head 10 and the operator is indicated by a specific figure (for example, a triangular mark MARK).

FIG. 7 is an example of a command list created in advance so as to correspond to the slot layout diagram of FIG.
1) Correspondence relationship between pin number DUTP # of DUT and pin number ATEP # of semiconductor test equipment 2) Slot number SLOT # in which corresponding pin electronics card 20 is stored and measurement channel mounted on pin electronics card 20 Coordinate information LOCATION of the pin number HWP # assigned to correspond to the number CH # and each measurement channel
3) Power supply unit numbers PMU (DUT) #, PMU (ATE) # for supplying predetermined power individually to each measurement channel of the DUT and semiconductor test equipment
Etc. are described.

  By performing such a series of processing, the pin position in the corresponding pin electronics card 20 accommodated in the test head 10 is specified as shown by the intersection of the straight lines Lx and Ly orthogonal to the layout diagram of FIG. it can.

  FIG. 9 is an example of a device definition file that is referred to in the first stage when two DUTs 30 are tested simultaneously. The number “2” of DUTs 30 to be tested simultaneously is designated in the front part a, and the pin number DUTP # of the DUT 30 is associated with the pin number ATEP # of the semiconductor test apparatus in the rear part b.

  For example, in “1 DPIN1 IO = 1, 25;” in the first row of the rear stage part b, the first pin of the DUT 30 is an IO pin, and the first pin of one DUT 30 is the pin number 1 of the semiconductor test apparatus. Is assigned, and the first pin of the other DUT 30 indicates that pin number 25 of the semiconductor test equipment is assigned.

  Patent Document 1 describes an LSI test apparatus that can arbitrarily perform cluster assignment of test pins regardless of the number of DUTs.

JP-A-11-64448

However, since there is a lot of information that must be associated with the conventional pin electronics card assignment process for each pin, it is difficult to intuitively grasp the pin position information of the pin electronics card, and the pin position information assignment process result There is a problem that it takes considerable work time to obtain.
This problem becomes more prominent when it is configured to test a plurality of DUTs simultaneously.

  The present invention pays attention to such conventional problems, and its purpose is to intuitively grasp the pin position information of the pin electronics card assigned to each pin of the DUT with a simple operation procedure. It is to provide a semiconductor test apparatus.

The invention of claim 1 which achieves such a problem,
In a semiconductor test apparatus having an operation display screen and configured to assign a predetermined pin of a DUT to each pin of a plurality of pin electronics cards housed in a test head according to a test item,
In the operation display screen,
A DUT pin designation area for inputting a pin number of the DUT to be searched;
A slot layout screen display area for displaying a slot layout screen indicating a slot layout relationship in a test head in which the plurality of pin electronics cards are stored;
A list display area for displaying a search result corresponding to the pin number of the DUT in a predetermined list display screen format is provided.

The invention of claim 2 is the semiconductor test apparatus according to claim 1,
The slot layout screen display in the slot layout screen display area changes in conjunction with selection of an arbitrary pin on the list displayed in the list display area.

The invention of claim 3 is the semiconductor test apparatus according to claim 1 or 2,
The operation display screen is provided with a 3D instruction button for instructing to display the slot layout screen three-dimensionally (3D).

The invention of claim 4 is the semiconductor test apparatus according to claim 3,
The operation display screen is provided with a rotation instruction button for arbitrarily changing and setting the display rotation angle of the three-dimensional display screen.

According to a fifth aspect of the present invention, in the semiconductor test apparatus according to any one of the first to fourth aspects,
A plurality of DUTs are tested at the same time.

  By these, it is possible to intuitively grasp the pin position information of the pin electronics card assigned to each pin of the DUT with a simple operation procedure.

It is a block diagram which shows one Example of this invention. FIG. 2 is a display screen example illustrating the operation of FIG. 1. It is an example figure of the main display screen in another Example. It is an example figure of the sub display screen in another Example. It is a block diagram which shows the conceptual structural example of the conventional semiconductor test apparatus. It is explanatory drawing which shows an example of the flow of a process for grasping | ascertaining the allocation relationship of each pin in the conventional semiconductor test apparatus. It is a prior art command list example figure. 2 is a layout example diagram of a pin electronics card 20 housed in a test head 10. FIG. It is a device definition file example figure in the case of performing two DUT tests simultaneously.

  Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the main part of the present invention. Each block is connected via a bus B.

  In FIG. 1, the device definition file storage unit 101 stores a device definition file for associating the pin number DUT # of the DUT 30 with the pin number ATEP # of the semiconductor test apparatus.

  The system configuration file storage unit 102 stores a system configuration file for associating the pin number ATEP # of the semiconductor test apparatus with the slot number SLOT # and the pin number HWP # of the pin electronics card 20.

  The slot layout file storage unit 103 stores a layout file indicating a slot arrangement relationship in the test head 10 in which a plurality of pin electronics cards 20 are stored.

The pin location command storage unit 104 stores a command list file created in advance in the semiconductor test apparatus so as to correspond to the slot layout file stored in the slot layout file storage unit 103. Specifically, similar to the command list of FIG.
1) Correspondence relationship between pin number DUTP # of DUT and pin number ATEP # of semiconductor test equipment 2) Slot number SLOT # in which corresponding pin electronics card 20 is stored and measurement channel mounted on pin electronics card 20 Coordinate information LOCATION of the pin number HWP # assigned to correspond to the number CH # and each measurement channel
3) Power supply unit numbers PMU (DUT) #, PMU (ATE) # for supplying predetermined power individually to each measurement channel of the DUT and semiconductor test equipment
Etc. are stored.

  The list display format storage unit 105 stores a list display screen format for listing and displaying the allocation relationship of each pin.

  The operation input unit 106 is a man-machine interface for instructing and inputting data and commands necessary for the semiconductor test apparatus, and includes a keyboard and a mouse.

  The input pin related information search unit 107 searches the device definition file storage unit 101, the system configuration file storage unit 102, the slot layout file storage unit 103, and the like based on the DUT pin number DUTP # input from the operation input unit 106. Then, the positional information such as the pin number ATEP #, the slot number SLOT #, the pin number HWP # of the pin electronics card 20 and the like of the semiconductor test apparatus related to the input DUT pin number DUTP # is extracted.

  The input pin related information list editing unit 108 edits the search result in the input pin related information search unit 107 so as to be expanded and displayed in a predetermined list display screen format stored in the list display format storage unit 105.

  The display screen generation unit 109 generates a display screen including a list edited by the input pin related information list editing unit 108 and a slot layout screen indicating the slot arrangement relationship in the test head 10.

  The slot layout screen 3D processing unit 110 performs a predetermined process for stereoscopically displaying the slot layout screen displayed on the display screen.

  The 3D screen rotation processing unit 111 performs a predetermined process for rotating and displaying the slot layout screen displayed three-dimensionally on the display screen at a specified angle in accordance with a setting input from the operation input unit 106.

  FIG. 2 is an example of a display screen for explaining the operation of FIG. 1. FIG. 2A shows an example of displaying the slot layout screen two-dimensionally, and FIG. 2B shows an example of displaying the slot layout screen three-dimensionally (3D). Show.

  2A and 2B, on the display screen 120, a slot layout screen display area 121 for displaying a slot layout screen showing a slot layout relationship in the test head 10 and a pin number DUTP of a DUT to be searched are displayed. A DUT pin designation area 122 for inputting # and a list display area 123 for displaying a search result in the input pin related information search unit 107 in a predetermined list display screen format are provided.

  A vertical scroll bar 124 and a horizontal scroll bar 125 are provided in the vicinity of the list display area 123.

  Further, in the vicinity of the slot layout screen display area 121, a 3D instruction button 126 for instructing execution of predetermined processing for stereoscopically displaying the slot layout screen as shown in FIG. Rotation instruction buttons 127 and 128 for instructing to rotate and display the slot layout screen in a predetermined direction are provided.

In the slot layout screen of the slot layout screen display area 121, the slot number SLOT # of the test head 10 in which the pin electronics card 20 is stored and the following functions of the measurement circuit mounted on each pin electronics card 20 are shown. Is displayed together.
DPS; DUT power supply card RVI; Reference voltage / current source card HR; High resolution card HS; High speed card opt; Option card DFC; DUT function test card SAPW; Utility power supply card STM; Time measurement card FCNT; card

  By inputting the DUT pin number DUTP # of the DUT to be searched from the operation input unit 106 to the DUT pin designation area 122, the input pin related information search unit 107 has a device definition file storage unit 101 and a system configuration file storage unit 102. The slot layout file storage unit 103 and the like are searched, and the semiconductor test equipment pin number ATEP #, slot number SLOT #, and pin number HWP # of the pin electronics card 20 associated with the input DUT pin number DUTP #, The slot number position information Loc and the like are extracted, and the extracted data is output to the input pin related information list editing unit 108.

  The input pin related information list editing unit 108 edits the result searched by the input pin related information search unit 107 so as to be expanded and displayed in a predetermined list display screen format stored in the list display format storage unit 105. And output to the display screen generation unit 109.

As a result, in the list display area 123 of the display screen 120 in FIGS. 2A and 2B, detailed information including the following items regarding the designated DUT pin numbers 1 to 4 is displayed in a list.
・ ATE → Semiconductor test equipment pin number ATEP #
SLOT → Test head 10 slot number SLOT #
・ HWpin → Pin number of pin electronics card 20 HWP #
Loc → Coordinate position information of a specified pin in the pin electronics card 20

  Then, on the list displayed in the list display area 123 of the display screen 120, when a line of an arbitrary pin is click-selected with the mouse of the operation input unit 106, for example, the selected line is highlighted and displayed. The position information of the selected pin in the pin electronics card 20 is displayed by the intersection of straight lines orthogonal to the slot layout screen display area 121.

  2A and 2B show a state in which the first pin of the DUT is selected and designated, and the ATE pin number “1”, the SLOT number “101”, the HWpin number “1”, and Loc. The coordinate position “E2” is highlighted and the coordinate position “E2” on the slot layout screen display area 121 of the selected pin in the pin electronics card 20 is an orthogonal X-coordinate line “E” and Y-coordinate line. It is indicated by the intersection of “2”.

  If there are too many pin numbers of DUTs to be searched and cannot be displayed at once in the list display area 123, the display contents are scrolled in the vertical direction by operating the vertical scroll bar 124, and the related items of each pin If the list display area 123 cannot be displayed at one time, the horizontal scroll bar 125 is operated to scroll the display contents in the horizontal direction.

  When the 3D instruction button 126 is selected on the two-dimensional display screen in FIG. 2A, the slot layout screen in the slot layout screen display area 121 is switched to the three-dimensional (3D) display screen in FIG.

  By operating the rotation instruction buttons 127 and 128 on the three-dimensional (3D) display screen of FIG. 2B, the display rotation angle of the slot layout screen in the slot layout screen display area 121 can be arbitrarily changed and set. When the 3D instruction button 126 is selected on the three-dimensional (3D) display screen, the screen is switched again to the two-dimensional display screen of FIG.

  By configuring in this way, the correspondence between the DUT pin number and the pin number of the semiconductor test apparatus can be achieved by simply inputting the pin number of the DUT to be searched into the DUT pin designation area 122 of the slot layout screen display area 121. The common display screen 120 can visualize the relationship, the correspondence between the slot number in which the pin electronics card is stored and the pin number assigned to the pin electronics card, and the pin position information on the pin electronics card. The result of pin position information assignment processing can be intuitively grasped in a short time.

  FIG. 3 and FIG. 4 are examples of display screens in another embodiment, showing an example of a semiconductor test apparatus configured to simultaneously test a plurality of DUTs.

  FIG. 3 is an example of a main display screen 130. A display area of a slot layout screen 131 showing a slot arrangement relationship in the test head 10 is provided in the lower part, and a DUT selection part 132 for selecting the DUT of interest is provided in the upper part. A display area is provided.

  In FIG. 3, the slot number (for example, “101”) in which the corresponding pin electronics card is stored in the slot layout screen 131 is highlighted by selecting the DUT of interest in the DUT selection unit 132. Here, when the highlighted slot number “101” is selected by clicking with the mouse of the operation input unit 106, for example, a sub display screen 140 shown in FIG. 4 is displayed.

  In FIG. 4, a display area of a pin layout screen 141 of the pin electronics card shown in (A) or a pin layout screen 142 as a semiconductor test apparatus shown in (B) is provided in the lower part, and the DUT of interest is selected in the upper part. A display area is provided for the DUT selection unit 143 to select, the HWpin selection unit 144 to select the pin layout screen 141 of the pin electronics card, and the ATE selection unit 145 to select the pin layout screen 142 as the semiconductor test apparatus.

  In FIG. 4A, the pin layout screen 141 of the pin electronics card is displayed by selecting “1” as the DUT and selecting the HWpin selection unit 144 by the DUT selection unit 143. Thereby, in this embodiment, the pin numbers 1 to 8 used in the selected DUT “1” are highlighted.

  In FIG. 4B, the DUT selection unit 143 selects “2” as the DUT and selects the ATE selection unit 145, thereby displaying the pin layout screen 142 as a semiconductor test apparatus. Thereby, in this embodiment, the pin numbers 89 to 96 used in the selected DUT “2” are highlighted.

  By configuring as shown in FIG. 3 and FIG. 4, in a multi-DUT test, pin position information of the pin electronics card assigned to each pin of the DUT can be grasped intuitively and accurately by displaying the display screen. .

  As described above, according to the present invention, it is possible to realize a semiconductor test apparatus that can intuitively grasp the pin position information of the pin electronics card assigned to each pin of the DUT with a simple operation procedure.

DESCRIPTION OF SYMBOLS 101 Device definition file storage part 102 System configuration file storage part 103 Slot layout file storage part 104 Pin location command storage part 105 List display format storage part 106 Operation input part 107 Input pin related information search part 108 Input pin related information list edit part 109 Display Screen Generation Unit 110 Slot Layout Screen 3D Processing Unit 111 3D Screen Rotation Processing Unit 120 Display Screen 121 Slot Layout Screen Display Area 122 DUT Pin Designation Area 123 List Display Area 124 Vertical Scroll Bar 125 Horizontal Scroll Bar 126 3D Instruction button 127, 128 Rotation instruction button

Claims (5)

In a semiconductor test apparatus having an operation display screen and configured to assign a predetermined pin of a DUT to each pin of a plurality of pin electronics cards housed in a test head according to a test item,
In the operation display screen,
A DUT pin designation area for inputting a pin number of the DUT to be searched;
A slot layout screen display area for displaying a slot layout screen indicating a slot layout relationship in a test head in which the plurality of pin electronics cards are stored;
A semiconductor test apparatus, comprising: a list display area for displaying a search result corresponding to the pin number of the DUT in a predetermined list display screen format.   2. The semiconductor test apparatus according to claim 1, wherein the slot layout screen display in the slot layout screen display area changes in conjunction with selection of an arbitrary pin on the list displayed in the list display area. .   3. The semiconductor test apparatus according to claim 1, wherein a 3D instruction button for instructing to display the slot layout screen in a three-dimensional (3D) manner is provided on the operation display screen.   4. The semiconductor test apparatus according to claim 3, wherein the operation display screen is provided with a rotation instruction button for arbitrarily changing and setting the display rotation angle of the three-dimensional display screen.   5. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is configured to simultaneously test a plurality of DUTs.