JP2011018845A - Semiconductor device equipped with diffusion layer resistance, and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a plurality of diffusion layer resistances each of which has a different resistance value, while reducing the manufacturing steps and manufacturing cost, and to provide a method for manufacturing the semiconductor device.SOLUTION: A protective film 41 is formed by oxidizing or nitriding the surface side of a semiconductor substrate, and a plurality of extended diffusion layer regions 21, 22 and 23, each of which contains conductive impurity are formed under the protective film. Then, a photoresist film is formed on at least one of the plurality of diffusion layer regions; and while a ground potential is supplied to the back side of the semiconductor substrate, plasma ashing processing is applied to the photoresist film so that the photoresist film can be removed. Finally, a wiring layer 60 electrically connected to each diffusion layer region is formed via an insulating layer 40 so that each diffusion layer region can be turned to be a diffusion layer resistor.

Description

  The present invention relates to a method of manufacturing a semiconductor device in which a P-type or N-type conductive diffusion layer is formed by implanting impurities into a predetermined region on a semiconductor substrate, and the diffusion layer is used as a diffusion layer resistance, and the semiconductor Relates to the device.

  Conventionally, in order to adjust an output voltage with respect to an input voltage in a circuit in a semiconductor device, the input voltage is divided using a plurality of diffusion layer resistors. In this case, in order to obtain a desired output voltage with respect to a predetermined input voltage, it is necessary to appropriately control each resistance value of the plurality of diffusion layer resistors in manufacturing the semiconductor device.

  Cited Document 1 discloses a semiconductor device in which impurities are implanted into a semiconductor substrate to form a diffusion layer for diffusion resistance, and an electrode is formed adjacent to the diffusion layer, and a method for manufacturing the same. With this configuration, the resistance value of the diffusion resistor can be controlled by controlling the voltage applied to the adjacent electrodes.

  However, depending on the conventional manufacturing method such as the cited document 1, a special electrode for controlling the resistance value is required, which complicates the manufacturing process and increases the manufacturing cost. In addition, the resistance value is used even in the use of the manufactured semiconductor device. Needed special voltage control for control and prevented easy use. In view of this, a method is conceivable in which a plurality of diffusion layers are provided and the resistance value of each diffusion layer resistance is controlled by changing the amount of impurities implanted into each diffusion layer.

  1A to 1E show a manufacturing method in which the resistance value of each diffusion layer resistance is controlled by changing the dose amount in impurity implantation. Here, each drawing shows a cross section of the semiconductor device in each step.

  FIG. 1A shows a first photolithography process and a first implant process. Here, a photoresist film 31 made of a photosensitive resin material is formed on the semiconductor substrate 11 made of a semiconductor material such as silicon using a photolithography technique as shown in the figure. The photoresist film 31 is formed so that a diffusion layer region for the N type diffusion layer resistors 21 and 22 is opened. Next, N-type diffusion layer resistors 21 and 22 are formed by ion implantation of N-type impurities such as phosphorus (P) at a predetermined implantation amount.

  FIG. 1B shows the first ashing step. Here, the ashing process is performed using a technique such as photoexcitation ashing or plasma ashing. Thus, the photoresist film 31 is ashed or peeled off and removed. For details of the technique of ashing the photoresist film, refer to, for example, cited documents 1 and 2.

  FIG. 1C shows a second photolithography process. Here, a photoresist film 32 made of a photosensitive resin material is formed on the semiconductor substrate 11 from which the photoresist film 31 has been removed, as shown in the drawing. In the photoresist film 32, a region for the N-type diffusion layer resistor 23 which requires a higher resistance than the N-type diffusion layer resistors 21 and 22 is opened.

  FIG. 1D shows a second implant process, in which N-type impurities are ion-implanted in the same manner as the first implant process. In this case, the resistance value of the formed N-type diffusion layer resistor 23 is set to a resistance different from that of the diffusion layer resistors 21 and 22 by setting the injection amount to an injection amount different from the predetermined injection amount in the first implant step. Adjust to the value.

  FIG. 1E shows a second ashing process. Here, the ashing process is performed using a technique such as photoexcitation ashing or plasma ashing. As a result, the photoresist film 32 is ashed or removed to be removed. Finally, a metal wiring layer electrically connected to each diffusion layer region of the N type diffusion layer resistors 21 to 23 is formed via an insulating layer (not shown).

JP-A-8-23075 JP-A-5-315280 Japanese Patent Laying-Open No. 2005-217061

  However, depending on the above-described conventional technology, it is necessary to form at least two diffusion layers having different resistance values. After performing ion implantation with one of the masks as shown in FIGS. 1A to 1E, However, it is necessary to perform the same process, which is disadvantageous in terms of the number of processes and cost.

  An object of the present invention is to provide a semiconductor device and a manufacturing method including a plurality of diffusion layer resistors each having a different resistance value while reducing the number of processes and the manufacturing cost.

  The manufacturing method according to claim 1 is a manufacturing method of a semiconductor device, wherein a protective film forming step of forming a protective film by oxidizing or nitriding the surface side of the semiconductor substrate, and the protection on the surface side of the semiconductor substrate A diffusion layer region forming step of forming a plurality of diffusion layer regions each extending under the film and containing impurities of any conductivity type; and a photo-resist on at least one diffusion layer region of the plurality of diffusion layer regions A photoresist film forming step for forming a resist film, and a photoresist film removal for removing the photoresist film by applying a plasma ashing process to the photoresist film while supplying a ground potential to the back surface side of the semiconductor substrate. And forming a wiring layer electrically connected to the diffusion layer region through an insulating layer, thereby making each diffusion layer region a diffusion layer resistor. A wiring layer forming step, characterized in that it comprises a.

  A semiconductor device according to claim 4 is a semiconductor device having a plurality of diffusion layer resistors, a semiconductor substrate, a protective film formed by oxidizing or nitriding the surface side of the semiconductor substrate, A plurality of diffusion layer regions extending under the protective film on the surface side and each containing impurities of any conductivity type, and formed on the semiconductor substrate via an insulating layer, electrically connected to the diffusion layer region A wiring layer having each of the diffusion layer regions as the diffusion layer resistance by being connected, and at least one diffusion layer resistance of the diffusion layer resistance is formed on the photoresist film A diffusion layer resistance whose resistance value is controlled by performing a plasma ashing process on the photoresist film and removing the photoresist film.

  The manufacturing method according to claim 5 includes a step of grounding the back surface of a semiconductor substrate having a front surface and a back surface, a step of forming first and second impurity regions on the front surface, and the first impurity region. Forming a first insulating film covering the first insulating film; forming a photosensitive photoresist film on the first insulating film formed on the first impurity region; and forming the photosensitive photoresist film on the photosensitive photoresist film. Plasma ashing is performed to remove the photosensitive resist and adjust the resistance value of the first impurity region, and the first insulating film on the first impurity region is formed into a second state. And a step of covering with an insulating film.

  According to the semiconductor device and the manufacturing method of the present invention, it is possible to obtain a semiconductor device and a manufacturing method provided with a plurality of diffusion layer resistors each having a different resistance value while reducing the number of steps and the manufacturing cost.

It is sectional drawing of the semiconductor device in a 1st photolithography process and a 1st implant process. It is sectional drawing of the semiconductor device in a 1st ashing process. It is sectional drawing of the semiconductor device in a 2nd photolithography process. It is sectional drawing of the semiconductor device in a 2nd implant process. It is sectional drawing of the semiconductor device in a 2nd ashing process. It is sectional drawing of the semiconductor device by this invention. It is a circuit diagram which shows the equivalent series resistance circuit of a semiconductor device provided with a diffused layer resistance. It is a figure which shows the change of the diffused layer resistance value obtained by resist ashing. It is sectional drawing of the semiconductor device in a protective film formation process. It is sectional drawing of the semiconductor device in a 1st photolithography process and a 1st implant process. It is sectional drawing of the semiconductor device in a 1st ashing process. It is sectional drawing of the semiconductor device in a 2nd photolithography process. It is sectional drawing of the semiconductor device in a 2nd ashing process. It is sectional drawing of the semiconductor device in an insulating layer and a wiring layer formation process. It is explanatory drawing explaining the principle of this invention.

  Embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 shows an embodiment of the present invention and shows a cross section of a semiconductor device according to the present invention. The semiconductor device 10 includes three diffusion layer resistors 21, 22 and 23 on the upper surface side of a semiconductor substrate 11 made of a material such as silicon. In this embodiment, the semiconductor device 10 is shown to include three diffusion layer resistors 21, 22 and 23. However, the present invention is not limited to this, and even if two diffusion layer resistors having different resistance values are formed. It may also include more than four diffusion layer resistors. The semiconductor device 10 may also be formed with other functional circuits including transistors or the like, and the functional circuit and the diffusion layer resistors 21, 22 and 23 may be electrically connected to each other.

  An insulating layer 40 is formed on the semiconductor substrate 11 including the diffusion layer resistors 21, 22 and 23. A plurality of conductor posts 51 to 56 made of a material such as copper are formed in the insulating layer 40. Each of the diffusion layer resistors 21, 22 and 23 is electrically connected to any one of the plurality of conductor posts 51 to 56. For example, two conductor posts 51 and 52 are connected to the diffusion layer resistor 21. The two conductor posts 51 and 52 are each formed at the end of the region of the diffusion layer resistor 21. For example, when a current flows from the conductor post 51 to the conductor post 52, the conductor posts 51 and 52 are connected to each other. It will have a resistance value in between. The positions of the conductor posts 51 and 52 may be at both ends of the diffusion layer resistor 21 in the direction perpendicular to the paper surface.

  Each of the conductor posts 51 to 56 is electrically connected according to an arbitrary circuit pattern by a metal wiring layer 60 made of a material such as copper or aluminum formed on the insulating layer 40. In the example of this figure, each of the diffusion layer resistors 21, 22, and 23 is connected in series via the metal wiring layer 60. For example, when a voltage V1 is applied to both ends of a series of diffusion layer resistors 21, 22 and 23 connected in series, a voltage V2 is obtained between the diffusion layer resistor 21 and the diffusion layer resistor 22, and the diffusion layer resistor 22 and the diffusion layer Each of the divided voltages is obtained in such a manner that the voltage V3 is obtained between the resistor 23 and the resistor 23. In order to obtain an arbitrary divided voltage, it is necessary to appropriately control the resistance values actually realized in each of the diffusion layer resistors 21, 22, and 23.

  FIG. 3 shows an equivalent series resistance circuit of a semiconductor device having a diffusion layer resistance. As a premise, the power supply voltage is V4, the power supply side voltage of the first diffusion layer resistor 21 is V1, the voltage between the first diffusion layer resistor 21 and the second diffusion layer resistor 22 is V2, and the second diffusion layer resistor The voltage between 22 and the third diffusion layer resistor 23 is V3. The power supply voltage V4 is 3V, for example.

  As shown in FIG. 3A, when there is no resistance value control, the resistances of the diffusion layer resistors 21, 22 and 23 are all 100Ω, for example. As a result, the output voltages are V1 = 3V, V2 = 2V, and V3 = 1V. On the other hand, when the resistance value is controlled as shown in FIG. 3B, the resistance of the diffusion layer resistor 23 is approximately 1.5 times, for example, 150Ω. As a result, the output voltages are V1 = 3V, V2 = 2.1V, and V3 = 1.2V. By controlling the resistance value in this way, each resistance value of the diffusion layer resistance can be changed, and an arbitrary voltage can be obtained on the metal wiring.

  In this embodiment, the resistance value is controlled by appropriately controlling the ashing of the photoresist film formed on the specific diffusion layer resistance region.

Here, the plasma ashing apparatus will be described again. The plasma ashing apparatus mainly generates a reactive gas plasma such as oxygen plasma in order to remove the photoresist remaining on the substrate after dry etching, and the organic ash in the gas phase. This is an apparatus for decomposing and removing the photoresist into CO _x , H ₂ O and the like. As a plasma ashing apparatus, a barrel type or parallel plate type plasma ashing apparatus was used at first.

  In the use of a barrel type or parallel plate type plasma ashing apparatus, there has been a problem that charged particles such as ions generated by plasma cause damage such as sputtering treatment by ion bombardment and charge up by charged particles. Therefore, in order to solve such a problem, a downflow type plasma ashing apparatus is often used at present.

  In the downflow ashing device, the plasma discharge chamber for generating plasma and the ashing chamber are provided separately, and charged particles that are generated by the plasma energy and may damage the substrate are confined in the discharge chamber. Only the reaction gas of particles is sent to a processing chamber located downstream to remove the resist. As a result, an ashing process with little damage to the substrate is realized.

  The operating conditions of the ashing plasma apparatus are represented by the operating temperature (unit: ° C.), the power of the microwave oscillator (unit: W) for exciting the reactive gas into the plasma, and the flow rate (unit: sccm) of the reactive gas. Here, the unit sccm (standard cc / min) of the flow rate means a flow rate (cc / min) per unit time at a standard temperature such as 1 atm (atmospheric pressure 1,013 hPa), 0 ° C. or 25 ° C.

  FIG. 4 shows changes in the diffusion layer resistance value obtained by resist ashing. In the graph of this figure, the vertical axis represents the resistance value per unit area (Ω / sq), and the horizontal axis represents the wafer number (WNO). The resistance value (Ω / sq) is a sheet resistance value, and indicates a resistance value per sheet resistance area (width × length) with a constant sheet resistance thickness.

  Here, when a normal plasma ashing device such as a barrel type or a parallel plate type is used (WNO = 7), a resistance value of about 4000 Ω / sq is realized. On the other hand, when a downflow type plasma ashing apparatus is used (WNO = 1), a resistance value of approximately 7000 Ω / sq is realized. That is, it has been demonstrated that the resistance value becomes higher only when the downflow type plasma ashing apparatus is used.

  5A to 5F show a method of manufacturing a semiconductor device having a diffusion layer resistance according to the present invention, and each drawing shows a cross-sectional view in each step.

  FIG. 5A shows a protective film forming step. First, a semiconductor substrate 11 made of a material such as silicon is prepared. Next, a mask oxide film 41 such as a silicon oxide film is formed as a protective film by oxidizing the surface side of the semiconductor substrate 11. Instead of the mask oxide film 41, a nitride film made of a silicon nitride film or the like may be formed.

  FIG. 5B shows a first photolithography process and a first implant process. Here, a photoresist film 31 is formed on the mask oxide film 41 using a photolithography technique as illustrated. In the photoresist film 31, each diffusion layer region for the N type diffusion layer resistors 21 to 23 is opened. Next, N-type impurities such as P (phosphorus) are ion-implanted, for example, at an acceleration voltage of about 80 keV to form low-concentration N-type diffusion layer resistors 21, 22 and 23. Each of the N type diffusion layer resistors 21, 22, and 23 is formed to extend under the mask oxide film 41 on the surface side of the semiconductor substrate 11 as shown in the figure.

  FIG. 5C shows the first ashing step. Here, ashing is performed using a downflow plasma ashing apparatus or a normal ashing apparatus. Thus, the photoresist film 31 is ashed or peeled off and removed.

  FIG. 5D shows a second photolithography process. Here, as shown in the drawing, a photoresist film 32 made of a photosensitive material is formed on the semiconductor substrate 11 from which the photoresist film 31 has been removed. The photoresist film 32 covers a region for the N type diffusion layer resistor 23 that requires a higher resistance than the N type diffusion layer resistors 21 and 22. Here, in the present embodiment, the normal second implant process as shown in FIG. 1D in the conventional process is unnecessary.

FIG. 5E shows the second ashing step. Here, an ashing process is performed using a downflow type ashing plasma apparatus under operating conditions of, for example, a temperature of 80 ° C., a microwave oscillator power of 1200 W, and an oxygen (O ₂ ) gas flow rate of about 700 sccm. As shown in the figure, the semiconductor substrate 11 is placed on the ground pedestal 30 and a ground potential is supplied to the back surface of the semiconductor substrate 11, that is, the back surface side facing the front surface side where the diffusion layer resistors 21 to 23 are formed. On the other hand, plasma containing active oxygen is generated using an excitation potential relative to the ground potential. The reactive gas of active oxygen is supplied onto the surface of the semiconductor substrate 11 from above the semiconductor substrate 11 by a downflow method. By this ashing process, the photoresist film 32 is ashed or removed to be removed, and only the resistance of the N-type diffusion layer resistor 23 covered with the photoresist film 32 is controlled to a high resistance.

  FIG. 5F shows an insulating layer and wiring layer forming step. Here, the insulating layer 40 is formed on the front surface side of the semiconductor substrate 11 while maintaining the ground potential on the back surface side of the semiconductor substrate 11. Next, a conductor post 50 that penetrates the insulating layer 40 and the mask oxide film 41 is formed, and a metal wiring layer 60 that is electrically connected to each of the N type diffusion layer resistors 21 to 23 through the conductor post 50 is formed. To do.

  FIG. 6 illustrates the principle of the present invention. As shown in FIG. 6A, by using the downflow type plasma ashing apparatus, the semiconductor substrate 11 to be ashed is placed on the ground pedestal 70 connected to the ground potential, and the downflow of the active particles starts from above. It is applied on the semiconductor substrate. At this time, a positive charge is charged only in the portion of the mask oxide film 41 where the photoresist film 32 disappeared due to ashing and becomes a positive potential. As a result, a reverse bias is applied from the front surface of the semiconductor substrate 11 to the back surface of the semiconductor substrate 11 by the positive potential, the depletion layer inside the N-type diffusion layer resistor 23 expands, and the resistance value increases. .

  Further, as shown in FIG. 6 (b), since the insulating layer 40 is formed on the mask oxide film 41, the charges charged on the mask oxide film 41 are trapped, and this state is maintained even after the wafer is completed. Thus, the resistance value of the N type diffusion layer resistor 23 is maintained.

  The above principle is the same for the P-type diffusion layer resistance. In other words, the N type diffusion layer resistor 23 is referred to as the P type diffusion layer resistor 23. In this state, a forward bias is applied from the surface of the semiconductor substrate 11 toward the back surface of the semiconductor substrate 11 by the positive potential of the mask oxide film 41. Thus, the depletion layer inside the P-type diffusion layer resistor 23 is narrowed, and the resistance value is reduced. Further, since the insulating layer 40 is formed on the mask oxide film 41, the charges charged on the mask oxide film 41 are trapped, and this state is maintained even after the wafer is completed, and the P-type diffusion layer resistor 23 The resistance value is maintained.

  As is clear from the above embodiments, in the present invention, after the semiconductor substrate is grounded, a photoresist film is formed again on the impurity diffusion layer whose resistance value is desired to be controlled, and then this photoresist film is removed. Then, down flow type plasma ashing is performed on the photoresist film. Thereby, the resistance value of the specific diffusion layer resistance can be controlled, and for example, the wiring resistance of the series resistance circuit can be intentionally changed to adjust the output voltage of the wiring.

  Furthermore, the present invention can reduce the number of processes and cost. As compared with the conventional case where the diffusion layer resistance region having a different resistance value is formed by a process consisting of “mask → ion implantation → resist removal → mask → ion implantation → resist removal” as in the conventional case, “mask → ion implantation → Two or more diffusion layer resistance regions having different resistance values are formed by a process consisting of “resist removal → mask → resist removal”. That is, according to the present invention, it is not necessary to perform the implant process twice or more, so that the manufacturing process can be reduced correspondingly, and the cost can be reduced.

  In the above embodiment, the N type diffusion layer resistance is described as the conductivity type. However, the present invention is not limited, and the diffusion element resistance according to the present invention may have a P type conductivity type.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor substrate 21-23 Diffusion layer resistance 31, 32 Photoresist film 40 Insulating layer 41 Mask oxide film 51, 52, 56 Conductor post 60 Metal wiring layer 70 Grounding base

Claims (7)

A method for manufacturing a semiconductor device, comprising:
A protective film forming step of forming a protective film by oxidizing or nitriding the surface side of the semiconductor substrate;
A diffusion layer region forming step of forming a plurality of diffusion layer regions extending under the protective film on the surface side of the semiconductor substrate and each containing impurities of any conductivity type;
A photoresist film forming step of forming a photoresist film on at least one diffusion layer region of the plurality of diffusion layer regions;
A photoresist film removing step of removing the photoresist film by applying a plasma ashing process to the photoresist film while supplying a ground potential to the back side of the semiconductor substrate;
Forming a wiring layer electrically connected to the diffusion layer region via an insulating layer, thereby forming each of the diffusion layer regions as a diffusion layer resistance; and
The manufacturing method characterized by including.   2. The photoresist film forming step according to claim 1, wherein a photoresist film is formed on at least one of the plurality of diffusion layer regions where higher resistance is desired compared to the other. Production method.   3. The manufacturing method according to claim 1, wherein in the photoresist film removing step, the plasma ashing process is performed using a down flow type plasma ashing apparatus. A semiconductor device comprising a plurality of diffusion layer resistors,
A semiconductor substrate;
A protective film formed by oxidizing or nitriding the surface side of the semiconductor substrate;
A plurality of diffusion layer regions each extending under the protective film on the surface side of the semiconductor substrate and each containing impurities of any conductivity type;
A wiring layer formed on the semiconductor substrate via an insulating layer, and electrically connected to the diffusion layer region to make each of the diffusion layer regions the resistance of the diffusion layer;
And at least one of the diffusion layer resistors has a resistance value obtained by performing a plasma ashing process on the photoresist film formed thereon and removing the photoresist film. A semiconductor device having a controlled diffusion layer resistance. Grounding the back surface of the semiconductor substrate having a front surface and a back surface;
Forming first and second impurity regions on the surface;
Forming a first insulating film covering the first impurity region;
Forming a photosensitive photoresist film on the first insulating film formed on the first impurity region;
Performing plasma ashing on the photosensitive photoresist film to remove the photosensitive resist and adjusting a resistance value of the first impurity region;
Covering the first insulating film on the first impurity region with a second insulating film;
A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 5, wherein the plasma ashing is performed using a downflow type plasma ashing apparatus. After the step of adjusting the resistance value of the first impurity region, forming an insulating layer covering the first and second impurity regions on the surface of the semiconductor substrate;
Forming a wiring layer electrically connected to each of the first and second impurity regions on the insulating layer;
The method of manufacturing a semiconductor device according to claim 5, wherein:

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