JP2011018737A - Semiconductor manufacturing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing system capable of operating a semiconductor manufacturing apparatus in efficient operation in an automated semiconductor production line.SOLUTION: A prediction unit 461 calculates a predicted processing time of processing on each of wafers stored in a plurality of carriers by one semiconductor manufacturing apparatus belonging to the semiconductor production line including a time needed for arrangement processing when the plurality of carriers reach the semiconductor manufacturing apparatus 5. A processing order change control unit 46 determines processing order of the plurality of carriers based upon the calculated predicted processing time so that the processing on the wafers stored in the plurality of carriers by the semiconductor manufacturing apparatus 5 is completed in a shortest time. A load port control unit 41, a handler control unit 42 and a process control unit 43 allow the semiconductor manufacturing apparatus 5 to perform the processing on the wafers stored in the plurality of carriers according to the determined processing order.

Description

  The present invention relates to a semiconductor manufacturing system, and more particularly to a technique for improving the efficiency of an automated semiconductor production line.

  As a technique for improving the efficiency of a conventional semiconductor production line, for example, there is a method for controlling a semiconductor manufacturing apparatus disclosed in Patent Document 1. In this method, when the wafer processing time, product processing time, and setup time are obtained quantitatively from past production results and the semiconductor wafer processing is started with a request from the subsequent process as a trigger, Completion time is automatically predicted by the computer. Also, for the semiconductor wafer to be processed next in the manufacturing apparatus, the total time of the transport time to the manufacturing apparatus, the previous (outside) setup time and the time required for the preprocessing is calculated, and the predicted semiconductor wafer processing end time The transport start time is calculated by subtracting the total time from. By starting the transfer of the next processing wafer at this transfer start time, during the semiconductor wafer processing in the manufacturing apparatus, the transfer and setup of the next semiconductor wafer to be processed are completed. Processing can be started.

JP-A-6-291006

  In order to efficiently operate a semiconductor manufacturing apparatus (hereinafter also simply referred to as an apparatus) and reduce its operating cost, it is necessary to minimize the occurrence of setup processing. Therefore, in the apparatus, it is preferable to process wafers under the same processing conditions as continuously as possible.

  A general manufacturing execution system (MES) or dispatcher takes into account the lot delivery date and processing priority, as well as the lots to be installed on the equipment from the stock lots for each equipment, taking into account the continuity of the above processing conditions. Is selected and processing reservation of the selected lot is made to the apparatus. However, in particular, in semiconductor production lines in which wafer containers (hereinafter also referred to as carriers) are automatically transported, the time required for the lot to be received after the transport carriage receives the transport instruction, The time required for conveyance depends not only on the positional relationship between the conveyance carriage and the apparatus but also on the traffic congestion on the way. That is, it is not always possible to control the arrival of carriers at the device in the order of selection.

  Also, depending on the manufacturing execution system or dispatcher, the next processing lot is selected with the occurrence of a stock lot for the device or the occurrence of a vacancy at the carry-in port of the device as a trigger. With such a configuration, there has been a problem that the carrier loading order into the apparatus is not always an efficient order for the apparatus.

  The present invention has been proposed in view of the circumstances of the prior art, and in an automated semiconductor production line, the processing of stock lots can be completed earlier and the semiconductor manufacturing apparatus can be operated efficiently. An object of the present invention is to provide a semiconductor manufacturing system that can perform the above-described process.

  In order to achieve the above object, a semiconductor manufacturing system according to the present invention includes a control computer, a semiconductor production line, a prediction unit, a processing order change control unit, and an execution unit. The semiconductor production line processes wafers accommodated in a plurality of wafer containers in accordance with instructions from a control computer. When a plurality of wafer containers arrive at one semiconductor manufacturing apparatus belonging to the semiconductor production line, the prediction unit requires an estimated processing time for processing in the semiconductor manufacturing apparatus for the wafers accommodated in each wafer container for the setup process. Calculate including time. The processing order switching control unit determines the processing order of the plurality of wafer containers so that the processing in the semiconductor manufacturing apparatus of the wafers accommodated in the plurality of wafer containers is completed in the shortest time based on the calculated expected processing time. . The execution unit causes the semiconductor manufacturing apparatus to execute processing of the wafers accommodated in the plurality of wafer containers according to the determined processing order.

  With this configuration, it is possible to shorten the total processing time for processing the wafers accommodated in the plurality of wafer containers.

  According to the present invention, efficient operation of a semiconductor manufacturing apparatus can be realized by suppressing the occurrence of setup processing and shortening the setup processing time. In particular, a high effect can be achieved in a semiconductor manufacturing apparatus that requires setup processing every time the recipe is switched or a high-throughput semiconductor manufacturing apparatus.

1 is a schematic configuration diagram of a semiconductor manufacturing system according to an embodiment of the present invention. The flowchart which shows the processing sequence change process in one semiconductor manufacturing apparatus which belongs to the semiconductor manufacturing system in one Embodiment of this invention. The flowchart which shows the transfer possibility determination process in the one semiconductor manufacturing apparatus which belongs to the semiconductor manufacturing system in one Embodiment of this invention. The flowchart which shows the required time calculation process in the other semiconductor manufacturing apparatus which belongs to the semiconductor manufacturing system in one Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  A schematic diagram of a semiconductor manufacturing system in an embodiment of the present invention is shown in FIG. This semiconductor manufacturing system includes a control computer 1 that is a MES or a host computer, a plurality of transport carts 2 that transport wafers (carriers) to be processed in a semiconductor production line, a transport controller 3 that drives the transport cart 2, a transport cart 2, A semiconductor manufacturing apparatus 5 that exchanges wafers (carriers) between them and performs wafer processing, and a control unit 4 that controls processing in the semiconductor manufacturing apparatus 5 and the like. In general, a semiconductor production line includes a plurality of semiconductor manufacturing apparatuses 5, but only the semiconductor manufacturing apparatus 5a and the semiconductor manufacturing apparatus 5b are shown here. The semiconductor manufacturing apparatus 5a and the semiconductor manufacturing apparatus 5b are apparatuses that can execute the same processing on a wafer. That is, when performing the process, the process is performed in any one of the devices selected from the semiconductor manufacturing apparatus 5a and the semiconductor manufacturing apparatus 5b. Moreover, in FIG. 1, only one conveyance cart 2 is illustrated.

  The control unit 4 is stored in, for example, a dedicated arithmetic circuit, hardware including a processor and a memory such as a RAM (Random Access Memory) or a ROM (Read Only Memory), and the memory, and operates on the processor. It can be realized as software. In the present embodiment, the control unit 4 is provided for each semiconductor manufacturing apparatus 5. That is, a control unit 4a is provided corresponding to the semiconductor manufacturing apparatus 5a, and a control unit 4b is provided corresponding to the semiconductor manufacturing apparatus 5b. The control unit 4 (4a, 4b) controls wafer transfer, wafer transfer, wafer processing, and the like with the transfer carriage 2 in the semiconductor manufacturing apparatus 5, and the later-described processing plan for the control computer 1. Request (instruction) to change

  Although not particularly limited, in the present embodiment, as shown in FIG. 1, the device unit 4 (4a, 4b) includes a load port control unit 41 (41a, 41b), a handler control unit 42 (42a, 42b), and process control. Unit 43 (43a, 43b), SECS (SEMI [Semiconductor Equipment and Materials International] Equipment Communications Standard) communication control unit 44 (44a, 44b), anti-transport device communication control unit 45 (45a, 45b), processing order change control unit 46 (46a, 46b), anti-conveyance controller communication I / F 47 (47a, 47b), anti-other machine communication I / F 48 (48a, 48b), and storage unit 49 (49a, 49b). The load port control unit 41, the handler control unit 42, and the process control unit 43 control the execution of wafer processing by the semiconductor manufacturing apparatus 5. That is, the load port control unit 41 controls the carry-in / out of the carrier to / from the load port provided in the semiconductor manufacturing apparatus 5. The handler control unit 42 controls the loading / unloading of the wafer in the carrier into the processing unit (processing chamber) of the semiconductor manufacturing apparatus 5. The process control unit 43 controls processing on the wafer in the processing unit. The SECS communication control unit 44 exchanges information with the control computer 1. The anti-conveyance device communication control unit 45 detects the approach of the transport carriage 2 and controls transfer of carriers between the transport carriage 2 and the load port together with the load port control unit 41. The processing order switching control unit 46 includes a prediction unit 461 (461a, 461b), and executes processing order switching described later based on the predicted processing time (processing end time) of each carrier calculated by the prediction unit 461. The transport controller communication I / F 47 is a communication interface for the transport controller 3, and the other machine communication I / F 48 is a communication interface for the control unit 4 of another semiconductor manufacturing apparatus 5. The control unit 4 (4a, 4b) may be provided in the semiconductor production line as a separate device from the semiconductor manufacturing apparatus 5 (5a, 5b), but in the present embodiment, the corresponding semiconductor manufacturing apparatus 5a. 5b, respectively.

  2, 3, and 4 are flowcharts showing processing performed by the semiconductor manufacturing system in the present embodiment. 2 and 3 are flowcharts showing a processing order change process and a transfer possibility determination process executed in one semiconductor manufacturing apparatus 5 (for example, the semiconductor manufacturing apparatus 5a), and FIG. 4 executes the same process. It is a flowchart which shows the process performed in the other possible semiconductor manufacturing apparatus 5 (for example, semiconductor manufacturing apparatus 5b). In the present embodiment, these processes are executed by the control units 4a and 4b provided in the respective semiconductor manufacturing apparatuses 5a and 5b. In the following, a case where the process shown in FIGS. 2 and 3 is executed in the semiconductor manufacturing apparatus 5a and the process shown in FIG. 4 is executed in the semiconductor manufacturing apparatus 5b will be described.

  The processing order changing process is premised on the occurrence of at least three wafer processes in one semiconductor manufacturing apparatus 5a. Here, the wafer processing is a control job, tracking, or the like, and means a series of processes that are executed separately from other processing in the semiconductor manufacturing apparatus 5a. Hereinafter, three wafer processes a1, wafer process a2, and wafer process a3 are generated in the order of a1, a2, and a3 in accordance with an instruction from the control computer 1 (MES), and each wafer process a1 to a3 corresponds to each wafer process a1 to a3. Each wafer process a1 to a3 is triggered by the target carrier being installed in a load port (or a carrier storage shelf for storing a process waiting carrier) of the semiconductor manufacturing apparatus 5a (hereinafter referred to as apparatus 5a). Explain the case. In the apparatus 5a, pre-setup processes b1, b2, and b3 respectively determined corresponding to the wafer processing types occur before the execution of the wafer processes a1 to a3. Here, it is assumed that the processing condition for wafer processing a1 is recipe R1, the processing condition for wafer processing a2 is recipe R2, and the processing condition for wafer processing a3 is recipe R3. In this case, the pre-setup processes b1, b2, and b3 are processes corresponding to the recipes R1, R2, and R3, respectively. These pre-setup processes are setup processes that occupy a semiconductor manufacturing apparatus such as a process chamber setup, and indicate processes that cannot be performed simultaneously with the wafer processes a1, a2, and a3. However, the pre-setup processes b1, b2, and b3 occur only as settings, and there are cases where no processing is actually performed in the apparatus 5a. For example, in the case where the wafer processing is continuously performed with the same recipe, in the apparatus 5 that does not require the setup of the processing chamber, the pre-setup process may be unnecessary.

  Further, the storage unit 49a of the control unit 4a provided in the apparatus 5a holds a history of wafer processing and pre-setup processing executed in the past. For example, with respect to wafer processing, as processing history, the required processing time is held for each recipe type and for each number of wafers in one tracking. In addition to these wafer processing histories, the standard time when using each recipe is stored as a setting. The standard time is used in place of the wafer processing history information when the wafer processing history for the recipe to be used is very small (for example, 10 processing or less). Similarly, with respect to the previous setup process, the time required for the process is held as a history for each content of the previous setup and for each recipe type executed immediately before. In addition, the storage unit 49a holds, as a setting, a standard time when each of the previous setup processes is used together with the previous setup process history. The standard time is used in place of the history information of the previous setup process when the previous setup process history for the recipe to be used is very small (for example, 10 processes or less). In addition, the time required for the pre-setup process when maintenance or the like was performed immediately before the pre-setup process and the specific wafer process was not executed is also classified into one category of recipe type in which there is no wafer process executed immediately before. And is held.

  Here, description will be made assuming that the device 5a is in a state where there is no carrier that is executing processing and carrier that is waiting for processing.

  As shown in FIG. 2, first, when the target carrier of the wafer processing a1 transferred by the transfer carriage 2 is installed in the load port of the apparatus 5a, the wafer processing is performed in the apparatus 5a according to an instruction from the control computer 1 accordingly. a1 occurs (step S201). When the wafer processing a1 occurs, the control computer 1 gives information necessary for execution of the wafer processing such as the recipe R1 for performing the wafer processing a1, the number of wafers to be processed N1, and the processing priority P1 based on the delivery date. ing.

  Subsequently, similarly, when the target carrier for the wafer processing a2 is installed in the load port of the apparatus 5a, the wafer processing a2 is generated in the apparatus 5a according to the instruction from the control computer 1 (step S202). When the wafer processing a2 occurs, the control computer 1 gives information necessary for executing the wafer processing such as the recipe R2 for performing the wafer processing a2, the number of wafers to be processed N2, and the processing priority P2 based on the delivery date. ing.

  Further, when the target carrier for the wafer processing a3 is installed in the load port of the apparatus 5a, the wafer processing a3 is generated in the apparatus 5a according to an instruction from the control computer 1 (step S204). Similarly to the above-described wafer processing a1 and a2, when the wafer processing a3 occurs, the apparatus 5a performs the wafer processing such as the recipe R3 for performing the wafer processing a3, the number of wafers to be processed N3, and the processing priority P3 based on the delivery date. Information required for execution is given from the control computer 1.

  The information given from the control computer 1 is stored in the storage unit 49a of the control unit 4a. FIG. 2 shows a state in which the actual processing of the wafer processing a1 starts after the wafer processing a2 occurs (step S203). This is because the generation interval of the wafer processing a2 from the generation of the wafer processing a1 is extremely large. This is because it is assumed that the time is short, and is not limited to the state. That is, it is only necessary that the processing of the wafer processing a1 (including the pre-setup processing b1) is started before the generation of the wafer processing a3, and the processing processing of the wafer processing a1 starts before the generation of the wafer processing a2. Good. The process control unit 43a of the control unit 4a starts measuring the elapsed time TL1 from when the processing of the wafer process a1 is started, that is, the elapsed time TL1 from the start of the pre-setup process b1 (step S1). S203).

  Next, in the above situation, the prediction unit 461a of the processing order switching control unit 46a calculates the required time T1 when the generated wafer processings a1, a2, and a3 are executed in the order of generation by the following method (step) S205, 206).

First, the prediction unit 461a calculates an expected processing time PT1a based on the actual value of the wafer processing time from the above-described wafer processing history held by the storage unit 49a for the wafer processing a1 (step S205). Although not particularly limited, here, the history information of the same number as the number of wafers to be processed N1 processed by the recipe R1 is extracted from the storage unit 49a, and the upper 10% (long time side) of the extracted processing time data and The median value of the correction processing time data excluding the low-order (short-time side) 10% data is calculated as the expected processing time PT1a of the wafer processing a1. At the same time, the prediction unit 461a calculates the standard deviation of the correction processing time data as the standard deviation s _PT1a for the predicted processing time PT1a.

Also, the prediction unit 461a calculates the predicted processing time PT1b based on the actual value of the previous setup processing time from the above-mentioned previous setup processing history held by the storage unit 49a for the previous setup processing b1 (step S205). Although not particularly limited, here, the history information of the pre-setup process b1 when the wafer process was not performed immediately before the pre-setup process is extracted from the storage unit 49a, and the upper (long time) of the extracted process time data is extracted. The median value of the correction processing time data excluding the 10% data on the side) and the 10% data on the lower side (short time side) is calculated as the expected processing time PT1b of the pre-setup process b1. At the same time, the prediction unit 461a calculates the standard deviation of the correction processing time data as the standard deviation s _PT1b for the predicted processing time PT1b. If the pre-setup process b1 is completed before the wafer process a3 occurs, the actual value becomes the expected process time PT1b, and the standard deviation s _PT1b = 0.

Similarly, the prediction unit 461a determines the expected processing time PT2a of the wafer processing a2 and the previous setup processing b2 based on the actual values of each processing time based on the wafer processing history and the previous setup processing history stored in the storage unit 49a. Estimated processing time PT2b is calculated (step S205). Here, the expected processing times PT2a and PT2b are calculated by a method similar to that for the wafer processing a1 and the pre-setup processing b1. That is, the prediction unit 461a extracts history information of the same number as the number of wafers to be processed N2 processed by the recipe R2 from the storage unit 49a, and the upper (long-term side) 10% of the extracted processing time data and The median value of the correction processing time data excluding lower 10% (short-time side) data is calculated as the expected processing time PT2a of the wafer processing a2. At the same time, the standard deviation of the correction processing time data is calculated as the standard deviation s _PT2a for the expected processing time PT2a. Further, the prediction unit 46a extracts the history information of the previous setup process b2 when the recipe R1 is performed immediately before the previous setup process from the storage unit 49a, and is higher in the extracted processing time data (longer time side). The median value of the correction processing time data excluding the 10% data and the low-order (short-time side) 10% data is calculated as the expected processing time PT2b of the previous setup process b2. At the same time, the standard deviation of the correction processing time data is calculated as the standard deviation s _PT2b for the expected processing time PT2b.

Similarly, the prediction unit 461a determines the expected processing time PT3a and the previous setup processing b3 of the wafer processing a3 based on the actual values of each processing time based on the wafer processing history and the previous setup processing history stored in the storage unit 49a. Estimated processing time PT3b is calculated (step S205). Here, the prediction unit 461a extracts history information of the same number as the number of wafers to be processed N3 processed by the recipe R3 from the storage unit 49a, and 10% of the extracted processing time data (long-term side) and 10% The median value of the correction processing time data, excluding the low-order (short-time side) 10% data, is calculated as the expected processing time PT3a of the wafer processing a3. At the same time, the standard deviation of the correction processing time data is calculated as the standard deviation s _PT3a for the expected processing time PT3a. In addition, the prediction unit 461a extracts the history information of the previous setup process b3 when the recipe R2 is performed immediately before the previous setup process from the storage unit 49a, and the higher order (longer time side) of the extracted process time data. The median value of the correction processing time data excluding the 10% data and the low-order (short-time side) 10% data is calculated as the expected processing time PT3b of the previous setup process b3. At the same time, the standard deviation of the correction processing time data is calculated as the standard deviation s _PT3b for the expected processing time PT3b.

The processing order change control unit 46a calculates the sum S1 of the predicted processing times PT1b, PT1a, PT2b, PT2a, PT3b, and PT3a calculated by the prediction unit 461a as described above. Then, by subtracting the elapsed time TL1 from the start of the wafer processing a1 processing from the total S1, the required time T1 that is the processing end timing when processing in the order of the wafer processing a1, a2, and a3 is calculated (step) S206). The required time T1 indicates the time required from the time when the required time T1 is calculated until the wafer processing a3 is completed (total time required for wafer processing). Further, the processing order changing control unit 46a calculates the sum s _S1 of the standard deviations s _PT1b , s _PT1a , s _PT2b , s _PT2a , s _PT3b , and s _PT3a calculated as described above.

  Next, the processing order change control unit 46a calculates a required time T2 when the wafer processing order is changed (step S207). In this example, since the wafer process a1 has already been started, it is left as the head without changing the process order. Therefore, the processing order of the wafer processing a2 scheduled for the second processing and the wafer processing a3 scheduled for the third processing are switched. Note that, as described above, the reason for the processing sequence change process is that at least three wafer processes are generated for this reason.

In the present embodiment, the processing order change control unit 46a calculates the required time T2 after changing the processing order by the same calculation method as the required time T1. As described above, in the configuration in which the pre-setup processing time is calculated separately from the wafer processing time, the expected processing time PT2a of the wafer processing a2, the standard deviation _sPT2a , and the expected processing time of the wafer processing a3 even when the processing order is changed. PT3a and standard deviation _sPT3a are the same. Moreover, since there is no change in the processing order of the wafer processing a1, the expected processing time PT1a wafer processing a1, the standard deviation s _PT1a, pre setup process expected processing time of b1 PT1b, also the standard deviation s _PT1b, of course identical. For this reason, in the present embodiment, the prediction unit 461a sets the estimated processing time only for the pre-setup process b3 of the wafer process a3 having the second process order and the pre-setup process b2 of the wafer process a2 having the third process order. Recalculate.

The prediction unit 461a calculates the predicted processing time PT4b based on the actual value of the processing time from the above-mentioned previous setup processing history held by the storage unit 49a for the previous setup processing b3 having the second processing order. Here, the history information of the previous setup process b3 when the recipe R1 is executed immediately before the previous setup process is extracted from the storage unit 49a, and the upper (long-term side) 10% and the lower order of the extracted processing time data (Short-time side) The median value of the correction processing time data excluding 10% data is calculated as the expected processing time PT4b of the pre-setup process b3. At the same time, the standard deviation of the correction processing time data is calculated as the standard deviation s _PT4b for the expected processing time PT4b.

Similarly, the prediction unit 461a calculates the predicted processing time PT5b based on the actual value of the processing time from the above-described previous setup processing history held by the storage unit 49a for the previous setup processing b2 having the third processing order. . Here, the history information of the previous setup process b2 when the recipe R3 is executed immediately before the previous setup process is extracted from the storage unit 49a, and the upper (long-term side) 10% and the lower order of the extracted processing time data (Short-time side) The median value of the correction processing time data excluding 10% of data is calculated as the expected processing time PT5b of the previous setup process b2. At the same time, the standard deviation of the correction processing time data is calculated as the standard deviation s _PT5b for the expected processing time PT5b.

The processing order change control unit 46a calculates the total sum S2 of the predicted processing times PT4b and PT5b calculated by the prediction unit 461a as described above and the predicted processing times PT1b, PT1a, PT2a and PT3a previously calculated. Then, the required time T2 is calculated by subtracting the elapsed time TL1 from the total sum S2. In this case, the required time T2 indicates the time required to complete the wafer processing a2 when the processing is performed in the order of the wafer processing a1, a3, and a2. The processing reordering control unit 46a performs the above in the calculated standard deviation s _PT4b, s _PT5b and standard deviation s _PT1b previously calculated, s _PT1a, s _PT2a, it calculates a total sum s _S2 of s _PT3a.

  The processing order switching control unit 46a that calculates the required times T1 and T2 as described above compares the magnitude relation between the required times T1 and T2 (step S208). When the required time T1 is equal to or shorter than the required time T2 of the other processing order (the required time T1 is the minimum), the processing order as instructed from the control computer 1 is maintained (Yes in Steps S208 and S209). If the other required time T2 is smaller, the device 5a does not follow the instruction from the control computer 1 and continues the processing in the processing order that results in the minimum required time T2 (No in steps S208 and S213). That is, in this example, the wafer processing is continued in the order in which the wafer processing a2 and the wafer processing a3 are interchanged. Thus, the processing order that minimizes the total processing time is selected. Here, the required time T1 obtained by subtracting the elapsed time TL1 from the total processing time S1 and the total processing time S2 is compared with the required time T2 in relation to the transfer possibility determination process described later. Since the order of the wafer processing a1 is not changed, the same result can be obtained even if the total processing time S1 is compared with the total processing time S2.

  Now, in the present embodiment, after the processing order switching control unit 46a determines the processing order as described above, another device that can perform wafer processing equivalent to the device 5a for the last wafer processing. The suitability of the transfer to 5b is examined by the following method (step S210). In the case described above, the last wafer process is the wafer process a3 when the process order is maintained (step S209), and the last wafer process is the wafer process a2 when the process order is changed (step S213). It is.

  FIG. 3 is a flowchart showing a transfer possibility determination process performed by the process order change control unit 46a. First, the case where the processing order is maintained (step S209) will be described.

The processing order switching control unit 46a sends the required time Tb and the standard deviation sum sb when the last wafer processing is executed in the apparatus 5b to the processing order switching control unit 46b of the control unit 4b provided in the apparatus 5b. An inquiry is made (step S301). In this case, the last wafer processing is wafer processing a3. In addition, the required time Tb and the standard deviation sum sb in this case are hereinafter referred to as the required time T3 and the standard deviation sum s _S3 .

  At this time, the processing order change control unit 46a reads information (recipe R3, number of wafers to be processed N3, processing priority P3 based on delivery date, etc.) stored in the storage unit 49a and required for executing the wafer processing a3, The information is transmitted to the processing order switching control unit 46b via the other-unit communication I / F 48a and the other-unit communication I / F 48b of the control unit 4b.

When receiving the inquiry, the processing order change control unit 46b of the device 5b performs a required time calculation process, and returns the required time T3 and the sum s _{S3 of the} standard deviation to the processing order change control unit 46a of the device 5a (step). S302).

FIG. 4 is a flowchart showing a required time calculation process performed by the process order change control unit 46b. Here, it is assumed that in the apparatus 5b, the wafer process a11 that has been started in the recipe R11 and the wafer process a12 that is waiting for the start of the process in the recipe R12 are generated (steps S401 and S402). In this case, the processing order change control unit 46b calculates a required time T3 and a standard deviation sum s _S3 when the wafer processing a3 by the received recipe R3 is added as the wafer processing a13. In the apparatus 5b, when the wafer processes a11, a12, and a13 are executed, pre-setup processes b11, b12, and b3 are required, respectively.

The processing sequence switching control unit 46b that has received the inquiry from the processing sequence switching control unit 46a checks the presence or absence of another carrier to be carried into the device 5b before calculating the required time T3 and the standard deviation sum s _S3. (Steps S404 and S405). Such confirmation can be performed by an inquiry to the conveyance controller 3 or the conveyance carriage 2.

If another carrier exists, the processing order switching control unit 46b sets the required time T3 = ∞ and the standard deviation sum s _S3 = 0 (steps S405 Yes, S409). This is because when there is another carrier to be carried in, it is meaningless to calculate the required time T3 without considering the carrier. If there is no other carrier, the processing order change control unit 46b copies the information about the wafer processing already instructed from the control computer 1 to the storage unit 49b, and receives the inquiry from the wafer processing a3. A virtual wafer processing queue to which (wafer processing a13) is added is created (steps S405 No, S406). In the apparatus 5b, the wafer processing already instructed from the control computer 1 is continued without being stopped.

In this embodiment, the expected processing time PT11b of the pre-setup process b11, the expected processing time PT11a of the wafer processing a11, the expected processing time and PT12a of the wafer processing a12, the standard deviation s _{PT11b of} the expected processing time PT11b, and the expected processing time PT11a. the standard deviation s _PT11a, standard deviation s _PT12a expected processing time PT12a of are included in the information relating to the wafer processing. In the present embodiment, the predicted processing times PT11b, PT11a, PT12a and the standard deviations _sPT11b , _sPT11a , _sPT12a are configured to be calculated by, for example, the prediction unit 461b of the processing order change control unit 46b that has received the inquiry. It has become. That is, the storage unit 49b of the control unit 4b provided in the apparatus 5b holds the above-described history of wafer processing and pre-setup processing executed in the past in the apparatus 5b, and the expected processing time PT1b by the above-described prediction unit 461a. , PT1a, PT2a, and standard deviations _sPT1b , _sPT1a , _PT2a are calculated by the same method. As described above, when the previous setup process b11 is completed before the inquiry by the process order change control unit 46b, the actual value becomes the expected processing time PT11b and the standard deviation _sPT11b = 0.

Similarly, the prediction unit 461b extracts history information of the same number as the number of wafers to be processed N3 processed by the recipe R3 used in the wafer processing a13 from the wafer processing history held in the storage unit 49b. Then, the median value of the corrected processing time data obtained by removing the upper (long-time side) 10% and the lower (short-time side) 10% of the extracted processing time data is set as the expected processing time PT13a of the wafer processing a13. calculate. At the same time, the standard deviation of the corrected processing time data is calculated as the standard deviation s _PT13a for the expected processing time PT13a.

  Now, since the wafer processing a11 has already started, the prediction unit 461b is left as the head without changing the processing order of the wafer processing a11, the wafer processing a13 is processed second, the wafer processing a12 is processed third. The time required for wafer processing when processing is calculated as the required time T3. Here, the reason for changing the processing order of the wafer processing a13 (wafer processing a3) to be inquired is that the carrier to be subjected to the wafer processing is not the apparatus 5b as a result of having determined that the control computer 1 is advantageous in the first place. This is because it is carried into the device 5a.

At this time, the prediction unit 461b extracts history information of the previous setup process b3 when the recipe R11 is performed immediately before the previous setup process, from the previous setup process history held by the storage unit 49b. Then, the median value of the corrected processing time data excluding upper 10% (long time side) data and 10% lower (short time side) data among the extracted processing time data is the estimated processing time PT14b of the pre-setup process b3. Calculate as At the same time, the standard deviation of the correction processing time data is calculated as the standard deviation s _PT14b for the expected processing time PT14b. Further, the prediction unit 461b extracts history information of the previous setup process b12 when the recipe R3 is performed immediately before the previous setup process, from the previous setup process history held by the storage unit 49b. Then, the median value of the corrected processing time data excluding upper 10% (long time side) data and 10% lower (short time side) data of the extracted processing time data is used as the expected processing time PT15b of the pre-setup process b12. Calculate as At the same time, the standard deviation of the correction processing time data is calculated as the standard deviation s _PT15b for the expected processing time PT15b.

Then, the processing order change control unit 46b performs the expected processing time PT11a for the wafer processing a11, the expected processing time PT12a for the wafer processing a12, the expected processing time PT13a for the wafer processing a13, the expected processing time PT11b for the previous setup processing b11, and the previous setup processing. The processing end time is obtained by subtracting the elapsed time LT11 from the start of processing of the wafer processing a11 (at the start of the previous setup process b11) from the sum S3 of the expected process time PT14b of b3 and the expected process time PT15b of the previous setup process b12. The required time T3 is calculated (step S407). Further, the processing order switching control unit 46a calculates the sum s _S3 of the standard deviations s _PT11b , s _PT11a , s _PT14b , s _PT13a , s _PT15b , s _PT12a calculated by the prediction unit 461b as described above (step S407). ).

As described above, in the apparatus 5b, the processing order change control unit 46b that calculates (or sets) the required time T3 and the standard deviation sum s _S3 when the wafer processing a3 is executed is the communication with other machine I / F 48b. Then, the calculated required time T3 and the sum s _{S3 of the} standard deviation are transmitted to the processing order switching control unit 46a through the communication with other machine I / F 48a (step S408).

  The processing order change control unit 46a compares the required time Ta in the apparatus 5a (here, the required time T1 because there is no order change) and the received required time T3 (Step S303 in FIG. 3). . When T1 ≦ T3, since the required time is not shortened even if the wafer processing a3 is transferred to the apparatus 5b, the processing order change control unit 46a determines that the transfer is impossible and ends the processing (steps S303 Yes and S306).

On the other hand, when the comparison result in step S303 of FIG. 3 is T1> T3, the processing order switching control unit 46a determines whether or not the processing priority P3 of the wafer processing a3 is equal to or lower than normal, and T1> T3 + s _S3 . It is determined whether or not there are (steps S303 and S304 in FIG. 3).

Here, since the sum s _S3 of the standard deviation is a variation amount of the processing time, the value obtained by adding the sum s _{S3 of the} standard deviation to the required time T3 is the most when the variation in the processing time is considered in the processing in the apparatus 5b. This corresponds to a large required time (latest end time). Therefore, when T1> T3 + s _S3 , even when the variation amount s _S3 of the required time T3 is taken into consideration, the processing end timing is longer when the wafer processing a3 is performed by the apparatus 5b than when the wafer processing a3 is performed by the apparatus 5a. It means getting faster. Further, when T1 ≦ T3 + s _S3 (that is, T3 <T1 ≦ T3 + s _S3 ), if it is determined only by the median processing time actual value, the wafer processing a3 is performed by the apparatus 5a when the wafer processing a3 is performed by the apparatus 5b. The processing end timing is earlier than that of performing the above, but considering the variation amount s _S3 of the required time T3, it means that the processing end timing may be delayed when the wafer processing a3 is performed by the apparatus 5b. Therefore, in the present embodiment, when T1 ≦ T3 + s _S3 , whether transfer is possible is determined in consideration of the processing priority P3 of the wafer processing a3. That is, when the processing priority P3 of the wafer processing a3 is below normal (non-priority progress), the possibility of shortening the processing time by performing the transfer is emphasized, and the processing priority P3 of the wafer processing a3 is high The (priority progress) emphasizes the possibility of extending the processing time by performing the transfer.

That is, when T1> T3 + s _S3 or when the processing priority P3 of the wafer processing a3 is normal or lower, the processing order change control unit 46a determines that the transfer is possible and ends the processing (steps S304 Yes and S305). If T1 ≦ T3 + s _S3 and the processing priority P3 of the wafer processing a3 is high, the processing order change control unit 46a determines that the transfer is impossible and ends the processing (steps S304 Yes and S306).

  As a result of the above-described transfer possibility determination process, when the process order change control unit 46a determines that transfer is not possible, the load port control unit 41a, the handler control unit 42a, and the process control unit 43a of the control unit 4a are controlled by the control computer 1. The wafer processing is executed in the order of processing as instructed, that is, the order of wafer processing a1, a2, and a3, and all wafer processing is completed (steps S210 No and S214 in FIG. 2). On the other hand, when it is determined that the transfer can be performed, the processing order switching control unit 46a performs the following processing, and transfers the wafer processing a3 to the apparatus 5b (step S210 Yes in FIG. 2).

  First, the processing order change control unit 46a transmits, through the SECS communication control unit 44, a notification indicating that it is advantageous to process the wafer processing a3 by the apparatus 5b to the control computer 1. Receiving this notification, the control computer 1 changes the processing plan so that the wafer to be subjected to wafer processing a3 of the apparatus 5a is processed by the apparatus 5b. That is, a processing reservation cancellation instruction for wafer processing a3 is immediately transmitted to the apparatus 5a (control unit 4a), and processing of the wafer that is the target of the wafer processing a3 is reserved to the apparatus 5b (control unit 4b). At the same time, the transfer controller 3 that supervises the transfer carriage 2 is instructed to take out the target carrier for the wafer processing a3 and carry it into the apparatus 5b.

  In the apparatus 5a (control unit 4a) that has received the instruction, the processing reservation cancellation of the wafer processing a3 is performed. Further, the transport controller 3 searches for an empty transport cart 2 that is closest in time to the device 5a, and instructs the transport cart 2 to execute the delivery of the carrier from the device 5a and to carry it into the device 5b. When the transport device communication control unit 45a detects the approach / arrival of the transport cart 2 that has received the instruction, the load port control unit 41a pays out the target carrier for the wafer processing a3.

  Thus, the wafer processing a1 and a2 are continuously executed in the apparatus 5a, while the wafer processing a3 is transferred to the apparatus 5b (steps S211 and S212 in FIG. 2). As a result, the total processing time of the wafer processing a1 to a3 can be shortened. That is, the semiconductor manufacturing apparatus can be efficiently operated even in a semiconductor production line including a MES and a dispatcher that select a next processing lot by using the generation of an inventory lot for the manufacturing apparatus or the generation of a vacancy at the entrance of the apparatus. .

  In the present embodiment, the time required for carrier conveyance between the device 5a and the device 5b is not considered. This is because the control computer 1 devises a processing plan in which a load is not concentrated on some semiconductor manufacturing apparatuses, and the same (three wafer processing) carriers stay in each semiconductor manufacturing apparatus. This is because it is assumed that the carrier can be conveyed during that time. When considering the carrier transport time, the carrier transport time is added to the required time T3. Such a carrier transfer time may be configured such that, for example, a standard time required for transfer between semiconductor manufacturing apparatuses is registered in advance in the storage unit 49b.

  Next, the transfer possibility determination process performed by the process order change control unit 46a when the process order is changed (step S213) will be briefly described with reference to FIGS.

The processing order switching control unit 46a sends the required time Tb and the standard deviation sum sb when the last wafer processing is executed in the apparatus 5b to the processing order switching control unit 46b of the control unit 4b provided in the apparatus 5b. An inquiry is made (step S301). When the processing order is changed (step S213), the last wafer processing is wafer processing a2. In addition, the required time Tb and the standard deviation sum sb in this case are hereinafter referred to as the required time T4 and the standard deviation sum s _S4 .

  At this time, the processing order change control unit 46a reads information (recipe R2, processing target wafer number N2, processing priority P2 based on delivery date, etc.) stored in the storage unit 49a and required for executing the wafer processing a2, The data is transmitted to the processing order switching control unit 46b through the other machine communication I / F 48a and the other machine communication I / F 48b.

When the processing order change control unit 46b of the device 5b receives the inquiry, the processing time change control unit 46b performs the required time calculation process described above, and returns the required time T4 and the sum s _{S4 of the} standard deviation to the processing order change control unit 46a of the device 5a. .

In this case, the processing order change control unit 46b creates a virtual wafer processing queue to which the wafer processing a2 is added (step S406), and the expected processing time of the wafer processing and the pre-setup processing according to the wafer processing a2. In addition, the standard deviation of the expected processing time is calculated, and the required time T4 and the sum s _{S4 of the} standard deviation are calculated (step S407).

As described above, in the apparatus 5b, the processing order change control unit 46b that calculates the required time T4 and the standard deviation sum s _S4 when the wafer processing a3 is executed is used for the other machine communication I / F 48b and the other machine. Via the communication I / F 48a, the calculated (or set) required time T4 and the standard deviation sum s _S4 are transmitted to the processing order change control unit 46a (step S408).

  The processing order change control unit 46a compares the required time Ta in the apparatus 5a (here, the required time T2 because there is an order change) and the received required time T4 (Step S303 in FIG. 3). . When T2 ≦ T4, since the required time is not shortened even if the wafer processing a2 is transferred to the apparatus 5b, the processing order change control unit 46a determines that the transfer is impossible and ends the processing (steps S303 Yes and S306).

On the other hand, when the comparison result in step S303 in FIG. 3 is T2> T4, the processing order change control unit 46a determines whether or not the processing priority P2 of the wafer processing a2 is normal or lower, and T2> T4 + s _S4 . It is determined whether or not there are (steps S303 and S304 in FIG. 3).

When T2> T4 + s _S4 or when the processing priority P2 of the wafer processing a2 is not higher than normal (non-priority progress), the processing order change control unit 46a determines that the transfer is possible and ends the processing (step) S304 Yes, S305). If T2 ≦ T4 + s _S4 and the processing priority P2 of the wafer processing a2 is high (priority progression), the processing order change control unit 46a determines that the transfer is impossible and ends the processing (steps S304 Yes and S306). .

  As a result of the above-described transfer possibility determination process, when the processing order switching control unit 46a determines that the transfer is impossible, the load port control unit 41a, the handler control unit 42a, and the process control unit 43a of the control unit 4a perform processing order switching control. The wafer processing is executed in the order of processing as determined by the unit 46a, that is, in the order of wafer processing a1, a3, and a2, and all wafer processing is completed (steps S210 No and S214 in FIG. 2). On the other hand, when it is determined that the transfer is possible, the processing order switching control unit 46a performs the above-described processing and transfers the wafer processing a2 to the apparatus 5b (step S210 Yes in FIG. 2). Thus, the wafer processing a1 and a3 are continuously executed in the apparatus 5a, while the wafer processing a2 is transferred to the apparatus 5b (steps S211 and S212 in FIG. 2). As a result, the total processing time of the wafer processing a1 to a3 can be shortened.

  In the above embodiment, transmission and reception of electrical signals such as instructions and inquiries between different computers (between devices) are performed by physical communication means such as IEEE 802.3 and logical such as HSMS (High-Speed SECS Message Services). Although it is performed using communication means, it is not specified as such means as long as it realizes transmission and reception of electrical signals that can be interpreted between different computers.

  In the above description, the processing time required for each carrier (wafer processing time, pre-processing time) is calculated based on the median value based on the history information, but it may be an average value or a minimum value.

  As described above, according to the present invention, efficient operation of the semiconductor manufacturing apparatus can be realized by reducing the number of setup processes and shortening the setup process. In particular, in a semiconductor manufacturing apparatus or a high-throughput semiconductor manufacturing apparatus that requires a setup process every time the recipe is switched, the product lead time can be shortened and the apparatus running cost can be reduced. In addition, since the processing sequence change processing and transfer processing to another semiconductor manufacturing device are performed in a state where the carrier has reached the semiconductor manufacturing device, the semiconductor manufacturing device can be efficiently used regardless of the traffic jam condition of the transport carriage route, etc. Can be operated systematically. In addition, since these processes are performed between semiconductor manufacturing apparatuses that perform the same kind of wafer processing independently of instructions from the control computer, the load on the control computer does not increase.

  The present invention is not limited to the embodiment described above, and various modifications and applications are possible without departing from the technical idea of the present invention. For example, in the above embodiment, the load port control unit 41, the handler control unit 42, the process control unit 43, the SECS communication control unit 44, the transport device communication control unit 45, the processing order change control unit 46, the transport controller communication I / The F47, the other-unit communication I / F 48, and the storage unit 49 constitute the control unit 4, but these units may be arranged in the semiconductor manufacturing apparatus 5, for example, and can communicate with each other Of course, the same effect can be obtained even if they are distributed in the production line. In this case, the communication interfaces (SECS communication control unit 44, anti-conveyance device communication control unit 45, anti-conveyance controller communication I / F 47, and anti-other machine communication I / F 48) may be appropriately arranged according to the arrangement of other parts. it can. In the above description, the storage unit 49 is configured to store the record data. However, the record data is stored in the control computer 1, and the processing time (wafer processing time) is stored using the record data stored in the control computer 1. , The pre-processing time) may be calculated.

  Further, in the above embodiment, the case where three wafer processes occur has been described, but even in the case where more wafer processes occur, only the number of combinations assumed when changing the processing order is increased. The same applies. For example, the processing order that minimizes the total processing time is extracted from the combination of the processing order according to the instruction from the control computer and the assumed processing order, and the other semiconductor manufacturing is performed in that order from the last wafer processing. What is necessary is just to set it as the structure which determines the propriety of transfer to an apparatus. Further, in the required time calculation process in the other semiconductor manufacturing apparatus shown in FIG. 4, if there are three or more wafer processes in the other semiconductor manufacturing apparatus at the time of the inquiry, an assumed processing sequence is performed. The processing order that makes the total processing time the shortest is extracted from the combination, and the processing end time when processing is performed in the processing order may be returned.

  Furthermore, in the above-described embodiment, the case where two semiconductor manufacturing apparatuses exist has been described, but the same applies even when there are three or more semiconductor manufacturing apparatuses capable of executing the same wafer processing. be able to.

  In addition, in the above-described embodiment, as a particularly preferable mode, a configuration has been described in which the processing order change control unit always considers the transfer of the last carrier after determining the presence or absence of the processing order. Even if the configuration is not performed, the total processing time of the wafer processing can be shortened, and the semiconductor manufacturing apparatus can be operated efficiently. In addition, in the transfer possibility determination process, it is possible to adopt a configuration in which transfer possibility is determined only by the determination in step S303 without performing the determination in step S304 in FIG.

  INDUSTRIAL APPLICABILITY The present invention is useful as a semiconductor manufacturing system because it has an effect that a stock lot can be processed earlier in an automated semiconductor production line and a semiconductor manufacturing apparatus can be operated efficiently.

DESCRIPTION OF SYMBOLS 1 Control computer 2 Conveyance cart 3 Conveyance controller 4, 4a, 4b Control part 5, 5a, 5b Semiconductor manufacturing apparatus

Claims (11)

A control computer;
A semiconductor production line for processing wafers contained in a plurality of wafer containers in accordance with instructions from the control computer;
When the plurality of wafer containers arrive at the first semiconductor manufacturing apparatus belonging to the semiconductor production line, an estimated processing time of processing in the first semiconductor manufacturing apparatus for the wafers accommodated in each wafer container is required for the setup process. A first prediction unit for calculating including time;
Based on the calculated expected processing time, a first processing order of the plurality of wafer containers is determined so that processing in the first semiconductor manufacturing apparatus of the wafers accommodated in the plurality of wafer containers is completed in the shortest time. A processing order switching control unit;
A first execution unit that causes the first semiconductor manufacturing apparatus to perform processing of the wafers contained in the plurality of wafer containers according to the determined processing order;
A semiconductor manufacturing system comprising: When there are a plurality of wafer containers in the first semiconductor manufacturing apparatus,
The first prediction unit calculates the time required for processing the wafers contained in each wafer container for each wafer container based on the history of processing time for the wafers already processed in the first semiconductor manufacturing apparatus, The time required for the set-up process performed corresponding to the process performed on the wafers contained in each wafer container and the process performed immediately before the set-up is the set-up process time already processed in the first semiconductor manufacturing apparatus. Calculated for each wafer container based on the history of
The first processing order switching control unit calculates a total processing time for all wafer containers in the first semiconductor manufacturing apparatus when processing is performed in the processing order of each wafer container instructed by the control computer for each wafer container. Is calculated as the sum of the time required for the wafer processing and the time required for the setup processing calculated for each wafer container in accordance with the processing order, and the first time the wafer is processed in the first semiconductor manufacturing apparatus. The processing time of all wafer containers in the first semiconductor manufacturing apparatus when processing is performed in the processing order of each other wafer container in a state in which the processing order of the wafer containers is fixed is calculated for each wafer container. According to the time required for wafer processing and the processing sequence Serial calculated as the sum of the time required for the calculated setup process for each wafer container, the calculated sum to determine the processing order is the minimum as the processing order of the plurality of wafer containers, according to claim 1 semiconductor manufacturing system according. A second semiconductor manufacturing apparatus capable of performing the same kind of wafer processing as the first semiconductor manufacturing apparatus;
A second prediction unit that has the same function as the first prediction unit, and calculates an expected processing time for the wafer accommodated in the wafer container in the second semiconductor manufacturing apparatus, including the time required for the setup process. When,
A second processing order switching control unit that has the same function as the first processing order switching control unit and determines a processing order of wafer containers in the second semiconductor manufacturing apparatus;
A second execution unit that causes the second semiconductor manufacturing apparatus to perform processing of the wafers accommodated in the wafer container according to the processing order determined by the second processing order replacement control unit;
A communication interface for transferring information between the first semiconductor manufacturing apparatus and the second semiconductor manufacturing apparatus;
Further comprising
The first processing order change control unit transmits information necessary for executing processing on the wafer accommodated in the last wafer container in the determined processing order to the second processing order change control unit through the communication interface. The second processing order change control unit is requested to calculate the processing end timing for the last wafer container and all of the wafer containers present in the second semiconductor manufacturing apparatus at that time, and the second interface is sent through the communication interface. 2 Based on the processing end time Tb received from the processing order change control unit and the processing end time Ta of the determined processing order, the second semiconductor manufacturing apparatus performs processing on the wafer accommodated in the last wafer container. The semiconductor manufacturing system according to claim 2, wherein it is determined whether or not to transfer to. The second prediction unit includes a time required for processing a wafer accommodated in a wafer container existing in the second semiconductor manufacturing apparatus at the time of a request from the first processing order change control unit and the last wafer container. The time required for processing the accommodated wafer is calculated for each wafer container based on the history of the processing time for the wafer already processed in the second semiconductor manufacturing apparatus, and the processing for the wafer accommodated in each wafer container and The time required for the setup process performed corresponding to the process performed immediately before the process is calculated for each wafer container based on the history of the setup process time already processed in the second semiconductor manufacturing apparatus. ,
The second processing order change control unit performs processing in the processing order of each other assumed wafer container in a state where the processing order of the first wafer container in which the wafer is processed in the second semiconductor manufacturing apparatus is fixed. In this case, the total processing time for all the wafer containers in the second semiconductor manufacturing apparatus is set up for each wafer container according to the time required for the wafer processing calculated for each wafer container and the processing order. 4. The semiconductor manufacturing system according to claim 3, wherein a processing end time Tb when processing is performed as a total sum of time required for processing and processing is performed in a processing order in which the calculated total sum is minimum is transmitted to the first processing order switching control unit. The second process order change control unit calculates an expected variation amount sb of the process end time together with the process end time Tb, and transmits the calculated amount of variation sb to the first process order change control unit.
The first processing order change control unit
When Tb ≧ Ta, even when Tb <Ta, Ta ≧ Tb + sb, and when the highest processing priority is given to the last wafer container, the determined processing order remains unchanged. The process is continued in the first execution unit,
The last wafer container in the first semiconductor manufacturing apparatus when Tb <Ta <Tb + sb and when Tb <Ta and when the highest wafer processing priority is not given to the last wafer container 5. The semiconductor manufacturing system according to claim 4, wherein the control computer is requested to cancel the process and transfer the process of the last wafer container to the second semiconductor manufacturing apparatus.   The said prediction part calculates the time required for the process with respect to the wafer accommodated in the said wafer container by the median value based on the history of the process time with respect to the wafer already processed in the said semiconductor manufacturing apparatus. A semiconductor manufacturing system according to claim 1.   The said prediction part calculates the time required for the process with respect to the wafer accommodated in the said wafer container by the minimum value based on the history of the process time with respect to the wafer already processed in the said semiconductor manufacturing apparatus. A semiconductor manufacturing system according to claim 1. The prediction unit determines the time required for processing the wafer stored in the wafer container.
The semiconductor manufacturing system according to claim 1, wherein the semiconductor manufacturing system calculates the average value based on a history of processing time for a wafer that has already been processed in the semiconductor manufacturing apparatus.   The predicting unit calculates a time required for the setup process performed corresponding to a process for the wafer accommodated in the wafer container by a median value based on a history of the setup process time already processed in the semiconductor manufacturing apparatus. The semiconductor manufacturing system according to claim 1 or 6.   The prediction unit calculates a time required for the setup process performed corresponding to the process for the wafer accommodated in the wafer container by a minimum value based on a history of the setup process time already processed in the semiconductor manufacturing apparatus. The semiconductor manufacturing system according to claim 1 or 7.   The prediction unit calculates the time required for the setup process performed corresponding to the process for the wafer accommodated in the wafer container based on an average value based on the history of the setup process time already processed in the semiconductor manufacturing apparatus. The semiconductor manufacturing system according to claim 1 or 8.

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