JP2010040678A - Semiconductor manufacturing equipment and production process of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide semiconductor manufacturing equipment that can reduce a setup time and can prevent a capacity utilization rate from being declined and a throughput from being deteriorated. <P>SOLUTION: When an equipment status controller 108 detects that a lot has been fed to the equipment 100, a lot processing sequence modifier 110 prepares all processing sequence patterns about lots included in the nominated lots for next processing including lots preprocessed and scheduled for feeding and lots under preprocessing and scheduled for feeding. With respect to all the processing sequence patterns, the setup time managed by a setup time controller 107 is used to calculate each process completion time for each of all the lots including a setup time when one lot is switched over to another and determine the order of the processing sequence patterns that ensures the shortest process completion time to request the lots to be fed according to the order determined. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method and an apparatus for improving the operating rate of a semiconductor manufacturing apparatus.

  In a manufacturing process of a semiconductor device or the like, a semiconductor device is processed using a plurality of manufacturing apparatuses. The processing contents differ for each manufacturing apparatus. Even in the same manufacturing apparatus, the processing conditions differ depending on the type of semiconductor device, and even in the case where the same type is processed in the same manufacturing apparatus, the processing conditions differ depending on the target process. . Furthermore, in the manufacturing process of a semiconductor device, since a product is processed through processes of 1000 steps or more, processing may be repeatedly performed using the same apparatus. Therefore, there are various lot transfer source devices sent to one manufacturing apparatus, and the distribution form is very complicated. Due to such a complicated physical distribution form, the operating rate of the semiconductor manufacturing apparatus has a characteristic that it largely varies depending on the order of stock and lot input. For this reason, various technological developments have been made in the semiconductor production line for the purpose of controlling the progress of lots and improving the operating rate of manufacturing equipment.

  As a method for manufacturing a semiconductor device that controls the conveyance of a lot without lowering the operating rate of the manufacturing apparatus, there is, for example, the one disclosed in Patent Document 1. Patent Document 1 discloses a method for preferentially processing a high-priority express lot process without reducing the operating rate of a semiconductor manufacturing apparatus.

FIG. 17 is a schematic diagram illustrating a configuration of a semiconductor device manufacturing line disclosed in Patent Document 1. In FIG. The manufacturing line includes manufacturing apparatuses EQ1, EQ2, and EQ3 that perform wafer processing steps, and transport apparatuses TEQ1 and TEQ2 that transport lots to the respective manufacturing apparatuses. These manufacturing apparatuses and transport apparatuses are managed and controlled by the factory host FHST. The factory host FHST includes a processing completion time management unit PFTC, an apparatus state management unit ECC, a lot state management unit LCC, a transport instruction issue unit CDP, and the like. Here, the lot conveyance determination to the next process is performed by predicting the lot processing completion time by the processing completion time management unit PFTC, the manufacturing apparatuses EQ1, EQ2, EQ3 and the conveyance apparatuses TEQ1, TEQ2 managed by the apparatus state management unit ECC. Judgment is made based on the state and work status of In other words, if the remaining processing time of the lot being processed in the next process manufacturing apparatus is equal to or greater than a set value or the number of vacant lot input ports of the next process manufacturing apparatus is 1 or less, the priority to be processed in the next process manufacturing apparatus Even if processing of a low-priced lot is completed, the lot is not transferred to the next process manufacturing apparatus. In addition, if the remaining processing time of a lot being processed in the next process manufacturing apparatus is greater than a certain set value, or if the number of available ports is 2 or more, the lot to be processed in the next process manufacturing apparatus regardless of priority. It is conveyed to the next process manufacturing device. In this configuration, a high-priority lot for which the previous process is scheduled to finish after a low-priority lot can be carried into the next-process manufacturing apparatus without delay, so that the operation of the semiconductor manufacturing apparatus is not reduced. It is possible to preferentially process lots with high priority.
JP 2003-316421 A

  However, in the above prior art, if the remaining processing time of the lot being processed in the next process manufacturing apparatus is less than a set value or the number of available ports is 2 or more, the lot is unconditionally input to the next process manufacturing apparatus. Therefore, it is not always possible to suppress a reduction in operating rate. For example, if processing such as chamber cleaning or beam setup needs to be executed before lot processing due to processing condition changes (recipe switching), etc., if a normal lot is input only with the remaining processing time Not only will the subsequent express lot be kept waiting longer than expected due to the time required for recipe switching, but it will also require extra setup time that does not add value to the lot processing. In such a case, waiting for the express lot can reduce the setup time, and as a result, it may be possible to suppress a decrease in the operating rate of the semiconductor manufacturing apparatus. That is, it can be said that the above-described conventional technique is an insufficient technique from the viewpoint of the apparatus operating rate.

  The present invention has been proposed in order to solve the problems of the prior art, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor manufacturing apparatus capable of suppressing a reduction in operating rate of the semiconductor manufacturing apparatus. It is said.

  In order to achieve the above object, the present invention employs the following technical means.

  First, the present invention is premised on a semiconductor manufacturing apparatus that is disposed on a semiconductor device manufacturing line and processes an input lot under one processing condition selected from a plurality of processing conditions. Then, the semiconductor manufacturing apparatus according to the present invention first displays all processing order patterns for lots included in the next processing candidate lot including the previous process end lot scheduled to be input and the previous process processing lot scheduled to be input. create. Next, for each created processing sequence pattern, processing for all lots including the previous process remaining processing time, transport time from the previous process, processing time for the input lot, and setup time at the time of lot switching is completed. Calculate time. Then, based on the calculated processing end time, a lot input is requested in the processing order of the processing order pattern in which the processing is completed in the shortest time.

  Further, in the semiconductor manufacturing apparatus of the present invention, when a lot is input, the lot processing order changing means is activated to determine the processing order in which the processing is completed in the shortest time from among the input lots. The processing order of the lots waiting for the processing order is changed according to the judgment result.

  According to the present invention, it becomes possible to change the order of lot input to the semiconductor manufacturing apparatus and the order of processing start of already input lots in ascending order of the processing end time of the lot including the setup time generated during the lot processing. Setup time during recipe switching that does not add value to wafer processing can be reduced. As a result, it is possible to improve the throughput of the semiconductor manufacturing apparatus and the operating rate of the semiconductor manufacturing apparatus.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following embodiments, the present invention is embodied as an arbitrary semiconductor manufacturing apparatus in a post-process in which a processing lot proceeds in a plurality of processing lots traveling on a semiconductor manufacturing line having a plurality of semiconductor manufacturing apparatuses.

  FIG. 1 is a schematic configuration diagram showing an embodiment of a semiconductor manufacturing apparatus of the present invention. A plurality of semiconductor manufacturing apparatuses according to the present embodiment exist in the semiconductor manufacturing line 101. Each semiconductor manufacturing apparatus is connected to the host computer 103 via the network line 102, and can exchange data and operation instructions with each other. In FIG. 1, the semiconductor manufacturing apparatus 100 according to the present embodiment and the semiconductor manufacturing apparatus 104 according to the present embodiment, which is one of the semiconductor manufacturing apparatuses that perform processing in the previous process of the semiconductor manufacturing apparatus 100. Only the semiconductor manufacturing apparatus is not shown.

  As shown in FIG. 1, the semiconductor manufacturing apparatus 100 of this embodiment includes a condition management unit 105, a lot processing progress management unit 106, a setup time management unit 107, an apparatus state management unit 108, a lot search unit 109, and a lot input order determination. Unit 110 and a lot processing order changing unit 111. Each unit includes, for example, a dedicated arithmetic circuit, hardware including a processor and a memory such as a RAM (Random Access Memory) and a ROM (Read Only Memory), and software stored in the memory and operating on the processor. Etc. can be realized. Note that “management” described below refers to holding data as a searchable database. Although not shown, the pre-process semiconductor manufacturing apparatus 104 also includes a condition management unit 105, a lot processing progress management unit 106, a setup time management unit 107, an apparatus state management unit 108, a lot search unit 109, and a lot input order. A determining unit 110 and a lot processing order changing unit 111 are provided.

  First, functions of each unit included in the semiconductor manufacturing apparatus 100 will be briefly described. The processing condition management unit 105 manages a recipe group used for lot processing in the semiconductor manufacturing apparatus 100 and a processing time corresponding to each recipe. Here, the processing time is managed as a calculation formula capable of calculating the processing time according to the number of wafers in a processing lot (hereinafter referred to as a lot).

  The lot processing progress management unit 106 manages the remaining processing time of the lot being processed in the semiconductor manufacturing apparatus 100. Here, the lot processing progress management unit 106 manages the remaining processing time calculated based on the processing time managed by the processing condition management unit 105 and the processing elapsed time of the lot being processed in the semiconductor manufacturing apparatus 100. .

  The setup time management unit 107 manages setup time such as chamber cleaning that occurs every time the recipe used during lot processing is switched. In the setup time management unit 107, setup times for all recipe switching that may occur in the semiconductor manufacturing apparatus 100 are registered in advance. In addition, although it is set as the structure by which a setup time is managed separately here, it is not limited to the said structure, A setup time may be included in recipe itself. In this case, it is preferable to manage the setup time with the processing time managed by the processing condition management unit 105.

  The apparatus state management unit 108 manages the process start, process end, and process wait as the state of the lot input to the port of the semiconductor manufacturing apparatus 100. Further, when the lot processing is completed, the device state management unit 108 notifies the host processing computer 103 or another semiconductor manufacturing apparatus that performs the subsequent processing of the completion of the lot processing, and when the lot is newly input to the port. The lot processing order changing unit 111 is notified that the lot has been input.

  The lot search unit 109 receives the end of the lot processing from the device state management unit 108 mounted on the semiconductor manufacturing apparatus (for example, the previous process semiconductor manufacturing apparatus 104) that performs the process of the process immediately preceding the semiconductor manufacturing apparatus 100. When notified, the host computer 103 that manages the progress flow of all the lots traveling on the semiconductor manufacturing line 101 is searched for a lot being processed by a plurality of semiconductor manufacturing apparatuses performing the previous process.

  The lot insertion order determination unit 110 is activated when the pre-process semiconductor manufacturing apparatus 104 notifies the end of the lot process, and is the shortest among the next process candidate lots including the lots being processed by the plurality of semiconductor manufacturing apparatuses performing the pre-process. Determine the order of lots to be processed in time. Then, the determined lot input sequence is notified to the host computer 103, and a lot input in the lot input sequence is requested.

  The lot processing order changing unit 111 starts when a lot is input to a lot input port of the semiconductor manufacturing apparatus 100, and ends processing of a lot that has been input to the semiconductor manufacturing apparatus 100 (hereinafter referred to as an already input lot). The processing order of the already-introduced lot with the shortest time is determined, and the lot starting order in the semiconductor manufacturing apparatus 100 is changed.

  FIG. 2 is a flowchart showing a processing flow executed by the lot insertion order determination unit 110 of the semiconductor manufacturing apparatus 100. As described above, the process is started when the lot process is completed in the pre-process semiconductor manufacturing apparatus 104.

  First, the lot insertion order determination unit 110 acquires empty port information from the apparatus state management unit 108, and determines whether there is an empty port (step S201). FIG. 3 is an example of management information used by the apparatus status management unit 108 used for the determination, and the status of the input lot is associated with each lot input port of the semiconductor manufacturing apparatus 100. In this example, the status of processing, waiting for processing, and the end of processing are recorded according to the status of the input lot, and if there is no already input lot on the lot input port, a vacancy is recorded.

  When there is no empty port, the lot insertion order determination unit 110 ends the process as it is (No in step S201). On the other hand, when there is an empty port, the lot input order determination unit 110 determines whether there is a lot (inventory) waiting for input to the semiconductor manufacturing apparatus 100 other than the lot that has been processed by the semiconductor manufacturing apparatus 104 ( Step S202). Here, the lot insertion order determination unit 110 obtains inventory information from the host computer 103 to determine whether there is inventory. FIG. 4 is an example of inventory information data managed by the host computer 103 used for the determination. As shown in FIG. 4, for example, the inventory data includes, for each semiconductor manufacturing apparatus ID, the number of inventory, the inventory lot ID, the recipe ID applied to the inventory lot, the number of lots being processed, the lot ID being processed, and the processing conditions ( It is desirable that the recipe ID) applied to the lot being processed is included.

  As a result of the determination in step S202, if there is an input waiting lot, the process is terminated (step S202 Yes). In addition, when there is no waiting lot for input, the lot input order determination unit 110 causes the lot search unit 109 to perform a semiconductor manufacturing apparatus (including a plurality of previous-process semiconductor manufacturing apparatuses 104) that performs processing of the previous process of the semiconductor manufacturing apparatus 100. The search is instructed whether there is a lot being processed by the semiconductor manufacturing apparatus) (step S203).

  FIG. 5 is a flowchart showing a flow of processing performed by the lot search unit 109 at this time. By this processing, another lot heading for the semiconductor manufacturing apparatus 100 is searched. First, when processing starts, the lot search unit 109 searches the management data (FIG. 4) of the host computer 103 for the presence or absence of a lot in process for a semiconductor manufacturing apparatus set as a previous process candidate of the semiconductor manufacturing apparatus 100. (Step S501). Here, the previous process candidates are all semiconductor manufacturing apparatuses that may perform the process of the process immediately preceding the semiconductor manufacturing apparatus 100. Here, in the lot search unit 109, a previous process candidate device list in which semiconductor manufacturing apparatuses that are previous process candidates are recorded is registered, and the lot search unit 109 performs the search based on the list. FIG. 6 shows registration information of a semiconductor manufacturing apparatus which is a previous process candidate apparatus of the semiconductor manufacturing apparatus 100. Device IDs of all semiconductor manufacturing apparatuses in which a lot is processed before proceeding to the semiconductor manufacturing apparatus 100 are set in advance. Yes.

  As a result of the search in step S501, if there is no lot being processed in the semiconductor manufacturing apparatus set as the previous process candidate, the lot search unit 109 ends the process (No in step S501). If there is a lot in process, the lot progress flow of the corresponding lot is retrieved from the host computer 103, and the next processing step apparatus of the corresponding lot extracts the lot that is the semiconductor manufacturing apparatus 100 (step S502). . As a result, only the lot to be input to the semiconductor manufacturing apparatus 100 after the processing is completed is extracted from the processing lot detected in step S501. FIG. 7 is a diagram showing an example of a lot progress flow table managed by the host computer 103. In the lot progress flow table, a lot progress process, a device ID of a semiconductor manufacturing apparatus to be used, and a processing recipe ID to be used in the semiconductor manufacturing apparatus are recorded for each lot. Although FIG. 7 shows only the lot progress flow table for one lot, the host computer 103 manages the lot progress flow table for all lots input to the semiconductor manufacturing line 101. In addition, as shown in FIG. 7, it is preferable that the progress result according to the actual lot progress is recorded in the lot progress flow table.

  Next, the lot search unit 109 lists the previous process end lot and the lot extracted based on the search result in step S502 as the next process candidate lot (step S503). FIG. 8 is a diagram showing a list of next processing candidate lots that is listed as a result of step S503. In the next process candidate lot list, a candidate lot ID, a recipe ID used for processing the lot, and a processing state are recorded in association with each other. In the present invention, the previous process end lot is a lot that has been triggered by the lot input sequence determination unit 110, that is, a semiconductor manufacturing apparatus that performs processing of the previous process of the semiconductor manufacturing apparatus 100. Here, the device state management unit 108 of the pre-process semiconductor manufacturing apparatus 104 indicates a lot notified of the end of lot processing.

  As described above, when the lot search process S203 ends, the lot insertion order determination unit 110 next executes the lot process end time calculation process for the next process candidate lot (step S204 in FIG. 2). FIG. 9 is a flowchart showing the flow of the processing. First, the lot input order determination unit 110 acquires lot information already input to the semiconductor manufacturing apparatus 100 from management data (FIG. 3) managed by the apparatus state management unit 108. Then, the next processing candidate lot list is updated by adding the acquired already input lot to the next processing candidate lot list (FIG. 8) (step S901). Next, all possible processing order patterns are created for the lots listed in the updated next processing candidate lot list (step S902). FIG. 10 is a diagram illustrating an example of a processing order pattern table created by the lot insertion order determining unit 110. In this example, lot C and lot D are recorded in the next processing candidate lot list (FIG. 8), and in semiconductor manufacturing apparatus 100, lot A is being processed and lot B has been loaded into the input port. ing. In this case, lot A, lot B, lot C, and lot D are recorded as candidate lot IDs shown in FIG. 10 in the updated next processing candidate lot list. In this case, the processing order pattern is a permutation of lots B, C, and D excluding the lot A being processed, and six patterns are created (see FIG. 10).

  Next, the lot processing end time is calculated for all the processing order patterns created by the processing in step S902. The lot input order determination unit 110 calculates the lot processing end time for all processing order patterns, the lot processing time T1 of each lot in the semiconductor manufacturing apparatus 100, and the lot processing in the semiconductor manufacturing apparatus used in the previous process. The remaining processing time T2, the setup time T3 corresponding to the recipe switching in the semiconductor manufacturing apparatus 100, and the transfer time T4 from the semiconductor manufacturing apparatus used in the previous process to the semiconductor manufacturing apparatus 100 are acquired (step S903). The lot processing time T1 is acquired from the processing condition management unit 105 of the semiconductor manufacturing apparatus 100, and the remaining lot processing time T2 is acquired from the lot processing progress management unit 106 of the semiconductor manufacturing apparatus used in the previous process. The time T3 is acquired from the setup time management unit 107 of the semiconductor manufacturing apparatus 100, and the transfer time T4 is acquired from the host computer 103.

  FIG. 11 is a diagram illustrating an example of a processing time table managed by the processing condition management unit 105. As shown in FIG. 11, in the processing time table, the recipe ID used in the semiconductor manufacturing apparatus 100 and the processing time corresponding to each recipe are recorded in association with each other. Here, the processing time is recorded as a function having the number of wafers in the lot as an argument. FIG. 12 is a diagram illustrating an example of a remaining processing time table managed by the lot processing progress management unit 106. As shown in FIG. 12, in the remaining processing time table, the lot being processed in the semiconductor manufacturing apparatus 100, the used recipe ID, and the remaining processing time T2 are recorded in association with each other. The remaining processing time T2 is a processing elapsed time (which is managed by the apparatus state management unit 108) from the lot processing time T1 obtained by substituting the number of wafers of the lot being processed into the processing time calculation formula shown in FIG. It is calculated by subtracting (see FIG. 3). FIG. 13 is a diagram illustrating an example of a setup time table managed by the setup time management unit 107. As shown in FIG. 13, the setup time table records the combination of the recipe ID before switching, the recipe ID after switching, and the setup time for all recipe switching that can occur in the semiconductor manufacturing apparatus 100. ing. FIG. 14 is a diagram illustrating an example of a transport time table managed by the host computer 103. As shown in FIG. 14, the transfer time table records the time required for lot transfer from an arbitrary transfer source device to an arbitrary transfer destination device in association with the combination of device IDs of the semiconductor manufacturing apparatus. Here, the transfer source apparatus is a semiconductor manufacturing apparatus used in the previous process, and the transfer destination apparatus is the semiconductor manufacturing apparatus 100.

  The lot insertion order determining unit 110 that has acquired the lot processing time T1, the remaining processing time T2, the setup time T3, and the transfer time T4 executes a lot processing end time calculation process for each of the processing order patterns (see FIG. 9) ( Step S904), the process is terminated. The lot processing end time calculation processing in step S904 is executed for each of all the processing order patterns created in step S902, but 1 except for the already-introduced lots (lot A and lot B in the above example). Different calculation methods are used for the process end time calculation for the lot and the process end time calculations for the second and subsequent lots.

  The following formula 1 is used to calculate the processing end time T (1) of the first lot.

  T (1) = T3 (1) + T1 (1) (1)

  In other words, the processing end time T (1) of the first lot is uniquely calculated regardless of the presence or absence of an already input lot in the semiconductor manufacturing apparatus 100. In Equation 1, T3 (1) is the setup time for the first lot, and T1 (1) is the lot processing time for the first lot.

  In addition, for the calculation of the processing end time T (n) of the nth lot after the second lot, when T (n−1) ≦ T2 (n) + T4 (n), the following formula 2 is used. When T (n-1)> T2 (n) + T4 (n) is used, the calculation formula shown in Equation 3 below is used. Here, T (n-1) is the processing end time of the (n-1) th lot. T2 (n) is the remaining processing time in the previous process of the nth lot, and T4 (n) is the transport time of the nth lot.

  T (n) = T2 (n) + T4 (n) + T3 (n) + T1 (n) (2)

  T (n) = T (n-1) + T3 (n) + T1 (n) (3)

  That is, by the time the (n-1) th lot is processed in the semiconductor manufacturing apparatus 100, the lot processed in the nth lot is processed in the semiconductor manufacturing apparatus in the previous process and transferred to the semiconductor manufacturing apparatus 100. If not complete, Equation 2 is used. In addition, the processing in the semiconductor manufacturing apparatus in the previous process and the transfer to the semiconductor manufacturing apparatus 100 of the lot processed in the nth lot are completed by the time the (n-1) th processing is completed in the semiconductor manufacturing apparatus 100. When complete, Equation 3 is used.

  When the process end time calculation process in step S904 is completed, the process in S204 is completed, and the lot insertion order determination unit 110 next determines a process order pattern in which the final lot process is completed in the shortest time (step S205). ). Then, the host computer 103 is requested to input lots in the order determined (step S206), and the process is terminated.

  FIG. 15 is a diagram illustrating a processing flow executed by the lot processing order changing unit 111 of the semiconductor manufacturing apparatus 100. The lot processing order changing unit 111 performs processing in the order shown in the flowchart, triggered by the lot being input to the lot input port of the semiconductor manufacturing apparatus 100. First, the lot processing order changing unit 111 determines whether there is an already input lot in the semiconductor manufacturing apparatus 100 (step S1501). If there is no already input lot, the process is terminated (No in step S1501).

  Next, when there is an already-introduced lot, the lot processing order changing unit 111 creates a process start order list of all patterns that can be assumed from the already-introduced lots (Yes in steps S1501 and S1502). FIG. 16 is a diagram showing an example in which all possible processing patterns are created, taking as an example the case where there are four lot input ports in the semiconductor manufacturing apparatus 100. In this example, the input lots are 3 lots (lots A, B, and C). The lot being processed is lot A, and the new input lot is lot D. That is, FIG. 16 shows the entire processing order pattern when the processing start order of the lots B, C, and D is changed with the lot A being processed as a reference.

  After creating the processing order pattern, the lot processing order changing unit 111 extracts the setup time at the time of recipe switching from the setup time management unit 107, and calculates the total setup time for each processing order pattern. Then, the processing order pattern that shortens the total setup time is determined (step S1503), the processing start order of the semiconductor manufacturing apparatus 100 is changed (step S1504), and then the processing ends. As a result, all lots input to the semiconductor manufacturing apparatus 100 are always processed in the processing order that minimizes the processing end time of the final lot. Note that the lot processing order changing unit 111 may calculate the end time of all lot processing including the setup time at the time of lot switching for each processing order pattern instead of the total setup time. In this case as well, the same result can be obtained by determining the processing order pattern that minimizes the end time of all lot processing.

  As described above, in the semiconductor manufacturing apparatus 100 according to the present embodiment, it is possible to determine a lot insertion order that minimizes the processing end time before lot input, and to request lot input in the input order. In addition, when a lot is input, the processing order of the input lot can be changed to the lot processing start order that minimizes the processing time.

  As described above, according to the present invention, all process order patterns that can be realized in the next process candidate lot by searching for the next process candidate lot in response to the occurrence of the process end lot in the semiconductor manufacturing apparatus in the previous process. The pattern that completes the processing in the shortest time is determined. Then, with the means of requesting lot input in the lot processing order of the pattern and the fact that lots are newly input to the semiconductor manufacturing equipment, all of the lots waiting for processing among the already input lots From all the processing order patterns that can be assumed in those lots, the lot processing order pattern that completes the lot processing in the shortest time is determined. By changing the lot processing order, the operating rate of the semiconductor manufacturing apparatus can be improved.

  INDUSTRIAL APPLICABILITY The present invention has the effect of reducing setup time and improving the actual operating rate of a semiconductor manufacturing apparatus that does not add value to lot processing, and can prevent a decrease in equipment operating rate and an increase in throughput. It is useful as a semiconductor manufacturing apparatus.

1 is a schematic configuration diagram showing a semiconductor manufacturing apparatus according to an embodiment of the present invention. The flowchart which shows the process of the lot injection | throwing-in order determination part in one Embodiment of this invention. The figure which shows the management data of the apparatus state management part in one Embodiment of this invention The figure which shows the inventory which the high-order host computer manages in one Embodiment of this invention, and lot data in process The flowchart which shows the process of the lot search process part in one Embodiment of this invention. The figure which shows the previous process registration equipment list in one Embodiment of this invention. The figure which shows the lot progress flow which the high-order host computer manages in one Embodiment of this invention The figure which shows the next process candidate lot list in one Embodiment of this invention The figure which shows the process order pattern of the next process candidate lot list in one Embodiment of this invention The flowchart which shows the lot processing end time calculation process in one Embodiment of this invention The figure which shows the management data of the process condition management part in one Embodiment of this invention. The figure which shows the management data of the lot process progress management part in one Embodiment of this invention The figure which shows the management data of the setup time management part in one Embodiment of this invention. The figure which shows the conveyance time data in one Embodiment of this invention. The figure which shows the flowchart which shows the process of the lot process order change part in one Embodiment of this invention. The figure which shows the processing order pattern of the already-added lot in one Embodiment of this invention Diagram showing the configuration of the prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor manufacturing apparatus 101 Manufacturing line 102 Network line 103 High-order host computer 104 Pre-process semiconductor manufacturing apparatus 105 Processing condition management part 106 Lot processing progress management part 107 Setup time management part 108 Equipment state management part 109 Lot search part 110 Lot input order determination Part 111 Lot processing order change part

Claims (4)

In a semiconductor manufacturing apparatus that processes a lot placed and placed in a semiconductor device manufacturing line under one processing condition selected from a plurality of processing conditions.
Means for creating all processing order patterns for the lots included in the next processing candidate lot including the previous process end lot scheduled for input and the previous process processing lot scheduled for input;
For each of the created processing sequence patterns, the processing of all lots including the previous process remaining processing time, the transport time from the previous process device, the processing time for the input lot, and the setup time at the time of lot switching is completed. Means for calculating time;
Based on the calculated processing end time, means for requesting the lot to be input in the processing order of the processing order pattern in which the processing is completed in the shortest time;
A semiconductor manufacturing apparatus comprising: In a semiconductor manufacturing apparatus that processes a lot placed and placed in a semiconductor device manufacturing line under one processing condition selected from a plurality of processing conditions.
Based on the processing conditions and processing status information of the input lot, calculate the lot processing end time including the setup time at the time of lot switching or the total time of the setup time for all combinations of processing order of the input lot. Means,
Based on the calculated processing end time or the total setup time, means for changing the processing start order of the input lots to the order in which all the input lots complete the processing in the shortest time;
A semiconductor manufacturing apparatus comprising: In a method of manufacturing a semiconductor device using a semiconductor manufacturing apparatus, wherein a lot placed and placed in a semiconductor device manufacturing line is processed under one processing condition selected from a plurality of processing conditions.
Creating a pattern of all processing orders for the lots included in the next processing candidate lot including the previous process end lot scheduled for input and the previous process processing lot scheduled for input;
For each of the created processing sequence patterns, the remaining process time of the previous process, the transfer time from the previous process, the process time of the process for the input lot, and the process end time of all lots including the setup time at the time of lot switching Calculating steps,
Based on the calculated processing end time, requesting the input of lots in the processing order of the processing order pattern in which the processing is completed in the shortest time;
A method for manufacturing a semiconductor device, comprising: In a semiconductor device manufacturing method using a semiconductor manufacturing apparatus that processes a lot placed and placed in a semiconductor device manufacturing line under one processing condition selected from a plurality of processing conditions.
Based on the processing conditions and processing status information of the input lot, calculate the lot processing end time including the setup time at the time of lot switching or the total time of the setup time for all combinations of processing order of the input lot. Steps,
Changing the processing start order of the input lots to the order in which all the input lots complete the processing in the shortest time based on the calculated processing end time or the total setup time;
A method for manufacturing a semiconductor device, comprising:

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