JP2011018414A - Semiconductor device, and variable impedance circuit and resonance circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of causing a switching circuit to be in a conducting state or nonconducting state based on storage data even when a power source voltage is being interrupted.SOLUTION: Memory transistors MA which have floating gates and control gates, and N channel MOS transistors QA of which the gates are connected to the floating gates of the memory transistors and which turns on or off in accordance with the storage data of the memory transistors MA, are included in the semiconductor integrated circuit device. Thus, the transistors QA can be turned on or off based on the storage data of the memory transistors MA even when the power source voltage VCC is being interrupted.

Description

  The present invention relates to a semiconductor device and a variable impedance circuit and a resonance circuit using the semiconductor device, and more particularly to a semiconductor device including a memory transistor, and a variable impedance circuit and a resonance circuit using the semiconductor device.

  Conventionally, a non-contact type power receiving apparatus that receives electric power in a non-contact manner has been developed. This non-contact power receiving device includes an antenna coil that receives high-frequency power, a variable capacitance circuit connected in parallel to the antenna coil, a flash memory for setting the capacitance value of the variable capacitance circuit to an optimum value, and the entire device. A control unit for controlling. The variable capacitance circuit includes a plurality of capacitors and a plurality of switches.

  At the time of shipment, the capacitance value of the variable capacitance circuit is adjusted so that the resonance frequency of the resonance circuit including the antenna coil and the variable capacitance circuit matches the frequency of the high frequency power, and information indicating whether each switch is turned on or off is flashed. Written to memory. The flash memory stores information even when the power supply voltage is interrupted (see, for example, Patent Document 1). When high frequency power is supplied from the outside, the control unit reads information from the flash memory and turns on or off each switch based on the information. Thereby, the capacitance value of the variable capacitance circuit is set to an optimum value, and the high frequency power is received efficiently.

Japanese Patent Laid-Open No. 9-213093

  However, in the conventional contactless power receiving device, each switch is turned on or off regardless of the storage information of the flash memory during the period from the start of reception of high-frequency power to the setting of the capacitance value of the variable capacitance circuit to the optimum value. Since the capacitance value of the variable capacitance circuit is not the optimum value because it is turned off, there is a problem that the efficiency is low.

  SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a semiconductor device capable of bringing a switch circuit into a conductive state or a non-conductive state based on stored data even when the power supply voltage is cut off, and a variable impedance circuit using the same. And providing a resonant circuit.

  A semiconductor device according to the present invention has a floating gate and a control gate, and stores a memory transistor for storing data according to a threshold voltage level change, and a switch that is turned on or off in accordance with the stored data of the memory transistor And a circuit. The switch circuit includes a field effect transistor having a gate connected to a floating gate.

  Preferably, a plurality of sets of memory transistors and switch circuits are provided. The semiconductor device further includes a write circuit that selects any one of a plurality of memory transistors according to an external address signal and writes data to the memory transistor.

  Another semiconductor device according to the present invention includes a plurality of memory transistors each having a floating gate and a control gate for storing data according to a change in threshold voltage level, and stored data of the plurality of memory transistors. And a switch circuit that is turned on or off in response. The switch circuit includes a plurality of field effect transistors provided corresponding to the plurality of memory transistors and connected in series. The gate of each field effect transistor is connected to the floating gate of the corresponding memory transistor.

  Preferably, a plurality of sets of a plurality of memory transistors and switch circuits are provided. The semiconductor device further includes a writing circuit that selects one of a plurality of memory transistors in accordance with an external address signal and writes data to the memory transistor.

  A variable impedance circuit according to the present invention includes the semiconductor device and an impedance element provided corresponding to each set and connected in series with a corresponding switch circuit.

  A resonance circuit according to the present invention includes the variable impedance circuit and a coil. The variable impedance element is a capacitor, and each set of switch circuits is connected in series with a corresponding capacitor between the terminals of the coil.

  In the semiconductor device according to the present invention, a memory transistor having a floating gate and a control gate and storing data according to a threshold voltage level change, and a switch that is turned on or off according to the stored data of the memory transistor The switch circuit includes a field effect transistor having a gate connected to the floating gate. Therefore, even when the power supply voltage is cut off, the switch circuit can be turned on or off based on the data stored in the memory transistor.

  Further, in another semiconductor device according to the present invention, each of which has a floating gate and a control gate, stores a plurality of memory transistors according to a threshold voltage level change, and stores data in the plurality of memory transistors. And a switch circuit that is turned on or off in response to the switch circuit. The switch circuit is provided corresponding to each of the plurality of memory transistors, and includes a plurality of field effect transistors connected in series. The gate is connected to the floating gate of the corresponding memory transistor. Therefore, even when the power supply voltage is cut off, the switch circuit can be turned on or off based on data stored in the plurality of memory transistors. Further, since the field effect transistor becomes conductive when broken, the switch circuit can be turned on or off even when one of the plurality of transistors connected in series is broken.

  A variable impedance circuit according to the present invention includes the semiconductor device and an impedance element provided corresponding to each set and connected in series with a corresponding switch circuit. Therefore, even when the power supply voltage is cut off, the impedance of the variable impedance circuit can be set to the optimum value based on the data stored in the memory transistor.

  A resonance circuit according to the present invention includes the variable impedance circuit and a coil. The variable impedance element is a capacitor, and each set of switch circuits is connected in series with a corresponding capacitor between the terminals of the coil. Therefore, even when the power supply voltage is cut off, the resonance frequency of the resonance circuit can be set to the optimum value based on the data stored in the memory transistor.

1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a diagram showing a layout of a memory transistor MA1 and transistors QA1, QC1 shown in FIG. It is the III-III sectional view taken on the line of FIG. FIG. 2 is a circuit block diagram illustrating a method for using the semiconductor integrated circuit device shown in FIG. 1. It is a block diagram which shows the structure of the semiconductor integrated circuit device by Embodiment 2 of this invention. FIG. 6 shows a layout of memory transistors MA1, MB1 and transistors QA1-QD1 shown in FIG. FIG. 6 is a circuit block diagram illustrating a method of using the semiconductor integrated circuit device shown in FIG. 5.

[Embodiment 1]
As shown in FIG. 1, this semiconductor integrated circuit device includes a switch circuit unit 1, a memory unit 2, a peripheral circuit unit 3, n switching terminals TC1 to TCn, where n is an integer of 2 or more, A terminal T1, a data output terminal T2, a control terminal T3, a clock terminal T4, a data input terminal T5, a power supply terminal T6, and a ground terminal T7 are provided.

  Switch circuit portion 1 includes n N-channel MOS transistors QA1 to QAn. The drains of the transistors QA1 to QAn are connected to the switching terminals TC1 to TCn, respectively, and their sources are all connected to the common terminal T1. A reference voltage (for example, ground voltage GND) is applied to the common terminal T1.

  Memory unit 2 includes n memory transistors MA1 to MAn and n N channel MOS transistors QC1 to QCn. Each of the memory transistors MA1 to MAn has a floating gate and a control gate, and stores data by changing the threshold voltage level. When electrons are injected into the floating gate, the memory transistor MA has a relatively high level threshold voltage VTHH, and the memory transistor MA stores data “1”. When electrons are extracted from the floating gate, the memory transistor MA has a relatively low threshold voltage VTHL, and the memory transistor MA stores data “0”.

  The floating gates of memory transistors MA1 to MAn are connected to the gates of transistors QA1 to QAn, respectively. Therefore, when electrons are injected into the floating gates of the memory transistors MA1 to MAn and the floating gates of the memory transistors MA1 to MAn are set to the “L” level, the transistors QA1 to QAn are turned off, respectively. When electrons are extracted from the floating gates of the memory transistors MA1 to MAn and the floating gates of the memory transistors MA1 to MAn are set to the “H” level, the transistors QA1 to QAn are turned on, respectively. Since the potential level of the floating gates of the memory transistors MA1 to MAn, that is, the stored data is retained even when the power supply voltage VCC is cut off, each of the transistors QA1 to QAn is turned on or off even when the power supply voltage VCC is cut off. Can do.

  The control gates and sources of the memory transistors MA1 to MAn are connected to the peripheral circuit unit 3. The sources of the transistors QC1 to QCn are connected to the drains of the memory transistors MA1 to MAn, respectively, and their gates and drains are connected to the peripheral circuit unit 3. A unique address signal is assigned in advance to each of the memory transistors MA1 to MAn. Writing of data to each of memory transistors MA1 to MAn is performed by peripheral circuit unit 3.

  Peripheral circuit unit 3 includes a control circuit 4, a high voltage generation circuit 5, a decoder 6, and a readout circuit 7. The chip select signal CS is given to the control circuit 4 from the outside via the control terminal T3. The clock signal CLK is given from the outside to the control circuit 4 via the clock terminal T4. The serial data signal DI is given to the control circuit 4 from the outside through the data input terminal DI.

  In the write mode, serial data signal DI includes a write instruction signal for instructing data writing and an address signal indicating the address of memory transistor MA to which data is to be written. In the erasing mode, the serial data signal DI includes an erasing instruction signal for instructing erasing data and an address signal indicating the address of the memory transistor MA from which data is to be erased. In read mode, serial data signal DI includes a read instruction signal for instructing data reading and an address signal indicating the address of memory transistor MA from which data is to be read.

  The control circuit 4 is inactivated when the chip select signal CS is at “L” level, and is activated when the chip select signal CS is at “H” level. The activated control circuit 4 operates in synchronization with the clock signal CLK, and controls the high voltage generation circuit 5, the decoder 6 and the read circuit 7 in accordance with the serial data signal DI.

  The high voltage generation circuit 5 is driven by the power supply voltage VCC supplied from the outside via the power supply terminal T6 and the ground voltage GND supplied from the outside via the ground terminal T7, and is controlled by the control circuit 4. A high voltage (for example, 18V) for writing and erasing is generated.

  The decoder 6 receives the high voltage generated by the high voltage generation circuit 5 and is controlled by the control circuit 4. In the write mode, decoder 6 is an “H” level signal at the gate and drain of the transistor (in this case, QC1) corresponding to the memory transistor (eg, MA1) indicated by the address signal included in serial data signal DI. Then, the transistor QC1 is turned on by applying a signal of "L" level, 0V is applied to each of the source and drain of the memory transistor MA1, and a high voltage is applied to the control gate.

  As a result, electrons are injected into the floating gate of the memory transistor MA1, the threshold voltage of the memory transistor MA1 becomes high, and data “1” is stored in the memory transistor MA1. Further, since the floating gate of the memory transistor MA1 and the gate of the transistor QA1 are connected, the transistor QA1 is turned off.

  In the erase mode, decoder 6 applies a high voltage to each of the gate and drain of the transistor (in this case, QC1) corresponding to the memory transistor (eg, MA1) indicated by the address signal included in serial data signal DI. The transistor QC1 is turned on, the source of the memory transistor MA1 is opened (high impedance state), and 0 V is applied to the control gate.

  As a result, electrons are extracted from the floating gate of the memory transistor MA1, the threshold voltage of the memory transistor MA1 becomes low, and data “0” is stored in the memory transistor MA1. Further, since the floating gate of the memory transistor MA1 and the gate of the transistor QA1 are connected, the transistor QA1 is turned on. It is also possible to erase the data of all the memory transistors MA1 to MAn at a time.

  In the read mode, decoder 6 is set to “H” level at each of the gate and drain of a transistor (in this case, QC1) corresponding to a memory transistor (eg, MA1) indicated by an address signal included in serial data signal DI. The transistor QC1 is turned on, and a read voltage VR at an intermediate level between the low level threshold voltage VTHL and the high level threshold voltage VTHH is applied to the control gate of the memory transistor MA1.

  When memory transistor MA1 stores data “1” and threshold voltage VTHH of memory transistor MA1 is higher than read voltage VR, the current of memory transistor MA1 is smaller than a predetermined threshold current ITH. Conversely, when the memory transistor MA1 stores data “0” and the threshold voltage VTHL of the memory transistor MA1 is lower than the read voltage VR, the current of the memory transistor MA1 becomes larger than the threshold current ITH. .

  In other words, when the read voltage VR is applied to the control gate of the memory transistor MA1, when the current of the memory transistor MA1 is smaller than the threshold current ITH, the stored data of the memory transistor MA1 is “1”, and the memory transistor MA1 Is greater than the threshold current ITH, the data stored in the memory transistor MA1 is “0”.

  In the read mode, read circuit 7 compares a current flowing through memory transistor MA1 to which read voltage VR is applied to the control gate by decoder 6 with threshold current VTH, and outputs data signal DO at a logic level corresponding to the comparison result. Output to the outside via the data output terminal T2.

  2 is a diagram showing a layout of the transistors QA1 and QC1 and the memory transistor MA1 shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2 and 3, a belt-like gate region 10a extending in the X direction in FIG. 2 is provided on the surface of a P-type silicon substrate 10. In FIG. One end portion (left end portion in FIG. 2) of the gate region 10a is formed wider than the other portions. In the gate region 10a, a gate insulating film 11, a floating gate 12, a gate insulating film 13, and a control gate 14 are stacked on the surface of the P-type silicon substrate 10.

  Further, a strip-shaped gate region 10b extending in the X direction in FIG. 2 is provided in the vicinity of the other end (right end in FIG. 2) of the gate region 10a. The gate regions 10a and 10b are arranged in parallel with a predetermined gap. In the gate region 10 b, the gate insulating film 15 and the gate 16 are stacked on the surface of the P-type silicon substrate 10.

  An N-type impurity diffusion region 10c is formed on the surface of the P-type substrate 10 so as to cross the gate regions 10a and 10b. The portions on both sides of the gate region 10a in the N-type impurity diffusion region 10c serve as the source and drain of the memory transistor MA1. The portions on both sides of the gate region 10b in the N-type impurity diffusion region 10c serve as the source and drain of the transistor QC1. A portion of the N-type impurity diffusion region 10c between the gate regions 10a and 10b serves as the drain of the memory transistor MA1 and the source of the transistor QC1.

  Further, an N-type impurity diffusion region 10d is formed on the surface of the P-type substrate 10 so as to cross a wide portion at one end of the gate region 10a. One part of the gate region 10a in the N-type impurity diffusion region 10d serves as the source of the transistor QA1, and the other part serves as the drain.

  That is, in this semiconductor integrated circuit device, the gate region 10a is provided in common to the memory transistor MA1 and the transistor QA1, and the floating gate of the memory transistor MA1 is the gate of the transistor QA1. Therefore, the transistor QA1 is turned off when electrons are injected into the floating gate of the memory transistor MA1 even when the power supply voltage VCC is cut off, and when the electrons are extracted from the floating gate of the memory transistor MA1. Turn on.

  Note that since the gate insulating film 13 and the control gate 14 are unnecessary in the transistor QA1, the gate insulating film 13 and the control gate 14 may be provided only in the memory transistor MA1. However, if the gate insulating film 13 and the control gate 14 are provided only in the memory transistor MA1, it is possible to simplify the manufacturing process if they are provided in both the transistor QA1 and the memory transistor MA1. Other memory transistors MA2 to MAn and transistors QA2 to QAn and QC2 to QCn are arranged in the same manner as memory transistor MA1 and transistors QA1 and QC1.

  FIG. 4 is a circuit block diagram illustrating a method of using the semiconductor integrated circuit device illustrated in FIGS. 1 to 3 and is a circuit block diagram illustrating a main part of the non-contact power receiving device. In FIG. 4, the terminals TC1 to TCn and T1 to T7 are not shown for simplification of the drawing.

  In FIG. 4, the non-contact type power receiving device includes an antenna coil 20, capacitors C <b> 1 to Cn, and a rectifier circuit 21 in addition to the semiconductor integrated circuit device. One electrodes of the capacitors C <b> 1 to Cn are commonly connected to one terminal 20 a of the antenna coil 20. The other electrodes of capacitors C1 to Cn are connected to the drains of transistors QA1 to QAn, respectively. The sources of the transistors QA1 to QAn are commonly connected to the other terminal 20b of the antenna coil 20. The capacitors C1 to Cn and the semiconductor integrated circuit device constitute a variable capacitance circuit. The variable capacitance circuit and the antenna coil 20 constitute a resonance circuit. The rectifier circuit 21 converts the high frequency power received by the antenna coil 20 into DC power PDC and supplies it to the load.

  At the time of shipment, whether the capacitance value of the variable capacitance circuit is adjusted so that the resonance frequency of the resonance circuit including the antenna coil 20 and the variable capacitance circuit matches the frequency of the high frequency power, and each of the transistors QA1 to QAn is turned on or off. Is written to the memory transistors MA1 to MAn. Even if the power supply voltage is cut off, the stored data of the memory transistors MA1 to MAn is retained, and each of the transistors QA1 to QAn is turned on or off according to the stored data of the memory transistors MA1 to MAn, so that the capacitance value of the variable capacitance circuit is The optimum value is maintained. Therefore, the high frequency power radiated from the outside toward the antenna coil 20 is always received by the antenna coil 20 with high efficiency.

[Embodiment 2]
FIG. 5 is a circuit block diagram showing a configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention, which is compared with FIG. 5, this semiconductor integrated circuit device is different from the semiconductor integrated circuit device of FIG. 1 in that N-channel MOS transistors QB1 to QB are added to the switch circuit portion 1, and memory transistors MB1 to MBn and N-channel are added to the memory portion 2. MOS transistors QD1 to QDn are added.

  The drains of the transistors QB1 to QBn are connected to the sources of the transistors QA1 to QAn, respectively, and the sources of the transistors QB1 to QBn are all connected to the common terminal T1. The memory transistor MB is the same as the memory transistor MA. The floating gates of memory transistors MB1 to MBn are connected to the gates of transistors QB1 to QBn, respectively. Therefore, transistors QB1-QBn are turned on or off according to the stored data of memory transistors MB1-MBn, respectively.

  The control gates and sources of the memory transistors MB1 to MBn are connected to the peripheral circuit unit 3. The sources of the transistors QD1 to QDn are connected to the drains of the memory transistors MB1 to MBn, respectively, and their gates and drains are connected to the peripheral circuit unit 3. A unique address signal is assigned in advance to each of the memory transistors MA1 to MAn and MB1 to MBn. Writing of data to each of the memory transistors MA1 to MAn and MB1 to MBn is performed by the peripheral circuit unit 3. The same logic data is written in the memory transistors MA1 and MB1, MA2 and MB2,..., MAn and MBn, respectively. Since the configuration and operation of peripheral circuit unit 3 are the same as those in the first embodiment, description thereof will not be repeated.

  Each of transistors QA1 to QAn and QB1 to QBn becomes conductive when broken. In the second embodiment, since the two transistors QA and QB are connected in series between the switching terminal TC and the common terminal T1, even when any one of the two transistors QA and QB is broken, Transistors QA and QB can be used as switches.

  FIG. 6 is a diagram showing a layout of transistors QA1, QB1, QC1, QD1 and memory transistors MA1, MB1 shown in FIG. 5, and is compared with FIG. In FIG. 6, gate regions 10e and 10f and N-type impurity diffusion regions 10h and 10g are provided in line symmetry with gate regions 10a and 10b and N-type impurity diffusion regions 10c and 10d around a one-dot chain line L in FIG. .

  In the gate region 10e, the gate insulating film 11, the floating gate 12, the gate insulating film 13, and the control gate 14 are stacked on the surface of the P-type silicon substrate 10 as in the gate region 10a. In the gate region 10f, the gate insulating film 15 and the gate 16 are stacked on the surface of the P-type silicon substrate 10 as in the gate region 10b.

  An N-type impurity diffusion region 10g is formed on the surface of the P-type substrate 10 so as to cross the gate regions 10e and 10f. The portions on both sides of the gate region 10e in the N-type impurity diffusion region 10g serve as the source and drain of the memory transistor MB1. The portions on both sides of the gate region 10b in the N-type impurity diffusion region 10g serve as the source and drain of the transistor QD1. A portion of the N-type impurity diffusion region 10g between the gate regions 10e and 10f serves as the drain of the memory transistor MB1 and the source of the transistor QD1.

  Further, an N-type impurity diffusion region 10 h is formed on the surface of the P-type substrate 10 so as to cross the wide portion at one end of the gate region 10 e. One part of the gate region 10e in the N-type impurity diffusion region 10h serves as the source of the transistor QB1, and the other part serves as the drain.

  That is, in this semiconductor integrated circuit device, the gate region 10e is provided in common to the memory transistor MB1 and the transistor QB1, and the floating gate of the memory transistor MB1 is the gate of the transistor QB1. Therefore, the transistor QB1 is turned off when electrons are injected into the floating gate of the memory transistor MB1 even when the power supply voltage VCC is cut off, and when the electrons are extracted from the floating gate of the memory transistor MB1. Turn on.

  Note that since the gate insulating film 13 and the control gate 14 are unnecessary in the transistor QB1, the gate insulating film 13 and the control gate 14 may be provided only in the memory transistor MB1. However, if the gate insulating film 13 and the control gate 14 are provided only in the memory transistor MA1, it is possible to simplify the manufacturing process if they are provided in both the transistor QB1 and the memory transistor MB1. Other memory transistors MA2-MAn, MB2-MBn and transistors QA2-QAn, QB2-QBn, QC2-QCn, QD2-QDn are also arranged similarly to memory transistors MA1, MB1 and transistors QA1, QB1, QC1, QD1. .

  FIG. 7 is a circuit block diagram illustrating a method of using the semiconductor integrated circuit device illustrated in FIGS. 5 and 6 and is a circuit block diagram illustrating a main part of the non-contact power receiving device. In FIG. 7, the terminals TC <b> 1 to TCn and T <b> 1 to T <b> 7 are not shown for simplification of the drawing.

  In FIG. 7, the non-contact power receiving device includes an antenna coil 20, capacitors C <b> 1 to Cn, and a rectifier circuit 21 in addition to the semiconductor integrated circuit device. One electrodes of the capacitors C <b> 1 to Cn are commonly connected to one terminal 20 a of the antenna coil 20. The other electrodes of capacitors C1 to Cn are connected to the drains of transistors QA1 to QAn, respectively. The sources of the transistors QA1 to QAn are connected to the drains of the transistors QB1 to QBn, respectively. The sources of the transistors QB1 to QBn are commonly connected to the other terminal 20b of the antenna coil 20. The capacitors C1 to Cn and the semiconductor integrated circuit device constitute a variable capacitance circuit. The variable capacitance circuit and the antenna coil 20 constitute a resonance circuit. The rectifier circuit 21 converts the high frequency power received by the antenna coil 20 into DC power PDC and supplies it to the load.

  At the time of shipment, the capacitance value of the variable capacitance circuit is adjusted so that the resonance frequency of the resonance circuit including the antenna coil 20 and the variable capacitance circuit matches the frequency of the high frequency power, and each of the transistors QA1 to QAn and QB1 to QBn is turned on. Information indicating whether to turn off is written in the memory transistors MA1 to MAn and MB1 to MBn. Even if the power supply voltage is cut off, the stored data of the memory transistors MA1 to MAn and MB1 to MBn are retained, and each of the transistors QA1 to QAn and QB1 to QBn is retained according to the stored data of the memory transistors MA1 to MAn and MB1 to MBn. On or off, the capacitance value of the variable capacitance circuit is maintained at the optimum value. Therefore, the high frequency power radiated from the outside toward the antenna coil 20 is always received by the antenna coil 20 with high efficiency.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Switch circuit part, 2 Memory part, 3 Peripheral circuit part, 4 Control circuit, 5 High voltage generation circuit, 6 Decoder, 7 Read circuit, T terminal, QA-QD N channel MOS transistor, MA, MB Memory transistor, 10P Type silicon substrate, 10a, 10b, 10e, 10f gate region, 10c, 10d, 10g, 10h N-type impurity diffusion region, 11, 12, 15 gate insulating film, 12 floating gate, 14 control gate, 16 gate, 20 antenna coil , 21 Rectifier circuit.

Claims (6)

A memory transistor having a floating gate and a control gate, and storing data according to a threshold voltage level change;
A switch circuit that is turned on or off in accordance with stored data of the memory transistor,
The switch circuit includes a field effect transistor having a gate connected to the floating gate. A plurality of sets of the memory transistor and the switch circuit are provided,
2. The semiconductor device according to claim 1, further comprising a write circuit that selects any one of the plurality of memory transistors in accordance with an external address signal and writes data to the memory transistor. A plurality of memory transistors, each having a floating gate and a control gate, for storing data according to a threshold voltage level change;
A switch circuit that is turned on or off in accordance with stored data of the plurality of memory transistors,
The switch circuit includes a plurality of field effect transistors provided corresponding to the plurality of memory transistors and connected in series,
A semiconductor device, wherein a gate of each field effect transistor is connected to a floating gate of a corresponding memory transistor. A plurality of sets of the plurality of memory transistors and the switch circuit are provided,
4. The semiconductor device according to claim 3, further comprising a write circuit that selects any one of the plurality of memory transistors in the plurality of sets according to an external address signal and writes data to the memory transistor. A semiconductor device according to claim 2 or claim 4,
A variable impedance circuit comprising an impedance element provided corresponding to each set and connected in series with a corresponding switch circuit. The variable impedance circuit according to claim 5;
A coil,
The variable impedance element is a capacitor;
Each set of switch circuits is a resonant circuit connected in series with a corresponding capacitor between the terminals of the coil.

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