JP2005184671A - Voltage level shifter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage level shifter circuit for boosting a low-voltage level signal to a high-voltage level signal at high speed. <P>SOLUTION: FETs Q11, Q7 with each gate connected in common and each drain connected to a signal feeding terminal of a high voltage level VPP, and two or more FETs Q10, Q9 connected in series between the common gate and the source of the FET Q11 and having each drain and each gate connected in common are provided. The voltage level shifter circuit 1 includes a charge pump circuit 5, in which a clock signal with a voltage lower than the voltage level VPP is applied to the odd-numbered FET Q10, out of two or more transistors Q10, Q9, from a view of the source side of FET Q11, and a reverse signal to the clock signal is applied to the even-numbered FET Q9 from a view of source side of the FET Q11. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a voltage level shifter circuit for switching (shifting) a low voltage level signal to a high voltage level signal that can be rewritten and erased, for example, in an EEPROM (Electric Erasable Programmable ROM).

  For example, an EEPROM in a semiconductor memory requires a high voltage level signal of, for example, 10 V or more in order to electrically rewrite / erase data.

  In this regard, conventionally, a configuration in which a high voltage level signal is supplied from the outside of an IC chip on which an EEPROM is mounted has been used. However, in recent years, a high voltage level signal is supplied by a booster circuit provided inside the EEPROM chip. By supplying, a voltage level shifter circuit operating by a single power source has become mainstream.

  In this chip-embedded voltage level shifter circuit, it is very important to prevent the occurrence of a through current in order to prevent malfunction.

  In particular, recently, there are an increasing number of applications installed in portable devices that operate with a low voltage level signal of one or two dry cells, and a voltage that can boost a low voltage level signal to a high voltage level at which data can be rewritten and erased. There is a need for a level shifter circuit.

  Furthermore, it is a well-known fact that in all devices including portable devices, there is an increasing demand for high-speed data rewriting / erasing, and high-speed operation is also required for voltage level shifter circuits.

In this regard, as an example of a conventional voltage level shifter circuit, there is a voltage conversion circuit disclosed in Patent Document 1.
Japanese Patent Laid-Open No. 1-91656

  The voltage conversion circuit disclosed in the above-mentioned patent publication surely converts a low voltage level signal into a high voltage level signal while preventing a through current.

  However, in the voltage conversion circuit, as shown in FIG. 1, the low voltage level signal (amplitude φ1) applied according to the clock cycle is boosted by the amplitude every clock cycle. The speed was slow and the high speed operation required for the voltage level shifter circuit could not be satisfied.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a voltage level shifter circuit capable of boosting a low voltage level signal to a high voltage level signal at high speed.

  In order to solve the above-mentioned problem, the invention according to claim 1 includes first and second transistors having gates connected in common and drains connected to a signal supply terminal having a first voltage level, and the common gate and An odd-numbered transistor as viewed from the source side of the first transistor in the plurality of transistors, including a plurality of transistors connected in series between the sources of the first transistors and having their drains and gates commonly connected Is applied with a second voltage level signal lower than the first voltage, and the second voltage level signal of the even-numbered transistor as viewed from the source side of the first transistor. A charge pump circuit to which an inverted signal is applied, and a transistor connected between the common gate and the source of the second transistor. The present invention includes a spher gate circuit and an output node connected to an output terminal on the source side of the second transistor of the transfer gate circuit for outputting the signal of the first voltage level. .

  In order to solve the above-mentioned problem, the charge pump circuit is connected to the gate and drain of the even-numbered transistors that are commonly connected in a plurality of transistors, and the second voltage level signal is output from the charge pump circuit. The gist of the present invention is to provide an inverting circuit that is inverted and applied to the gate and drain.

  According to the first and second aspects of the present invention, the second voltage lower than the first voltage with respect to the odd-numbered transistors as viewed from the source side of the first transistors in the plurality of transistors in the charge pump circuit. Since the level signal is applied and the inverted signal of the second voltage level signal is applied to the even-numbered transistors as viewed from the source side of the first transistor, the second voltage level signal is the charge pump. From a plurality of transistors in the circuit, voltage is boosted (level shift) by the amount corresponding to the connection of the transistors, that is, output as a voltage signal at a high voltage level.

  Since the voltage signal of the high voltage level is applied to the gates of the first and second transistors, the first voltage level signal applied to the signal supply terminal when the first and second transistors are turned on becomes the transfer gate. It is supplied to the output node via a circuit.

  That is, according to the present invention, the voltage level applied to the gates of the first and second transistors can be increased by the number of connected transistors, and therefore a voltage signal having a low voltage level can be used as the second voltage signal. Even when used, the voltage level applied to the gates of the first and second transistors can be increased at high speed.

  As a result, it is possible to improve the supply speed of the first voltage level signal to the output node, and it is possible to provide a voltage level shifter circuit whose operation speed is improved as a whole.

  A voltage level shifter circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a voltage level shifter circuit 1 according to the present embodiment.

  As shown in FIG. 1, the voltage level shifter circuit 1 converts a voltage level of a high voltage level output terminal T4 connected to, for example, an EEPROM word line or bit line to a low voltage level (for example, a power supply voltage VDD level). This is a circuit that boosts (shifts) to a high voltage level (VPP: for example, 10 V or more) necessary for data erasing / rewriting of the EEPROM by a signal of about 5 V).

  That is, the voltage level shifter circuit 1 has a node N1 to which the high voltage level output terminal T4 is connected, and has a capacitor C3 connected to the node N1, and the capacitor C3 indicates its load capacity.

  The voltage level shifter circuit 1 includes an N channel field effect transistor (FET) Q6 having a drain connected to the node N1, a source connected to the logic input terminal T5, and a gate applied with the power supply voltage VDD. And an N-channel FET Q8 constituting a transfer gate circuit having a source connected to the node N1 and a gate to which a power supply voltage VDD is applied.

  Further, the voltage level shifter circuit 1 includes N-channel FETs Q7 (corresponding to the second transistor) and Q11 (corresponding to the first transistor) whose drains are commonly connected to the VPP terminal to which the high voltage level (VPP) signal is applied. Correspondence). The gates of the N-channel FETs Q7 and Q11 are connected in common through the node N2, and are connected to the drain of the N-channel FET Q8 through the node N2 and the node N3. The source of the N-channel FET Q7 is connected to the source of the N-channel FET Q8. It is connected.

  The voltage level shifter circuit 1 is connected between the gate and source of the N-channel FET Q11, and includes a charge pump circuit 5 for boosting the voltage level of the node N1 through the N-channel FET Q8.

  As shown in FIG. 1, the charge pump circuit 5 has an input terminal T6 to which a clock signal that is a low voltage level signal (for example, about 2.5 V that is a power supply voltage VDD level) is input via a node N4. A first input line L1 and a second input line L2 connected in parallel, capacitors C4 and C5 inserted in the middle of the first and second input lines L1 and L2, respectively, and a second input line L2 And an inverter U1 inserted between the node N4 and the capacitor C5.

  Further, the charge pump circuit 5 includes an N-channel FET Q10 having a drain and a gate commonly connected to the first input line L1, and an N-channel FET Q10 having a drain and a gate commonly connected to the second input line L2. The channel FET Q9 is provided, the source of the N channel FET Q10 is connected to the drain of the N channel FET Q9, and a charge pump circuit having two stages of FETs Q10 and Q9 connected in series is configured.

  The drain of the N channel FET Q10 is connected to the source of the N channel FET Q11 via the node N5, and the source of the N channel FET Q9 is connected to the common gate of the N channel transistors Q7 and Q11 via the node N2.

  Next, the overall operation of this embodiment will be described.

  When a high level signal is applied to the logic input terminal T5, the voltage level of the node N1 (and the output terminal T4) rises through the FET Q6 whose voltage VDD is applied to the gate, and the voltage of the node N1 As the level rises, the gate voltages of the FETs Q7 and Q11 are raised through the FET Q8 having the voltage VDD applied to the gate. Due to this rise in the gate voltage, the FET Q11 is not completely turned on, and the gate voltage of the FET Q10 in the charge pump circuit 5 is raised.

  When a low level (0 [V]) clock signal is input from the input terminal T6 in the charge pump circuit 5 in a state where the gate voltage of the FET Q10 is increased, the capacitor C4 in the first input line L1 is connected to the capacitor C4 via the FET Q11. Charge is accumulated. Subsequently, when a clock signal having an amplitude of VDD, which is the power supply voltage level, is input to the input terminal T6, the voltage at the node N4 becomes VDD, and the charge accumulated in the capacitor C4 is connected to the diode with the drain connected to the gate. It moves to the capacitor C5 in the second input line L2 via the FET Q10 of the type. Note that the potential of the node N6 on the second input line L2 at this time is at a low level (0 [V]) because it passes through the inverter U1 from the input terminal T6. Subsequently, when a low level (0 [V]) clock signal is input to the input terminal T6, charge is accumulated in the capacitor C4 via the FET Q11, and the node N6 from the input terminal T6 via the inverter U1. Becomes a high level, and the charge accumulated in the capacitor C5 charges the gate capacitances of the FETs Q7 and Q11 through the diode-connected FET Q9 having the drain connected to the gate, and pushes up the potential of the node N2. Thereafter, the same operation is repeated according to the clock of the input terminal T6, and the potential of the node N2 rises rapidly. As the potential at the node N2 rises, the FETs Q7 and Q11 also gradually turn on, and the potential rise at the node N1 and the charge accumulated in the capacitor C4 when a low level clock signal is input from the input terminal T6 increases. When the potential of the node N2 exceeds the threshold value of the FET Q7, the FET Q7 is completely turned on, and the high voltage Vpp is output to the output terminal T4.

  At this time, since a high level voltage signal is applied to the drain of the FET Q6, the FET Q6 maintains the OFF state, and the logic input terminal T5 can be protected from the high voltage.

  Subsequently, when a low level signal is applied to the logic input terminal T5, the FET Q6 and FET Q8 having the voltage VDD applied to their gates are turned ON, respectively. As a result, the voltage level of the node N1, and the FETs Q7 and Q11 are turned on. The gate voltage decreases.

  As described above, according to this configuration, since the charge pump 5 having a two-stage boosting function is used as the boosting means for the node N1, the low-voltage level clock signal is used even though it is used. Based on the two-stage boosting function of the charge pump 5, the voltage level of the high voltage level output terminal T4 can be rapidly boosted to a high voltage level (VPP) necessary for data erasing / rewriting of the EEPROM.

  Here, in order to confirm the high-speed operation of the voltage level shifter circuit 1 according to this embodiment, the charge pump circuit in the voltage level shifter circuit of the present invention is replaced with the charge pump circuit 5a disclosed in the conventional Japanese Patent Laid-Open No. 1-91656. FIG. 2 shows the voltage level shifter circuit 1a when replaced. In FIG. 2, the symbol “a” is added to the components corresponding to the voltage level shifter circuit 1 shown in FIG. 1, and the charge pump circuit 5a in the voltage level shifter circuit 1a shown in FIG. An N-channel FET Q20 having a source connected to the drain, a drain connected to the source of the FET Q11a, and a gate connected to the input terminal T6a via a capacitor C10 is provided.

  The time until the FETs Q7 and Q7a are turned on between the voltage level shifter circuit 1 and the voltage level shifter circuit 1a according to this embodiment, that is, the time until the gate voltage VG of the FETs Q7 and Q7a exceeds the threshold voltage Vth is shown in FIG. Shown in

  Since the charge pump circuit 5a in the voltage level shifter circuit 1a performs a boosting action by one FET Q20, the voltage level of the node N3a is higher than that of the voltage level shifter circuit 1 every cycle of the clock signal (high level / low level switching). Will be low.

  Therefore, as shown in FIG. 3, the time until the FET Q7 is turned on by the voltage level shifter circuit 1 of this embodiment (the time until the gate voltage VG exceeds the threshold voltage Vth) t1 is the time when the FET Q7a by the voltage level shifter circuit 1a is ON. It can be seen that the time is significantly faster than the time t1a (time until the gate voltage VG exceeds the threshold voltage Vth).

  That is, according to the present embodiment, even when a low voltage level signal of the power supply voltage VDD level (about 2.5 V) is used, the voltage level of the output terminal for data rewriting / erasing of the EEPROM is prevented, and a through current is prevented. The pressure can be increased at high speed.

  In the present embodiment, the two FETs Q9 and Q10 are connected in series and the two-stage charge pump circuit is used. However, the present invention is not limited to this configuration, and three or more It is also possible to use a multiple-stage charge pump circuit in which the FETs are connected in series. In this case, the clock signal from the input terminal T6 may be inverted and input to the even-numbered FET when the FET connected to the input terminal T6 via the capacitor is the first and first FET.

  In this embodiment, an N-channel FET is used as the FET. However, the present invention is not limited to this configuration, and a P-channel FET can also be used. In this case, the booster circuit boosts the node N1 in the negative direction.

  The present invention is not limited to the above-described embodiments and modifications, and various modifications can be made to the above-described embodiments and modifications within the scope belonging to the present invention.

1 is a block diagram showing a schematic configuration of a voltage level shifter circuit according to an embodiment of the present invention. The block diagram which shows schematic structure of the voltage level shifter circuit which is a comparative example of the voltage level shifter circuit concerning this Embodiment. 3 is a graph showing time until FETs Q7 and Q7a are turned on in the voltage level shifter circuit shown in FIG. 1 and the voltage level shifter circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Voltage level shifter circuit 5 ... Charge pump circuit T4 ... High voltage level output terminal T5 ... Logic input terminal C3-C5 ... Capacitor Q6-Q11 ... N channel FET
U1 ... Inverter N1-N6 ... Node

Claims (2)

First and second transistors having gates connected in common and drains connected to a signal supply terminal of a first voltage level;
A plurality of transistors connected in series between the sources of the common gate and the first transistor and having their drains and gates connected in common, and viewed from the source side of the first transistor in the plurality of transistors; A signal having a second voltage level lower than the first voltage is applied to the odd-numbered transistor, and the second transistor is applied to the even-numbered transistor as viewed from the source side of the first transistor. A charge pump circuit to which an inverted signal of the voltage level signal is applied;
A transfer gate circuit connected between the common gate and the source of the second transistor;
An output node connected to the source-side output terminal of the second transistor of the transfer gate circuit for outputting the signal of the first voltage level;
A voltage level shifter circuit comprising: The charge pump circuit includes an inverting circuit that is connected to a commonly connected gate and drain of the even-numbered transistors in a plurality of transistors, and inverts the second voltage level signal and applies the inverted signal to the gate and drain. 2. The voltage level shifter circuit according to claim 1, wherein:

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