JP2011017822A - Liquid crystal display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display panel configured to suppress poor coverage by means of an organic resin film for covering the surface of a connection electrode composed of a transparent conductive member, in a bridge connection portion between a first routed wiring and a second routed wiring, thereby suppress corrosion of the connection electrode.SOLUTION: The liquid crystal display panel includes: the first routed wiring 16a covered with a gate insulating film 17, a passivation film 20 and a flattening film OVL; and the second routed wiring 16b formed on the surface of the gate insulating film 17 and covered with the passivation film 20 and the flattening film OVL; wherein, in performing a bridge connection by the connection electrode 23 covering a first contact hole 21 which exposes the surface of the first routed wiring 16a and a second contact hole 22 which exposes the surface of the second routed wiring 16b, the flattening film is removed from the bridge connection portion A in a wiring switching region, and the surface of the connection electrode 23 is covered with an alignment film 24.

Description

In the present invention, scanning lines and signal lines, and lead lines such as first lead lines and second lead lines are formed in the peripheral area of the display area, and a planarizing film is formed in the display area and the lead line forming area. Relates to a liquid crystal display panel. More specifically, in the present invention, the routing wiring is bridge-connected by the connection electrode in a state where the planarizing film is partially removed in a predetermined wiring switching region, and further, the connection electrode is an organic film having a substantially uniform film thickness. The present invention relates to a liquid crystal display panel coated with a resin film.

Liquid crystal display panels are characterized by their light weight, thinness, and low power consumption compared to CRTs (cathode ray tubes), and are therefore used in many electronic devices for display purposes. As a method of applying an electric field to a liquid crystal layer of a liquid crystal display panel, there are a vertical electric field type and a horizontal electric field type. In a vertical electric field type liquid crystal display panel, electrodes are provided on a pair of transparent substrates arranged with a liquid crystal layer interposed therebetween, and an electric field in a substantially vertical direction is applied to liquid crystal molecules by the pair of electrodes. This vertical electric field type liquid crystal display panel includes TN (Twisted Nematic) mode, VA (Vertica
l Alignment) mode, MVA (Multi-domain Vertical Alignment) mode, etc. are known.

In addition, a horizontal electric field type liquid crystal display panel is provided with a pair of electrodes insulated only on one inner surface side of a pair of substrates arranged with a liquid crystal layer sandwiched therebetween, and an electric field in a horizontal direction is generally used as liquid crystal molecules. In contrast, it is applied. This horizontal electric field type liquid crystal display panel includes an IPS (In-Plane Switching) mode in which a pair of electrodes do not overlap in a plan view, and an FFS (Fringe Field S) overlapping.
witching) mode is known.

As described above, a plurality of types of liquid crystal display panels are known. Each of these liquid crystal display panels includes a pixel electrode and a common electrode that form an electric field for changing the orientation of liquid crystal molecules, a scanning line for changing the voltage of the pixel electrode for each pixel arranged in a matrix, and Signal lines are formed in the display area of the array substrate.

Electrode terminals for electrical connection with the driver IC are formed in the non-display area of the array substrate, and the scanning lines and signal lines are made of the same material as the scanning lines, and wiring lines and signals are formed on these electrode terminals. The wiring is electrically connected via a routing wire composed of a signal wire routing wire made of the same material as the wire. These lead-out lines are formed in the peripheral area of the display area. However, since the number of lead-out lines for the scanning lines and signal lines is very large, a wide peripheral area is required. In particular, when the driver IC is arranged in the extending direction of the signal line, in order to make the display area arranged in the center without being biased to either the left or right of the liquid crystal display panel, Since it is necessary to route the scanning lines for the scanning lines from both the left and right sides of the display area in the signal line extending direction, a wider peripheral area is required.

In order to reduce the area required for such a peripheral region, Patent Document 1 below discloses a liquid crystal display panel in which the lead wiring has a multilayer structure. Here, the configuration of the lead wiring of the liquid crystal display panel disclosed in Patent Document 1 below will be described with reference to FIGS. 5A is a partially enlarged plan view showing the arrangement of the routing wirings on the left side of the peripheral region of the liquid crystal display panel of the conventional example, and FIG. 5B is a sectional view taken along the line IVB-IVB in FIG. 4A. 6A is a plan view of a wiring switching region of a conventional liquid crystal display panel, and FIG. 6B is a cross-sectional view taken along line VB-VB in FIG. 5A.

In order to facilitate understanding, in FIG. 5A, a conductive member formed of the same material as the scanning line is indicated by a dotted line, and a conductive member formed of the same material as the signal line is indicated by a solid line.

In the liquid crystal display panel 50 disclosed in Patent Document 1 below, the array substrate AR includes a display area in which scanning lines 12 and signal lines 13 are arranged in a matrix on the surface of a transparent glass substrate 11, and a display area. It is divided into left and right sides (only the left side is shown in FIG. 5A) and a peripheral region located on the lower side. A scanning line electrode terminal 14 and a signal line electrode terminal 15 for connection to a driver IC (not shown) or an external circuit are provided in the peripheral region in the extending direction of the signal line 13. The region further includes a scanning line 12 and a scanning line electrode terminal 14.
A lead wiring 16 for connecting the two is formed.

The lead wiring 16 includes a first lead wiring 16 a made of the same material as the scanning line 12 and a second lead wiring 16 b made of the same material as the signal line 13. As shown in FIG. 5B, the first routing wiring 16a and the second routing wiring 16b have a two-layer structure with a first insulating film (generally referred to as a gate insulating film) 17 interposed therebetween. In general, they are alternately arranged adjacent to each other without overlapping each other in plan view. In this type of liquid crystal display panel 50, when a flattening film made of a transparent resin material is formed in the display area, as shown in FIG. 5B, the flattening film OVL is also formed in the lead wiring formation area. Is formed.

A part of the first routing wiring 16 a disposed below the first insulating film 17 has one end directly connected to the end of the scanning line 12 and the other end formed below the first insulating film 17. The scanning line electrode terminal 14 is directly connected. Further, the second routing wiring 16b formed on the upper side of the first insulating film 17 is electrically connected to the scanning line 12 in the first wiring switching region 18, and is again connected to the first routing wiring 16a in the second wiring switching region 19. To be electrically connected to the scanning line electrode terminal 14. Further, the signal line 13 is electrically connected to the signal line electrode terminal 15 by being directly switched by the signal line routing wiring 16c or appropriately switched to another routing wiring (not shown) made of the same material as the scanning line. Yes.

6A and 6B are diagrams showing wiring switching regions of a VA mode liquid crystal display panel as an example. As shown in FIG. 6A, in the first wiring switching region 18 (see FIG. 5A), the first routing wiring 16a and the second routing wiring 16b are arranged adjacent to each other with a certain distance L therebetween. ing.

Then, as shown in FIG. 6B, a first insulating film 17 covering the surface of the first routing wiring 16a, and a second insulating film (generally referred to as a passivation film) 20 covering the surface of the first insulating film 17. In the planarizing film OVL made of a transparent resin film covering the surface of the second insulating film 20, a first contact hole 21 that exposes a part of the surface of the first routing wiring 16a is formed. The planarization film OVL is formed so as to cover the entire so-called array substrate AR in order to planarize the surface of the pixel electrode and the like formed on the surface of the planarization film OVL in the display region. This example shows a VA mode liquid crystal display panel. If the FFS mode horizontal electric field type liquid crystal display panel has a pixel electrode and a common electrode formed on the array substrate AR, a flattening film may be used. The surface of the OVL is further covered with a third insulating film (generally called an interelectrode insulating film).

On the other hand, as shown in FIG. 6B, the second contact hole 22 that exposes a part of the surface of the second routing wiring 16b is exposed to the second insulating film 20 and the planarization film OVL covering the surface of the second routing wiring 16b. Is formed. Then, a connection electrode 23 made of a transparent conductive material, for example, the same material as the pixel electrode is formed on the surface of the planarizing film OVL so as to cover the first contact hole 21 and the second contact hole 22. By this connection electrode 23, the first routing wiring 16a and the second routing wiring 16b are bridge-connected.

In the case where the liquid crystal display panel operates in the FFS mode, the planarizing film OVL
Further, there is a third insulating film between the connection electrode 23 and the connection electrode 23, and the connection electrode 23 is formed on the surface of the third insulation film. Also in this case, the second wiring switching region 19 (FIG. 5A)
The configuration of (see) is substantially the same as the configuration of the first wiring switching region 18 and is not shown.

According to the liquid crystal display panel 50 disclosed in the following Patent Document 1, since the routing wiring 16 including the first routing wiring 16a and the second routing wiring 16b has a two-layer structure, the pitch between the routing wirings is reduced. The area occupied by the peripheral region can be reduced.

JP 2005-91962 A

In the wiring switching region of such a liquid crystal display panel, the surface of the connection electrode 23 is
Further, an organic resin film 24 such as an alignment film is formed. The organic resin film 24 is formed by being applied to the surface of the connection electrode 23 almost uniformly by a roller or the like in an uncured state and then solidifying.

However, the planarization film OVL existing between the first contact hole 21 and the second contact hole 22 is formed through the exposure / development process.
In addition, since it is exposed to the etching medium for forming the second contact hole 22, it is formed in a raised shape as shown in FIG. 6B. For this reason, when the organic resin film forming material is applied to the surface of the connection electrode 23, the organic resin film forming material immediately after the application is applied to the first contact from the vicinity of the top of the flattening film OVL in this raised portion (region A). Since it flows into the hole 21 and the second contact hole 22 side, there is a problem in this region A that it is difficult to ensure sufficient coverage of the connection electrode 23.

In such a region A, the organic resin film laminated on the connection electrode 23 does not have a uniform film thickness, and a coverage defect phenomenon occurs and the surface of the connection electrode 23 is exposed.
3 is likely to corrode, and as a result, good electrical connection between the first routing wiring 16a and the second routing wiring 16b may be hindered. Furthermore, since the number of lead-out wirings increases with the increase in the number of pixels accompanying the increase in definition of the liquid crystal display panel, leaving such a problem as a major factor in image quality degradation.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a first lead wire and a second lead wire in a liquid crystal display panel in which a planarizing film is formed in the display region and the lead wire formation region. Even when the connection between the wiring and the contact via the contact hole made of a transparent conductive material is performed using a contact electrode made of a transparent conductive material, the coverage failure of the connection electrode due to the organic resin film is suppressed. Another object of the present invention is to provide a liquid crystal display panel that can provide stable display image quality.

In order to solve the above problem, a liquid crystal display panel of the present invention includes a first transparent substrate and a second transparent substrate that are disposed to face each other with a liquid crystal layer interposed therebetween, and the liquid crystal layer side of the first transparent substrate is disposed on the liquid crystal layer side. The scanning line electrode terminal and the signal line electrode terminal electrically connected to the scanning line and the signal line of the display area, respectively, are formed in the periphery of the display area by the lead wiring. A liquid crystal display panel in which an alignment film made of an organic resin film is formed on the liquid crystal layer side,
A flattening film is formed in the display area and the formation area of the routing wiring, and the routing wiring includes a plurality of scanning line routing wirings that respectively route the scanning lines to the plurality of scanning line electrode terminals, and the signal. A plurality of signal line routing wirings that respectively route lines to the plurality of signal line electrode terminals, and the plurality of scanning line routing wirings and / or the plurality of signal line routing wirings are made of the same scanning line material as the scanning lines. The second routing wiring formed from the same signal line material that is electrically insulated from the first routing wiring and formed of the same signal line material as the second routing wiring; The routing wiring is switched and connected in a predetermined wiring switching region, and the first insulating film, the second insulating film, and the planarizing film are connected to the wiring switching region. A first contact hole exposing the surface of the first routing wiring, and a second contact hole penetrating the second insulating film and the planarizing film to expose the surface of the second routing wiring. The first routing wiring and the second routing wiring are bridge-connected by connection electrodes covering the first and second contact holes, and the bridge connection portion of the wiring switching region is the planarization The film is removed, and the surface of the connection electrode is covered with an organic resin film made of the same material as the alignment film.

According to the liquid crystal display panel of the present invention, since the planarization film is removed at the bridge connection portion in the wiring switching region, the surface of the connection electrode existing between the first and second contact holes in the bridge connection portion is correspondingly removed. Only flattened. Therefore, even if a fluidized organic resin made of an alignment film forming material is subsequently applied to the surface of the connection electrode, the amount of fluidized organic resin flowing into the first and second contact holes decreases, so that the fluidized state When the organic resin is solidified, an organic resin film having a sufficient thickness can be formed on the surface of the connection electrode. Therefore, according to the liquid crystal display panel of the present invention, since the surface of the connection electrode is suppressed from being exposed, corrosion of the connection electrode is suppressed, and the liquid crystal display panel with little deterioration in display image quality is obtained.

In the liquid crystal display panel of the present invention, a lower electrode, a third insulating film, and a slit-shaped opening are formed on the planarizing film on the liquid crystal layer side of the display area of the first transparent substrate. An upper electrode is sequentially laminated, and in the wiring switching region, the third insulating film is formed on the first transparent substrate side of the connection electrode, and the connection electrode is made of the same material as the upper electrode It is preferable that it is formed.

According to the liquid crystal display panel of this aspect, an FFS mode horizontal electric field type liquid crystal display panel having the effects of the present invention can be obtained without particularly increasing the number of manufacturing steps of the connection electrode.

In the liquid crystal display panel of the present invention, a pixel electrode made of a transparent conductive material is formed on the planarizing film on the liquid crystal layer side of the display area of the first transparent substrate, and the connection electrode It can be made of the same material as the pixel electrode.

According to the liquid crystal display panel of this aspect, the vertical electric field type liquid crystal display panel or the IPS mode such as the TN mode, VA mode, and MVA mode that achieve the effects of the present invention can be obtained without particularly increasing the number of manufacturing steps of the connection electrode. An electric field type liquid crystal display panel is obtained. If the liquid crystal display panel is of a vertical electric field type such as TN mode, VA mode, MVA mode, etc., a common electrode made of a transparent conductive material is formed on the liquid crystal layer side of the second transparent substrate, and If the liquid crystal display panel is an IPS mode liquid crystal display panel, a common electrode is formed in the same layer as the pixel electrode.

It is a schematic plan view which shows the array substrate of the liquid crystal display device of 1st Embodiment. 2A is a schematic enlarged plan view showing a first wiring switching region in the peripheral region in the FFS mode liquid crystal display panel of the present embodiment, and FIG. 2B is a cross-sectional view taken along the line IIB-IIB in FIG. 2A. It is a figure which shows the manufacturing method of the liquid crystal display panel of embodiment in order of a process. It is a figure which shows the manufacturing method of the liquid crystal display panel of embodiment following FIG. 3 in order of a process. 5A is a diagram showing a display region and a peripheral region of a liquid crystal display panel common to the present embodiment and the conventional example, and FIG. 5B is a cross-sectional view taken along the line VB-VB in FIG. 5A. 6A is a plan view of a wiring switching region of a conventional liquid crystal display panel, and FIG. 6B is a cross-sectional view taken along line VIB-VIB in FIG. 6A.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the embodiment shown below is
The liquid crystal display panel which operates in the FFS mode for embodying the technical idea of the present invention is illustrated, and is not intended to specify the present invention as the FFS mode liquid crystal display panel. The present invention is equally applicable to other embodiments within the scope of the claims, for example, a vertical electric field type liquid crystal display panel such as a TN mode, a VA mode, and an MVA mode, or an IPS mode horizontal electric field type liquid crystal display panel. In each drawing used for the description in this specification, each layer and each member are displayed in different scales so that each layer and each member can be recognized on the drawing. However, it is not necessarily displayed in proportion to the actual dimensions.

FIG. 1 is a schematic plan view showing an array substrate of the liquid crystal display device of the first embodiment. The liquid crystal display panel 10 of this embodiment includes a display area DA on which various images are displayed and a frame area PF formed around the display area DA, and a driver IC is provided on one end side of the frame area PF. Or, a terminal portion Dr for external connection is formed. In the frame area PF, the wiring lines 16 and the signal lines 13 that route the scanning lines 12 in the display area DA to the terminal portions Dr are connected to the terminal portions D.
A routing wiring 16C leading to r is provided.

Note that the configuration of the lead-out wiring portion on the left side of the peripheral region in the liquid crystal display panel 10 of this embodiment is not substantially different from that of the conventional example shown in FIG. 5A, and therefore will be described with the aid of FIG. 5A as appropriate. In addition, the same components as those of the conventional example will be described with the same reference numerals.

The terminal portion Dr is formed on the surface of the glass substrate (corresponding to the first transparent substrate of the present invention) 11 in the extending direction of the signal line 13, and as shown in FIG. Electrode terminal 14
And a signal line electrode terminal 15 formed of a signal line material. The scanning line 12 and the scanning line electrode terminal 14 are connected by a plurality of lead wires 16. The lead wiring 16 includes a first lead wiring 16a made of a scanning line material and a second lead wiring 16b made of a signal line material.
And is formed from. These first lead-out wiring 16a and second lead-out wiring 16b are provided between the gate insulating film 17 and the liquid crystal display panel of the conventional example shown in FIG. 5B.
The two-layer structure is sandwiched between them and they are alternately arranged adjacent to each other without overlapping each other in plan view.

At this time, one end of the first routing wiring 16 a disposed below the first insulating film 17 is directly connected to the end of the scanning line 12, and the other end is below the gate insulating film 17. It is directly connected to the formed scanning line electrode terminal 14. Also, the second formed on the upper side of the gate insulating film 17.
The routing wiring 16 b is electrically connected to the scanning line 12 in the first wiring switching area 18, and is switched again to the first routing wiring 16 a in the second wiring switching area 19 and is electrically connected to the scanning line electrode terminal 14. Has been. Further, the signal line 13 is connected to the signal line 13 and the second line.
The lead wire 16c is directly connected to the signal line electrode terminal 15 directly.

2A is a schematic enlarged plan view showing the first wiring switching region 18 between the first routing wiring 16a and the second routing wiring 16b in the peripheral region in the FFS mode liquid crystal display panel 10 of the present embodiment, and FIG. It is sectional drawing of the IIB-IIB line | wire of 2A. In the first wiring switching area 18, as shown in FIG. 2A, the first routing wiring 16a and the second routing wiring 16b are fixed on the surface of the glass substrate 11 made of a glass substrate or the like, with their end portions being constant. Are arranged adjacent to each other with a distance L. As shown in FIG. 2B, the surface of the first routing wiring 16a made of a scanning line material is covered with a gate insulating film (corresponding to the first insulating film of the present invention) 17, and a first wiring made of a signal line material is used. The two routing wirings 16b are formed on the surface of the gate insulating film 17, and the surface is covered with a passivation film (corresponding to the second insulating film of the present invention) 20. Further, a planarizing film OVL is formed on the surface of the passivation film 20, and an interelectrode insulating film (corresponding to the third insulating film of the present invention) 32 is formed on the surface of the planarizing film OVL.

A gate insulating film 17 and a passivation film 20 covering the surface of the first routing wiring 16a
The first contact hole 21 is formed in the planarizing film OVL and the interelectrode insulating film 32 so as to expose the surface of the first routing wiring 16a. Also, the second routing wiring 16b
The passivation film 20, the planarizing film OVL and the interelectrode insulating film 32 covering the surface of
A second contact hole 22 is formed so as to expose the surface of the second routing wiring 16b.

The first contact hole 21 and the second contact hole 22 are an upper electrode in which a plurality of slit-like openings 30 formed in the surface of the interelectrode insulating film 32 are formed in the display region (see FIG. 4E). ) The same material as 31, for example, ITO (Indium Thin Oxide) or I
It is covered with a connection electrode 23 made of a transparent conductive material such as ZO (Indium Zinc Oxide). By this connection electrode 23, the first routing wiring 16a and the second routing wiring 16b are bridge-connected. Further, the surface of the connection electrode 23 is covered with an organic resin film 24 made of an alignment film forming material.

As apparent from FIG. 2B, in the liquid crystal display panel 10 of the present embodiment, the planarizing film OVL is not formed in the region A between the first contact hole 21 and the second contact hole 22. That is, in the region A, the flattening film is removed by the exposure / development process when forming the flattening film. For this reason, in the liquid crystal display panel according to the present embodiment, since the raised portions due to the planarizing film OVL as shown in the region A of FIG. 5B corresponding to the conventional example are eliminated, the connection electrodes are also formed in the region A. The surface of 23 is flattened, and the organic resin film 24 having a sufficient thickness can be reliably coated on the surface.

In the present embodiment, the case of the first wiring switching area 18 has been described. However, the configuration of the second wiring switching area 19 is the same as that of the first wiring switching area 18 and is not shown. In this embodiment, the signal line 13 is connected to the signal line electrode terminal 15 by the signal line 13 and the second routing wiring 16c. However, the signal line electrode terminal 15 is on the same layer as the scanning line 12. If formed, the same configuration as that of the second wiring switching region 19 described above is employed. Also in this case, illustration is omitted.

Next, the manufacturing method of the liquid crystal display panel 10 of this embodiment is demonstrated using FIG.3 and FIG.4.
Here, only the method for manufacturing the FFS mode array substrate AR is shown, and the color filter substrate is not different from that of the conventional example, and the description thereof is omitted. 3 and 4, one sub-pixel of the display area is shown on the left side, and the wiring switching area of the peripheral area is shown on the right side.

First, a conductive layer is formed on the surface of the glass substrate 11 by a sputtering method using a scanning line material made of aluminum, an aluminum alloy, molybdenum, or the like, and a part thereof is etched away so as to form a predetermined pattern. . By this step, a part of the scanning line 12 is partially widened in the vicinity of the intersection between the scanning line 12 and the signal line (not shown).
Alternatively, by extending a part of the scanning line 12, the gate electrode G of the thin film transistor TFT is formed at the same time. Further, in the peripheral region, the same scanning line material is used to make the first
Lead wiring 16a, common wiring (not shown), and scanning line electrode terminal 14 (see FIG. 5A)
Is formed by patterning (FIG. 3A).

Next, the plasma C is formed so as to cover the entire surface of the glass substrate 11 obtained by the above process.
A gate insulating film 17 made of, for example, silicon nitride is formed by the VD method. As the source gas, a gaseous silicon compound such as disilane gas or silane gas and a gaseous nitrogen compound such as ammonia are used (FIG. 3B).

Next, a semiconductor film made of, for example, an amorphous silicon (a-Si) layer and an ohmic contact (n ⁺ a-Si) layer is formed on the surface of the gate insulating film 17 and etched, so that the gate electrode G is formed above the gate electrode G. A semiconductor layer 28 to be a part of the TFT is formed (FIG. 3C).
).

Next, a conductor layer is formed by a sputtering method using a signal line material made of aluminum, an aluminum alloy, molybdenum, or the like, and a part thereof is removed by etching so as to form a predetermined pattern. Through this step, a plurality of signal lines (not shown) extending in a direction intersecting the scanning line 12, a source electrode S extending from the signal line and overlapping a part of the semiconductor layer 28,
The drain electrode D and the second routing wiring 16b are formed by patterning. A channel region ch of the TFT is formed between the drain electrode D and the source electrode S (FIG. 3D).

Next, the entire surface of the glass substrate 11 obtained by the above process, that is, the signal line, the source electrode S, the drain electrode D, the second routing wiring 16b, and further the channel region ch of the TFT are covered by the plasma CVD method. A passivation film 20 made of, for example, silicon nitride is formed (FIG. 3E).

Next, a planarizing film OVL is formed by applying, for example, a photoresist material to the surface of the substrate formed by the above process, exposing and developing. The planarizing film OVL is
Although formed over the entire surface of the substrate, the position corresponding to the drain electrode D in the display area and the position corresponding to the wiring switching area A of the lead-out line in the peripheral area are open, that is, those portions Then, the surface of the passivation film 20 is formed so as to be exposed (FIG. 3F).

Next, a transparent conductive film made of ITO, IZO or the like is formed in a predetermined area of the display area by sputtering, and further, a lower electrode 27 that operates as a common electrode is formed on the surface of the planarization film OVL by etching (see FIG. FIG. 4 (A)). The lower electrode 27 is electrically connected to a common wiring (not shown), for example, in the peripheral region. An interelectrode insulating film 32 made of, for example, a silicon nitride film is formed on the entire surface of the substrate thus obtained by plasma CVD (FIG. 4).
(B)). However, the plasma CVD conditions for forming the interelectrode insulating film 32 are the gate insulating film 17 and the passivation film 20 so as not to roughen the surface of the planarizing film OVL.
The conditions should be milder than when forming.

Next, a contact hole 29 is formed by plasma etching at a predetermined position of the passivation film 20 and the interelectrode insulating film 32 so that a part of the surface of the drain electrode D is exposed in the display region. At the same time, in the peripheral region, the first routing wiring 16a is stopped at a predetermined position of the gate insulating film 17, the passivation film 20, and the interelectrode insulating film 32 so that a part of the surface of the first routing wiring 16a is exposed. The first contact hole 21 is formed as a member by plasma etching. Further, at the same time, plasma etching is performed using the second lead wiring 16b as a stopper member at a predetermined position of the passivation film 20 and the interelectrode insulating film 32 so that a part of the surface of the second lead wiring 16b is exposed in the peripheral region. A second contact hole 22 is formed by the method (FIG. 4C).

Next, a transparent conductive film made of ITO, IZO or the like is formed in a predetermined area of the display area by a sputtering method, and further, an upper electrode 31 in which a slit-like opening 30 is formed for each pixel area by an etching method. Is formed on the surface of the interelectrode insulating film 32. At this time, the upper electrode 31 operates as a pixel electrode because it is electrically connected to the drain electrode D through the contact hole 29. At the same time, in the peripheral region, the first routing wiring 16a and the second routing wiring 16a
A connection electrode 23 is formed to cover the exposed surface of the routing wiring 16b (FIG. 4D).
.

Then, over the entire surface of the substrate obtained by the above process, an organic resin that is an alignment film forming material is applied by, for example, a roller, and the organic resin film is cured to form an alignment film 8 made of an organic resin. An array substrate is completed (FIG. 4E). Then, the array substrate manufactured in this way and the separately manufactured color filter substrate (counter substrate) are opposed to each other, the periphery is sealed with a sealing material, and liquid crystal is injected between the two substrates to achieve this embodiment. The FFS mode liquid crystal display panel 10 can be obtained.

In the above embodiment, an FFS mode liquid crystal display panel in which the upper electrode 31 operates as a pixel electrode and the lower electrode 27 operates as a common electrode is shown. However, the present invention operates as a pixel electrode by electrically connecting the lower electrode 27 to the drain electrode D, and operates as a common electrode by electrically connecting the upper electrode to the common wiring in the peripheral region. The liquid crystal display panel can also be used.

In the above embodiment, the case of the FFS mode liquid crystal display panel which is a horizontal electric field type liquid crystal display panel including the planarizing film OVL has been described as an example. However, the present invention
It is equally applicable to liquid crystal display panels having other flattening films, for example, the same IPS mode liquid crystal display panel of the same horizontal electric field type, and vertical electric field type liquid crystal display panels such as TN mode, VA mode, and MVA mode. It is.

For example, a lateral electric field type IPS mode liquid crystal display panel including a planarizing film OVL, TN
In the case of a vertical electric field type liquid crystal display panel such as the mode, VA mode, and MVA mode, the configuration of the connection region corresponding to FIG. 2B is merely the absence of the interelectrode insulating film 32, and the display region Since these configurations are not different from those of the conventional example corresponding to each operation mode, description of these specific configurations is omitted.

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display panel 11 ... Glass substrate (1st transparent substrate) 12 ... Scanning line 13 ... Signal line 14 ... Scanning line electrode terminal 15 ... Signal line electrode terminal 16 ... Leading wiring 16a
... 1st routing wiring 16b, 16c ... 2nd routing wiring 17 ... 1st insulating film (gate insulating film) 18 ... 1st wiring switching area 19 ... 2nd wiring switching area 20 ... 2nd insulating film (passivation film) 21 ... 1st contact hole 22 ... 2nd contact hole
DESCRIPTION OF SYMBOLS 23 ... Connection electrode 24 ... Organic resin film (alignment film) 27 ... Common electrode 28 ... Semiconductor layer 29
... Contact hole 30 ... Slit 31 ... Pixel electrode 32 ... Interelectrode insulating film (third insulating film) OVL ... Flattening film

Claims (3)

A first transparent substrate and a second transparent substrate, which are opposed to each other with a liquid crystal layer interposed therebetween, are provided on the liquid crystal layer side of the first transparent substrate, and the display region is scanned around the display region by a lead-out wiring. A scanning line electrode terminal and a signal line electrode terminal electrically connected to the line and the signal line are formed, and an alignment film made of an organic resin film is formed on the liquid crystal layer side of the display area. A liquid crystal display panel,
A flattening film is formed in the display region and the formation region of the routing wiring,
The routing wiring is
A plurality of scanning line routing wirings that respectively route the scanning lines to the plurality of scanning line electrode terminals; a plurality of signal line routing wirings that respectively route the signal lines to the plurality of signal line electrode terminals; and the plurality of scannings. The line routing wiring and / or the plurality of signal line routing wirings are electrically insulated from the first routing wiring formed from the same scanning line material as the scanning line, the first routing wiring, and the signal A second routing wire formed of the same signal line material as the wire, and the second routing wire is switched and connected in a predetermined wiring switching region,
In the wiring switching area,
A first contact hole penetrating the first insulating film, the second insulating film, and the planarizing film to expose a surface of the first routing wiring; and penetrating the second insulating film and the planarizing film. A second contact hole exposing the surface of the second routing wiring is formed,
The first routing wiring and the second routing wiring are bridge-connected by a connection electrode that covers the first and second contact holes,
The bridge connection portion of the wiring switching region has the planarizing film removed,
The surface of the connection electrode is covered with an organic resin film made of the same material as the alignment film,
A liquid crystal display panel characterized by that. On the liquid crystal layer side of the display area of the first transparent substrate, on the planarizing film, a lower electrode,
The third insulating film and the upper electrode in which the slit-shaped opening is formed are sequentially laminated,
In the wiring switching region, the third insulating film is formed on the first transparent substrate side of the connection electrode,
The liquid crystal display panel according to claim 1, wherein the connection electrode is made of the same material as the upper electrode. A pixel electrode made of a transparent conductive material is formed on the planarizing film on the liquid crystal layer side of the display area of the first transparent substrate, and a transparent conductive material is formed on the liquid crystal layer side of the second transparent substrate. 2. The liquid crystal display panel according to claim 1, wherein a common electrode made of a conductive material is formed, and the connection electrode is made of the same material as the pixel electrode.

Images