JP2011009579A - Field-effect transistor on insulating substrate, and integrated circuit thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure for achieving a bipolar transistor by improving a maximum allowable voltage of an output voltage with respect to a field-effect transistor formed in a semiconductor thin film on an insulating substrate, and an integrated circuit thereof.SOLUTION: A body contact region is sandwiched between source regions in order to achieve a larger maximum allowable voltage with small area. The body contact region and source regions are connected through a conductive thin film or a junction of a low resistance. There is provided a constitution of the transistor consisting of: a drain region and source regions, and a first gate and a body contact region; and a part where first conductivity type second regions are provided side by side, that are a second gate, and source regions and a drain region. Thus, the bipolar transistor having a large channel width is achieved, and there is provided the transistor which can operate with both positive and negative potentials in relation to a conventional body potential, with this constitution.

Description

  The present invention relates to an SOI (Silicon on Insulator), polycrystalline silicon on a glass substrate, a field effect transistor formed on a semiconductor thin film on an insulating substrate represented by SOS (Silicon on Sapphire), and an integrated circuit thereof.

  Conventionally, a MOS field effect transistor (abbreviated as a MOS transistor) formed in SOI or the like has a drain when the drain voltage is increased when a silicon thin film portion called a body in which a channel is formed is in a floating state. A high electric field generated between the bodies generates a current between the drain bodies, and this current flows from the body to the source. Due to this current inflow, the body and the source are forward biased, and the gate threshold voltage Vth of the MOS transistor is lowered. Further, this current is amplified by a parasitic bipolar transistor having a source as an emitter and a body as a base, and further draws a current from a drain operating as a collector. Due to this positive feedback phenomenon, the drain current increases rapidly above a certain drain voltage, and the breakdown voltage of the MOS transistor using the body in a floating state decreases. Even in a drain voltage region that is smaller than the drain voltage that causes a sudden increase in current, the output conductance is increased and the voltage amplification factor of the analog circuit is adversely affected. A typical increase phenomenon of the output current is called a kink effect, and when the drain-source voltage is 3 to 4 V, a step-like increase is seen in the drain current.

  In order to improve this phenomenon, in order to fix the body to a constant potential, a T-type transistor structure shown in a plan view in FIG. 1, an H-type transistor structure shown in a plan view in FIG. 2, and a plane in FIG. The source / tie structure shown in the figure and the hollow body contact structure shown in the sectional view in FIG. 4 were used.

  In the figure, 111 is a drain region of the first conductivity type, 121 is a source region of the first conductivity type, 131 is a body contact region of reverse conductivity type, and 400 is a conductive gate region. 113, 123, 133, and 403 are contact holes provided on the drain region, the source region, the body contact region, and the gate region, respectively, and connect the respective regions to the metal thin film wirings 501, 502, 503, and 504. . Under the gate region 400 between the drain region 111 and the source region 121, as shown in FIG. 4, a gate insulating film 200 and a body portion 100 in which a channel is formed are provided. In FIG. 4, 10 is a supporting substrate, 102 is a part where the body is inserted, 20 is an insulating layer that insulates the supporting substrate and the semiconductor thin film (111 + 121 + 131 + 100 + 102), 300 is a so-called field insulating film that separates elements, and 310 is a wiring and a semiconductor thin film It is an insulating layer which insulates.

  In the T-type structure of FIG. 1 and the H-type structure of FIG. 2, the body portion is connected to the body contact region through the body contact region 131 and the gate region between the source and drain regions. In these structures, since the body contact region is arranged with respect to the source and drain regions, so-called bipolar circuit operation in which the roles of the source and drain are switched is possible. Since the source region and the body contact region are connected to each other in the source tie structure in FIG. 3 and the embedded body contact structure in FIG. 4, the roles of the source region and the drain region cannot be interchanged. Only operation is possible.

  Both the T and H types fix the body potential via the body contact electrode 503 in order to achieve a practical source-drain voltage (several volts or more) while avoiding the so-called floating body effect. The body contact is made at the end of the gate in the width direction through the body below the gate. The source tie structure also has body contacts at both ends of the source in the gate width direction.

However, as the gate width W of the transistor increases, in the T-type transistor, the resistance between the body contact and the portion on the opposite side of the contact farthest from the contact increases, and the effect of fixing the body potential decreases. When the gate width W of the H-type transistor and the source / tie structure is increased, the effect of fixing the body potential is reduced at the center of the gate.
The contact body contact structure has a structure in which the contact portion 131 and the body 100 under the gate are continuous through the lower side of the source 121. Therefore, when the source junction is deepened, the contact 102 between the body contact and the body under the gate 102 is formed. The resistance of the portion increases, and the effect of fixing the body potential is reduced. Since the technology will evolve in the direction of thinner semiconductor thin films in the future, it will be inevitable that the resistance of the concavities will increase.

  The T-type and H-type transistors have limitations in circuit application. That is, the above-mentioned advantage that circuit operation with bipolar polarity is possible is in the range of so-called reverse polarity with respect to the body contact potential. For example, once the potential of the p-type body is fixed, both the source and drain have a negative potential. The operation at (strictly, a negative potential exceeding the forward voltage of the pn junction) was not guaranteed. Therefore, conventional T-type and H-type transistors have problems even in unipolar circuit operation.

  In view of the current state of the art as described above, an object of the present invention is to provide a structure capable of suppressing a decrease in drain breakdown voltage or an increase in output conductance even when the gate width is increased. In the case of the source / tie structure, it becomes unipolar, and a bidirectional circuit application in which the drain and the source are interchanged cannot be performed. However, an object of the present invention is to provide a structure that solves this problem.

  Even in the above T-type and H-type transistors, after the body contact potential is defined for circuit application, the drain / source operable potential is only guaranteed to operate in one of the positive and negative polarities from the body contact potential. The purpose is to eliminate the limitation of the polarity of the potential.

In the present invention, in forming a field effect transistor in a semiconductor thin film formed on an insulating substrate,
An insulating substrate as a first means;
A semiconductor thin film provided on the insulating substrate;
A gate insulating film provided on the semiconductor thin film;
A first gate electrode having a length and a width provided on the surface of the semiconductor thin film via a gate insulating film;
A first region of the first conductivity type and a second region of the first conductivity type provided on or in the surface of the semiconductor thin film and provided on both sides in the length direction when viewed from the plane of the first gate electrode. Area of
A third region of reverse conductivity type disposed adjacent to the second region in a gate width direction perpendicular to the direction connecting the first region and the second region;
A conductive thin film connected to the second region and the third region;
A second gate electrode having a length and a width provided on the surface of the semiconductor thin film through the gate insulating film along the second region;
A fourth region of the first conductivity type provided on the surface of the semiconductor thin film on both sides in the length direction of the second gate electrode together with the second region;
The first region and the fourth region are at least configured as output regions.
The first means provides a solution that achieves bidirectional operation, high drain breakdown voltage and low output conductance.

In the first means, the third region is juxtaposed with the second region and has a first conductivity type and a reverse conductivity type, and is in contact with the second region by forming a low resistance junction. If it is, the conductive thin film becomes unnecessary. That is,
An insulating substrate;
A semiconductor thin film provided on the insulating substrate;
A gate insulating film provided on the semiconductor thin film;
A first gate electrode having a length and a width provided on the surface of the semiconductor thin film via the gate insulating film;
A first region of the first conductivity type and a second region of the first conductivity type provided on or in the surface of the semiconductor thin film and provided on both sides in the length direction when viewed from the plane of the first gate electrode. Area of
The first gate electrode has a first conductivity type and an opposite conductivity type juxtaposed with the second region in the gate width direction of the first gate electrode, and is in contact with the second region by forming a low-resistance junction. A third region, and
A second gate electrode having a length and a width provided on the surface of the semiconductor thin film through the gate insulating film along the second region;
A fourth region of the first conductivity type provided on the semiconductor thin film or in the surface thereof on the opposite side of the second region with respect to the second gate electrode;
The first region or the fourth region is an output region according to a bidirectional circuit operation without applying a predetermined bias potential to the third region. A field effect transistor formed on an insulating substrate;
Can also be a means for solving the above-mentioned problems.

When the second region and the third region each have an impurity concentration of 10 ¹⁹ atoms / cc or more, a low resistance junction can be formed.

  Since the body contact region can perform the present invention by absorbing the reverse conductivity type carrier or controlling the Fermi level of the reverse conductivity type carrier, the body contact region is in contact with a part of the body. A metal or silicide thin film may be used.

When the third region is a silicide or metal thin film partially in contact with the semiconductor thin film, the second region has an impurity concentration of 10 ¹⁹ atoms / cc or more in the vicinity of the junction. The region and the third region form a low resistance junction.

  As a second means, in the field effect transistor formed on an insulating substrate, the second region is further formed as a plurality of regions, and the plurality of second regions serve as the third region in the gate width direction. Place it so that it is sandwiched between the two.

As a third means, in the field effect transistor formed on the insulating substrate, the third region is further formed as a plurality of regions, and the plurality of third regions serve as the second region in the gate width direction. Arrange them so that they are sandwiched between.
The second and third means provide a solution for realizing a high drain breakdown voltage and a low output conductance even in a device having a large gate width.

As a fourth means, the first region or the fourth region is relatively divided into a portion having a relatively high impurity concentration (for example, an impurity concentration of 10 ²⁰ atoms / cc or more) and a portion having a relatively low concentration (for example, 10 ²⁰ to The impurity concentration is about 10 ¹⁸ atoms / cc), and a portion with a relatively low impurity concentration is disposed near the gate electrode, and if necessary, partly overlaps with the gate electrode via the insulating film.
The fourth means provides a solution for realizing high drain breakdown voltage and low output conductance.

  In the present invention, the insulating substrate refers to a substrate in which an insulating film such as a silicon oxide film or a silicon nitride film is formed on the surface of a semiconductor substrate such as silicon, an insulating substrate such as quartz glass or alumina, or an insulating material such as sapphire. Refers to a crystalline substrate. For the formation of a semiconductor thin film, a method in which a semiconductor substrate is bonded to an insulating substrate and then polished to form a thin film, a method in which the semiconductor substrate is bonded to the insulating substrate and then a portion that becomes a thin film is peeled off, and a heterogeneous substrate is formed on a crystal substrate such as sapphire. A method of epitaxial growth, a method called SIMOX in which oxygen ions are ion-implanted into the surface of a silicon substrate and an oxide film and a silicon thin film are formed on the surface by subsequent heat treatment, a method of forming a film on an insulating substrate using CVD, etc. Use.

  The field effect transistor is not a partial depletion type or a full depletion type, and even if the semiconductor thin film is close to an “intrinsic semiconductor”, a reverse conductivity type third region generated by a high electric field between the drain and the body is used. The object of the present invention is realized.

By using the first means,
In the circuit operation, the potential of the body contact automatically changes to the optimum potential following the switching of the polarity of the output voltage without externally controlling the potential of the body contact. Therefore, it is possible to realize a bipolar transistor that can output positive and negative potentials and is compatible with the source and drain with respect to the conventional body contact potential.

In conventional H-type and T-type transistors, the length in the W direction is limited by the drain breakdown voltage or the output conductance, and cannot be designed greatly. According to the present invention, the length in the W direction can be designed to be as large as possible from the chip area.
Therefore, the on-resistance or mutual conductance of the transistor can be designed to a value necessary for circuit operation.

  On the other hand, assuming that a large number of conventional transistors are juxtaposed in order to form a transistor with a large W, an H-type transistor is juxtaposed, resulting in a complicated interconnection and a high breakdown voltage or high output conductance. In order to obtain a transistor, one unit that is juxtaposed cannot have a large W, so that the area required to connect the transistors that constitute the one unit is approximately the same as the area of the one unit. As a result, the layout of the transistor according to the present invention is simplified to the extent that there are no complicated interconnections.

  In the structure of the present invention, one of the first region and the fourth region functioning as a source is forward-biased with the body. However, since minority carriers injected from the source into the body are absorbed by the second region in the floating state, the minority carriers have little influence on the body between the second region and the drain region.

  Since the transistor of the present invention operates in such a manner that the channel under the first gate electrode (length L1) and the channel under the second gate electrode (length L2) are connected in series, the unit channel width ( Although it is necessary to consider that the on resistance per W) is (L1 + L2) / L1 times or the output current is L1 / (L1 + L2), these decreases can be improved by the following method.

  As described above, when the source and the body are forward-biased, the Vth of the channel in this part becomes smaller than the channel on the drain side. For this reason, the channel resistance connected in series to the source side is smaller than that on the drain side. In particular, when the gate bias is a value close to the Vth of the drain side channel, the effect of this phenomenon improves the drain current reduction. Further, when the output voltage is high when the SOI is a partially depleted SOI, the voltage drop in the source side channel is clamped to the forward voltage of the diode between the source bodies, so that the output current value is also improved in this case.

An example of a plan view of a conventional T-type bipolar transistor that is actually unipolar operation. An example of a plan view of a conventional H-type bipolar transistor that is actually unipolar operation. The example of a top view of the conventional source tie type unipolar transistor. A cross-sectional view of a conventional boring body contact. FIG. 2 is a plan view of an embodiment of a bidirectional transistor of the present invention. Sectional drawing which cut | disconnected the AA 'part of FIG. 5 of this invention. Sectional drawing which cut | disconnected the BB 'part of FIG. 5 of this invention. Output characteristics of source tie transistor. Output characteristics when the source of the source-tie transistor in FIG. 8A is used as an output terminal. Output characteristics of the bipolar transistor of the present invention. Output characteristics of a transistor with a distance between third regions of 100 μm. Output characteristics of a transistor with a distance between the third regions of 10 μm. An experimental example showing the relationship between the maximum allowable voltage and the distance between the third regions.

An example of the planar structure of the present invention is shown in FIG. Examples of cross-sectional structures are shown in FIGS.
In FIG. 5, 110 is a first region of the first conductivity type, 120 is a second region of the first conductivity type, 130 is a third region of the opposite conductivity type, and 140 is a first region of the first conductivity type. 4, 401 and 402 are first and second conductive gate electrodes, and 412 is a conductive thin film connecting the first and second conductive gate electrodes. In this embodiment, the conductive gate electrode (For example, two layers of polycrystalline silicon or tungsten silicide and polycrystalline silicon, two layers of titanium silicide or cobalt silicide and polycrystalline silicon). 114 and 144 are portions of low impurity concentration provided in the first and fourth regions, and partially overlap with the gate electrodes 401 and 402 through the gate insulating film. Note that 114 and 144 can be omitted when the first and fourth regions that are output regions do not require a large breakdown voltage. 113, 123, 133, 143, and 403 are contact holes to the first, second, third, and fourth regions and the gate electrode, respectively. The respective regions and the metal thin film wirings 511, 532, 514, and 504 are connected to each other. Connected. The metal thin film wiring 532 connects the second and third regions through the contact holes 123 and 133, but the potential is not fixed.

6 is a cross-sectional view of the AA ′ portion of FIG. 5 according to the embodiment of the present invention, and FIG. 7 is a cross-sectional view of the BB ′ portion of FIG. In the figure, 10 is a supporting substrate, 100 is a body, 200 is a gate insulating film, 20 is an insulating layer that insulates the supporting substrate and a semiconductor thin film (110 (+114) +120 +130 (not shown in FIG. 6) +140 (+144) +100). , 300 is a so-called field insulating film that separates the elements, and 310 is an insulating layer that insulates the wiring from the semiconductor thin film. The channel is formed on the surface or inside of the body between the first region and the second region, and on the surface or inside of the body between the second region and the fourth region, via the gate insulating film on the body. The electric resistance of the channel is controlled by the potential of the first gate electrode and the second gate electrode. As shown in FIG. 7, the body 100 is continuous with the body contact region 130. The body contact region can be formed of a semiconductor region whose resistance is reduced by adding 10 ¹⁹ atoms / cc or more of a reverse conductivity type impurity (for example, boron), but the body contact region absorbs a reverse conductivity type carrier or Since the present invention can be implemented by fulfilling the function of controlling the Fermi level of the reverse conductivity type carrier, the body contact region may be a metal or silicide thin film in contact with a part of the body.
In this case, it can be formed as a common region with the wiring 532 in the second region. Further, it may be a heterogeneous semiconductor region that forms a heterojunction with the body.
The third region (herein referred to as body contact region) is in contact with the second region, and the second region has an impurity concentration of 10 ¹⁹ atoms / cc or more in the vicinity of the contact portion. Thus, the second region and the third region form a low resistance junction. Since the second semiconductor region usually has a peak value of about 10 ²⁰ atoms / cm ³ as in the following example, this condition is satisfied. When the third region is a semiconductor region, a low resistance junction is formed under the above conditions when an impurity of 10 ¹⁹ atoms / cc or more is added and the third region is a metal or silicide thin film. Is done.

The body may be the reverse conductivity type, the intrinsic type, or the first conductivity type. In the case of the first conductivity type, in order to obtain an enhancement type transistor, it is desirable that the carrier is depleted from the body surface to the back surface when the gate voltage is 0V.
The dimension of the third region in the gate width direction may be the minimum dimension that can be achieved by lithography.
The contact hole to the second region and the contact hole to the third region do not need to be provided separately, and a common contact hole may be provided to a portion including the boundary between the second region and the third region. .

The electric characteristics of the transistor of the embodiment of the present invention are compared with those of the source-tie transistor shown in FIG. The transistor structure and material parameters used in the measurement are as follows. The transistor body, first, second, third, and fourth regions, and the second region have the same dimension w2 in the channel width direction or the same impurity concentration.
body: Thickness = 400 nm, conductivity type = p-type silicon, impurity concentration = 10 ¹⁶ atoms / cm ³
Gate: n-type polysilicon, gate length: L1 = 10, L2 = 5μm
Gate oxide thickness = 30nm, insulation layer 20 thickness = 400nm
Impurity concentrations in the first, second and fourth regions: peak value to 10 ²⁰ atoms / cm ³
Impurity concentration in the third region: peak value to 5 × 10 ¹⁹ atoms / cm ³
Length of the third area: 3μm
Impurity concentration of the lightly doped region of the first and fourth regions: 2.5 × 10 ¹⁷ atoms / cm ³ , length: 2 μm
w2 = 25μm
8A and 8B show the output characteristics of a conventional source-tie transistor. 8A shows a case where the first region is a drain and the second region is a source, and FIG. 8B shows a case where the second region is a drain and the first region is a source. The output characteristics shown in FIG. 8B indicate that when the output voltage exceeds about 1 V, the output current does not exhibit saturation current characteristics as in a normal MOS transistor, but increases as the output voltage increases. From this measured characteristic, it can be seen that the withstand voltage of the source-tie transistor is almost lost when the second region is the drain.

  On the other hand, FIG. 9 shows output characteristics of the transistor having the structure of FIG. This output characteristic is the one when the first region is the drain and the fourth region is the source, but the output characteristic is almost the same when the reverse connection is made. Compared with FIG. 8A, the output current is reduced by about the increase in channel length (L1 / (L1 + L2)) in the portion where the gate voltage is large. In the voltage range where the gate voltage is close to the gate threshold voltage, the decrease in output current is improved.

  Among the transistor structure and material parameters, the output current-output voltage characteristics of a transistor having a gate length of 2 μm, a total channel width of 100 μm, and changing only w2 were examined. The characteristic of w2 = 100 μm is shown in FIG. 10, and the characteristic of w2 = 10 μm is shown in FIG. When the output voltage is increased under a constant gate voltage, the output conductance dIout / dVout increases and the output voltage that becomes equal to the channel conductance of the transistor is the maximum allowable voltage of the output voltage, as shown in FIG. . When w2 = 100μm, the maximum allowable voltage is greatly reduced due to the kink effect described above. Since the kink effect itself is observed at an output voltage of 4V + ΔV, it can be seen that the maximum allowable voltage is improved to 5.4V at w2 = 100μm, but w2 is w2 which is 50 times the channel length (about 1.5μm). = 75μm further reduces the kink effect, and the maximum allowable voltage is greatly influenced by the following causes. This condition corresponds to a width of the second region of 25 times the channel length and 75/2 = 38 μm when the third region is provided between the two second regions.

  Next to the reduction of the kink effect, the maximum allowable voltage is determined by how much minority carriers generated by carrier multiplication at the drain-body junction are absorbed into the third region. For this reason, it was found that if w2 is 10 times or less the channel length, the maximum allowable voltage can be greatly improved.

  According to the structure of the present invention, by providing a plurality of third regions, it is possible to reduce the distance w2 between the plurality of third regions and efficiently absorb the generated minority carriers of the opposite polarity. Due to this effect, an increase in the maximum allowable voltage of the output voltage can be realized as in the above embodiment. In order to realize the same effect with a conventional bipolar transistor, the H-type structure is used. In the above example, the channel width needs to be about 10 times the channel length or less, and the overhead area of the H structure is ignored. It becomes impossible to realize the necessary current capacity by repeating this unit structure. As a result, the areas are almost the same, which is disadvantageous because the wiring to the body contacts of each unit H structure is complicated.

  An advantage of the present invention that is more useful in circuit applications is that a transistor capable of operating at both positive and negative potentials with respect to conventional body potentials is provided.

10 Support substrate 100 body
110 1st area | region 120 2nd area | region 130 3rd area | region 140 4th area | region 200 Gate insulating film 300 Field insulating film 532 Metal thin film wiring

Claims (14)

An insulating substrate;
A semiconductor thin film provided on the insulating substrate;
A gate insulating film provided on the semiconductor thin film;
A first gate electrode having a length and a width provided on the surface of the semiconductor thin film via the gate insulating film;
A first region of the first conductivity type and a second region of the first conductivity type provided on or in the surface of the semiconductor thin film and provided on both sides in the length direction when viewed from the plane of the first gate electrode Area of
A third region of a first conductivity type and a reverse conductivity type juxtaposed with the second region in the gate width direction of the first gate electrode;
A conductive thin film connected together to the second region and the third region;
A second gate electrode having a length and a width provided on the surface of the semiconductor thin film through the gate insulating film along the second region;
A fourth region of the first conductivity type provided on the semiconductor thin film or in the surface thereof on the opposite side of the second region with respect to the second gate electrode;
A field effect transistor formed over an insulating substrate, wherein the first region or the fourth region is used as an output region in accordance with a circuit operation.   2. The field effect transistor formed on an insulating substrate according to claim 1, wherein the third region is a silicide or metal thin film partially in contact with the semiconductor thin film. An insulating substrate;
A semiconductor thin film provided on the insulating substrate;
A gate insulating film provided on the semiconductor thin film;
A first gate electrode having a length and a width provided on the surface of the semiconductor thin film via the gate insulating film;
A first region of the first conductivity type and a second region of the first conductivity type provided on or in the surface of the semiconductor thin film and provided on both sides in the length direction when viewed from the plane of the first gate electrode Area of
The first gate electrode has a first conductivity type and an opposite conductivity type juxtaposed with the second region in the gate width direction of the first gate electrode, and is in contact with the second region by forming a low-resistance junction. A third region, and
A second gate electrode having a length and a width provided on the surface of the semiconductor thin film through the gate insulating film along the second region;
A fourth region of the first conductivity type provided on the semiconductor thin film or in the surface thereof on the opposite side of the second region with respect to the second gate electrode;
The first region or the fourth region is an output region according to a bidirectional circuit operation without applying a predetermined bias potential to the third region. A field effect transistor formed on an insulating substrate. 4. The field effect transistor formed on an insulating substrate according to claim 3, wherein each of the second region and the third region has an impurity concentration of 10 ¹⁹ atoms / cc or more. The third region is a silicide or metal thin film partially in contact with the second region, and the second region has an impurity concentration of 10 ¹⁹ atoms / cc or more in the vicinity of the junction. A field effect transistor formed on an insulating substrate according to claim 3.   4. The insulating substrate according to claim 1, wherein the second region includes a plurality of regions, and the third region is disposed so as to be sandwiched between the plurality of second regions in the gate width direction. Field effect transistor formed in   4. The insulating substrate according to claim 1, wherein the third region is composed of a plurality of regions, and the second region is disposed so as to be sandwiched between the plurality of third regions in the gate width direction. Field effect transistor formed on top.   7. The field effect transistor formed on an insulating substrate according to claim 6, wherein the distance between the third regions is within 50 times the channel length.   7. The field effect transistor formed on an insulating substrate according to claim 6, wherein the distance between the third regions is within 10 times the channel length.   The first and fourth regions have a relatively thin portion and a dark portion having a relatively low impurity concentration, and the relatively thin portion is located closer to the first or second gate electrode than the relatively dark portion. A field effect transistor formed on an insulating substrate according to claim 1 or 3.   4. The field effect transistor formed on an insulating substrate according to claim 1, wherein the insulating substrate is made of an insulating material including one of glass, sapphire, and ceramic.   4. The field effect transistor formed on an insulating substrate according to claim 1, wherein the insulating substrate is formed by forming an insulating film on a silicon substrate. An insulating substrate;
A semiconductor thin film provided on the insulating substrate;
A gate insulating film provided on the semiconductor thin film;
A first gate electrode having a length and a width provided on the surface of the semiconductor thin film via the gate insulating film;
A first region of the first conductivity type and a second region of the first conductivity type provided on or in the surface of the semiconductor thin film and provided on both sides in the length direction when viewed from the plane of the first gate electrode Area of
A third region of a first conductivity type and a reverse conductivity type juxtaposed with the second region in the gate width direction of the first gate electrode;
A conductive thin film connected together to the second region and the third region;
A second gate electrode having a length and a width provided on the surface of the semiconductor thin film through the gate insulating film along the second region;
A fourth region of the first conductivity type provided on the semiconductor thin film or in the surface thereof on the opposite side of the second region with respect to the second gate electrode;
An insulating substrate characterized in that the first region or the fourth region becomes an output region in accordance with bidirectional circuit operation without applying a predetermined bias potential to the third region. Field effect transistor formed on top.   14. The field effect transistor formed on an insulating substrate according to claim 3, wherein the width of the second region is within 25 times the channel length.