JP2011009556A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently suppress dispersion of a composition on a surface of lower-layer Cu wiring by sufficiently obtaining processing controllability of a via hole regardless of an opening size of the via hole when a SiOCH film is used as a wiring insulation film.SOLUTION: A laminate structure 20 formed on lower-layer Cu wiring 3 includes a cap insulation film 4 containing silicon and carbon, and a SiOCH film as a wiring insulation film 5 formed on the cap insulation film 4. A process of forming via holes 8, 9 on the laminate structure 20 is executed by combining first and second dry etching. In the first dry etching, a first mixed gas is used in which Oconcentration is set so that an etching rate of the via hole 9 having a small opening size is set larger than that of the via hole 8 having a large opening size. In the second etching, a second mixed gas is used in which Oconcentration is set so that the etching rate of the via hole 8 is set larger than that of the via hole 9.

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  With the progress of miniaturization and integration of semiconductor devices, the miniaturization of multilayer wiring formed on the upper layer of a transistor formed on a silicon substrate is rapidly progressing. This multilayer wiring has a plurality of layers of trench wirings connecting transistor elements in the horizontal direction and vias connecting these trench wirings in the vertical direction. After the 65 nm node, copper (Cu) is used as a wiring material, and a SiOCH film mainly composed of silicon (Si), carbon (C) and oxygen (O) having a low dielectric constant is used as a wiring insulating film material. It has become common. As a method for forming a copper wiring pattern, a dual damascene processing method in which a trench wiring and a via are simultaneously formed is most popular.

  Among the dual damascene processing methods, in the via first dual damascene processing method formed first from the via hole, etching is stopped at the cap insulating film on the copper wiring, and so-called over-etching is performed in which the etching process is continued for a certain time. Thus, each via hole is formed to a depth reaching the cap insulating film regardless of the in-plane variation in the film thickness of the wiring insulating film, the in-plane variation in the etching rate, or the like.

  In general, a silicon carbide film (SiC) mainly composed of silicon (Si) and carbon (C) is used as a cap insulating film, but a silicon carbonitride film SiCN added with nitrogen or a silica added with oxygen. A carbon composite film (SCC: Silica-carbon-composite) is also used.

  After protecting the lower layer Cu wiring with such a cap insulating film, by forming a via hole in the upper layer of the lower layer Cu wiring, variation in the degree of surface alteration such as oxidation of the lower layer Cu wiring layer connected to the via can be achieved. This suppresses variations in connection resistance and deterioration of reliability.

  Therefore, the etching stop property of the cap insulating film is very important. Until now, the cap insulating film should have a sufficient thickness, and the cap insulating film should have a sufficient etching selectivity with the wiring insulating film. It was general.

  In recent years, in response to the miniaturization of LSI (Large Scale Integration), a single SiOCH film having a relative dielectric constant of 3.0 or less has been used as a wiring insulating film. However, in the via wiring formation process, when a carbon-rich SiOCH film having a high C concentration in the wiring insulating film, that is, a high concentration ratio (C / Si) between C and Si in the wiring insulating film, is used as an etching stopper. It has become apparent that the difference in composition between a certain cap insulating film and a SiOCH film as a wiring insulating film is reduced, and the etching selectivity between the cap insulating film and the wiring insulating film is reduced.

FIG. 8 is a diagram showing the relationship between the carbon concentration ratio (horizontal axis) between the wiring insulating film (SiOCH film) and the cap insulating film and the etching selectivity (vertical axis) between the cap insulating film and the wiring insulating film. . As shown in FIG. 8, the higher the carbon concentration of the wiring insulating film (SiOCH film) is relative to the carbon concentration of the cap insulating film (as it goes to the left in FIG. 8), The etching selectivity is lowered. As shown in FIG. 8, as the wiring insulating film, the concentration ratio (C / Si) between C and Si in the wiring insulating film is 1 / C of the concentration ratio (C / Si) between C and Si in the cap insulating film. When a carbon-rich SiOCH film larger than 2 is used (in the range of (C / Si) _{cap insulating film} / (C / Si) _{SiOCH film in} FIG. 8 being less than 2), wiring insulation with respect to the cap insulating film is performed. The decrease in the etching selectivity of the film becomes significant (for example, 10 or less).

  Due to such a decrease in the selection ratio, the via hole processing controllability deteriorates. For this reason, the variation in the oxidation state of the surface of the lower layer Cu wiring at the bottom of the via hole (the variation in the composition of the surface) results in variation in the connection resistance between the lower layer Cu wiring and the via, and the semiconductor device having a multilayer wiring structure May adversely affect yield and reliability.

For such a problem, for example, Patent Document 1 discloses a structure using an organic film not containing silicon as a wiring insulating film. In the technique of Patent Document 1, paying attention to the fact that the carbon concentration of the organic film is higher than that of the cap insulating film, the organic film is etched using O ₂ gas as a main etching gas to form a via hole. In the technique of Patent Document 1, by using O ₂ gas as a main etching gas, it is possible to secure high etching selectivity of the wiring insulating film (organic film) with respect to the cap insulating film and stop the etching at the cap insulating film. it can.

On the other hand, as in Patent Documents 2 and 3, in the technique of finely processing a SiOCH film that is a wiring insulating film, pattern size dependency of an etching rate typified by a microloading effect or the like occurs. As a countermeasure, there is known a method of adding a gas (deposition gas) that generates a large amount of deposits such as fluorocarbon (CHxFy) -based gas or C ₄ F ₆ gas to an etchant gas for etching the SiOCH film. . According to this method, since the consumption rate of the etchant gas is high at a location where the etching rate is high, the concentration of the deposition gas not directly involved in etching is relatively increased, and hydrocarbon-based (CHx) deposits are present at that location. Are easily deposited selectively. As a result, the etching rate of the SiOCH film at that location is lowered, and the pattern size dependency of the etching rate (dependence on the opening diameter of the via hole) is reduced. In particular, as in Patent Document 3, the etching process is divided into two steps, and the addition amount of the deposition gas is changed in these two steps, so that the via hole is uniformly processed regardless of the opening diameter of the via hole. Is common.

JP 2001-345380 A JP-A-7-74156 JP 2008-198659 A International Publication No. 2008/076649 Pamphlet International Publication No. 2007/132879 Pamphlet

Since the SiOCH film containing silicon cannot be etched only with O ₂ gas, the technique of Patent Document 1 that performs etching with oxygen gas cannot be applied to the etching of the SiOCH film.

  Further, when the oxygen gas described in Patent Document 1 is used as an etchant, a high etching selectivity with respect to the cap insulating film is required to absorb the difference in etching rate between patterns. If the requirement is not satisfied, the cap insulating film under the via hole is etched, the underlying Cu wiring appears, and the surface is oxidized. When Cu at the bottom of the via hole is oxidized, the connection resistance between the via and the lower layer Cu wiring is increased and the reliability is deteriorated. In the technique of Patent Document 1, an etching selectivity ratio 100 of the organic film to the cap insulating film can be ensured, but the SiOCH film contains Si like the cap insulating film. For this reason, when the SiOCH film is used as the wiring insulating film, unlike the case where the wiring insulating film is an organic film, it is not possible to ensure the etching selectivity 100 of the SiOCH film to the cap insulating film.

  For this reason, when a SiOCH film is used as the wiring insulating film, it is necessary to increase the thickness of the cap insulating film in order to absorb the etching rate difference due to the difference in the opening ratio of the via hole pattern due to the microloading effect. However, since the cap dielectric film generally has a higher relative dielectric constant than the wiring interlayer dielectric film, increasing the film thickness increases the effective dielectric constant, which hinders high performance and low power consumption of the LSI. . Therefore, it is not realistic to increase the thickness of the cap insulating film.

Further, in the case of the etching gas mainly containing oxygen described in Patent Document 1, it is CHx-based deposits that reduce the etching rate. This deposit is removed by O ₂ plasma such as resist ashing. Therefore, even if a deposition gas as described in Patent Documents 2 and 3 is added to the oxygen gas that is an etchant gas, the deposit itself is immediately etched with the oxygen gas, and the etching rate is increased. The effect of reducing the pattern size dependency is lost. Further, if a deposit that cannot be removed by oxygen gas is generated, clogging occurs in the via hole during etching, and the clogged via hole becomes an unopened pattern.

  Therefore, if the etching mainly composed of oxygen gas described in Patent Document 1 and the technology for suppressing the microloading effect with the fluorocarbon-based deposits described in Patent Document 2 and Patent Document 3 are simply combined. The pattern size dependency of the etching rate on the SiOCH film cannot be avoided, and the processing controllability of the via hole cannot be ensured sufficiently.

  As described above, when a SiOCH film is used as the wiring insulating film, it is possible to sufficiently secure the processing controllability of the via hole regardless of the opening diameter of the via hole and sufficiently suppress the variation in the composition of the surface of the lower layer Cu wiring. It was difficult.

The present invention includes a via hole forming step of forming a plurality of via holes including via holes having first and second opening diameters in a laminated structure formed on a lower layer Cu wiring, and the laminated structure includes silicon (Si). And a cap insulating film containing carbon (C), and a SiOCH film as a wiring insulating film formed on the cap insulating film. In the via hole forming step, the first mixed gas is an etching gas. The first dry etching used as the second dry etching and the second dry etching using the second mixed gas as an etching gas are combined to form the plurality of via holes in the wiring insulating film, and the first and second mixed gases each has at least one gas of a CF-based gas and CHF-based gas, and O ₂ gas, containing, O ₂ concentration of the first gas mixture An etching rate of a via hole having a relatively small first opening diameter among the first and second opening diameters is set to be larger than an etching rate of a via hole having a relatively large second opening diameter. The method for manufacturing a semiconductor device is characterized in that the O ₂ concentration of the mixed gas is set so that an etching rate of the via hole having the second opening diameter is larger than an etching rate of the via hole having the first opening diameter. I will provide a.

  According to this method for manufacturing a semiconductor device, the first dry etching using the first mixed gas and the second dry etching using the second mixed gas are appropriately combined to perform the via hole forming step. The etching depths of the via hole having a small first opening diameter and the via hole having a relatively large second opening diameter can be made uniform. That is, by appropriately combining the first dry etching and the second dry etching, the processing controllability of the via hole when using the SiOCH film as the wiring insulating film is sufficiently ensured regardless of the opening diameter of the via hole. Can do. Thereby, the variation in the composition of the surface of the lower layer Cu wiring located in the lower layer of the via hole can be reduced. Therefore, variations in connection resistance between the via and the lower layer Cu wiring can be suppressed, and the reliability of the semiconductor device can be improved.

  Moreover, this invention has a lower layer Cu wiring and the laminated structure formed on the said lower layer Cu wiring, and the said laminated structure contains a silicon | silicone (Si) and carbon (C). And an SiOCH film as a wiring insulating film formed on the cap insulating film, and the SiOCH film has an atomic composition ratio (C / Si) between C and Si in the SiOCH film of the SiOCH film. A carbon-rich SiOCH film having a C / Si atomic composition ratio (C / Si) larger than ½ in the cap insulating film, and the laminated structure includes a plurality of via holes including via holes having different opening diameters. The Cu dual damascene wiring connected to the lower Cu wiring is formed in each via hole so as to reach the lower Cu wiring, and is connected to each Cu dual damascene wiring. The surface composition of the lower layer Cu wiring is to provide a semiconductor device which is a homogeneous without depending on the opening diameter of each via hole that.

  According to the present invention, when the SiOCH film is used as the wiring insulating film, the processing controllability of the via hole is sufficiently obtained regardless of the opening diameter of the via hole, and as a result, the variation in the composition of the surface of the lower layer Cu wiring is obtained. Sufficient suppression can be easily performed.

It is a cut end view for demonstrating the via hole formation process in the manufacturing method of the semiconductor device which concerns on embodiment. It is a cut end view for demonstrating the mechanism of the via-hole formation process in the manufacturing method of the semiconductor device which concerns on embodiment. It is a cut end view for demonstrating a series of processes of the manufacturing method of the semiconductor device concerning an embodiment. It is a schematic diagram of the film-forming apparatus used with the manufacturing method of the semiconductor device which concerns on embodiment. It is a diagram showing a pattern dependency of the etching rate according to the flow rate of O ₂ in the etching gas. It is a figure for demonstrating the effect (resolution of pattern dependence) by embodiment. Is a diagram showing an etching rate corresponding to the flow rate of CF ₄ in the etching gas. It is a figure which shows the relationship between the carbon concentration ratio of a wiring insulating film (SiOCH film) and a cap insulating film, and an etching selection ratio.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

[First Embodiment]
FIG. 1 is a cut end surface of a main part of a semiconductor device for explaining a via hole forming step in the method for manufacturing a semiconductor device according to the embodiment. FIG. 2 is a cut end view of the main part of the semiconductor device for explaining the mechanism of the via hole forming step in the method of manufacturing a semiconductor device according to the embodiment. FIG. 3 is a cross-sectional end view of the main part of the semiconductor device for explaining a series of steps of the method for manufacturing the semiconductor device according to the embodiment. FIG. 4 is a schematic view of a film forming apparatus such as a SiOCH film used in the method for manufacturing a semiconductor device according to the embodiment. FIG. 5 is a diagram showing the pattern dependency of the etching rate according to the flow rate of O _{2 in} the etching gas, FIG. 6 is a diagram for explaining the effect (elimination of the pattern dependency) according to the embodiment, and FIG. 7 is the etching gas. is a diagram showing an etching rate corresponding to the flow rate of CF ₄ in.

In the method of manufacturing a semiconductor device according to the present embodiment, a plurality of via holes 8 and 9 including via holes 8 and 9 having first and second opening diameters are formed in the stacked structure 20 formed on the lower layer Cu wiring 3. A via hole forming step; The laminated structure 20 includes a cap insulating film 4 containing silicon (Si) and carbon (C), and a SiOCH film as the wiring insulating film 5 formed on the cap insulating film 4. In the via hole forming step, a plurality of via holes 8 are formed in the wiring insulating film 5 by combining the first dry etching using the first mixed gas as an etching gas and the second dry etching using the second mixed gas as an etching gas. 9 is formed. Each of the first and second mixed gases contains at least one of a CF-based gas and a CHF-based gas, and O ₂ gas. The O ₂ concentration of the first mixed gas is higher than the etching rate of the via hole 8 having the relatively large second opening diameter in which the via hole 9 having the relatively small first opening diameter out of the first and second opening diameters. Is also set to be large. The O ₂ concentration of the second mixed gas is set so that the etching rate of the via hole 8 having the second opening diameter is larger than the etching rate of the via hole 9 having the first opening diameter.
Further, the semiconductor device according to the present embodiment includes the lower layer Cu wiring 3 and the stacked structure 20 formed on the lower layer Cu wiring 3. The laminated structure 20 includes a cap insulating film 4 containing silicon (Si) and carbon (C), and a SiOCH film as the wiring insulating film 5 formed on the cap insulating film 4. The SiOCH film is a carbon whose atomic composition ratio (C / Si) between C and Si in the SiOCH film is larger than ½ of the atomic composition ratio (C / Si) between C and Si in the cap insulating film 4. It is a rich SiOCH film. In the stacked structure 20, a plurality of via holes 8 and 9 including via holes 8 and 9 having different opening diameters are formed to a depth that reaches the lower layer Cu wiring 3 through the stacked structure 20. In each via hole 8, 9, a Cu dual damascene wiring (metal layer 14) connected to the lower Cu wiring 3 is formed, and the surface composition of the lower Cu wiring 3 in contact with each Cu dual damascene wiring is different from each via hole 8, 9. It is homogeneous without depending on the opening diameter.

FIG. 5 shows the pattern dependence of the etching rate for the SiOCH film according to the flow rate of O _{2 in} the etching gas. As shown in FIG. 5, the etching rate for the SiOCH film depends on the O ₂ concentration in the etching gas. In other words, the etching rate for the SiOCH film depends on the O concentration in the plasma. In addition, the etching rate corresponding to the opening diameter of the via holes 8 and 9 (see FIG. 1) formed by dry etching is reversed depending on the O ₂ concentration in the etching gas (in the example of FIG. 5, the O ₂ flow rate is about With a boundary of 15 sccm as a boundary, the etching rate of via hole 8 having a relatively large opening diameter (large opening diameter in FIG. 5) and the etching rate of via hole 9 having a relatively small opening diameter (small opening diameter in FIG. 5). ) Is reversed). In the manufacturing method of the semiconductor device according to the present embodiment, the via holes 8 and 9 are formed to a uniform depth by dry etching using such dependency.

  Here, in etching, oxygen generated from the SiOCH film by etching is also used as an etchant. As shown in FIG. 2, the finer pattern (pattern with a smaller opening diameter) has a narrower interval between the side walls, and the generated O (active oxygen 21 in FIG. 2) is concentrated. That is, in the comparison between the via hole 8 having a relatively large opening diameter (FIG. 2A) and the via hole 9 having a relatively small opening diameter (FIG. 2B), the latter was generated by etching. Active oxygen (oxygen ions or oxygen radicals) 21 is concentrated in the via hole 8. For this reason, in the fine pattern, the etching by the active oxygen 21 generated from the via bottom and the via sidewall proceeds more.

  When the supply amount of the active oxygen (oxygen ions or oxygen radicals) 22 from the etchant gas to the pattern having a large opening diameter (via hole 8) is A, the opening diameter of the fine pattern (via hole 9) is small, so that the active oxygen 22 Although the supply amount is smaller than A and αA (α <1), active oxygen 21 that is an etching product of the SiOCH film is also used as an etchant, so that active oxygen that can be used for etching in a fine pattern (via hole 9) is used. The amount of 21 and 22 is larger than the supply amount A (becomes αA + β), and the etching rate is improved.

  Further, since the etchant generated inside the pattern is used, the etching rate can be made constant regardless of the density difference of the patterns as long as the patterns have the same opening area.

  In the case of the present embodiment, for example, the first dry etching (FIG. 1A) and the second dry etching (FIG. 1B) are performed in this order to form the via holes 8 and 9 (via hole forming step). I do).

Of these, in the first dry etching (FIG. 1A), the flow rate of O ₂ in the etching gas is reduced, and the amount of active oxygen 21 and 22 used as an etchant in a pattern having a small opening diameter is reduced. By increasing the amount per unit volume of active oxygen 21 and 22 used as an etchant in a pattern with a large aperture, the etching rate for a pattern with a small aperture is made larger than that for a pattern with a large aperture. This controls the difference in etching rate between patterns due to the microloading effect. In the first dry etching, the via hole 9 having a relatively small opening diameter reaches the cap insulating film 4 or the cap insulating film 4 without considering the film thickness distribution of the SiOCH film and the etching rate distribution due to the microloading effect. This is done until reaching the vicinity of.

On the other hand, in the second dry etching (FIG. 1B), the O ₂ flow rate is increased as compared with the first dry etching, and the unit volumes of the active oxygens 21 and 22 used as the etchant in the pattern having a large opening diameter. By making the hit amount larger than the amount per unit volume of the active oxygens 21 and 22 used as the etchant in the pattern having a small opening diameter, the etching rate in the pattern having a large opening diameter can be increased. Make it bigger. For this reason, by performing the second dry etching, the etching with the pattern with the large opening diameter proceeds faster than the etching with the pattern with the small opening diameter, and the etching depth in the pattern with the large opening diameter is increased. Catch up with the etching depth of small-diameter patterns.

  In other words, after correcting the imbalance of the etching rate generated in the second dry etching in advance by the first dry etching, the etching depth after the second dry etching is set to the opening diameter by performing the second dry etching. It is possible to make the same level regardless of

  As described above, by combining the first dry etching and the second dry etching, it is possible to cancel the pattern difference, and it is possible to achieve both processing controllability and uniformity.

Note that the etching gas (first mixed gas and second mixed gas) is not only O ₂ gas but also CF gas (for example, CF ₄ ) and CHF gas (for example, CHF ₃ , CH ₂ F ₂ ). At least one of them). Further, the etching gas (first mixed gas and second mixed gas) contains, for example, at least one of Ar and N ₂ . More specifically, the etching gas can be, for example, a mixed gas containing Ar and N ₂ as main components and further containing CF ₄ and O ₂ . Via holes 8 and 9 can be formed by etching Si, C, and H constituting the SiOCH film with N ₂ , CF ₄ , and O ₂ gases.

  Hereinafter, the manufacturing method of the semiconductor device according to the present embodiment will be described in more detail.

  As shown in FIG. 3A, a lower layer Cu wiring 3 is formed on a silicon substrate (not shown) by, for example, a single damascene method. That is, an SiOCH wiring interlayer film 1 is formed on a silicon substrate, a barrier metal 2 and a lower layer Cu wiring 3 are formed in a groove formed in the SiOCH wiring interlayer film 1, and then an excess barrier metal 2 and CMP are formed by CMP. The lower Cu wiring 3 is removed.

  Thereafter, a cap insulating film 4 covering the lower layer Cu wiring 3 is formed. The cap insulating film 4 contains, for example, silicon (Si) and carbon (C) as main components. That is, the cap insulating film 4 contains silicon (Si) and carbon (C), for example, 20 atomic% or more in total. Specifically, the cap insulating film 4 can be a SiCN film, for example. However, the cap insulating film 4 is not limited to this example, and may be a SiC film or a laminated film of a SiCN film and a SiC film. Further, the cap insulating film 4 may be a silica carbon composite film having an unsaturated hydrocarbon film and an amorphous carbon film, or a laminated film of this silica carbon composite film and a SiCN film or a SiC film. Alternatively, a laminated film of this silica carbon composite film, a SiCN film and a SiC film may be used.

Next, as shown in FIG. 3B, a wiring insulating film 5 for forming an upper Cu wiring is formed on the cap insulating film 4. The wiring insulating film 5 has an atomic composition ratio (C / Si) of C and Si in the SiOCH film constituting the wiring insulating film 5 such that the atomic composition ratio of C and Si in the cap insulating film 4 ( It is a carbon-rich SiOCH film that is larger than 1/2 of (C / Si). Next, a SiO ₂ hard mask 6 is formed on the wiring insulating film 5. The cap insulating film 4, the wiring insulating film 5, and the SiO ₂ hard mask 6 can be sequentially formed by, for example, a CVD method.

  Here, the atomic composition ratio of SiCN constituting the cap insulating film 4 can be, for example, Si: C: N = 1: 0.45: 1.58, and the carbon-rich SiOCH constituting the wiring insulating film 5 The atomic composition ratio of the film can be, for example, Si: C: O = 1: 2.7: 0.9. Therefore, in this case, the atomic composition ratio (C / Si) of C and Si in the wiring insulating film 5 is 2.7, and the atomic composition ratio of C and Si in the cap insulating film 4 (C / Si). Is 0.45, “the atomic composition ratio (C / Si) of C and Si in the SiOCH film (wiring insulating film 5) is the atomic composition ratio of C and Si (C / Si in the cap insulating film 4). The condition “greater than ½ of Si)” is satisfied. Furthermore, in this case, the condition that the atomic composition ratio (C / Si) of C and Si in the SiOCH film (wiring insulating film 5) is larger than 1 is also satisfied.

  When the atomic composition ratio (C / Si) of C and Si in the SiOCH film (wiring insulating film 5) is larger than 1, that is, when the C content in the wiring insulating film 5 is large, the wiring insulating film 5 Since the etching reaction with respect to oxygen gas becomes remarkable, it becomes easy to control the etching rate using oxygen as an etching product. For this reason, it is preferable that the atomic composition ratio (C / Si) of C and Si in the SiOCH film (wiring insulating film 5) is larger than 1.

  Further, in the range where the atomic composition ratio (C / Si) between C and Si in the SiOCH film (wiring insulating film 5) is larger than 1, the higher the C concentration in the SiOCH film (wiring insulating film 5), Since the difference in composition between the cap insulating film 4 and the wiring insulating film 5 is increased, the etching selectivity between the wiring insulating film 5 and the cap insulating film 4 is improved, and the processing selectivity is improved.

  Further, as the SiOCH film constituting such a wiring insulating film 5, there is a SiOCH film having a plurality of holes (porous SiOCH film) having an average diameter of these holes of less than 0.8 nm. Can be mentioned. In addition, it is preferable that each hole is arrange | positioned mutually independently.

  Such a wiring insulating film 5 can be formed by, for example, a plasma CVD method using a film forming apparatus shown in FIG. Among the configurations of the film forming apparatus, the reservoir 101 is a container for supplying a monomer material constituting the wiring insulating film 5. The raw material pressure feeding unit 102 pressurizes with a pressure feed gas in order to send out the monomer raw material in the reservoir 101. As this pressurized gas, for example, He is used. The liquid mass flow controller 104 is a device that controls the flow rate of the monomer raw material supplied from the reservoir 101. The vaporizer 106 is a device that vaporizes the monomer raw material supplied from the reservoir 101 via the liquid mass flow controller 104. The carrier gas supply unit 103 supplies a carrier gas (for example, He) that transports the monomer raw material (raw material gas) vaporized by the vaporizer 106. The gas mass flow controller 105 is a device that controls the flow rate of the carrier gas supplied from the carrier gas supply unit 103 to the vaporizer 106. The reaction vessel (reactor) 107 is a vessel for forming a carbon-rich SiOCH film constituting the wiring insulating film 5 on the substrate 108 by plasma polymerizing the source gas. An RF (Radio Frequency) power source 109 is a device that supplies electric power for converting the source gas and the carrier gas into plasma. The substrate 108 is a semiconductor substrate (semiconductor wafer (hereinafter referred to as wafer)) formed by chemical vapor deposition. The exhaust pump 110 is an apparatus that exhausts the source gas and the carrier gas from the reaction vessel 107.

  Hereinafter, a process for forming a carbon-rich SiOCH film using the film forming apparatus of FIG. 4 will be described. As the monomer raw material, for example, a raw material having a cyclic organic silica structure represented by the following general formula (Formula 1) is used. Here, R1 and R2 are an unsaturated carbon compound containing a vinyl group or a saturated carbon compound containing an alkyl group, and the vinyl group is any one of a methyl group, an ethyl group, a propyl group, an isopropyl group, and a butyl group. The alkyl group is also a methyl group, an ethyl group, a propyl group, an isopropyl group, or a butyl group. R1 and R2 may be the same as or different from each other.

  More specifically, the cyclic organic silica structure is, for example, a structure represented by the following formula (Formula 2) or (Formula 3).

  The monomer raw material is sent out from the reservoir 101 by the pumping gas pumped from the raw material pumping unit 102, and the flow rate thereof is controlled by the liquid mass flow controller 104. On the other hand, carrier gas is supplied from the carrier gas supply unit 103, and the flow rate is controlled by the gas mass flow controller 105. For example, the monomer material and the carrier gas are mixed with each other immediately before the vaporizer 106 and then introduced into the vaporizer 106. A heated heater block (not shown) exists in the vaporizer 106, and the liquid monomer raw material is vaporized in the heater block and introduced into the reaction vessel 107. In the reaction vessel 107, the vaporized monomer raw material and carrier gas are turned into plasma by high frequency power of 13.56 MHz, for example, and a carbon-rich SiOCH film is formed on the substrate 108 by plasma polymerization. The supply amount of the raw material monomer is preferably 0.1 g / min or more and 10 g / min or less, and more preferably 2 g / min or less. The supply amount of He as a carrier gas is preferably 50 sccm or more and 5000 sccm or less, and more preferably 2000 sccm or less. The pressure in the reaction vessel 107 is preferably 133 to 1333 Pa. The output of the RF power source 109 is preferably 2000 W or less, and more preferably 1000 W or less.

Thus, the wiring insulating film 5 can be formed. The cap insulating film 4, the wiring insulating film 5, and the SiO ₂ hard mask 6 can be continuously formed using, for example, a film forming apparatus shown in FIG.

Next, as shown in FIG. 3B, a resist mask 7 is formed in a predetermined pattern shape on the SiO ₂ hard mask 6. The resist mask 7 has openings with various inner diameters corresponding to the opening diameters of the via holes 8 and 9 formed in a later process.

Next, by dry etching the underlying film (SiO ₂ hard mask 6, wiring insulating film 5, and cap insulating film 4) of the resist mask 7 through the resist mask 7, via holes 8 having different opening diameters, A plurality of via holes 8 and 9 including 9 are formed.

Dry etching for forming the via holes 8 and 9 is performed using a mixed gas containing O ₂ as an etching gas. Specifically, this dry etching is performed by combining the first dry etching using the first mixed gas and the second dry etching using the second mixed gas. Among the first and second mixed gases, the first mixed gas is relatively so that the etching rate of the via hole 9 having a relatively small opening diameter is larger than the etching rate of the via hole 8 having a relatively large opening diameter. Is set to a low O ₂ concentration. Conversely, the second mixed gas has a relatively high O ₂ concentration so that the etching rate of the via hole 8 having a relatively large opening diameter is larger than the etching rate of the via hole 9 having a relatively small opening diameter. Is set.

  In the case of this embodiment, for example, as shown in FIG. 3C, first, dry etching that can preferentially form the via hole 9 having a relatively small opening diameter is performed. This first dry etching is performed until the via hole (for example, via hole 9) having the smallest opening diameter among the plurality of via holes 8 and 9 reaches the cap insulating film 4 or reaches the vicinity of the cap insulating film 4. . At this stage, the bottom of the via hole 8 having a relatively larger opening diameter than the via hole 9 is located (shallow) above the bottom of the via hole 9. FIG. 3C shows a state in which the first dry etching is performed until the via hole having the smallest opening diameter (for example, the via hole 9) reaches the cap insulating film 4.

  Next, for example, as shown in FIG. 3D, second dry etching is performed in which the via hole 8 having a relatively large opening diameter can be formed preferentially. This second dry etching is performed until the over-etching that reaches the cap insulating film 4 occurs in the etching of the via holes 8 and 9 (until a part of the cap insulating film 4 is also etched).

In the second dry etching, since the etching rate of the via hole 8 having a large opening diameter is larger than the etching rate of the via hole 9 having a small opening diameter, the depth of the via hole 8 is reduced during the over etching of the via hole 9. The via hole 8 can be over-etched. As a result, as shown in FIG. 3D, the overetching amounts of the via holes 8 and 9 can be made substantially equal to each other. In order to make the overetching amounts of the via holes 8 and 9 after the second dry etching similar to each other in this way, the composition of the first and second mixed gases (especially O ₂ concentration) and the first dry etching The ratio of the length of time for performing the etching and the length of time for performing the second dry etching may be appropriately set.

  By etching the via holes 8 and 9 by combining the first dry etching and the second dry etching in this way, processing controllability and pattern uniformity equivalent to the case of using a low carbon concentration SiOCH film as a wiring insulating film are realized. can do.

  Here, when etching a carbon-rich SiOCH film (for example, the atomic composition ratio (C / Si) of C and Si in the carbon-rich SiOCH film is larger than 1), the oxygen concentration in the etching gas is The higher the etching selectivity of the wiring insulating film 5 relative to the cap insulating film 4 is, the higher it is. Therefore, in the second dry etching, the etching rate of overetching performed in the via hole 9 having a relatively small opening diameter can be reduced, while the carbon-rich SiOCH film formed in the via hole 8 having a relatively large opening diameter is used. Since the etching rate can be increased, the overetching amounts of the via holes 8 and 9 can be preferably made equal to each other. In this case, in the first dry etching, the etching amount can be set without considering the film thickness distribution of the carbon-rich SiOCH film and the etching rate distribution due to the microloading effect. Further, it can be said that the second dry etching in this case includes a step of performing overetching for correcting the film thickness distribution of the SiOCH film and the etching rate distribution due to the microloading effect. That is, in the second dry etching, for example, while performing over-etching in a pattern with a small opening diameter, etching with a pattern with a large opening diameter proceeds, and the etching depth in the pattern with a large opening diameter is the opening diameter. Keep up with the etching depth of small patterns.

  In other words, after correcting the imbalance of the etching rate generated in the second dry etching in advance by the first dry etching, the etching depth after the second dry etching is set to the opening diameter by performing the second dry etching. It is possible to make the same level regardless of

  Next, cap openings 11 and 12 (FIG. 3E) are formed in the cap insulating film 4 by performing dry etching using an etching gas having a composition different from that of the first and second mixed gases. The etching gas used here is a gas that increases the etching selectivity of the cap insulating film 4 to the SiOCH film.

  By forming the cap openings 11 and 12 in this way, the surface of the lower layer Cu wiring 3 is exposed through the cap insulating film 4. Here, before the dry etching for forming the cap openings 11 and 12 is performed, the thickness of the remaining film of the cap insulating film 4 located at the bottom of the via holes 8 and 9 is the opening diameter of the via holes 8 and 9. It is equivalent regardless of. For this reason, the cap opening 11 immediately below the via hole 8 having a large opening diameter and the cap opening 12 directly below the via hole 9 having a small opening diameter are opened almost simultaneously. Therefore, the amount of overetching and damage received by the lower layer Cu wiring 3 due to the dry etching for forming the cap openings 11 and 12 are equal regardless of the opening diameters of the via holes 8 and 9. Therefore, the surface composition and the surface shape of the lower layer Cu wiring 3 are uniform without depending on the opening diameters of the via holes 8 and 9.

  Next, as shown in FIG. 3E, after removing the resist mask 7, a resist mask 10 for forming a wiring groove is formed by a photolithography method. Next, as shown in FIG. 3F, wiring trenches 16 and 17 are formed by dry etching the wiring insulating film 5 through the resist mask 10, and then the resist mask 10 is removed.

  Next, Cu oxide, etching products, and the like on the surface of the lower layer Cu wiring 3 are removed through the via holes 8 and 9 and the cap openings 11 and 12 by chemical treatment, and the surface is cleaned. The chemical solution used for this chemical treatment preferably contains fluorine. As described above, the amount of over-etching of the lower layer Cu wiring 3 through the cap openings 11 and 12 is the same over the entire surface of the wafer regardless of the opening diameters and densities of the via holes 8 and 9. For this reason, the cleaning effect by the chemical treatment is also the same over the entire surface of the wafer regardless of the opening diameter and density of the via holes 8 and 9. Therefore, even at this stage, the surface composition and surface shape of the lower layer Cu wiring 3 immediately below the cap openings 11 and 12 are uniform in the wafer plane regardless of the opening diameter and density of the via holes 8 and 9.

  In the present embodiment, since the surface composition and surface shape of the lower layer Cu wiring 3 immediately below the cap openings 11 and 12 can be controlled in this way, a via (a part of a metal layer 14 described later) and a lower layer can be controlled. It is possible to suppress variation in resistance at the connection portion with the Cu wiring 3.

Next, as shown in FIG. 3G, a barrier metal 13 having a stacked structure of a TaN film and a Ta film is formed on the entire surface of the wafer by ionization sputtering, and a Cu thin film ( (Not shown). Next, the metal layer 14 made of Cu or Cu alloy is embedded by electroplating using this Cu thin film as an electrode. Thereafter, after heat treatment for Cu grain growth, as shown in FIG. 3 (h), the excess metal layer 14, the barrier metal 13 and the SiO ₂ hard mask 6 are removed by CMP, and the wiring insulating film 5 is formed. Expose the surface. In this way, a via and an upper layer Cu wiring can be formed. That is, portions of the metal layer 14 embedded in the via holes 8 and 9 constitute a via, and portions embedded in the wiring grooves 16 and 17 constitute an upper layer Cu wiring.

  Next, as shown in FIG. 3I, a cap insulating film 15 is formed on the metal layer 14 and the wiring insulating film 5. The cap insulating film 15 can be made of the same material as the cap insulating film 4, and can be, for example, a SiCN film. In this way, a semiconductor device having two wiring layers of the lower layer Cu wiring 3 and the upper layer Cu wiring (the metal layer 14 in the wiring grooves 16 and 17) can be manufactured.

  Here, as the state of the surface layer of the lower layer Cu wiring 3 under the via holes 8 and 9, the TEM-EELS (TEM: Transmission Electron Microscope) and the electron energy are used for the composition, the oxidation state, and the impurity concentration such as carbon. It can be observed by loss spectroscopy (EELS: Electron Energy-Loss Spectroscopy). When such an observation is performed on the semiconductor device manufactured by the manufacturing method according to the present embodiment, the via hole 8 having a large opening diameter such as a slit via or a ring seal is directly below each of the via holes 8 and 9. It can be observed that the composition of the surface layer of the lower Cu wiring 3 is almost uniform.

  Hereinafter, a more specific example of the semiconductor device manufacturing method according to the present embodiment as described above will be described.

First, the carbon-rich SiOCH film as the wiring insulating film 5 is formed by using the raw material including the cyclic organic silica structure shown in the above formula (Formula 2) so as to have a film thickness of 200 nm (see FIG. 4). It is formed by a plasma CVD method using The relative dielectric constant of the carbon-rich SiOCH film is 2.5. After the wiring insulating film 5 is formed in this way, a He plasma treatment is subsequently performed in the same film forming apparatus (FIG. 4) for a treatment time of 15 to 30 seconds. This He plasma treatment is performed for the purpose of forming a surface modification layer on the surface layer of the wiring insulating film 5. Further, subsequently, a SiO ₂ film having a thickness of 200 nm is formed as a SiO ₂ hard mask 6 by the plasma CVD method using SiH ₄ as a source gas in the same film forming apparatus (FIG. 4). Alternatively, TEOS (tetraethoxysilane) may be used as a source gas for forming the SiO ₂ film. The formation of the surface modification layer by the He plasma treatment and the film formation of the SiO ₂ hard mask 6 may be performed by different film forming apparatuses. Next, a resist mask 7 for processing a via hole is formed by photolithography (FIG. 3B).

  Next, via holes 8 and 9 are formed by dry etching (a via hole forming step is performed).

In this via hole forming step, first, the first dry etching is performed at a low oxygen flow rate (a condition where the oxygen flow rate is lower than that of the second dry etching), and the via hole 9 having a high etching rate is formed until the cap insulating film 4 is reached. In FIG. 3C, the via holes 8 and 9 have an isolated sparse pattern, but may be a dense pattern in which a plurality of via holes 8 and 9 are densely packed. Etching conditions for the first dry etching are, for example, Ar: 400 to 800 sccm, N ₂ : 100 to 500 sccm, CF ₄ : 20 to 60 sccm, O ₂ : 5 to 15 sccm, pressure: 15 to 30 mtorr, RF power: 500 to 1500 W. Time: It is preferable to set to 10 to 60 seconds. The O ₂ concentration in the etchant gas used in the first dry etching is less than 1.2% by volume.

Next, second dry etching at a high oxygen flow rate (conditions where the oxygen flow rate is higher than that of the first dry etching) is performed until the cap insulating film 4 is over-etched, for example, by about 5 to 15 nm at the bottom of each via hole 8 and 9. Perform (FIG. 3D). Here, the etching conditions with a high oxygen flow rate have a higher etching selectivity between the SiOCH film and the cap insulating film 4 than the etching conditions with a low oxygen flow rate. That is, the SiOCH film is preferentially etched over the cap insulating film 4. For this reason, contrary to the step of FIG. 3C, the etching rate of the via hole 8 having a large opening diameter is large. As a result, the etching depths of the via hole 8 and the via hole 9 having different opening diameters are aligned. Etching conditions for the second dry etching are, for example, Ar: 400 to 800 sccm, N ₂ : 100 to 500 sccm, CF ₄ : 20 to 60 sccm, O ₂ : 16 to 30 sccm, pressure: 15 to 30 mtorr, RF power: 500 to 1500 W. Time: It is preferable to set to 10 to 60 seconds. The O ₂ concentration in the etchant gas used in the second dry etching is 1.2% by volume or more.

  Here, the cap insulating film 4 is, for example, either a SiCN film or a SiC film, or a laminated film thereof. Alternatively, the cap insulating film 4 may be a silica-carbon composite film (SCC: Silica-carbon-composite) having an unsaturated hydrocarbon film and an amorphous carbon film, and the silica-carbon composite film and the SiCN film or A laminated film of an SiC film may be used, or a laminated film of the silica carbon composite film, an SiCN film and an SiC film may be used. Here, the SCC film is a film obtained by plasma polymerization of a linear organic silica raw material represented by the following general formula (Formula 4), and Si: O: C = 1: 1: 1.2.

ここで、Ｒは、アルキル基を含有する飽和炭素化合物であり、具体的には、例えば、メチル基、エチル基、プロピル基、イソプロピル基、ブチル基などである。

Here, R is a saturated carbon compound containing an alkyl group, and specifically, for example, a methyl group, an ethyl group, a propyl group, an isopropyl group, a butyl group, or the like.

  Next, cap openings 11 and 12 are formed in the cap insulating film 4 to expose the surface of the lower layer Cu wiring 3, and then a resist mask 10 is formed, and the wiring insulating film is formed by dry etching through the resist mask 10. 5, wiring grooves 16 and 17 are formed (FIGS. 3E and 3F).

  Next, the surface of the lower layer Cu wiring 3 is cleaned through the via holes 8 and 9 and the cap openings 11 and 12 by a chemical treatment using a chemical solution containing fluorine.

  Next, a TaN film, a Ta metal barrier metal 13 and a Cu thin film (not shown) are formed on the entire surface of the wafer by ionization sputtering, and Cu or Cu alloy is formed by electroplating using this Cu film as an electrode. The metal layer 14 is embedded (FIG. 3G).

Next, heat treatment is performed at 350 ° C. for 2 minutes in a nitrogen atmosphere for Cu grain growth, and then the excess metal layer 14 is removed by CMP. Then, the surplus barrier metal 13 and the SiO ₂ hard mask 6 are removed by CMP by changing the slurry and the polishing head, and the surface of the wiring insulating film 5 is exposed (FIG. 3H).

  Next, a film (for example, a SiCN film) of the same material as the cap insulating film 4 is formed as a cap insulating film 15 on the entire surface of the metal layer 14 and the wiring insulating film 5 (FIG. 3I). In this way, a semiconductor device having a two-layer wiring layer of the lower layer Cu wiring 3 and the upper layer Cu wiring (the metal layer 14 in the wiring grooves 16 and 17) using the carbon-rich SiOCH film as the wiring insulating film 5 can be manufactured. it can.

  Here, the carbon-rich SiOCH film constituting the wiring insulating film 5 is preferably one having a high C content. Specifically, the atomic composition ratio (C / Si) between C and Si in the carbon-rich SiOCH film is preferably 1 or more. A film having a high C content has a remarkable etching reaction with respect to oxygen gas, and it becomes easy to control the etching rate using oxygen as an etching product. Further, the difference in carbon composition with respect to the cap insulating film 4 becomes large. That is, the atomic composition ratio (C / Si) of C and Si in the wiring insulating film 5 >> the atomic composition ratio of C and Si in the cap insulating film 4 (C / Si) × 1/2. Since the etching selectivity between the film 5 and the cap insulating film 4 is improved, the processing selectivity is improved.

FIG. 5 shows respective etching rates when the via holes 8 and 9 having different opening diameters are simultaneously dry-etched. From FIG. 5, when the oxygen flow rate is about 15 sccm or more, the larger opening diameter (via hole 8) has a larger etching rate, and when the oxygen flow rate is less than about 15 sccm, the smaller opening diameter (via hole 9) has a larger etching rate. It can be seen that the etching rate of the large opening diameter (via hole 8) and the small opening diameter (via hole 9) are interchanged at a portion of about 15 sccm. Etching conditions other than the oxygen flow rate at this time are, for example, Ar: 800 sccm, N ₂ : 400 sccm, CF ₄ : 60 sccm, pressure: 30 mtorr, and RF power: 500 to 1200 W. Under this condition, the oxygen flow rate of 15 sccm is 1.2% by volume of the whole. Further, FIG. 6 is a photograph showing a cross section when the via holes having different opening diameters are simultaneously dry-etched under this condition and with an oxygen flow rate of 15 sccm. FIG. 6 shows that the etching rate is the same regardless of the opening diameter of the via hole.

Next, referring to FIG. 7, in the above-described first dry etching (dry etching in which the etching rate of via hole 9 having a low oxygen flow rate and a small opening diameter is larger than the etching rate of via hole 8), A case where the flow rate is 10 sccm will be described. FIG. 7 shows the etching rate of the SiOCH film when the oxygen flow rate is fixed at 10 sccm and the CF ₄ flow rate is changed. It can be seen that when the oxygen flow rate is fixed, the etching rate is saturated when the CF ₄ flow rate exceeds the reference value. When the atomic composition ratio (C / Si) between C and Si in the SiOCH film exceeds 1, both O and F are required for etching the SiOCH film, and when either is insufficient, C or Si remains. As a result, the etching rate does not increase. By using this phenomenon and controlling the amount of O in the via hole by using O as an etching product, the etching rate changes between patterns even if there is a difference in the amount of CF ₄ supplied between the patterns. do not do. Therefore, even when the pattern opening diameter and density are different, the etching rate in via hole processing can be controlled.

  According to the embodiment as described above, by performing the via hole forming step by appropriately combining the first dry etching using the first mixed gas and the second dry etching using the second mixed gas, The etching depths of the via hole 9 having a small opening diameter and the via hole 8 having a relatively large opening diameter can be made uniform. That is, by performing the first dry etching and the second dry etching in an appropriate combination, the processing controllability of the via holes 8 and 9 when the SiOCH film is used as the wiring insulating film 5 is set to the opening diameter of the via holes 8 and 9. Regardless, it can be secured sufficiently. Thereby, the variation of the composition of the surface of the lower layer Cu wiring 3 located in the lower layer of the via holes 8 and 9 can be reduced. Therefore, variation in connection resistance between the via and the lower layer Cu wiring 3 can be suppressed, and the reliability and yield of the semiconductor device can be improved.

  That is, for example, as shown in FIG. 3D, even if the via holes 8 and 9 have an in-plane distribution of opening diameters, the lower layer Cu wiring 3 is surely connected to the cap insulating film immediately after the formation of the via holes 8 and 9. By being protected by 4, it is possible to suitably suppress surface oxidation and contamination by carbon to the lower layer Cu wiring 3 immediately below the via holes 8 and 9.

  In particular, when the atomic composition ratio (C / Si) of C and Si in the carbon-rich SiOCH film constituting the wiring insulating film 5 is larger than 1, a semiconductor device with low power consumption and high reliability can be obtained with high yield. While being able to manufacture, the etching selectivity of the wiring insulating film 5 with respect to the cap insulating film 4 can be improved.

  In addition, the semiconductor device manufacturing method according to the present embodiment includes the lower layer Cu wiring 3 and the stacked structure 20 formed on the lower layer Cu wiring 3. The stacked structure 20 includes silicon (Si) and carbon. A cap insulating film 4 containing (C) and a SiOCH film as a wiring insulating film 5 formed on the cap insulating film 4, and this SiOCH film is composed of C and Si in the SiOCH film. Is a carbon-rich SiOCH film whose atomic composition ratio (C / Si) is larger than 1/2 of the atomic composition ratio (C / Si) of C and Si in the cap insulating film 4. A plurality of via holes 8 and 9 including via holes 8 and 9 having different opening diameters are formed to a depth reaching the lower layer Cu wiring 3 through the laminated structure 20, and the lower layer Cu wiring 3 is formed in each via hole 8 and 9. Cu dual dashes connected to A semiconductor device in which a thin wiring (metal layer 14) is formed and the surface composition of the lower Cu wiring 3 in contact with each Cu dual damascene wiring (metal layer 14) is uniform without depending on the opening diameters of the via holes 8 and 9 Can be manufactured. Conversely, it can be said that the semiconductor device having such characteristics has a high probability of being manufactured by the method of manufacturing a semiconductor device according to the present embodiment.

  In the above embodiment, an example in which the wiring layer has only two layers of the lower layer Cu wiring and the upper layer Cu wiring has been described, but it is needless to say that there may be three or more layers.

DESCRIPTION OF SYMBOLS 1 SiOCH wiring interlayer film 2 Barrier metal 3 Lower layer Cu wiring 4 Cap insulating film 5 Wiring insulating film 6 SiO ₂ hard mask 7 Resist mask 8 Via hole 9 Via hole 10 Resist mask 11 Cap opening part 12 Cap opening part 13 Barrier metal 14 Metal layer 15 Cap insulating film 16 Wiring groove 17 Wiring groove 20 Laminated structure 21 Active oxygen 22 Active oxygen 101 Reservoir 102 Raw material pumping section 103 Carrier gas supply section 104 Liquid mass flow controller 105 Gas mass flow controller 106 Vaporizer 107 Reaction vessel 108 Substrate 109 RF power supply 110 Exhaust pump

Claims (17)

A via hole forming step of forming a plurality of via holes including via holes having first and second opening diameters in the laminated structure formed on the lower layer Cu wiring;
The stacked structure includes a cap insulating film containing silicon (Si) and carbon (C), and a SiOCH film as a wiring insulating film formed on the cap insulating film,
In the via hole forming step, the first dry etching using a first mixed gas as an etching gas and the second dry etching using a second mixed gas as an etching gas are combined to form the plurality of via holes in the wiring insulating film. Form the
Each of the first and second mixed gases contains at least one gas of CF-based gas and CHF-based gas, and O ₂ gas,
The O ₂ concentration of the first mixed gas is higher than the etching rate of a via hole having a relatively large second opening diameter, which is a relatively small first opening diameter of the first and second opening diameters. Is set to be large,
The O ₂ concentration of the second mixed gas is set so that the etching rate of the via hole having the second opening diameter is larger than the etching rate of the via hole having the first opening diameter. Manufacturing method. In the via hole forming step, the first dry etching and the second dry etching are performed in this order,
The first dry etching is performed until the via hole having the first opening diameter reaches the cap insulating film or reaches the vicinity of the cap insulating film,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the second dry etching is performed until an over-etching of the cap insulating film occurs in each via hole.   The SiOCH film as the wiring insulating film has an atomic composition ratio (C / Si) of C and Si in the SiOCH film of an atomic composition ratio (C / Si) of C and Si in the cap insulating film. The method for manufacturing a semiconductor device according to claim 1, wherein the film is a carbon-rich SiOCH film larger than ½. The O ₂ concentration in the first mixed gas is less than 1.2% by volume;
4. The method of manufacturing a semiconductor device according to claim 1, wherein the O ₂ concentration in the second mixed gas is 1.2% by volume or more. 5. 5. The method of manufacturing a semiconductor device according to claim 1, wherein each of the first and second mixed gases contains at least one of Ar and N ₂ .   6. The method of manufacturing a semiconductor device according to claim 1, wherein an atomic composition ratio (C / Si) of C and Si in the SiOCH film is larger than 1. 6. The SiOCH film has a plurality of holes,
The method for manufacturing a semiconductor device according to claim 1, wherein an average diameter of the holes is less than 0.8 nm.   The method for manufacturing a semiconductor device according to claim 7, wherein the holes of the SiOCH film are arranged independently of each other.   9. The method of manufacturing a semiconductor device according to claim 1, wherein the cap insulating film is one of a SiCN film and a SiC film, or a laminated film thereof. . The cap insulating film is
A silica carbon composite film having an unsaturated hydrocarbon film and an amorphous carbon film,
A laminated film of the silica carbon composite film and a SiCN film or a SiC film,
Alternatively, the semiconductor device manufacturing method according to claim 1, wherein the semiconductor device is a laminated film of the silica carbon composite film, a SiCN film, and a SiC film. 11. The method of manufacturing a semiconductor device according to claim 1, wherein the SiOCH film has a cyclic organic silica structure represented by the following general formula (formula 1).

Here, R1 and R2 are an unsaturated carbon compound containing a vinyl group or a saturated carbon compound containing an alkyl group, and the vinyl group is any one of a methyl group, an ethyl group, a propyl group, an isopropyl group, and a butyl group. The alkyl group is any one of a methyl group, an ethyl group, a propyl group, an isopropyl group, and a butyl group, and R1 and R2 may be the same as or different from each other. The method for manufacturing a semiconductor device according to claim 11, wherein the cyclic organic silica structure has a structure represented by the following formula (formula 2) or (formula 3).

Lower layer Cu wiring,
A laminated structure formed on the lower layer Cu wiring;
Have
The stacked structure includes a cap insulating film containing silicon (Si) and carbon (C), and a SiOCH film as a wiring insulating film formed on the cap insulating film,
In the SiOCH film, the atomic composition ratio (C / Si) of C and Si in the SiOCH film is larger than 1/2 of the atomic composition ratio (C / Si) of C and Si in the cap insulating film. A carbon-rich SiOCH film,
In the multilayer structure, a plurality of via holes including via holes having different opening diameters are formed to a depth reaching the lower layer Cu wiring through the multilayer structure, and connected to the lower layer Cu wiring in each via hole. Cu dual damascene wiring is formed,
A semiconductor device characterized in that a surface composition of the lower layer Cu wiring in contact with each Cu dual damascene wiring is uniform without depending on an opening diameter of each via hole.   14. The semiconductor device according to claim 13, wherein an atomic composition ratio (C / Si) of C and Si in the carbon-rich SiOCH film is larger than 1. The carbon-rich SiOCH film has a plurality of holes,
15. The semiconductor device according to claim 13, wherein the average diameter of the holes is less than 0.8 nm.   16. The semiconductor device according to claim 13, wherein the holes of the SiOCH film are arranged independently of each other.   The semiconductor device according to claim 13, wherein the cap insulating film is either a SiCN film or a SiC film, or a laminated film thereof.

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