JP2011009339A - Zinc oxide-based semiconductor element, and method of growing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element excellent in an element characteristic, an element life, and mass producibility by eliminating a trouble such as chipping, cracking, and separation of the element, in an element separation process.SOLUTION: A ZnO-based crystal layer having grown on a substrate of a sapphire (AlO) single crystal has a solid solution layer formed by solidly solving aluminum (Al) of the substrate in an interface with the substrate.

Description

  The present invention relates to a zinc oxide semiconductor device and a growth method thereof, and more particularly to a zinc oxide semiconductor device formed on a sapphire substrate by MOCVD and a growth method thereof.

  Zinc oxide (ZnO) is a direct transition type semiconductor having a band gap energy of 3.37 eV at room temperature, and is expected as a material for optical elements in the blue or ultraviolet region. In particular, the exciton binding energy is 60 meV and the refractive index n = 2.0, which is very suitable for a semiconductor light emitting device. Further, the present invention can be widely applied not only to light emitting elements and light receiving elements but also to surface acoustic wave (SAW) devices, piezoelectric elements, and the like. In addition, the raw material is inexpensive and harmless to the environment and the human body. In particular, it is expected to realize a semiconductor light emitting device with high efficiency and low power consumption by such a material system.

  Conventionally, when a semiconductor element is cut out from a wafer on which a semiconductor crystal layer constituting a semiconductor element is formed, an element dividing groove or a scribe groove is formed on the wafer, and the element is separated using a knife edge or the like. . For example, zincblende structure crystals such as GaAs (gallium arsenide) compound semiconductors and InP (indium phosphorous) compound semiconductors have good cleavage properties on the (110) plane. There were few. However, a wafer on which a nitride semiconductor layer having a wurtzite structure is formed has a problem that cutting defects such as cracks are likely to occur due to poor cleavage (for example, Patent Documents 1, 2, and 3). For example, Patent Document 2 discloses that in the cutting of a wafer in which a nitride semiconductor layer is formed on a sapphire substrate, split grooves are formed on the nitride semiconductor layer side and the sapphire substrate side.

  However, although it is a crystal of the same hexagonal wurtzite structure as the nitride semiconductor, a zinc oxide (ZnO) -based compound semiconductor crystal having different material properties and physical properties from the nitride semiconductor is generated during the element isolation process. The problem was not fully examined.

Japanese Patent No. 2661420 Japanese Patent No. 2780618 (2nd page, FIG. 1) JP 2003-086541 A

  The present invention has been made in view of the above-described points, and an object of the present invention is to provide an element separation process for a wafer in which a zinc oxide (ZnO) -based element structure (device layer) is formed on a sapphire substrate. An object of the present invention is to provide a semiconductor device that can eliminate defects such as chipping, cracking, and peeling, and has excellent device characteristics, device life, and mass productivity, and a growth method thereof. In particular, it is an object to provide a high-performance semiconductor light-emitting device excellent in light emission efficiency and device lifetime, and excellent in mass productivity, and a growth method thereof.

The present invention is a semiconductor element having a ZnO-based crystal layer grown on an α sapphire (Al ₂ O ₃ ) single crystal substrate and a device layer grown on the ZnO-based crystal layer,
The ZnO-based crystal layer has a solid solution layer in which aluminum (Al) of the substrate is dissolved at the interface with the substrate.

  The present invention is also a method for growing a semiconductor device in which a ZnO-based crystal layer and a device layer are grown in this order on an α-sapphire single crystal substrate, wherein the ZnO-based crystal layer is disposed on the interface with the substrate. It has a solid solution layer in which aluminum (Al) is dissolved.

  Further, the present invention is a substrate with a growth layer in which a ZnO-based crystal layer is grown on an α-sapphire single crystal substrate, and the ZnO-based crystal layer is formed by fixing aluminum (Al) of the substrate at the interface with the substrate. It is characterized by having a dissolved solid solution layer.

It is a figure which shows typically the structure of the MOCVD apparatus used for crystal growth. It is sectional drawing which shows the ZnO type | system | group semiconductor layer grown on the sapphire substrate by this invention. It is a figure which shows the crystal growth sequence used for the crystal growth by MOCVD method. It is sectional drawing which shows typically the structure of the semiconductor light-emitting device (LED) wafer which is Example 2 of this invention. It is a figure which shows the crystal growth sequence used for the crystal growth of the board | substrate with an LED device layer. It is a top view of a board | substrate with an LED device layer. It is sectional drawing which shows the outline of the element separation process of a board | substrate with an LED device layer. It is the top view and sectional drawing of a semiconductor light emitting element (LED). It is sectional drawing which shows typically the structure of the crystal growth layer of the comparative example formed by RF-MBE method. 3 is a SIMS analysis result of the crystal growth layer of Example 1. FIG. It is a figure which expands and shows the profile in the interface (X) vicinity of Al concentration and Zn ion intensity which are shown in FIG. It is a SIMS analysis result of the sample of a comparative example. It is a differential microscope image of the growth layer surface of Example 1 (EMB1). It is a SEM image of the growth layer surface of Example 1 (EMB1). These are (002) ω and (100) ω rocking curves when the thickness (t) of the ZnO layer is 1 μm. These are (002) ω and (100) ω rocking curves when the thickness (t) of the ZnO layer is 3 μm. It is a figure explaining the principle of braking at the time of forming a device layer on a sapphire substrate.

  Hereinafter, a method for manufacturing a wafer in which a zinc oxide (ZnO) -based element structure (device layer) is formed on a sapphire substrate by MOCVD will be described in detail with reference to the drawings. Further, a semiconductor light emitting element (LED: Light Emitting Diode) will be described as an example of the semiconductor element. In the drawings described below, substantially the same or equivalent parts are denoted by the same reference numerals.

  FIG. 1 schematically shows the configuration of the MOCVD apparatus 5 used for crystal growth. Details of the apparatus configuration of the MOCVD apparatus 5 will be described below. The crystal growth material will be described in detail later.

[Device configuration]
The MOCVD apparatus 5 includes a gas supply unit 5A, a reaction vessel unit 5B, and an exhaust unit 5C. 5 A of gas supply parts are comprised from the part which vaporizes and supplies organometallic compound material, the part which supplies gaseous material gas, and the transport part provided with the function to convey these gas.

  An organometallic compound material that is liquid (or solid) at room temperature is vaporized and supplied as vapor. In this example, DMZn (dimethylzinc) was used as the zinc (Zn) source, Cp2Mg (biscyclopentadienylmagnesium) was used as the magnesium (Mg) source, and TEGa (triethylgallium) was used as the gallium (Ga) source.

  First, the supply of DMZn will be described. As shown in FIG. 1, the nitrogen gas is adjusted to a predetermined flow rate by a flow rate adjusting device (mass flow controller) 121S and sent to the DMZn storage container 121C through the gas supply valve 121M to saturate the DMZn vapor in the nitrogen gas. Then, the DMZn saturated nitrogen gas is taken out through the valve 121E and the pressure adjusting device 121P to the first vent pipe (hereinafter referred to as the first VENT line (VENT1)) 128V during the growth standby, and to the first run pipe (hereinafter referred to as the first RUN) during the growth. Line (RUN1).) Supply to 128R. At this time, the internal pressure of the storage container is adjusted to be constant by the pressure adjusting device 121P. Further, the DMZn storage container is kept at a constant temperature in the thermostatic chamber 121T.

  The same applies to other organometallic compound materials Cp2Mg and TEGa. That is, nitrogen gas having a predetermined flow rate is supplied to the storage containers 122C (Cp2Mg) and 123C (TEGa) for storing these materials through the flow rate adjusting devices 122S and 123S, and the take-off valves 122E and 123E and the pressure adjusting device 122P are supplied. , 123P, these gases are supplied to the first VENT line (VENT1) 128V during growth standby and to the first RUN line (RUN1) 128R during growth.

In addition, H ₂ O (water vapor), which is a liquid material as an oxygen source, is supplied with nitrogen gas at a predetermined flow rate through the flow rate adjusting device 124S to the containment vessel 124C, and waits for growth through the extraction valve 124E and the pressure adjusting device 124P. Sometimes it is supplied to the second vent pipe (hereinafter referred to as the second VENT line (VENT2)) 129V, and at the time of growth to the second run pipe (hereinafter referred to as the second RUN line (RUN2)) 129R.

As the p-type impurity source, NH ₃ (ammonia) gas, which is a gaseous material, was used. The NH ₃ gas is supplied at a predetermined flow rate by the flow rate adjusting device 125S. The power is supplied to the second VENT line 129V during standby and to the second RUN line 129R during growth. Note that the gas may be diluted with an inert gas such as nitrogen or Ar (argon).

  The liquid or solid material vapor and the gas material (hereinafter referred to as material gas) are supplied to the shower head 130 of the reaction vessel 5B through the first RUN line 128R and the second RUN line 129R. The first RUN line 128R and the second RUN line 129R are also provided with flow rate adjusting devices 120C and 120B, respectively, and the material gas is a shower attached to the upper part of the reaction vessel (chamber) 139 by a carrier gas (nitrogen gas). It is sent to the head 130.

  The shower head 130 has an ejection surface that faces the main surface (growth surface) of the substrate 10, and a large number of material gas ejection holes in the row and row directions (for example, several 10 to 10). 100) formed. The effective ejection diameter of the ejection surface is larger than the outer diameter of the substrate.

The ejection holes include a first ejection hole from which the organometallic compound material gas (group II gas) supplied from the first RUN line 128R is ejected, and H ₂ O (water vapor) (VI) supplied from the second RUN line 129R. A second ejection hole from which a group gas) is ejected. The gas from the first RUN line 128R and the gas from the second RUN line 129R are configured to be ejected from the first ejection hole and the second ejection hole, respectively, without being mixed. The first ejection holes and the second ejection holes are provided in the same number and at intervals of several mm, and are alternately arranged in each column and each row so that the organometallic compound gas and H ₂ O are uniformly mixed. ing.

  In the reaction vessel 139, a shower head 130 that blows a material gas onto the substrate 10, a substrate 10, a susceptor 119 that holds the substrate 10, and a heater 149 that heats the susceptor 119 are installed. The heater 149 can heat the substrate from room temperature to about 1100 ° C.

  Note that the substrate temperature in this embodiment refers to the temperature of the surface of the susceptor 119 on which the substrate is placed. That is, in the case of the MOCVD method, heat transfer from the susceptor 119 to the substrate 10 is performed by direct contact and a gas existing between the susceptor 119 and the substrate 10. Between the growth pressures of 1 kPa to 120 kPa (Pa: Pascal) used in this example, the surface temperature of the substrate 10 is about 0 ° C. to 10 ° C. lower than the surface temperature of the susceptor 119.

  The reaction vessel 139 is provided with a rotation mechanism for rotating the susceptor 119. More specifically, the susceptor 119 is supported by a susceptor support cylinder 148, and the susceptor support cylinder 148 is rotatably supported on the stage 141. The rotation motor 143 rotates the susceptor support cylinder 148 to rotate the susceptor 119 (that is, the substrate 10). The heater 149 is installed in the susceptor support cylinder 148.

  The exhaust part 5C includes a container internal pressure adjusting device 151 and an exhaust pump 152. The internal pressure adjusting device 151 can adjust the pressure in the reaction container 139 to about 0.01 kPa to 120 kPa. .

[Crystal growth material]
In this example, a material that does not contain oxygen in the constituent molecules was used as the organometallic compound material (or organometallic material). An organometallic material that does not contain oxygen is highly reactive with water vapor (oxygen material or oxygen source), and has a low growth pressure, or a flow rate ratio of water vapor to organometallic (MO) (F _H2O / _FMO ratio) or VI / ZnO-based crystals can be grown even in a region where the II ratio is low.

  In this example, DMZn, Cp2Mg, and TEGa were used, but DEZn (diethylzinc), MeCp2Mg (bismethylpentadienylmagnesium), EtCp2Mg (bisethylpentadienylmagnesium), etc., were used as group II materials. Can do. Further, TMGa (trimethylgallium), TMAl (trimethylaluminum), TEAl (triethylaluminum), TIBA (triisobutylaluminum), or the like can be used as the group III material.

As the oxygen material (hereinafter referred to as oxygen source), a polar oxygen material (polar oxygen source) is suitable. In particular, H ₂ O (water vapor) is highly polarized to δ ⁺ and δ ⁻ on the side where hydrogen atoms are bonded in the molecule and on the side of the lone pair, and has an excellent adsorption ability to the oxide crystal surface.

The H ₂ O molecule has a tetrahedral structure with hydrogen atom bonds and lone pairs, and oxides of sp ³ -type hybrid orbital (Zincblende / Cubic) and wurtzite (Wurtzeite / Hexagonal). Crystal growth is an excellent oxygen source that is preferentially oriented and adsorbed to oxygen sites. As other oxygen sources, similarly, lower alcohols having a large dipole moment and O atoms taking sp ³ type hybrid orbitals may be used. Specifically, as the oxygen source, in addition to H ₂ O (water vapor), lower alcohols, in particular, lower alcohols having 1 to 5 carbon atoms such as methanol, ethanol, propanol, butanol, and pentanol can be used. . In this example, H ₂ O was used, and O ₂ (oxygen) and N ₂ O (nitrous oxide) were used in the comparative example.

As the p-type impurity source, a compound that can easily be substituted for the O (oxygen) site of the zinc blende structure or the wurtzite structure in the crystal growth process is suitable. In particular, NH ₃ is suitable because it has the same action as the above H ₂ O. Specifically, as p-type impurity materials, hydrazines such as NH ₃ (ammonia), (CH ₃ ) ₂ NNH ₂ (dimethylhydrazine), (CH ₃ ) NHNH ₂ (monomethylhydrazine), PH3 (phosphine), R ₁ PH _2, R ₂ PH, alkyl phosphorus compounds, such as R ₃ P, AsH3 _{(arsine), R 1 PH 2, R} 2 PH, available as alkyl arsenic compounds, such as R ₃ P. Further, TEGa (triethylgallium) was used as the n-type impurity source. Note that these gases may be diluted with an inert gas such as nitrogen or Ar (argon).

As the carrier gas (atmosphere gas), an inert gas that does not react with the crystal growth material described above is suitable. Further, a gas that does not prevent adsorption of the crystal growth material such as H ₂ O (water vapor) or NH _{3 on} the substrate surface is preferable. Specifically, a chemically inert gas such as He (helium), Ne (neon), Ar (argon), or N ₂ (nitrogen) can be used as the carrier gas and the atmospheric gas. Liquid or solid material vapor and gaseous material (hereinafter referred to as material gas) are fed into the showerhead by the carrier gas and supplied to the substrate.

The substrate 10 is an α-sapphire single crystal sapphire (Al ₂ O ₃ ) substrate having a corundum structure. Representative substrate cutting planes of α-sapphire crystal are c-plane which is {0002} plane, a-plane which is {11-20} plane, m-plane which is {10-10} plane, {10-12} plane There is an R surface that is. In this example, the a-plane (hereinafter also referred to as sapphire a-plane) that is the {11-20} plane was used as the crystal growth plane. In the following, a substrate having a sapphire a-plane as a main surface (crystal growth surface) is also referred to as an a-plane sapphire substrate. Here, the Miller index {} indicates a representative value of an equivalent surface.

FIG. 2 is a cross-sectional view showing a zinc oxide based semiconductor crystal layer (hereinafter referred to as a ZnO based semiconductor layer or a ZnO based crystal layer) grown on the substrate 10 according to the present invention. More specifically, the first ZnO layer 11A, the second ZnO layer 11B, and the ZnO-based semiconductor layer 12 were grown on the sapphire substrate using the MOCVD method. In the following, a case where Mg _x Zn _(1-x) O (0.1 ≦ x ≦ 0.68) is grown as the ZnO-based semiconductor layer 12 will be described as an example.

  In the following, the ZnO-based semiconductor may be another compound crystal based on ZnO. For example, a ZnO-based compound crystal in which a part of Zn (zinc) is replaced with calcium (Ca) may be used. Alternatively, a ZnO-based compound crystal in which part of O (oxygen) is replaced with selenium (Se), sulfur (S), tellurium (Te), or the like may be used.

  FIG. 3 shows a crystal growth sequence used for crystal growth by the MOCVD method. First, the a-plane sapphire substrate 10 was set on the susceptor 119 in the MOCVD apparatus, and the reaction vessel pressure was adjusted to 10 kPa (kilopascal) (time T = T1). Further, the sapphire substrate 10 was rotated at a rotation speed of 10 rpm by a rotation mechanism.

Next, nitrogen (N ₂ ) gas was supplied from the first RUN line 128R and the second RUN line 129R to the shower head 130 at a flow rate of 2000 cc / min (total 4000 cc / min) and sprayed onto the sapphire substrate 10.

  The gas flow rate supplied from the first RUN line 128R and the second RUN line 129R to the shower head 130 was always kept constant. That is, when supplying the organometallic material gas and the gaseous material, the flow rates of the flow control devices 120C and 120B provided in the first RUN line 128R and the second RUN line 129R are increased or decreased by the flow rate of the organometallic material gas and the gaseous material. The gas flow rate supplied to the shower head 130 was kept constant.

Next, supply of H ₂ O (water vapor) as an oxygen source from the shower head to the substrate 10 at a flow rate of 640 μmol / min was started (T = T2). Next, the substrate 10 was heated from room temperature (RT) to 900 ° C. with a heater, and the sapphire substrate 10 was heat-treated for 10 minutes (T = T3 to T4). Thereafter, H ₂ O (water vapor) was kept flowing at the same flow rate until the growth was completed. Thereafter, H ₂ O (water vapor) continued to flow at the same flow rate until the end of growth.

  After the heat treatment of the substrate 10, the substrate temperature was lowered to 300 ° C. (first low growth temperature), and DMZn (dimethylzinc) as a zinc raw material was supplied to the substrate 10 at a flow rate of 3 μmol / min for 5 minutes (T = T5− T6: Growth period of the first ZnO layer 11A, period G1A in FIG.

  Thus, a ZnO layer (first low-temperature grown single crystal layer, which has a growth temperature (Tg) of 300 ° C. under a reduced pressure growth condition (growth pressure Pg = 10 kPa), a growth rate of 5 nm / min, and a layer thickness of 25 nm. Hereinafter, it is also simply referred to as a first single crystal layer.) 11A was grown.

  In the present specification, a crystal growth temperature suitable for growing a ZnO single crystal is generally referred to as a “high growth temperature”, and a temperature lower than the temperature is referred to as a “low growth temperature”.

  After the growth of the ZnO layer 11A, the substrate temperature was raised to 1000 ° C., and heat treatment (annealing) for 20 minutes was performed (T = T7 to T8). This heat treatment further improved the crystallinity and flatness of the ZnO layer 11A.

After the heat treatment (annealing) of the first ZnO layer (first single crystal layer) 11A was completed, the second ZnO layer 11B was grown at a higher temperature and higher pressure than in the case of the first ZnO layer 11A. More specifically, the substrate temperature was lowered from the heat treatment temperature (1000 ° C.) to 600 ° C. (second low growth temperature) higher than the first low growth temperature in 3 minutes. The reaction vessel pressure was increased from 10 kPa (low growth pressure) to 80 kPa (high growth pressure). Then, after waiting for 1 minute and the substrate temperature was stabilized, DMZn was supplied onto the ZnO layer 11A from the shower head at a flow rate of 10 μmol / min (T = T9 to T10: growth period of the second ZnO layer 11B, FIG. 3 period G1B). DMZn was supplied for about 2.5 minutes, the growth rate was 16 nm / min, and the thickness of the second ZnO layer (the second low-temperature grown single crystal layer, hereinafter simply referred to as the second single crystal layer) was 40 nm. ) 11B was formed. The flow rate ratio (F _H2O / F _MO ratio) of water vapor flow rate and organometallic this time (DMZn), so-called VI / II ratio is 64.

After the growth of the second ZnO layer (second single crystal layer) 11B was completed, the ZnO-based semiconductor layer 12 was grown at a temperature (high growth temperature) higher than that of the second ZnO layer 11B. More specifically, the substrate temperature was raised from 600 ° C. (second low growth temperature) to 800 ° C. (high growth temperature) while maintaining the reaction vessel pressure at 80 kPa. Then, after waiting for 1 minute and the substrate temperature was stabilized, DMZn was supplied onto the ZnO layer 11B from the shower head at a flow rate of 10 μmol / min (T = T11 to T12: growth period of the ZnO-based semiconductor layer 12, FIG. Period G2). DMZn was supplied to the substrate 10 for about 30 minutes, and a ZnO-based semiconductor layer (ZnO single crystal layer) 12 having a growth rate of 17 nm / min and a layer thickness of 0.5 μm was formed. The flow rate ratio (F _H2O / F _MO ratio) of water vapor flow rate and organometallic this time (DMZn), so-called VI / II ratio is 64.

  Note that the waiting time until the substrate temperature is stabilized before the growth of the ZnO-based semiconductor layer 12 can also be used as the heat treatment of the second ZnO layer 11B.

In this embodiment, the case where ZnO is grown as the ZnO-based semiconductor layer 12 will be described as an example, but the present invention is not limited to this. For example, in addition to DMZn, a Mg _x Zn _(1-x) O crystal that is a ternary crystal is grown by using Cp2Mg (biscyclopentadienylmagnesium) that is an organometallic compound that does not contain an oxygen atom. be able to.

  After the growth of the ZnO-based semiconductor layer 12 was completed, the pressure of 80 kPa was maintained while flowing water vapor until the substrate temperature reached 300 ° C. When the substrate temperature became 300 ° C. or lower, the water vapor was stopped (T = T13), and the substrate was waited until the substrate temperature reached room temperature, and then taken out from the reaction vessel.

  As described above, the first ZnO layer (first single crystal layer) 11A, the second ZnO layer (second single crystal layer) 11B, and the ZnO-based semiconductor layer (third single crystal) are formed on the substrate. The substrate with growth layer 15 (hereinafter, also simply referred to as the substrate 15) on which the layer 12 was grown was manufactured.

  FIG. 4 is a cross-sectional view schematically showing the structure of a semiconductor light emitting device (LED) wafer 25 that is Embodiment 2 of the present invention. FIG. 5 shows a crystal growth sequence used for crystal growth of an LED wafer (hereinafter also referred to as a substrate with an LED device layer) 25.

  More specifically, the first ZnO layer (first single crystal layer) 11A, the second ZnO layer (second single crystal layer) 11B, and the ZnO-based semiconductor layer 12 are formed by the same method as in the first embodiment. And a light emitting device layer (hereinafter referred to as an LED) composed of a first n-type ZnO-based semiconductor layer 21, a second n-type ZnO-based semiconductor layer 22, a ZnO-based semiconductor light-emitting layer 23, and a p-type ZnO-based semiconductor layer 24. 20) was formed. The first ZnO layer 11A, the second ZnO layer 11B, and the ZnO-based semiconductor layer 12 are undoped semiconductor layers.

  Here, in this specification, the device layer refers to a layer composed of a semiconductor to be included for the semiconductor element to perform its function. For example, a simple transistor includes an n-type semiconductor layer, a p-type semiconductor layer, and a structural layer constituted by these pn junctions. A semiconductor structure layer that includes an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer and emits light by recombination of injected carriers is particularly referred to as a light-emitting device layer.

After the growth of the ZnO-based semiconductor layer 12 was finished, the n-type ZnO-based semiconductor layer 21 was grown. More specifically, the DMZn flow rate was increased from 10 μmol / min to 30 μmol / min while maintaining a growth temperature of 800 ° C., a growth pressure of 80 kPa, and a H ₂ O (water vapor) flow rate of 640 μmol / min. At the same time, TEGa as an n-type impurity material was supplied to the substrate 15 with a growth layer (T = T12). Thereby, the first n which is a Ga-doped ZnO single crystal semiconductor layer having a layer thickness of 3 μm and a Ga concentration of 5 × 10 ¹⁸ cm ⁻³ with a growth time of 60 minutes (T = T12 to T21: period D1 in FIG. 5). A type ZnO-based semiconductor layer 21 was grown (T = T21).

Next, the pressure was reduced to 10 kPa at a substrate temperature of 800 ° C. Further, the flow rate of DMZn was set to 10 μmol / min, the flow rate of Cp2Mg was set to 0.5 μmol / min, and at the same time, TEGa was supplied to the substrate 15 as an n-type impurity material to grow MgZnO crystals (T = T22 to T23: period D2 ). That is, the second n-type ZnO-based semiconductor layer 22 which is a Mg _x Zn _(1-x) O (x = 0.15) single crystal semiconductor layer having a layer thickness of 70 nm and a Ga concentration of 5 × 10 ¹⁷ cm ^−3. Grew up.

  Next, a ZnO-based semiconductor light emitting layer 23 was grown. Specifically, the substrate temperature is maintained at 800 ° C., the growth pressure is set to 80 kPa, the supply amount of DMZn is reduced to 1 μmol / min, and the ZnO-based semiconductor light emitting layer which is a ZnO single crystal semiconductor layer having a layer thickness of 30 nm. 23 was formed (T = T24 to T25: period D3).

After the light emitting layer 23 was grown, a p-type ZnO based semiconductor layer 24 was grown. Specifically, the substrate temperature is maintained at 800 ° C., the growth pressure is 10 kPa, the supply amount of DMZn is 10 μmol / min, and at the same time, NH ₃ (ammonia) is supplied as a p-type impurity material at a flow rate of 180 μmol / min. Then, a p-type ZnO-based semiconductor layer 24 which is a Mg _x Zn _(1-x) O (x = 0.15) single crystal semiconductor layer having a layer thickness of 70 nm and a nitrogen impurity concentration of 8 × 10 ¹⁹ cm ⁻³ is grown. (T = T26 to T27: period D4).

After the growth of the p-type ZnO-based semiconductor layer 24 is completed, the pressure of 80 kPa is maintained with water vapor flowing until the substrate temperature reaches 300 ° C. (T = T28), and the substrate temperature is increased to room temperature. The extracted points are the same as in the first embodiment.
[Manufacture of semiconductor light emitting devices]
Using the substrate 25 with the LED device layer manufactured in the above process, a semiconductor light emitting element (LED) was manufactured by the following process.

  FIG. 6 is a top view of the substrate 25 with an LED device layer. FIG. 7 is a cross-sectional view illustrating an outline of an element separation process for performing an electrode formation process, which will be described later, on the substrate 25 with an LED device layer and separating the LED into individual pieces. FIG. 8A is an element top view of the semiconductor light emitting element (LED) 30, and FIG. 8B is a cross-sectional view of the LED 30. FIG. 8B shows that two LEDs 30 and an element partitioning groove 32 for separating them by braking are formed.

  First, using a photolithography technique, a resist mask having a shape covering the region (element region) in the element section 31 was formed. Next, using wet etching, the p-type ZnO-based semiconductor layer 24, the light-emitting layer 23, and the n-type ZnO-based semiconductor layer 22 in the opening outside the element section 31 were partially removed to a predetermined depth. Finally, the resist was washed away to form element partition grooves 32 (STEP 2 in FIGS. 6 and 7). As shown in FIG. 6, the element section 31 was formed with an inclination of 36.3 ° with respect to the OF (orientation flat). Further, the element partition groove 31 was formed so that the depth was 200 nm deeper than the interface position between the light emitting layer 23 and the n-type ZnO-based semiconductor layer 22.

  Next, a resist mask having a shape opened to a p-side electrode shape was formed using a photolithography technique. Then, EB (electron beam) deposition was used to form a p-side electrode 33 with a thickness of Ni (nickel) of 0.3 to 10 nm and Au (gold) of 5 to 20 nm. Finally, the vapor deposition material other than the p-side electrode 33 was removed by a lift-off method, and a p-side electrode 507 was formed on the surface of the p-type Zn oxide semiconductor layer 505. The formed p-side electrode 33 was treated with RTA (Rapid Thermal Annealer) in a 10% oxygen atmosphere at 500 ° C. for 30 seconds to form a translucent electrode.

  Next, a resist mask having an opening in the shape of the p-side connection electrode 34 was formed so as to be in contact with a partial region of the p-side electrode 34 by using a photolithography technique. And by EB vapor deposition, the Ni / Pt / Au electrode pad material was laminated | stacked in this order with the thickness of 10 nm / 100 nm / 1000 nm, respectively, and the p side connection electrode 34 was formed (FIG.8 (B)). The notation of Ni / Pt / Au means the first layer / second layer / third layer from the p-side electrode 34 side.

  Further, a resist mask having an opening in the shape of the n-side connection electrode 35 was formed on the exposed surface of the n-type ZnO-based semiconductor layer 22 by using a photolithography technique. Then, Ti / Au was laminated at a thickness of 10 nm / 1000 nm by EB vapor deposition, and then the vapor deposition material other than the mask opening was removed by a lift-off method to form the n-side connection electrode 35.

  The electrode-formed LED operation layer 20 side on which the electrodes were formed was attached to a protective substrate, set on a grinding machine, and ground until the substrate thickness was 120 μm. Then, the polishing material was gradually lowered and polished until the ground surface became a mirror surface by a polishing apparatus, and formed into a wafer having a thickness of about 100 μm.

  Next, after a protective sheet is pasted on the surface side on which the electrodes are formed, for example, scribe grooves 36 that are orthogonal to each other are formed on the back surface corresponding to the central portion of the element partition groove 32 by a scribe device using diamond points (see FIG. 7 STEP2, FIG. 8 (B)).

  As will be described in detail later, in braking, the knife edge 37 was applied from the element partitioning groove 32 side of the opposing surface of the scribe groove 36, loaded with the knife edge 37, and cleaved in the scribe groove direction. Similarly, the substrate was rotated 90 ° and cleaved in the direction of the scribe groove 36 perpendicular to the substrate.

  In this way, the semiconductor light emitting element 30 was manufactured (FIGS. 8A and 8B). Various sizes of the semiconductor light emitting element 30 are not limited to this, but for example, the die size is 400 μm square (FIG. 6, L1 = L2 = 400 μm), the element partition size is 300 μm square, and the diameter of the p-side electrode pad is φ100 μm, the diameter of the n-side electrode pad is φ100 μm, and the thickness is about 100 μm.

In addition, although the case where the composition X = 0.15 was described as an example of the crystal layer containing Mg (Mg _x Zn _1-x O layer), the present invention is not limited thereto. What is necessary is just to select the composition (band gap) of each semiconductor layer in the range of 0 <= x <= 0.68 according to the required characteristic etc. of a semiconductor element. Also, the layer thickness, conductivity type, dope concentration (carrier concentration), and the like can be appropriately modified or selected according to the required characteristics of the semiconductor light emitting device.
[Comparative example]
In order to evaluate the ZnO-based single crystal layer grown according to the above-described examples, as a comparative example, crystal growth was performed under the following growth method and growth conditions.

  FIG. 9 is a cross-sectional view schematically showing the structure of the crystal growth layer of the comparative example. Specifically, the ZnO single crystal layer 101 and the ZnO-based crystal layer 102 were formed on the a-plane sapphire substrate 100 by an RF-MBE (radical source MBE) apparatus.

  That is, the RF-MBE apparatus used for the crystal growth of the comparative example irradiates Zn (zinc), Mg (magnesium), and Ga (gallium) with a Knudsen cell, and O (oxygen) and N (nitrogen) which is a p-type impurity. ) Is configured to irradiate with an RF radical gun (generator). Each Knudsen cell and the exit of the RF radical gun are provided with a shutter, which can individually irradiate the substrate with molecular beams. Further, the substrate is structured to be heated by a resistance heater. More specifically, the substrate 105 with a crystal growth layer of the comparative example was grown by the following procedure.

  First, the a-plane sapphire substrate 100 was subjected to a heat treatment at a temperature of 900 ° C. for 10 minutes under vacuum to dissipate and desorb adsorbed material on the substrate surface.

  Next, the substrate temperature was lowered from 900 ° C. to 300 ° C. When the temperature was stabilized, the O (oxygen) radical gun shutter was opened and the substrate was irradiated with O radicals. Subsequently, the Zn Knudsen cell shutter was opened and the substrate was irradiated with a Zn beam to form a ZnO single crystal layer (buffer layer) having a thickness of 30 nm as the first ZnO layer 101 at a low temperature (300 ° C.).

  Next, heat treatment of the first ZnO layer 101 was performed. More specifically, while the substrate is irradiated with O radicals, the substrate temperature is raised from 300 ° C. to 800 ° C., heat treatment is performed for 5 minutes, and a ZnO single crystal layer (first ZnO layer) formed at a low temperature of 300 ° C. 101) was recovered.

  After the heat treatment of the first ZnO layer 101, the substrate temperature was lowered again from 800 ° C. to 700 ° C. When the substrate temperature was stabilized, the Zn Knudsen cell shutter was opened, and the first ZnO layer 101 was irradiated with a Zn beam to form a ZnO single crystal layer having a thickness of 1 μm as the second ZnO layer. As described above, the substrate 105 with the ZnO crystal layer of the comparative example was formed by the steps described above.

[Detailed evaluation results and physical properties of crystal growth layer]
The evaluation results and physical properties of the crystal growth layers of the above-described examples and comparative examples will be described in detail below with reference to the drawings. Further, the crystal growth layer described above was evaluated and analyzed by the following method.

  The surface morphology was evaluated by a differential polarization microscope, SEM (Scanning Electron Microscope) and AFM (Atomic Force Microscope). Crystal orientation and flatness were evaluated by RHEED (reflection high-energy electron diffraction). The crystal orientation and the defect / dislocation density were evaluated by X-ray diffraction (XRD). The impurity concentration in the crystal was evaluated by secondary ion mass spectrometry (SIMS).

  FIG. 10 shows SIMS analysis results of the crystal growth layer of Example 1 (hereinafter also referred to as <EMB1>). That is, concentration profiles in the depth direction of Al (aluminum) and Si (silicon) are shown. In the figure, LM (Al) and LM (Si) indicate the lower detection limits of Al and Si, respectively.

As shown in FIG. 10, the concentration of Al (aluminum) decreases from the interface (X) between the sapphire substrate and the ZnO crystal growth layer (indicated as “ZnO epi” in the figure) in the growth direction. The interface (X) between the sapphire substrate (denoted as “Sub” in the figure) and the ZnO crystal growth layer was identified as a position where the Zn ion intensity sharply decreased. The upper limit of SIMS measurement is 1 × 10 ²¹ (pieces / cm ³ ).

  That is, it was found that Al, which is a constituent element of sapphire, which is a substrate, does not decrease completely steeply (stepwise) at the interface (X) but diffuses into the ZnO crystal growth layer. . More specifically, due to the diffusion of Al into the ZnO growth layer, a solid solution layer (SC in the figure) in which Al exists in the solid solution state in the vicinity of the interface (X) is formed in the ZnO growth layer, Furthermore, it was found that a transition layer, which is a layer in a transition state from a solid solution state to a diffusion state (an intermediate state between the solid solution state and the diffusion state), is formed. That is, it was found that a layer composed of a solid solution layer (SC) and a transition layer (hereinafter referred to as a solid solution diffusion layer (SD)) was formed. That is, a region other than the solid solution layer (SC) in the solid solution diffusion layer (SD) is a transition layer. This point will be described in more detail below.

FIG. 11 is an enlarged view of the profile in the vicinity of the interface (X) between the Al concentration and the Zn ion intensity in FIG. The horizontal axis represents the growth layer thickness, and is zero at the interface (X). When the Al concentration in the ZnO growth layer is equal to or higher than a certain value (upper limit concentration CC; point P in the figure), it can be said that Al is in a solid solution state in the crystal in a solid solution state. In general, the upper limit concentration at which Al acts as an n-type impurity is 8 × 10 ²⁰ atoms / cm ³ , and it can be said that a region with an Al concentration higher than this is a solid solution state region. That is, from FIG. 11, the region from the interface (X) to the point P is an Al solid solution layer (SC), and when the upper limit concentration (CC) is 8 × 10 ²⁰ / cm ³ , The thickness of SC) is 40 nm.

  Regarding the upper limit concentration acting as an n-type impurity, for example, “Low-temperature growth of ZnO thin film”, Shinya Akiba, 2006, Master's program, Department of Electrical and Electronic Engineering, Graduate School of Engineering, Mie University, February, H19 6th page (see http://hdl.handle.net/10076/9109).

The Al concentration is composed of a region (R1) that decreases with a sharp concentration gradient from the interface toward the growth direction and a region (R2) that decreases with a gentle concentration gradient. If the intersection of the tangents of concentration change in these regions R1 and R2 is Q, the region from the interface (X) to the point Q is a solid solution diffusion layer (SD), and the thickness of the solid solution diffusion layer (SD) is , 100 nm. Therefore, the thickness of the transition layer (that is, the solid solution diffusion layer SD) between the solid solution layer (solid solution layer: SC) and the diffusion layer (diffusion layer) is 60 nm. The Al concentration at the intersection point Q determined by the above method was 1 × 10 ¹⁹ / cm ³ . Therefore, a region having an Al concentration of 1 × 10 ¹⁹ atoms / cm ³ or more can be defined as a solid solution diffusion layer (SD).

  As described above, according to the present invention, a layer in which the Al composition is continuously changed from the sapphire substrate to the ZnO growth layer is formed, and the Al solid solution layer (SC) and the solid solution diffusion layer (SD) are formed. Is formed.

Further, as shown in FIG. 10, in the diffusion layer on the solid solution diffusion layer (SD) (the growth layer after the Q point in the figure), the Al concentration is further reduced, and the thickness of the ZnO single crystal layer is 1 μm. It decreases to 1 × 10 ¹⁵ pieces / cm ^{3 in the} vicinity. Therefore, if the ZnO growth layer is 1 μm or more, the concentration of Al impurity is sufficiently lowered, so that there is no problem when manufacturing a semiconductor element. That is, for example, when manufacturing a semiconductor light emitting device such as an LED that forms an n-type ZnO-based semiconductor layer doped with impurities for controlling the conductivity type, a light-emitting layer, and a p-type ZnO-based semiconductor layer, Al diffusion is not a problem.

  On the other hand, FIG. 12 shows the SIMS analysis result of the sample of the comparative example. More specifically, SIMS analysis results of a ZnO-based crystal growth layer (hereinafter also referred to as <CMP>) formed on the a-plane sapphire substrate formed by the RF-MBE method are shown. That is, concentration profiles in the depth direction of Al (aluminum) and Si (silicon) are shown. When formed by the RF-MBE method, it was found that a steep interface was formed between the sapphire substrate and the ZnO growth layer, Al did not diffuse into the growth layer, and no solid solution layer was formed.

  In the present invention, it should be further noted that the surface morphology is good even though the Al solid solution layer is formed at the interface between the sapphire substrate and the ZnO layer. FIGS. 13 and 14 show a differential microscope image and an SEM image of the growth layer surface of Example 1 (EMB1), respectively. Thus, it was confirmed from the observation result of the differential microscope and SEM that it has high flatness from a wide area to a micro area (also macroscopically and microscopically).

  In addition, the introduction of defects and dislocations into the growth layer is reduced. 15A and 15B show the case where the layer thickness (t) of the ZnO layer 12 is 1 μm, and FIGS. 16A and 16B show the XRD when the layer thickness (t) is 3 μm. 002) ω rocking curve and (100) ω rocking curve. A comparison table of these measurement results is shown below.

  For example, the full width at half maximum (FWHM) of the (002) ω rocking curve is 276 arcsec at a layer thickness t = 1 μm, but is improved to 144 arcsec at t = 3 μm. It was also found that the FWHM of the (100) ω rocking curve improved from 631 arcsec (t = 1 μm) to 270 arcsec (t = 3 μm) as the growth layer thickness increased. The lattice mismatch between the c-axis direction <0001> of the sapphire substrate and the a-axis direction <11-20> of the ZnO growth layer is 0.07%, and the m-axis direction <10-10> of the sapphire substrate and the ZnO growth layer Although the lattice mismatch with the m-axis direction <10-10> is 2.46%, as described above, it was found from these measurement results that the lattice mismatch was relaxed and grew. Also, the surface morphology was good with a mirror surface.

By the way, in conventional semiconductor crystals such as GaN and GaAs, when impurities such as Zn and Mg are mixed in about 1 × 10 ²⁰ cm ⁻³ or more, the crystal arrangement starts to be disturbed, and defects and dislocation density increase. Furthermore, when it is added at about 5 × 10 ²⁰ cm ⁻³ or more, the surface morphology is deteriorated or polycrystallized. As described above, it is known that the non-oxygen-based compound semiconductor crystal deteriorates when the impurity element diffuses in the growth layer at a high concentration. In the present invention, as described above, it was found that the surface morphology and lattice matching are good, and a growth layer having high quality crystallinity such as reduction of defects and dislocations can be formed.

Thus, according to the present invention, an Al solid solution layer and a solid solution diffusion layer can be easily formed. As will be described later, if the Al solid solution layer is formed at the interface between the sapphire substrate and the ZnO layer, the interface brittleness is eliminated, so the layer thickness of the solid solution layer (SC) may be about several nm. However, it is difficult to control the layer thickness, and the layer thickness of the solid solution layer (SC) is preferably 100 nm or less. More preferably, it is 50 nm or less. Alternatively, as described above, when a region having an Al concentration of 1 × 10 ¹⁹ pieces / cm ³ or more is defined as a solid solution diffusion layer (SD), the thickness of the solid solution diffusion layer (SD) is 200 nm or less. If there is, it is good. Moreover, it is preferably 150 nm or less, and more preferably 100 nm or less.

[Evaluation results of element isolation]
1.1 Comparison Results of Element Isolation Element isolation (separation by braking) was performed on the substrates with growth layers (or light emitting element wafers) of Examples 1, 2 and Comparative Examples. The results are shown in the following table.

The element isolation yield of Example 1 in which the Al solid solution layer was formed was 80 to 95%. In Example 2 in which the n-type ZnO-based semiconductor layer 22 was an Mg _x Zn _{(1-x) 2} O (x = 0.15) layer, an element isolation yield of 95% or more was obtained. On the other hand, the device isolation yield of the comparative example manufactured by the MBE method in which the Al solid solution layer was not formed was a low result of less than 70%. Further, in the element isolation of Example 1 and Example 2, there was almost no chipping or cracking of the ZnO-based semiconductor on the cleavage plane, but in the comparative example, the ZnO-based semiconductor on the cleavage plane was small even in the separation good product. The lack was noticeable.

  According to the present invention, the reason why the element isolation can be satisfactorily performed without chipping or cracking is interpreted as follows. With reference to FIG. 17, the principle of braking when a ZnO-based crystal growth layer (LED device layer) is formed on a sapphire substrate will be described. 17A shows a case where an Al solid solution layer is not formed between the sapphire substrate and the ZnO-based crystal layer, and FIG. 17B shows an Al solid solution layer (SC) between the sapphire substrate and the ZnO-based crystal layer. It is typical sectional drawing explaining the principle of braking in the case of being formed.

  In the element isolation step, a scribe groove 36 is formed on the back surface side of the substrate, and then a knife edge 37 is applied to the surface side portion coinciding with the scribe groove 36 and the load is cleaved to separate the elements. However, when loading with the knife edge 37, the applied force diverges at the interface X between the sapphire substrate and the ZnO-based growth layer (LED device layer), which is a heterogeneous bonding surface, and the ZnO-based growth layer is chipped, cracked, Defects such as peeling occur. Such a defect occurs because of the heterogeneous crystal junction structure. That is, the first is a discontinuous crystal structure in which a c-plane (a-plane) ZnO-based crystal layer is laminated on an a-plane (r-plane) sapphire surface. Secondly, the Mohs hardness of the sapphire crystal and the ZnO-based crystal is 9 and 4, respectively, which is caused by a structure in which a soft crystal is laminated on a hard crystal. In particular, the influence of the Mohs hardness difference is large. That is, the force loaded by the knife edge is not transmitted efficiently to the sapphire substrate, but acts in the direction of spreading the ZnO-based crystal layer in the lateral direction. Further, at this time, in the case of the substrate with the LED device layer in which the c-plane (a-plane) ZnO-based crystal layer is laminated on the a-plane (r-plane) sapphire substrate, the above problem occurs because the interface is fragile.

  More specifically, since the crystal hardness (for example, Mohs hardness 4-5) of the ZnO crystal is softer than the crystal hardness of sapphire (Mohs hardness 9), the knife edge bites into the ZnO crystal layer. As shown in FIG. 17A, the knife edge 37 bites in and a pushing force F ′ acts on the ZnO-based crystal layer having a low crystal hardness. Then, a force Fh in the direction parallel to the substrate that spreads the ZnO crystal acts. Due to this force Fh, peeling occurs at the interface between the fragile sapphire substrate and the ZnO-based crystal. That is, the weak interface between the sapphire substrate and the ZnO-based crystal is chipped, and defects such as cracking and peeling occur.

  On the other hand, peeling is prevented by forming the Al solid solution layer SC (or solid solution diffusion layer SD) at the interface. That is, when the Al solid solution layer is provided, the bonding force at the interface is high, so that it does not peel off, and the load of the knife edge 37 is transmitted downward and can be cleaved. More specifically, as shown in FIG. 17B, the drag force F ′ ′ acts and balances against the biting force F ′ of the knife edge 37. As a result, the load F acts on the sapphire substrate and is cleaved. In addition, although it is slight, compressive stress acts on the ZnO-based crystal layer due to the load, and the crystal hardness increases and the chipping becomes difficult. At this time, tensile stress acts on the substrate. As described above, the Al solid solution layer (and the solid solution diffusion layer) not only eliminates the fragility of the interface, but also functions to increase the crystal hardness on the ZnO-based crystal layer side.

  In addition, in a structure in which a GaN-based crystal layer is laminated on a sapphire substrate, orientation shift is the main cause of element (chip) chipping and the like. For example, when an a-plane sapphire substrate is used, c-plane GaN crystals are oriented and stacked in the same manner as ZnO crystals. When a c-plane sapphire substrate is used, the c-axis of the GaN crystal is oriented and laminated with the c-axis of the GaN crystal shifted by 30 ° from the c-axis of the sapphire substrate. For this reason, the cleavage plane of the sapphire crystal and the cleavage plane of the GaN crystal are shifted. As a result, an element (chip) chipping or the like occurs during element isolation. This is because the Mohs hardness of the sapphire crystal and the GaN crystal is equal to 9 and is hard, so that the force loaded by the knife edge is effectively transmitted from the GaN layer to the sapphire substrate.

  On the other hand, in the structure in which the ZnO-based crystal is laminated on the sapphire crystal, as described above, since the characteristic that the Mohs hardness difference is large is added, the conventional structure used in the structure in which the GaN-based crystal layer is laminated on the sapphire substrate. The element isolation method cannot solve defects such as chipping, cracking, and peeling.

1.2 Relationship between element isolation and ZnO-based crystal composition As described above, the cause of the peeling of the ZnO crystal layer is that the crystal hardness of the ZnO crystal is low. Therefore, the peeling stress Fh can be reduced by increasing the hardness of the crystal on the contact surface with the knife edge. When the ZnO crystal and the MgZnO crystal are compared, the MgZnO crystal hardness is high. The hardness of the MgO crystal is 5.5. In addition, although the a-axis length of the MgZnO crystal is longer than the a-axis length of the ZnO crystal, it is lattice-coherently matched with the ZnO crystal. Therefore, when an MgZnO crystal layer is stacked on the ZnO crystal layer, compressive stress acts on the MgZnO layer itself. .

Therefore, when the n-type ZnO-based crystal is formed as an MgZnO layer and the element partition groove is formed at a depth up to the n-type MgZnO layer as shown in the second embodiment, the knife edge hits the n-type MgZnO layer. Due to the crystal hardness of the type MgZnO layer and the compressive stress due to the laminated structure, the amount of biting of the knife edge is reduced, and the exfoliation of the ZnO-based crystal layer can be further suppressed. Therefore, as shown in Table 2, the element isolation yield is also improved. Empirically, when the Mg composition x of the Mg _x Zn _(1-x) O (0 ≦ x ≦ 0.68) crystal is 0.1 or more, the amount of biting is significantly reduced, and is 0.15 or more. , Knife edge will not bite. Particularly preferred is 0.2 or more.

  As described above in detail, according to the present invention, since an Al solid solution layer (and a solid solution diffusion layer) is formed at the interface between the sapphire substrate and the ZnO-based crystal layer, the fragility of the interface can be eliminated, In element isolation, problems such as chipping, cracking, and peeling can be avoided. Moreover, the above-mentioned malfunction can be avoided more effectively by making the crystal hitting the knife edge a MgZnO layer having a crystal hardness higher than that of the ZnO crystal. As described above, according to the present invention, it is possible to suppress the exfoliation of the ZnO-based crystal layer and to improve the element isolation yield.

[Formation of solid solution layer]
In the above embodiment, the case where the Al solid solution layer and the solid solution diffusion layer are formed by the MOCVD method has been described as an example. However, other growth methods such as MBE method, PLD (Pulsed Laser Deposition) method, halide VPE ( The solid solution layer may be formed by HVPE) method, plasma CVD method, sputtering method, or the like. In short, it is sufficient if an Al solid solution layer is provided at the interface between the sapphire substrate and the ZnO-based crystal growth layer.

  In addition, the growth conditions of the ZnO-based crystal for forming the Al solid solution layer at the interface between the sapphire substrate and the ZnO-based crystal growth layer shown in the above examples are merely examples, and are not limited thereto. Below, details of the properties and growth conditions of the ZnO-based crystal growth layer for growing a ZnO-based crystal on the sapphire substrate using the MOCVD method and forming an Al solid solution layer at the interface between the substrate and the growth layer are described in detail. explain.

  In the following, for ease of explanation and understanding, the growth layer grown on the sapphire substrate is referred to as a connection layer (or first growth layer), and the crystal layer grown on the connection layer is referred to as a device layer ( Or a second growth layer).

1. Properties of the ZnO-based crystal growth layer (connection layer) Properties and state of the ZnO-based crystal growth layer (connection layer) in the case of dissolving Al in the substrate are those in which the domain diameter is small and the surface unevenness difference is large Is good. That is, in the heat treatment step, the larger the change rate of the growth layer shape, the easier it is to dissolve Al of the sapphire substrate.

  However, when grown under excessive conditions, single crystallinity is impaired, and crystallinity recovery by heat treatment after growth becomes insufficient. That is, the crystallinity of a ZnO-based crystal layer such as a device layer grown on the connection layer is lowered, and diffusion of solid solution Al cannot be suppressed. In addition, when the connection layer is, for example, a polycrystal or an amorphous crystal, the Al component is segregated at the grain boundary in the heat treatment step, so that sufficient crystallinity cannot be recovered, and the device layer grows at a high growth temperature. This is because defects and dislocations are introduced at high density at this stage, and Al diffusion cannot be suppressed.

  In the above embodiment, the first ZnO layer (first single crystal layer) 11A and the second ZnO layer (second single crystal layer) 11B are formed on the sapphire substrate as a connection layer at a low growth temperature. The case where the ZnO-based semiconductor layer 12 is formed at a high growth temperature has been described. However, even if only the first single crystal layer (ZnO-based single crystal layer) is formed as a connection layer, and a ZnO-based crystal layer such as a device layer is grown on the first single crystal layer (connection layer). Good.

1.1 Growth Temperature The growth temperature of the connection layer is generally lower than the crystal growth temperature (referred to as “high growth temperature”) for growing a ZnO single crystal (referred to as “low growth temperature”). Is appropriate. This is because at the high growth temperature, island-like growth is easy and layered single crystals are hardly formed.

  More specifically, the growth temperature is preferably in the range of 250 ° C to 450 ° C. Furthermore, it is more preferable that it exists in the temperature range of 300 to 400 degreeC. At 250 ° C. or lower, the migration length becomes short, so that it becomes easy to be amorphous or polycrystallized. Further, as described above, when the temperature is higher than 450 ° C., island-like growth is likely to occur, and the growth layer on the connection layer is difficult to become a layered single crystal.

1.2 Growth pressure Since the connection layer does not undergo segregation or the like due to the heat treatment after growth, and sufficient crystallinity is recovered, and because the growth layer on the connection layer grows single crystal, It is necessary that the crystallinity is not impaired. That is, for the single crystal growth of the connection layer, the migration length of the reactive chemical species (DMZn, H ₂ O, intermediate products, Zn atoms before crystallization, O atoms before crystallization, etc.) on the substrate surface. Is better. Therefore, the reduced pressure growth is suitable, and specifically, the growth pressure is preferably 1 kPa to 30 kPa, more preferably 5 kPa to 20 kPa. When the growth pressure is 1 kPa or less, the growth rate is remarkably slowed.

1.3 Material gas In order to promote the formation of a solid solution layer by forming a ZnO single crystal layer under a low growth pressure and a low growth temperature, it is necessary to select a material having high mutual reactivity. This is because if the mutual reactivity is low, the crystal does not grow, or becomes amorphous or polycrystallized. As the Zn source, an organometallic compound that does not contain oxygen in the constituent molecules and has high reactivity with the oxygen source material is suitable. In addition to the DMZn described above, for example, there is DEZn (diethyl zinc). As an oxygen source, H ₂ O (water vapor) having a large intramolecular polarization and high reactivity is suitable.

1.4 Heat treatment conditions As described above, the formation of the solid solution layer requires that the connection layer be single crystallized and heat treatment in a polar oxygen source (H ₂ O: water vapor). More specifically, although the connection layer is a single crystal, it has domains and irregularities, and the crystal properties change in a direction that minimizes the interface energy by heat treatment. At this time, the Al element of the sapphire substrate is dissolved in a high concentration in the ZnO single crystal. Therefore, the higher the heat treatment temperature and the longer the treatment time, the higher the solid solution concentration of Al.

  Further, since sapphire is a very stable substance, it is difficult to sufficiently dissolve and diffuse Al in the connection layer at a low temperature. Furthermore, a high temperature of 800 ° C. or higher is preferable for recovering the crystallinity of the connection layer in a state containing Al at a high concentration.

  Therefore, it is appropriate that the heat treatment of the connection layer is performed at a high temperature. Specifically, the temperature is more preferably 100 ° or higher than the growth temperature of a ZnO-based crystal layer such as a device layer, or 900 ° or higher.

  In order to improve single crystallinity and flatness, it is preferable to perform the heat treatment under a low pressure where the migration length becomes long. Note that the pressure range suitable for the heat treatment is the same as the range of the growth pressure of the connection layer described above.

  As described above in detail, according to the present invention, since an Al solid solution layer (and a solid solution diffusion layer) is formed at the interface between the sapphire substrate and the ZnO-based crystal layer, the fragility of the interface can be eliminated, In element isolation, problems such as chipping, cracking, and peeling can be avoided. Moreover, the above-mentioned malfunction can be avoided more effectively by making the crystal hitting the knife edge a MgZnO layer having a crystal hardness higher than that of the ZnO crystal. As described above, according to the present invention, it is possible to suppress the peeling of the ZnO-based crystal layer in the breaking of the element isolation process, and it is possible to improve the element isolation yield. In addition, a fine crack due to chipping, cracking, peeling, or the like propagates into the device layer, and there is an effect of preventing problems such as deterioration of element characteristics and reduction of element life.

  Accordingly, problems such as chipping, cracking, and peeling of the element can be solved, and a semiconductor element excellent in element characteristics, element lifetime, and mass productivity can be provided. In particular, it is possible to provide a high-performance semiconductor light-emitting device excellent in light emission efficiency and device lifetime, and excellent in mass productivity, and a method for manufacturing the same.

  In the element isolation method of the present invention, the scribing method using diamond points and the braking method using knife edges have been described as examples. However, according to the principle of the present invention, the element isolation method of the present invention is not limited to this. For example, a scribe groove may be formed by a laser scribe method, or a method of separating elements by braking with a roller may be used.

DESCRIPTION OF SYMBOLS 10 Substrate 11A 1st low temperature growth layer 11B 2nd low temperature growth layer 12 ZnO type compound semiconductor layer (high temperature growth single crystal layer)
15 substrate with growth layer 20 device layer 21 first n-type semiconductor layer 22 second n-type semiconductor layer 23 light emitting layer 24 p-type semiconductor layer 25 substrate with LED operation layer SC solid solution layer SD solid solution diffusion layer

Claims (14)

A semiconductor device having a ZnO-based crystal layer grown on an α-sapphire (Al ₂ O ₃ ) single crystal substrate and a device layer grown on the ZnO-based crystal layer,
The ZnO-based crystal layer has a solid solution layer in which aluminum (Al) of the substrate is dissolved in an interface with the substrate. The semiconductor element according to claim 1, wherein an Al concentration of the solid solution layer is 8 × 10 ²⁰ pieces / cm ³ or more.   The semiconductor element according to claim 1, wherein a thickness of the solid solution layer is 100 nm or less. ^3. The layer thickness of a solid solution diffusion layer having a concentration of Al dissolved at the interface with the substrate of 1 × 10 ¹⁹ atoms / cm ³ or more is 200 nm or less. 4. Semiconductor element.   The semiconductor element according to claim 1, wherein a crystal growth surface of the substrate is a [11-20] plane. The semiconductor device according to claim 1, wherein the device layer includes a Mg _x Zn _{(1-x) 2} O (0.1 ≦ x ≦ 0.68) layer.   7. The semiconductor element according to claim 1, wherein the device layer is an LED (light emitting diode) device layer including an n-type ZnO single crystal layer, a light emitting layer, and a p type ZnO single crystal layer. . A method for growing a semiconductor device comprising a ZnO-based crystal layer and a device layer grown in this order on an α-sapphire (Al ₂ O ₃ ) single crystal substrate,
The growth method characterized in that the ZnO-based crystal layer has a solid solution layer in which aluminum (Al) of the substrate is dissolved at an interface with the substrate. The growth method according to claim 8, wherein the Al concentration of the solid solution layer is 8 × 10 ²⁰ pieces / cm ³ or more.   The growth method according to claim 8 or 9, wherein a thickness of the solid solution layer is 100 nm or less.   The growth method according to claim 8, wherein the crystal growth surface of the substrate is a [11-20] plane. A substrate with a growth layer in which a ZnO-based crystal layer is grown on an α-sapphire (Al ₂ O ₃ ) single crystal substrate,
The substrate with a growth layer, wherein the ZnO-based crystal layer has a solid solution layer in which aluminum (Al) of the substrate is dissolved at an interface with the substrate. 13. The substrate with a growth layer according to claim 12, wherein the Al concentration of the solid solution layer is 8 × 10 ²⁰ pieces / cm ³ or more.   14. The substrate with a growth layer according to claim 12, wherein the solid solution layer has a thickness of 100 nm or less.