JP2010524059A - 異なる種類の集積回路メモリ素子を有する階層メモリモジュールを含むシステム - Google Patents
異なる種類の集積回路メモリ素子を有する階層メモリモジュールを含むシステム Download PDFInfo
- Publication number
- JP2010524059A JP2010524059A JP2010501086A JP2010501086A JP2010524059A JP 2010524059 A JP2010524059 A JP 2010524059A JP 2010501086 A JP2010501086 A JP 2010501086A JP 2010501086 A JP2010501086 A JP 2010501086A JP 2010524059 A JP2010524059 A JP 2010524059A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- volatile memory
- elements
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims description 30
- 238000011144 upstream manufacturing Methods 0.000 claims description 18
- 238000012546 transfer Methods 0.000 claims description 12
- 230000009977 dual effect Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 claims description 2
- 238000009825 accumulation Methods 0.000 claims 1
- 238000013507 mapping Methods 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 12
- 230000002950 deficient Effects 0.000 description 10
- 230000008054 signal transmission Effects 0.000 description 8
- 230000004044 response Effects 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 230000002457 bidirectional effect Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000013506 data mapping Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000002776 aggregation Effects 0.000 description 3
- 238000004220 aggregation Methods 0.000 description 3
- 230000008520 organization Effects 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000003542 behavioural effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000011960 computer-aided design Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 239000002071 nanotube Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- -1 wiring Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
- G06F12/0851—Cache with interleaved addressing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/32—Serial access; Scan testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1003—Interface circuits for daisy chain or ring bus memory arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/202—Non-volatile memory
- G06F2212/2022—Flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/205—Hybrid memory, e.g. using both volatile and non-volatile memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/30—Providing cache or TLB in specific location of a processing system
- G06F2212/304—In main memory subsystem
- G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/608—Details relating to cache mapping
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C2029/3202—Scan chain
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Dram (AREA)
Abstract
Description
本明細書における開示は、一般的には集積回路素子および/またはこのような素子の高速信号伝送に関する。
各種メモリ技術およびそのような各種メモリ技術を実施するメモリシステムの性能、耐久性、密度、コスト、および消費電力には著しい違いがある。特定のメモリ技術が比較的短い待ち時間または読み出しアクセス時間を有し得るのに対して、同じメモリ技術は、用途によっては適さないことがあり得る比較的長い書き込み時間を有し得る。特定のメモリ技術は、特定のメモリロケーションへの比較的少数の書き込み動作に制限され得る。限られた書き込み動作量を超えた後では、情報を確実にメモリロケーションに記憶し、メモリロケーションから検索することができない可能性がある。あるメモリ技術は、他のメモリ技術のおよそ4〜10倍の密度であり得、または他のメモリ技術よりもはるかに小さな表面面積/容積を占有し得る。あるメモリ技術は、他のメモリ技術のおよそ半分のコストである。異なるメモリ技術でのメモリアクセス動作中、異なる電力消費率に繋がる様々な電圧または電流が使用され得る。したがって、あるメモリ技術は、他よりも大きな電力を消費する。
メモリシステムは、他の実施形態もあるがこの実施形態では、コントローラと、異なる種類の集積回路メモリ素子を有するメモリモジュール階層とを含む。階層(メモリモジュールの)は、特定の種類の集積回路メモリ素子を有する1つまたは複数のメモリモジュールを含む。メモリモジュール階層は、単一の種類の集積回路メモリ素子を有するメモリモジュールを有するシステムと比較して、全体的なシステム性能を増大させることができる。第1の階層内の第1の種類の集積回路メモリ素子を使用することにより、全体的なシステム読み出し待ち時間を低減させ、書き込みデータの耐久性を増大させることができ、その一方で、より少ないコストおよびより低い消費電力を有する第2の種類の集積回路メモリを使用することにより、全体的なコストおよび消費電力は低減する。例えば、第1の階層は、コントローラおよび第2の階層の読み出し/書き込みキャッシュとして機能することができるように、少なくとも1つの揮発性メモリ素子が第1の階層に配置され、少なくとも1つの不揮発性メモリ素子が第2の階層に配置される。
Claims (17)
- メモリコントローラと、
第1のメモリ階層を定義する揮発性メモリ素子の第1のセットであって、少なくとも1つの第1のメモリモジュール上に配置され、前記少なくとも1つの第1のメモリモジュールは、前記メモリコントローラにデイジーチェーン構成で結合され、第1の集積回路バッファ素子を含む、揮発性メモリ素子の第1のセットと、
第2のメモリ階層を定義する不揮発性メモリ素子の第2のセットであって、少なくとも1つの第2のメモリモジュール上に配置され、前記少なくとも1つの第2のメモリモジュールは、前記少なくとも1つの第1のメモリモジュールにデイジーチェーン構成で結合され、第2の集積回路バッファ素子を含む、不揮発性メモリ素子の第2のセットと
を備える、メモリシステム。 - 前記メモリコントローラと前記第2のメモリ階層との間で伝送される信号は、前記第1のメモリ階層を通過する、請求項1に記載のメモリシステム。
- 前記少なくとも1つの第1のメモリモジュールは、第1の集積回路バッファ素子をそれぞれ含む複数の第1のメモリモジュールを備え、前記第1の集積回路バッファ素子のそれぞれは、ポイントツーポイントリンクの各セットを介してデイジーチェーン様式で結合される、請求項1に記載のメモリシステム。
- 前記ポイントツーポイントリンクの各セットは、信号を前記メモリコントローラに向けて送信する少なくとも1つの上流信号パスと、信号を前記メモリコントローラから離れて送信する少なくとも1つの下流信号パスとを備える、請求項3に記載のメモリシステム。
- 各ポイントツーポイントリンクは単方向シリアルリンクを含む、請求項4に記載のメモリシステム。
- 前記揮発性メモリ素子はダイナミックランダムアクセスメモリ(DRAM)素子を含む、請求項1に記載のメモリシステム。
- 前記不揮発性メモリ素子はフラッシュメモリ素子を含む、請求項1に記載のメモリシステム。
- 前記少なくとも1つの第1のメモリモジュールは、完全バッファ型デュアルインラインメモリモジュールを含む、請求項1に記載のメモリシステム。
- 前記少なくとも1つの第2のメモリモジュールは、第2の集積回路バッファ素子をそれぞれ含む複数の第2のメモリモジュールを含み、前記第2の集積回路バッファ素子のそれぞれは、ポイントツーポイントリンクの各セットを介してデイジーチェーン様式で互いに結合される、請求項1に記載のメモリシステム。
- 前記ポイントツーポイントリンクの各セットは、信号を前記メモリコントローラに向けて送信する少なくとも1つの上流信号パスと、信号を前記メモリコントローラから離れて送信する少なくとも1つの下流信号パスとを備える、請求項9に記載のメモリシステム。
- 各ポイントツーポイントリンクは単方向シリアルリンクを含む、請求項10に記載のメモリシステム。
- 少なくとも1つの第1のメモリモジュール上に配置された揮発性メモリ素子の第1のセットにデイジーチェーン様式で結合されたメモリコントローラを有するメモリシステムの動作方法であって、前記メモリシステムは、前記少なくとも1つの第1のメモリモジュールにデイジーチェーン接続された少なくとも1つの第2のメモリモジュール上に配置された不揮発性メモリ素子の第2のセットを含み、前記方法は、
書き込みデータを前記メモリコントローラから前記揮発性メモリ素子の第1のセットの部分に下流信号パスに沿って送信すること、
前記書き込みデータを前記揮発性メモリ素子の第1のセットの部分に蓄積すること、および
前記書き込みデータを前記揮発性メモリ素子の第1のセットから前記不揮発性メモリ素子の第2のセットの部分に第2の下流信号パスに沿って転送すること
を含む、方法。 - 前記送信動作、前記蓄積動作、および前記転送動作のうちの少なくとも2つは、同時に行われる、請求項12に記載の方法。
- 前記揮発性メモリ素子はダイナミックランダムアクセスメモリ素子を含み、前記不揮発性メモリ素子はフラッシュメモリ素子を含み、
前記書き込みデータを蓄積することは、前記書き込みデータをDRAM素子の同様のアドレスの並列セットに書き込むことを含み、
前記書き込みデータを前記揮発性メモリ素子の第1のセットから前記不揮発性メモリ素子の第2のセットに転送することは、前記書き込みデータを前記ダイナミックランダムアクセスメモリ素子の第1のセット内の同様のアドレスの並列セットから、前記フラッシュメモリ素子のうちの1つの中のブロックにリマッピングすることを含む、請求項12に記載の方法。 - 少なくとも1つの第1のメモリモジュール上に配置された揮発性メモリ素子の第1のセットにデイジーチェーン様式で結合されたメモリコントローラを有するメモリシステムの動作方法であって、前記メモリシステムは、前記少なくとも1つの第1のメモリモジュールにデイジーチェーン接続された少なくとも1つの第2のメモリモジュール上に配置された不揮発性メモリ素子の第2のセットを含み、前記方法は、
読み出しデータを前記不揮発性メモリ素子の第2のセットの部分から上流データパスに沿って前記揮発性メモリ素子の第1のセットに転送すること、
前記読み出しデータを前記揮発性メモリ素子の第1のセットの部分に記憶すること、
前記揮発性メモリ素子の第1のセットの前記部分に記憶されたデータにアクセスすること
を含む、方法。 - 前記転送動作、前記記憶動作、および前記アクセス動作のうちの少なくとも2つは、同時に行われる、請求項15に記載の方法。
- 少なくとも1つの第1のメモリモジュール上に配置された揮発性メモリ素子の第1のセットにデイジーチェーン様式で結合されたメモリコントローラを有するメモリシステムの動作方法であって、前記メモリシステムは、前記少なくとも1つの第1のメモリモジュールにデイジーチェーン接続された少なくとも1つの第2のメモリモジュール上に配置された不揮発性メモリ素子の第2のセットを含み、前記方法は、
第1の読み出しデータを、前記不揮発性メモリ素子の第2のセットの第1の部分から第1の上流データパスに沿って前記揮発性メモリ素子の第1のセットに転送すること、
前記第1の読み出しデータを前記不揮発性メモリ素子の第1のセットの第2の部分に書き込むこと、
前記不揮発性メモリ素子の第1のセットの第3の部分に記憶された第2のデータを識別すること、および
前記第1のデータを前記第2のデータと併合することであって、
前記第1の読み出しデータおよび前記第2のデータを前記揮発性メモリ素子の第1のセットの第1および第2の部分を下流データパスに沿って前記不揮発性メモリ素子の第2のセットに転送し、前記第1および第2のデータを前記不揮発性メモリ素子の第2のセットのブロック部分に書き込むことによって併合することを含む、方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US90935907P | 2007-03-30 | 2007-03-30 | |
US60/909,359 | 2007-03-30 | ||
PCT/US2008/057471 WO2008121559A1 (en) | 2007-03-30 | 2008-03-19 | System including hierarchical memory modules having different types of integrated circuit memory devices |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010524059A true JP2010524059A (ja) | 2010-07-15 |
JP2010524059A5 JP2010524059A5 (ja) | 2011-05-06 |
JP5401444B2 JP5401444B2 (ja) | 2014-01-29 |
Family
ID=39512709
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010501086A Active JP5401444B2 (ja) | 2007-03-30 | 2008-03-19 | 異なる種類の集積回路メモリ素子を有する階層メモリモジュールを含むシステム |
Country Status (5)
Country | Link |
---|---|
US (5) | US9195602B2 (ja) |
EP (2) | EP2132635B1 (ja) |
JP (1) | JP5401444B2 (ja) |
CN (1) | CN101689145A (ja) |
WO (1) | WO2008121559A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9569144B2 (en) | 2013-03-27 | 2017-02-14 | Hitachi, Ltd. | DRAM with SDRAM interface, and hybrid flash memory module |
US9658783B2 (en) | 2013-03-27 | 2017-05-23 | Hitachi, Ltd. | DRAM having SDRAM interface and flash memory consolidated memory module |
US9858181B2 (en) | 2013-06-20 | 2018-01-02 | Hitachi, Ltd. | Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein |
US10324854B2 (en) | 2015-03-23 | 2019-06-18 | Fujitsu Limited | Information processing apparatus and control method for dynamic cache management |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008057557A2 (en) | 2006-11-06 | 2008-05-15 | Rambus Inc. | Memory system supporting nonvolatile physical memory |
WO2008131058A2 (en) | 2007-04-17 | 2008-10-30 | Rambus Inc. | Hybrid volatile and non-volatile memory device |
US8055809B2 (en) * | 2008-12-24 | 2011-11-08 | International Business Machines Corporation | System and method for distributing signal with efficiency over microprocessor |
US9123409B2 (en) | 2009-06-11 | 2015-09-01 | Micron Technology, Inc. | Memory device for a hierarchical memory architecture |
US8245024B2 (en) * | 2009-08-21 | 2012-08-14 | Micron Technology, Inc. | Booting in systems having devices coupled in a chained configuration |
US9483399B2 (en) * | 2009-12-31 | 2016-11-01 | Micron Technology, Inc. | Sub-OS virtual memory management layer |
US8799553B2 (en) | 2010-04-13 | 2014-08-05 | Apple Inc. | Memory controller mapping on-the-fly |
US8463959B2 (en) * | 2010-05-31 | 2013-06-11 | Mosaid Technologies Incorporated | High-speed interface for daisy-chained devices |
JP5498933B2 (ja) * | 2010-12-27 | 2014-05-21 | 株式会社リガク | X線検出器 |
GB2493340A (en) * | 2011-07-28 | 2013-02-06 | St Microelectronics Res & Dev | Address mapping of boot transactions between dies in a system in package |
CN104303167B (zh) * | 2012-05-08 | 2018-01-23 | 马维尔国际贸易有限公司 | 计算机系统和存储器管理的方法 |
CN104216837A (zh) * | 2013-05-31 | 2014-12-17 | 华为技术有限公司 | 一种内存系统、内存访问请求的处理方法和计算机系统 |
US20150106547A1 (en) * | 2013-10-14 | 2015-04-16 | Micron Technology, Inc. | Distributed memory systems and methods |
WO2015127327A1 (en) * | 2014-02-23 | 2015-08-27 | Rambus Inc. | Distributed procedure execution and file systems on a memory interface |
US20150363309A1 (en) * | 2014-06-17 | 2015-12-17 | Kingtiger Technology (Canada) Inc. | System and method of increasing reliability of non-volatile memory storage |
CN105760562B (zh) * | 2014-12-19 | 2019-05-10 | 吴国盛 | 基于分层读取的集成电路设计架构 |
US10169257B2 (en) | 2015-03-06 | 2019-01-01 | Rambus Inc. | Module based data transfer |
WO2016145328A2 (en) * | 2015-03-11 | 2016-09-15 | Rambus Inc. | High performance non-volatile memory module |
KR102430561B1 (ko) * | 2015-09-11 | 2022-08-09 | 삼성전자주식회사 | 듀얼 포트 디램을 포함하는 메모리 모듈 |
EP3356943B1 (en) | 2015-10-01 | 2021-11-03 | Rambus Inc. | Memory system with cached memory module operations |
US11054992B2 (en) * | 2015-12-28 | 2021-07-06 | SK Hynix Inc. | Memory module and memory system including the memory module |
US9830086B2 (en) * | 2016-03-03 | 2017-11-28 | Samsung Electronics Co., Ltd. | Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group |
EP4145447A1 (en) * | 2016-06-27 | 2023-03-08 | Apple Inc. | Memory system having combined high density, low bandwidth and low density, high bandwidth memories |
US10847196B2 (en) * | 2016-10-31 | 2020-11-24 | Rambus Inc. | Hybrid memory module |
KR102681170B1 (ko) * | 2017-01-17 | 2024-07-04 | 에스케이하이닉스 주식회사 | 메모리 장치, 이를 포함하는 메모리 시스템, 및 그의 리페어 동작 방법 |
US10402521B1 (en) * | 2017-01-19 | 2019-09-03 | Xilinx, Inc. | Programmable integrated circuits for emulation |
US10147712B1 (en) * | 2017-07-21 | 2018-12-04 | Micron Technology, Inc. | Memory device with a multiplexed command/address bus |
US10959872B2 (en) | 2017-08-02 | 2021-03-30 | Samsung Electronics Co., Ltd. | Motion assistance apparatus |
US10490245B2 (en) | 2017-10-02 | 2019-11-26 | Micron Technology, Inc. | Memory system that supports dual-mode modulation |
US11403241B2 (en) | 2017-10-02 | 2022-08-02 | Micron Technology, Inc. | Communicating data with stacked memory dies |
US10446198B2 (en) | 2017-10-02 | 2019-10-15 | Micron Technology, Inc. | Multiple concurrent modulation schemes in a memory system |
US10725913B2 (en) | 2017-10-02 | 2020-07-28 | Micron Technology, Inc. | Variable modulation scheme for memory device access or operation |
US10355893B2 (en) | 2017-10-02 | 2019-07-16 | Micron Technology, Inc. | Multiplexing distinct signals on a single pin of a memory device |
CN111433749B (zh) | 2017-10-12 | 2023-12-08 | 拉姆伯斯公司 | 具有dram高速缓存的非易失性物理存储器 |
KR102414047B1 (ko) * | 2017-10-30 | 2022-06-29 | 에스케이하이닉스 주식회사 | 통합 메모리 디바이스 및 그의 동작 방법 |
US11544168B2 (en) | 2017-10-30 | 2023-01-03 | SK Hynix Inc. | Memory system |
CN107797945A (zh) * | 2017-10-31 | 2018-03-13 | 郑州云海信息技术有限公司 | 一种存储系统及其数据存储方法、装置、系统及设备 |
US11099779B2 (en) | 2018-09-24 | 2021-08-24 | Micron Technology, Inc. | Addressing in memory with a read identification (RID) number |
US11403035B2 (en) * | 2018-12-19 | 2022-08-02 | Micron Technology, Inc. | Memory module including a controller and interfaces for communicating with a host and another memory module |
US11416422B2 (en) | 2019-09-17 | 2022-08-16 | Micron Technology, Inc. | Memory chip having an integrated data mover |
US11163490B2 (en) | 2019-09-17 | 2021-11-02 | Micron Technology, Inc. | Programmable engine for data movement |
US11397694B2 (en) | 2019-09-17 | 2022-07-26 | Micron Technology, Inc. | Memory chip connecting a system on a chip and an accelerator chip |
US20210081318A1 (en) * | 2019-09-17 | 2021-03-18 | Micron Technology, Inc. | Flexible provisioning of multi-tier memory |
US11604744B2 (en) | 2020-10-16 | 2023-03-14 | Alibaba Group Holding Limited | Dual-modal memory interface controller |
US20240152279A1 (en) * | 2022-11-08 | 2024-05-09 | Micron Technology, Inc. | Memory sub-system for memory cell in-field touch-up |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04324194A (ja) * | 1991-04-25 | 1992-11-13 | Nec Corp | Rom回路 |
JP2002366429A (ja) * | 2001-06-11 | 2002-12-20 | Hitachi Ltd | 半導体記憶装置 |
JP2004502240A (ja) * | 2000-06-27 | 2004-01-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | フラッシュを備えた集積回路 |
WO2005038660A2 (en) * | 2003-10-17 | 2005-04-28 | Micron Technology, Inc. | Method and apparatus for sending data from multiple sources over a communications bus |
US20060095671A1 (en) * | 2004-10-29 | 2006-05-04 | International Business Machines Corporation | System, method and storage medium for providing data caching and data compression in a memory subsystem |
JP2006313538A (ja) * | 2005-05-03 | 2006-11-16 | Samsung Electronics Co Ltd | メモリモジュール及びメモリシステム |
JP2007080258A (ja) * | 2005-09-12 | 2007-03-29 | Samsung Electronics Co Ltd | ポイントツーポイントリンクを有するメモリシステム及び方法 |
WO2008074140A1 (en) * | 2006-12-20 | 2008-06-26 | Mosaid Technologies Incorporated | Hybrid solid-state memory system having volatile and non-volatile memory |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5359569A (en) | 1991-10-29 | 1994-10-25 | Hitachi Ltd. | Semiconductor memory |
US6170047B1 (en) * | 1994-11-16 | 2001-01-02 | Interactive Silicon, Inc. | System and method for managing system memory and/or non-volatile memory using a memory controller with integrated compression and decompression capabilities |
AU1798999A (en) * | 1997-12-05 | 1999-06-28 | Intel Corporation | Memory system including a memory module having a memory module controller |
US6553450B1 (en) | 2000-09-18 | 2003-04-22 | Intel Corporation | Buffer to multiply memory interface |
US6625687B1 (en) | 2000-09-18 | 2003-09-23 | Intel Corporation | Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing |
US6877079B2 (en) | 2001-03-06 | 2005-04-05 | Samsung Electronics Co., Ltd. | Memory system having point-to-point bus configuration |
JP4863749B2 (ja) * | 2006-03-29 | 2012-01-25 | 株式会社日立製作所 | フラッシュメモリを用いた記憶装置、その消去回数平準化方法、及び消去回数平準化プログラム |
US7966469B2 (en) * | 2006-08-14 | 2011-06-21 | Qimonda Ag | Memory system and method for operating a memory system |
US7564722B2 (en) * | 2007-01-22 | 2009-07-21 | Micron Technology, Inc. | Memory system and method having volatile and non-volatile memory devices at same hierarchical level |
US8185685B2 (en) * | 2007-12-14 | 2012-05-22 | Hitachi Global Storage Technologies Netherlands B.V. | NAND flash module replacement for DRAM module |
US9547589B2 (en) * | 2008-06-18 | 2017-01-17 | Super Talent Technology, Corp. | Endurance translation layer (ETL) and diversion of temp files for reduced flash wear of a super-endurance solid-state drive |
KR102534648B1 (ko) * | 2018-03-08 | 2023-05-22 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 그것의 동작 방법 |
US11442635B2 (en) * | 2019-01-10 | 2022-09-13 | Western Digital Technologies, Inc. | Data storage systems and methods for optimized scheduling of background management operations |
-
2008
- 2008-03-19 JP JP2010501086A patent/JP5401444B2/ja active Active
- 2008-03-19 US US12/529,323 patent/US9195602B2/en active Active
- 2008-03-19 WO PCT/US2008/057471 patent/WO2008121559A1/en active Application Filing
- 2008-03-19 EP EP08732464.6A patent/EP2132635B1/en active Active
- 2008-03-19 CN CN200880010770A patent/CN101689145A/zh active Pending
- 2008-03-19 EP EP17186301.2A patent/EP3279798B1/en active Active
-
2015
- 2015-10-15 US US14/883,916 patent/US9460021B2/en active Active
-
2016
- 2016-09-30 US US15/282,932 patent/US9767918B2/en active Active
-
2017
- 2017-08-30 US US15/691,646 patent/US10755794B2/en active Active
-
2020
- 2020-08-21 US US17/000,130 patent/US11823757B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04324194A (ja) * | 1991-04-25 | 1992-11-13 | Nec Corp | Rom回路 |
JP2004502240A (ja) * | 2000-06-27 | 2004-01-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | フラッシュを備えた集積回路 |
JP2002366429A (ja) * | 2001-06-11 | 2002-12-20 | Hitachi Ltd | 半導体記憶装置 |
WO2005038660A2 (en) * | 2003-10-17 | 2005-04-28 | Micron Technology, Inc. | Method and apparatus for sending data from multiple sources over a communications bus |
US20060095671A1 (en) * | 2004-10-29 | 2006-05-04 | International Business Machines Corporation | System, method and storage medium for providing data caching and data compression in a memory subsystem |
JP2006313538A (ja) * | 2005-05-03 | 2006-11-16 | Samsung Electronics Co Ltd | メモリモジュール及びメモリシステム |
JP2007080258A (ja) * | 2005-09-12 | 2007-03-29 | Samsung Electronics Co Ltd | ポイントツーポイントリンクを有するメモリシステム及び方法 |
WO2008074140A1 (en) * | 2006-12-20 | 2008-06-26 | Mosaid Technologies Incorporated | Hybrid solid-state memory system having volatile and non-volatile memory |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9569144B2 (en) | 2013-03-27 | 2017-02-14 | Hitachi, Ltd. | DRAM with SDRAM interface, and hybrid flash memory module |
US9658783B2 (en) | 2013-03-27 | 2017-05-23 | Hitachi, Ltd. | DRAM having SDRAM interface and flash memory consolidated memory module |
US9858181B2 (en) | 2013-06-20 | 2018-01-02 | Hitachi, Ltd. | Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein |
US10324854B2 (en) | 2015-03-23 | 2019-06-18 | Fujitsu Limited | Information processing apparatus and control method for dynamic cache management |
Also Published As
Publication number | Publication date |
---|---|
WO2008121559A1 (en) | 2008-10-09 |
US20160098354A1 (en) | 2016-04-07 |
US20210035652A1 (en) | 2021-02-04 |
US11823757B2 (en) | 2023-11-21 |
EP2132635A1 (en) | 2009-12-16 |
EP3279798A1 (en) | 2018-02-07 |
US20100115191A1 (en) | 2010-05-06 |
US9767918B2 (en) | 2017-09-19 |
US9460021B2 (en) | 2016-10-04 |
US9195602B2 (en) | 2015-11-24 |
US20170025187A1 (en) | 2017-01-26 |
US10755794B2 (en) | 2020-08-25 |
EP2132635B1 (en) | 2017-08-16 |
JP5401444B2 (ja) | 2014-01-29 |
EP3279798B1 (en) | 2020-07-29 |
CN101689145A (zh) | 2010-03-31 |
US20170365354A1 (en) | 2017-12-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11823757B2 (en) | System including hierarchical memory modules having different types of integrated circuit memory devices | |
JP6339280B2 (ja) | ハイブリッドメモリのためのシステム、方法及び装置 | |
US7313644B2 (en) | Memory device interface | |
US7451273B2 (en) | System, method and storage medium for providing data caching and data compression in a memory subsystem | |
US10545689B2 (en) | Data storage device and operating method thereof | |
US10978120B2 (en) | Memory interface circuit, memory storage device and signal generation method | |
EP4170658A1 (en) | Semiconductor memory devices and methods of operating the same | |
US20240241646A1 (en) | Memory system and method of operating memory system | |
US20240125851A1 (en) | Multi-modal memory apparatuses and systems | |
CN114842887A (zh) | 存储器系统 | |
CN118430628A (zh) | 包括修复电路的存储器设备及其操作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110318 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110318 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130128 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130206 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130502 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20130528 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130927 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20131004 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131022 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131028 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5401444 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |