JP2010512560A - Information processing apparatus and nonvolatile semiconductor memory drive - Google Patents

Abstract

  The control unit of the nonvolatile semiconductor memory drive initializes an address management table indicating a correspondence relationship between each logical block address and each physical address of the nonvolatile semiconductor memory, and user data is written in the storage area of the nonvolatile semiconductor memory. A first erasing mode that is set to a non-existing state, the address management table is initialized, the storage area is set to a state in which no user data is written, and each block other than a defective block included in the storage area is set A second erasing mode to be erased, the address management table is initialized, the storage area is set to a state in which no user data is written, and each of the blocks including the defective block included in the storage area is erased. 3 erase modes.

Description

  The present invention relates to an information processing apparatus and a nonvolatile semiconductor memory drive.

  In recent years, data storage devices such as hard disks have been widely used.

  Patent Document 1 discloses a data storage device having a scramble / descramble function. This data storage device includes transmission / reception means, scrambler means, a hard disk, descrambler means, memory, and initial value changing means. The transmission / reception means receives information from the outside and transmits information in the data storage device to the outside. The scrambler means randomizes information from the outside received by the transmission / reception means. The output signal of the scrambler means is recorded on the hard disk. The descrambler means descrambles the signal read from the hard disk. The memory outputs initial values to the scrambler means and the descrambler means. The initial value changing means changes the initial value when erasing data recorded on the hard disk.

  In this data storage device, when erasure of data on the hard disk is instructed via the transmission / reception means, the initial value changing means generates new initial values for the scrambler means and the descrambler means. The newly recorded data is scrambled and descrambled based on the new initial value.

  On the other hand, data already recorded on the hard disk before the change of the initial value is reproduced after being descrambled based on an initial value different from the initial value before the change. For this reason, data already recorded on the hard disk before the change of the initial value is descrambled with a completely different initial value from that when the data was recorded, so that data with a different value is read out.

  Therefore, data stored before the change of the initial value cannot be normally read out, and thus the change of the initial value virtually erases the hard disk. Therefore, it is possible to virtually erase data instantaneously without overwriting recording the erased data on the hard disk of the data storage device. As a result, it is possible to significantly reduce the work time required for the reuse and disposal of the hard disk.

JP 2006-196135 A

  However, according to the conventional data storage device, it is difficult to decode the scrambled data, but it is easy to extract the scrambled data, so that it can be decoded by the progress of decoding technology. Sex cannot be denied.

  An object of the present invention is to provide an information processing apparatus and a non-volatile semiconductor memory drive capable of reliably erasing written information and reliably preventing information leakage.

  According to one aspect of the present invention, an information processing apparatus body, a nonvolatile semiconductor memory drive housed in the information processing apparatus body, and a nonvolatile semiconductor memory having a storage area including a plurality of blocks, and a logical block A first erase mode for initializing an address management table indicating a correspondence relationship between each address and each physical address of the nonvolatile semiconductor memory and setting the storage area in a state in which no user data is written; and the address management table , And sets the storage area to a state where no user data is written, and initializes a second erase mode for erasing each block included in the storage area other than a defective block, and the address management table. The storage area is set to a state in which no user data is written, and A third erase mode for erasing each block including a defective block included in the memory, and selectively using the first erase mode, the second erase mode, and the third erase mode, There is provided an information processing apparatus comprising control means for executing an erasing operation on the storage area.

  According to this information processing apparatus, it is possible to reliably erase the written information and reliably prevent information leakage.

FIG. 1 is a perspective view showing an appearance of an information processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the embodiment. FIG. 3 is a block diagram showing a schematic configuration of the SSD provided in the information processing apparatus according to the embodiment. FIG. 4 is a schematic diagram showing the storage capacity and storage area of the SSD shown in FIG. FIG. 5 is a schematic configuration diagram of a NAND memory provided in the SSD shown in FIG. FIG. 6 is a schematic diagram for explaining three types of erasing methods that can be executed by the SSD shown in FIG. FIG. 7 is a flowchart showing an example of a pseudo erase procedure executed by the SSD shown in FIG. FIG. 8 is a flowchart showing an example of a normal erasing procedure executed by the SSD shown in FIG. FIG. 9 is a flowchart showing an example of an extended erase procedure executed by the SSD shown in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Configuration of information processing apparatus>
FIG. 1 is a perspective view showing an appearance of an information processing apparatus according to an embodiment of the present invention. As shown in FIG. 1, the information processing apparatus 1 includes a main body 2 and a display unit 3 attached to the main body 2.

  The main body 2 has a box-shaped housing 4, and the housing 4 includes an upper wall 4 a, a peripheral wall 4 b, and a lower wall 4 c. The upper wall 4a of the housing 4 includes a front part 40, a central part 41, and a back part 42 in order from the side closer to the user who operates the information processing apparatus 1. The lower wall 4c faces the installation surface on which the information processing apparatus 1 is placed. The peripheral wall 4b has a front wall 4ba, a rear wall 4bb, and left and right side walls 4bc, 4bd.

  The front unit 40 includes a touch pad 20 that is a pointing device, a palm rest 21, and a light emitting diode (LED) 22 that lights up in conjunction with the operation of each unit of the information processing apparatus 1.

  The central portion 41 includes a keyboard placement portion 23 to which a keyboard 23a capable of inputting character information and the like is attached.

  The back part 42 includes a battery pack 24 that is detachably attached. On the right side of the battery pack 24, a power switch 25 for turning on the information processing apparatus 1 is provided. A pair of hinge portions 26 a and 26 b that rotatably support the display unit 3 are provided on the left and right sides of the battery pack 24.

  The left side wall 4bc of the housing 4 is provided with a discharge port (not shown) for discharging wind from the inside of the housing 4 to the outside. Further, on the right side wall 4bd, for example, an ODD (optical disc drive) 27 capable of reading and writing data from and on an optical storage medium such as a DVD, and a card slot 28 in which various cards are inserted and removed are arranged.

  The casing 4 is formed by a casing cover including a part of the peripheral wall 4b and the upper wall 4a, and a casing base including a part of the peripheral wall 4b and the lower wall 4c. The housing cover is detachably combined with the housing base to form an accommodation space with the housing base. In this accommodation space, an SSD (solid state drive) 10 that functions as a nonvolatile semiconductor memory drive is accommodated. Details of the SSD 10 will be described later.

  The display unit 3 includes a display housing 30 having an opening 30a and a display device 31 including an LCD or the like that can display an image on a display screen 31a. The display device 31 is accommodated in the display housing 30, and the display screen 31a is exposed to the outside of the display housing 30 through the opening 30a.

  In the housing 4, in addition to the SSD 10, the battery pack 24, the ODD 27, and the card slot 28, a main circuit board, an expansion module, a fan, and the like (not shown) are accommodated.

  FIG. 2 is a block diagram schematically showing the system configuration of the information processing apparatus 1.

As shown in FIG. 2, the information processing apparatus 1 includes the SSD 10, the expansion module 12, the fan 13, the touch pad 20, the LED 22, the keyboard 23a, the power switch 25, the ODD 27, the card slot 28, and the display device 31. , EC (Embedded Controller) 111, Flash Memory 112 for storing BIOS (Basic Input Output System) 112a, South Bridge 113, North Bridge 114, CPU (Central Processing Unit) 115, GPU (Graphic Processing Unit) 116 and a main memory 117.

  An EC (embedded controller) 111 is an embedded system that controls each unit. The north bridge 114 is an LSI that controls connections among the CPU 115, the GPU 116, the main memory 117, and various buses. The CPU 115 is a processor that performs arithmetic processing on various signals, and executes an operating system and various application programs loaded from the SSD 10 to the main memory 117. The GPU 116 is a display controller that performs display control by processing video signals.

  The extension module 12 includes an extension circuit board, a card socket provided on the extension circuit board, and an extension module board inserted into the card socket. The card socket corresponds to a standard such as Mini-PCI, for example. Examples of the extension module substrate include a 3G (third generation) module, a television tuner, a GPS module, and a Wimax (registered trademark) module.

  The fan 13 is a cooling unit that cools the inside of the housing 4 based on the blown air, and discharges the air in the housing 4 to the outside as a wind through a discharge port (not shown).

  The EC 111, the flash memory 112, the south bridge 113, the north bridge 114, the CPU 115, the GPU 116, and the main memory 117 are electronic components mounted on the main circuit board.

<Configuration of SSD>
FIG. 3 is a block diagram showing a schematic configuration of the SSD applied to the information processing apparatus of the present embodiment. The SSD 10 is a nonvolatile semiconductor memory drive used as an external storage device of the information processing apparatus 1 instead of a hard disk. As shown in FIG. 3, the SSD 10 includes a connector 102, a control unit 103, NAND memories (NAND flash EEPROMs) 104 </ b> A to 104 </ b> H, a DRAM (memory) 105, and a power supply circuit 106. Has been. The SSD 10 is an external storage device that stores data and programs and whose stored contents are not lost even when power is not supplied. Unlike a hard disk drive, the SSD 10 does not have a drive mechanism such as a magnetic disk or a head. It is a drive that can store data created based on it in a readable and writable manner for a long time and can operate as a startup drive of the information processing apparatus 1.

  The control unit 103 is connected to the connector 102, the eight NAND memories 104A to 104H, the DRAM 105, and the power supply circuit 106, respectively. The control unit 103 is connected to the host device 8 via the connector 102, and is connected to the external device 9 as necessary.

  The power source 7 is a battery pack 24 or an AC adapter (not shown). For example, DC 3.3 V is supplied to the power circuit 106 via the connector 102. The power source 7 supplies power to the entire information processing apparatus 1.

  In the present embodiment, the host device 8 is the information processing apparatus main body 2 (the main circuit board of the main body 2). The south bridge 113 mounted on the main circuit board is connected to the control unit 103 via the connector 102. Data transmission / reception is performed between the south bridge 113 and the control unit 103 based on a standard such as serial ATA.

  The external device 9 is another information processing device different from the information processing device 1. The external device 9 is connected to the control unit 103 based on a standard such as RS-232C, for example, with respect to the SSD 10 removed from the information processing device 1, and has a function of reading data stored in the NAND memories 104A to 104H. Have.

  The board on which the SSD 10 is mounted has an outer size equivalent to, for example, a 1.8 inch type or 2.5 inch type HDD (hard disk drive). In this embodiment, it is equivalent to the 1.8 inch type.

  The control unit 103 controls reading and writing of data with respect to the NAND memories 104A to 104H. Specifically, the control unit 103 executes data reading and writing with respect to the NAND memories 104A to 104H in response to a request (read command, write command, etc.) from the information processing apparatus body 2 functioning as the host device 8. To control. Each NAND memory has a plurality of sectors. Control of execution of data read and write for each of the sectors of the NAND memories 104A to 104H is executed in units of a predetermined number of sector groups called clusters. The data transfer rate is, for example, 100 MB / Sec when reading data and 40 MB / Sec when writing.

  Each of the NAND memories 104A to 104H is, for example, a nonvolatile semiconductor memory having a storage capacity of 16 GB. Each of the NAND memories 104A to 104H is composed of, for example, an MLC (multilevel cell) -NAND memory (multilevel NAND memory) capable of recording 2 bits in one memory cell. The MLC-NAND memory has a smaller number of rewritable times than an SLC (single level cell) -NAND memory, but has a feature that it is easier to increase the storage capacity than an SLC (single level cell) -NAND memory. Have.

  The DRAM 105 is a buffer in which data is temporarily stored when data is read from and written to the NAND memories 104A to 104H under the control of the control unit 103. The DRAM 105 functions as a write cache that temporarily stores write data from the information processing apparatus main body 2 that functions as the host device 8.

  The connector 102 has a shape based on a standard such as serial ATA. Note that the control unit 103 and the power supply circuit 106 may be connected to the host device 8 and the power supply 7 by separate connectors, respectively.

  The power supply circuit 106 converts DC 3.3V supplied from the power supply 7 into, for example, DC 1.8V, 1.2V, and the like, and supplies these three types of voltages to each unit according to the drive voltage of each unit of the SSD 10. .

<Storage capacity of SSD>
FIG. 4 is a schematic diagram showing the storage capacity and storage area of the SSD 10. The control unit 103 of the SSD 10 manages seven types of storage capacities 104a to 104g shown in FIG.

  The storage capacity 104a is a NAND capacity, and is the maximum storage capacity using the storage areas of all the NAND memories 104A to 104H. That is, the storage capacity 104a is a total value of physical storage capacities of the NAND memories 104A to 104H. For example, when the storage capacity of each of the NAND memories 104A to 104H is 16 GB, the storage capacity 104a is 128 GB. The storage capacity 104a, that is, NAND Capacity is given by NAND configuration information of a manufacturing information write command of UART (Universal Asynchronous Receiver Transmitter), for example.

  The storage capacity 104b is Max Logical Capacity, and is the maximum storage capacity that can be accessed by a logical block address (LBA).

  The storage capacity 104c is S.I. M.M. A. R. The T log area start LBA is provided to divide the storage capacity 104b and the storage capacity 104d described below. S. M.M. A. R. The T log area start LBA indicates the head LBA of the storage area for storing the log data.

  The storage capacity 104d is a Vender Native Capacity, and is the maximum storage capacity given as a user use area. The storage capacity 104d is given by, for example, initial Identical Device data of an ATA special command. The storage capacity 104d is determined at the design stage of the SSD 10 by the manufacturer (Vender) based on the IDEMA (The International Disk Drive Equipment and Materials Association) standard, and is expressed by the following equation.

LBA = 97,696,368 + (1,953,504, × ((Capacity in GB)-50))
The storage capacity 104e is an OEM Native Capacity, and is a storage capacity determined at the time of manufacture according to a request from an OEM (Original Equipment Manufacturer). The storage capacity 104e is given, for example, by writing unique information of an ATA special command. The storage capacity 104e is a value returned by the Device Configuration Identify command when the Device Configuration Overlay Feature Set is supported.

  The storage capacity 104f is a native capacity, and the initial value is the same as the storage capacity 104e. When Feature set is supported, it is a value that can be changed with the Device Configuration Set command. The storage capacity 104f is a value returned by a Read Native Max Address (EXT) command.

  The storage capacity 104g is a current capacity and is a storage capacity in use by the user, and an initial value is the same as the storage capacity 104f. It can be changed with the Set Max Address command. It is a value returned by Word 61:60 and Word 103: 100 of the Identify Device command.

  In addition, the storage area of the SSD 10 exists between the storage capacities 104a to 104g.

  In a storage area (management area) between the storage capacities 104a and 104b, management data 107a for operating the SSD 10 and an address conversion table (logical / physical table) 108a are stored. The address conversion table (logical / physical table) 108a is an address management table for converting a logical block address LBA into a physical address corresponding to a sector which is a storage unit of the NAND memories 104A to 104H. This address conversion table (logical / physical table) 108a shows the correspondence between each logical block address LBA and each physical address of the NAND memories 104A to 104H. For example, in the address conversion table (logical / physical table) 108a, the correspondence between the logical block address LBA and the physical addresses of the NAND memories 104A to 104H is managed in cluster units. Each cluster is composed of a predetermined number of sectors as described above. Each of the NAND memories 104A to 104H has a plurality of sectors.

  Each of the management data 107a and the logical / physical table 108a is data recorded in a fixed area in the NAND memories 104A to 104H. No LBA is assigned to each of the management data 107a and the logical / physical table 108a. Therefore, the management data 107a and the logical / physical table 108a cannot be accessed using the LBA as a key. The control unit 103 has a fixed access path for accessing the management data 107a and the logical / physical table 108a, and accesses the management data 107a and the logical / physical table 108a through the fixed access path. Execute.

  The storage area between the storage capacity 104b and the storage capacity 104c includes S.I. M.M. A. R. T.A. (Self-Monitoring Analysis and Reporting Technology) Log data 107b is stored. S. M.M. A. R. T.A. The log data 107b is statistical information such as temperature information, for example. S. M.M. A. R. T.A. The LBA assigned to the log data 107b is the firmware executed in the control unit 103 as S.P. M.M. A. R. T.A. This is used locally to access the log data 107b. The firmware executed in the control unit 103 is S.M. M.M. A. R. T.A. The log data 107b can be accessed using the LBA as a key. M.M. A. R. T.A. The log data 107b cannot be accessed.

  For example, an unused storage area having a storage capacity of 2 MB is set in the storage area between the storage capacities 104c and 104d. This is because the minimum storage unit of LBA is 8 sectors and is a storage unit corresponding to 4 KB (a large storage unit is 1 MB), but the actual minimum recording unit of data is naturally 1 sector. By providing a free storage area having a storage capacity of 1 MB or more between the capacities 104c and 104d, the S.I. M.M. A. R. T.A. This is because the log data 107b and the data recorded below the storage capacity 104d are handled independently.

  The storage areas between the storage capacities 104d and 104e are unused and the storage capacities 104d and 104e have the same value except in special cases.

  The storage area between the storage capacities 104e and 104f is a storage area used by the OEM, and the unique information 107e determined by the OEM request is written as described above.

  The storage area between the storage capacities 104f and 104g is a storage area used by the OEM or the user, and data is written according to the setting of the OEM or the user.

  The storage area of the storage capacity 104g is a storage area used by the user, and data is written according to user settings.

  The storage capacities 104a to 104g satisfy the relationship represented by the following formula.

Storage capacity 104a> Storage capacity 104b> Storage capacity 104c> Storage capacity 104d ≧ Storage capacity 104e ≧ Storage capacity 104f ≧ Storage capacity 104g
At the time of shipment from the manufacturer (Vender), the storage capacities 104d to 104g have the same value.

<Configuration of NAND memory>
FIG. 5 is a schematic configuration diagram of a NAND memory used in this embodiment, and FIG. 6 is a schematic diagram for explaining three types of erasing methods used in this embodiment. Since the NAND memories 104A to 104H have the same function and configuration, the NAND memory 104A will be described below. Note that the numbers 0 to 7 given to the left of the cluster (storage unit) 1041 and the sector 1042 indicate the cluster number and the sector number. Also, Free 1070 shown in FIG. 6 schematically represents a group (first storage area) of blocks 1040 in which data can be written, and Active 1071 is a write in which data has already been written. The block (second storage area) of the completed blocks 1040a is schematically represented, and the Bad Block 1072 schematically represents a group (third storage area) of defective blocks 1043 that cannot be corrected later. Free 1070, Active 1071, and Bad Block 1072 are stored in the management data 107a as parameters indicating the state of each block 1040. In addition, hatched lines in FIG. 6 indicate that data is stored.

  The NAND memory 104A is composed of a plurality of blocks 1040. Each block 1040 is composed of 1024 clusters 1041, and each cluster 1041 is composed of 8 sectors 1042.

  When writing write data less than the data size of one cluster 1041, the control unit 103 reads a predetermined number (for example, eight) sectors 1042 constituting the cluster 1041 based on the management data 107a. The data of those sectors is temporarily stored in the DRAM 105. Then, the control unit 103 writes the write data to the read cluster on the DRAM 105, and writes the cluster in which the write data is written from the DRAM 105 to the cluster 1041 of the corresponding NAND memory.

  In FIG. 5, a defective block 1043 indicated by hatching is a block in which an error occurs when data is written or read. As an example, for example, the block 1040 in which the SSD 10 has been erased or an error has occurred.

<Operation>
Hereinafter, the operation of the information processing apparatus 1 according to the present embodiment will be described focusing on three types of erasing methods with reference to the drawings.

  First, an outline of three types of erasing methods will be described.

  The control unit 103 controls writing and reading of data to and from the storage areas (NAND storage areas) of the NAND memories 104A to 104H using the logical / physical table 108a. The control unit 103 has a security erase function for erasing all user data stored in the NAND storage area.

  The control unit 103 has a pseudo erase mode, a normal erase mode, and an extended erase mode as erase operation modes for erasing all user data stored in the NAND storage area. The control unit 103 executes an erase operation on the NAND storage area by selectively using the pseudo erase mode, the normal erase mode, and the extended erase mode.

  The pseudo erase mode is a first erase mode in which the logical / physical table 108a is initialized and a NAND storage area including a plurality of blocks 1040 is set in a state in which user data is not written. The process of initializing the logical / physical table 108a is a process of setting the logical / physical table 108a to a state in which the physical address corresponding to each logical block address LBA is not written in the logical / physical table 108a. In the process of initializing the logical / physical table 108a, the control unit 103, for example, deletes the physical address corresponding to each LBA from the logical / physical table 108a, or stores the logical address in each LBA stored in the logical / physical table 108a. On the other hand, a process for setting a flag indicating that the storage area corresponding to the LBA is in an unwritten state is executed. Thus, by initializing the logical / physical table 108a, each block in which user data is written results in a state in which user data is not yet written, that is, an unused free block. Thus, in the pseudo erase mode, the process of actually erasing each block or the process of writing zero data to each block is not executed, but instead, the logical / physical table 108a is initialized. As a result, user data can be erased at a higher speed than when processing for writing zero data in all blocks is performed.

  When receiving a command (special command) designating the pseudo erase mode from the host device 8, the control unit 103 initializes the logical / physical table 108a and sets each block to a state in which user data is not yet written. However, S. M.M. A. R. T.A. The physical address corresponding to the log data is not deleted from the logical / physical table 108a.

  When receiving the read command from the host device 8, the control unit 103 refers to the logical / physical table 108a to determine whether or not the storage area specified by the LBA included in the read command is in an unwritten state. To do. If the storage area specified by the LBA is in an unwritten state, the control unit 103 sends a predetermined value (for example, zero data) indicating that the storage area specified by the LBA has been erased to the host device 8. .

  In the normal erase mode, the logical / physical table 108a is initialized, the NAND storage area including the plurality of blocks 1040 is set to a state in which user data is not written, and each of the non-defective blocks included in the NAND storage area is included. This is the second erase mode for erasing the block. That is, in the normal erase mode, by initializing the logical / physical table 108a, in addition to the process of making each block in which user data has been written a free block, a process for erasing each free block (block erase process) is performed. Executed. In the normal erase mode, the defective block is excluded from the erase process target. A defective block is a block in which an error occurs when data is written or read.

  When receiving a command designating the normal erasing mode from the host device 8, the control unit 103 initializes the logical / physical table 108a and other than management data (including SMART log data). Each block storing user data (user data) is set to a state in which user data is not yet written (free block). And the control part 103 performs a block erase process with respect to all the free blocks.

  The extended erase mode is an erase mode in which each defective block is erased in addition to the erase operation in the normal erase mode. In other words, in the extended erase mode, the logical / physical table 108a is initialized to set the NAND storage area to a state where no user data is written, and each block including a defective block included in the NAND storage area is set. This is the third erase mode for erasing.

  When receiving a command designating the extended erasure mode from the host device 8, the control unit 103 initializes the logical / physical table 108a, and other than management data (including SMART log data). Each block storing user data (user data) is set to a state in which user data is not yet written (free block). And the control part 103 performs a block erase process with respect to all the free blocks and each bad block.

  Hereinafter, an example of the operation of the information processing apparatus 1 will be described.

  When the user presses the power switch 25, the EC 111 that detects the pressing of the power switch 25 starts to supply power from the power supply 7 to each unit of the information processing apparatus 1. Then, the EC 111 activates the information processing apparatus 1 based on the BIOS 112a.

  When the activation of the information processing apparatus 1 is completed, the user performs an operation on the information processing apparatus 1 using the touch pad 20 and the keyboard 23a while viewing the display screen 31a of the display apparatus 31.

  When the information processing apparatus 1 receives an operation by the user, the information processing apparatus 1 performs a predetermined operation in accordance with the operation. For example, when the CPU 15 of the information processing apparatus 1 accepts an operation for displaying the data stored in the SSD 10 on the display device 31, the CPU 115 sends a read command for instructing reading of data to the SSD 10. Next, the control unit 103 of the SSD 10 reads data from the NAND memories 104A to 104H and sends the data to the GPU 116 via the south bridge 113 and the north bridge 114. Then, the GPU 116 displays the data on the display device 31 as an image.

<Pseudo erase>
FIG. 7 is a flowchart showing an example of the pseudo erase mode as the first erase mode used in the present embodiment. First, an example of the method of the pseudo erase 10A will be described with reference to the flowchart of FIG.

For example, the user operates the image displayed on the display screen 31a of the display device 31 by operating the application via the touch pad 20 and the keyboard 23a, and deletes, for example, the document stored in the SSD 10 by using the touch pad 20 and An instruction is given using the keyboard 23a (step S1), and the CPU 115 instructs the SSD 10 to delete the data (predetermined information) of the document instructed to be deleted.

  When the control unit 103 of the SSD 10 receives a command from the CPU 115 via the connector 102, the control unit 103 refers to the management data 107a of each of the NAND memories 104A to 104H and searches the NAND memory in which the document data is stored. Based on the management data 107a, the control unit 103, for example, includes the sector data included in the block 1044 whose status is Active 1071 shown in FIG. 6 (for example, the data included in the block 1040 shown in FIG. 5). It is determined whether it is stored in the sector 1042a). If the data of the document to be erased is stored in the sector included in the block 1044 whose status is Active 1071, the control unit 103 changes the status of the management data 107a corresponding to this block 1044 from Active 1071 to Free 1070. Update (step S2). Note that the block 1044 stores only document data to be erased.

  The above-described erasing method is called pseudo-erasing 10A, and only the status of the management data 107a of the document data to be erased is updated. Since the document data itself is not erased, it can be performed at high speed. In this erasing method, for example, when the SSD 10 in which highly confidential data is stored is discarded, the data itself may remain in the SSD 10 and the data may be read out.

  Although the case where the pseudo erase 10A is applied to erase for a specific block has been described here, the pseudo erase 10A is applied to all blocks in which data other than management data (user data) is written. Applicable. That is, when receiving a command (special command) designating the pseudo erasure mode from the CPU 115, the control unit 103 initializes the logical / physical table 108a, and each block in which user data is written (each active block). ) Is set to a state in which user data is not written (free block). As a result, S.I. M.M. A. R. T.A. Almost all blocks other than the block storing the log data are free blocks.

<Normal deletion>
FIG. 8 is a flowchart for normal erasure as the second erasure according to the present embodiment. Next, the normal erasing method 10B will be described with reference to the flowchart of FIG. In the following description, operations common to the pseudo erase 10A are omitted.

  Similar to the above-described pseudo erasure 10A, when the user instructs the erasure of the document (step S3), the control unit 103 determines that the data of the document to be erased is based on the management data 107a, for example, as shown in FIG. As shown, when stored in the sector (written sector) 1042a of the block 1045 whose state is Active 1071, the block 1045 is erased to erase the data stored in the block 1045, and the management corresponding to the block 1045 The state of the data 107a is updated from Active 1071 to Free 1070 (step S4). Note that the block 1045 stores only document data to be erased.

  The above erasing method is called normal erasing 10B, and the data of the document to be erased is erased and the management data 107a is updated. For example, when the SSD 10 in which highly confidential data is stored is discarded, the normal erasure 10B can be performed more securely than the pseudo erasure 10A. However, since the data stored in the bad block 1043 in the Bad Block 1072 state is not erased, it cannot be said that complete erasure that makes it impossible to read highly confidential data has been performed.

  Here, the case where the normal erase 10B is applied to erase for a specific block has been described, but the normal erase 10B is applied to all blocks in which data other than management data (user data) is written. Applicable. That is, when receiving a command designating the normal erasing mode from the CPU 115, the control unit 103 first initializes the logical / physical table 108a and sets each block in which user data is written (each block in an active state). The user data is not written (free block). Thereafter, the control unit 103 erases each block included in the NAND storage area other than the defective block, that is, each of all the free blocks by block erasure.

  Next, an extended erase 10C, which is a complete erase method that makes it impossible to read highly confidential data, will be described.

<Extended erase>
FIG. 9 is a flowchart for extended erasure as the third erasure.

  The extended erase 10C deletes all data (user data) of the SSD 10. As an example, when an optical disk storing an operating system necessary for starting the information processing apparatus 1 is inserted into the ODD 27, the information processing apparatus 1 is started from the optical disk, and an application that can execute the extended erasure 10C of the SSD 10 is started. Is assumed.

  As an example, the user instructs extended erasure 10C using the touch pad 20 and the keyboard 23a while viewing the erasure item displayed on the display screen 31a (step S5), and the CPU 115 instructs the SSD 10 to execute the extended erasure 10C. To do.

  When the extended deletion 10C of the SSD 10 is instructed by the user, the control unit 103 deletes all data stored in the Free 1070, Active 1071, and Bad Block 1072 and updates the management data 107a (Step S6). The update of the management data 107a is to update the block 1043 and the block 1040 in the state of the Active 1071 and the Bad Block 1072 to the state of the Free 1070.

  The above-described erasing method is called extended erasing 10C, and is erasing including the Bad Block 1072, so that data can be erased more reliably than other erasing methods. This extended erasure 10C is suitable, for example, when discarding the SSD 10 storing highly confidential data.

The execution of the extended erase 10C may be performed by a command operation or the like, not by the activation of the application stored on the optical disk.

  In step S6, for example, the following processing is executed. That is, when receiving a command designating the extended erasure mode from the host device 8, the control unit 103 initializes the logical / physical table 108a and includes management data (SMAT log data). Each block storing data (user data) other than () is set to a state in which user data has not been written (free block). And the control part 103 performs a block erase process with respect to all the free blocks and each bad block.

  According to the above-described embodiment, the pseudo erase 10A can set each block to a data unwritten state at high speed. Since the normal erase 10B also actually erases the data in each block, the data erase is more reliable than the pseudo erase 10A. Further, since the extended erase 10C also erases the Bad Block 1072 that was not erased in the normal erase 10B, for example, information leakage from the information processing apparatus 1 or SSD 10 in which highly confidential data is stored is prevented. The information processing apparatus 1 or the SSD 10 can be safely discarded.

  Therefore, in this embodiment, these pseudo erase mode, normal erase mode, and extended erase mode can be selectively used according to the application.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

Claims (8)

An information processing apparatus main body;
A non-volatile semiconductor memory drive housed in the information processing apparatus body, the non-volatile semiconductor memory having a storage area including a plurality of blocks, and correspondence between each logical block address and each physical address of the non-volatile semiconductor memory A first erasing mode for initializing an address management table indicating the relationship and setting the storage area to a state in which no user data is written, and initializing the address management table and no user data being written in the storage area A second erase mode for erasing each block other than a defective block included in the storage area, and initializing the address management table to set the storage area to a state in which no user data is written. And a block including a bad block included in the storage area. And a third erasing mode for erasing each of the erasing operations, and selectively using the first erasing mode, the second erasing mode, and the third erasing mode to execute an erasing operation on the storage area. And a non-volatile semiconductor memory drive.   The information processing apparatus according to claim 1, wherein the control unit selects one of the first erasing mode, the second erasing mode, and the third erasing mode in accordance with a command from the information processing apparatus body.   The information processing apparatus according to claim 1, wherein the defective block is a block in which an error occurs when data is written or read.   2. The information according to claim 1, wherein the process of initializing the address management table includes a process of setting the address management table in a state in which a physical address corresponding to each logical block address is not written in the address management table. Processing equipment. A non-volatile semiconductor memory drive used as an external storage device of an information processing device,
A nonvolatile semiconductor memory having a storage area including a plurality of blocks;
A first erase mode for initializing an address management table indicating a correspondence relationship between each logical block address and each physical address of the nonvolatile semiconductor memory and setting the storage area in a state in which no user data is written; and A second erase mode for initializing a management table to set the storage area to a state in which user data is not written and erasing each block included in the storage area other than a defective block; and the address management table. A third erasing mode for initializing and setting the storage area in a state in which no user data is written, and erasing each block including a defective block included in the storage area. Selectively using the second erase mode and the third erase mode. The nonvolatile semiconductor memory drive and control means for performing an erase operation for said storage area.   6. The nonvolatile semiconductor memory drive according to claim 5, wherein the control means selects one of the first erase mode, the second erase mode, and the third erase mode in accordance with a command from the information processing apparatus. .   6. The nonvolatile semiconductor memory drive according to claim 5, wherein the defective block is a block in which an error occurs when data is written or read.   6. The nonvolatile memory according to claim 5, wherein the process of initializing the address management table includes a process of setting the address management table to a state in which a physical address corresponding to each logical block address is not written in the address management table. Semiconductor memory drive.

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