JP2004240660A - Control method for nonvolatile memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method for an indirectly addressing type nonvolatile memory device quickly producing an address conversion table and an erasure management table in time of initialization. <P>SOLUTION: This control method for the indirectly addressing type nonvolatile memory device has: a registration step for registering an invalid physical block written with invalid data or written with valid data and related to no logical address, and an erasure-completed block, into the erasure management table as an erasure-completed block, and producing the first address conversion table wherein a plurality of logical addresses are assigned to one physical address at initialization; a decision step for extracting the erasure-completed block from the erasure management table and deciding whether the erasure-completed block is actually erased or not in data writing; an erasure step for erasing the block for non-erasure in the decision step; and a writing step for writing data after the erasure step. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for controlling a nonvolatile semiconductor memory system, and more particularly to a method for controlling a nonvolatile semiconductor memory card.
[0002]
[Prior art]
2. Description of the Related Art In recent years, non-volatile memory devices such as flash memories have attracted attention as storage devices for portable information devices (for example, portable personal computers, digital still cameras, and PDAs) that handle music and video data.
First, the configuration of the nonvolatile memory device will be described.
FIG. 1 is a block diagram illustrating an example of a configuration of a nonvolatile memory device. In FIG. 1, 101 is a host, and 102 is a nonvolatile memory device. The nonvolatile memory device 102 includes a controller 111, an address conversion table 112, an erase management table 113, a host I / F unit 114, a data buffer 115, a memory control unit 116, and a nonvolatile memory 117.
[0003]
The configuration of the nonvolatile memory 117 will be described using a 512-Mbit NAND flash memory as an example.
FIG. 2 is a configuration diagram example of the nonvolatile memory 117 (512 Mbit NAND flash memory) of the nonvolatile memory device 102. One flash memory is composed of 4096 blocks. One block is a basic unit of erasing. One block is further divided into 32 pages. One page is a basic unit for reading and writing. The capacity of one page is 528 bytes. Of the 528 bytes, 512 bytes are a data area and the remaining 16 bytes are a redundant area. The data area is an area used by the user, and the redundant area is an area used by the memory control unit 116 of the nonvolatile memory device 102.
[0004]
FIG. 18 is an example of a configuration diagram of one physical block of the nonvolatile memory 117 (direct addressing system) of the nonvolatile memory device 102. The write start flag 301, the logical address 302, and the address table invalidation flag 303 are arranged in the redundant area of the first page. The write end flag 305 is located in the redundant area of the last page. The logical address 302 and the address table invalidation flag 303 may be arranged on a page different from the page shown in FIG. These flags and data will be described below.
[0005]
Generally, in a nonvolatile memory storage device using a flash memory, a logical address specified externally such as the host 101 does not match a physical address arranged in the flash memory. If they match, the address of the defective block in the flash memory cannot be used, which places a burden on the application or frequently writes to a specific address, so that the block corresponding to that address is guaranteed to be rewritten in a short period of time This is because there is an inconvenience of exceeding the number of times and shortening the service life.
[0006]
The physical block stores the logical address to which it is assigned (associated) in the redundant area (the logical address 302 in FIG. 18). When the power of the host 101 on which the nonvolatile memory device 102 is mounted is turned on or when the nonvolatile memory device 102 is inserted into the host, all of the data written in the redundant area of the nonvolatile memory 102 Of the logical address 302 is read. Note that the initial table creation and command analysis from the host may be performed by the controller 111, but the following description is based on the assumption that the memory control unit 116 performs processing. The memory control unit 116 creates an address conversion table 112 for converting a logical address and a physical address. At the same time, the memory control unit 116 checks whether or not each block has been erased, and creates an erasure management table 113. The address conversion table 112 and the erasure management table 113 are created on the RAM.
[0007]
When a data read command is input from the host 101 to the nonvolatile memory device 102, the memory control unit 116 specifies a physical address in the address conversion table 112 based on the logical address specified by the host 101. The memory control unit 116 accesses the specified physical block and reads data.
When a data write command is input from the host 101 to the nonvolatile memory device 102, the memory control unit 116 extracts an erased block from the erase management table 113. The memory control unit 116 writes data in the extracted block, and registers the physical block in which the data is written in the address conversion table 112. If the logical address specified by the host 101 has already been registered, the data write processing is overwritten. In the case of overwriting, the memory control unit 116 deletes the old physical block in the address conversion table 112 and registers the new physical block in which the data is written in the address conversion table 112. Since the erase state of the physical block changes in writing, the memory control unit 116 updates the information of the block in the erase management table 113.
[0008]
In the address conversion table 112 described above, one physical block (one physical address) is directly assigned to one logical block (one logical address). In this case, there is a problem that the RAM size of the address conversion table 112 increases in proportion to the increase in the capacity of the nonvolatile memory 117, and the nonvolatile memory device 102 becomes expensive.
Therefore, a plurality of (k) logical blocks (logical addresses) are assigned to one physical address (referred to as a “primary physical address”) in the address conversion table, and the logical blocks are assigned to the redundant area of the physical block specified by the physical address. Indirect addressing systems have been considered that have an address table storing a plurality of physical addresses (referred to as “secondary physical addresses”) respectively associated with a plurality of logical addresses.
[0009]
FIG. 3 is an example of a configuration diagram of one physical block of the nonvolatile memory (indirect addressing system) of the nonvolatile memory device 102. 3, the same blocks as those in FIG. 18 are denoted by the same reference numerals. FIG. 3 differs from FIG. 18 in that an address table 304 is added to the redundant area on the second page. In the address table 304, addresses (secondary physical addresses) of k physical blocks respectively associated with k (k is a positive integer of 2 or more) logical blocks are written. In FIG. 3, the primary physical address (the address of the physical block in which the address table 304 is written) is also described in the address table 304 as one of the secondary physical addresses. The k physical addresses described in the address table 304 are respectively associated with k consecutive logical addresses in order from the beginning. The address table 304 may be arranged on a page different from the page shown in FIG. In other respects, FIG. 3 is the same as FIG.
FIG. 4 is a diagram showing the relationship between the address conversion table 112, the erasure management table 113, and the nonvolatile memory 117 in the nonvolatile memory device 102. In this example, k = 2, that is, two logical addresses are assigned to one physical address in the address conversion table 112.
[0010]
When a data read command is input from the host 101 to the nonvolatile memory device 102, the memory control unit 116 specifies a primary physical address in the address conversion table 112 based on the logical address specified by the host 101. Further, the memory control unit 116 specifies the original physical address (the physical address associated with the logical address specified by the host 101) from the address table 304 of the specified redundant area of the primary physical block. The memory control unit 116 accesses the specified original physical block and reads data. In this example, the table is referred to twice in order to obtain the target data. However, a system in which the table is referred to twice or more is also possible. If the number of stages increases, the size of the address conversion table can be reduced, but there is a disadvantage that the number of blocks lost due to table abnormality increases.
[0011]
When a data write command is input from the host 101 to the nonvolatile memory device 102, the memory control unit 116 first searches the erase management table 113 for an unrecorded physical block. The memory control unit 116 reads the address table 304 of the physical block registered in the address conversion table 112. The memory control unit 116 replaces one address of the secondary physical address in the address table 304 with the address of a physical block to be written from now on (searched unrecorded physical block) to obtain updated address table information. To the unrecorded physical block. When the writing is completed, the memory control unit 116 registers the new physical block address in the address conversion table 112. The memory control unit 116 marks the address table invalidation flag of the block having the old table as invalid by overwriting. Note that only the address table in the redundant area is invalidated, and data is not necessarily invalidated. For example, there is a case where data of a logical address (included in the address table 304) other than the logical address associated with the physical block storing the old address table 304 is rewritten. In this case, the physical block storing the old address table 304 is linked from the new address table. In the indirect addressing system, when writing or erasing is performed, the information in the erasure management table 113 is updated similarly.
[0012]
Also, writing is not always performed normally. It is also necessary to consider that interruption due to power-off (card removal) during writing or erasing occurs. The write start flag 301 is to be marked prior to writing. Therefore, by inspecting the write start flag 301, it can be determined whether or not the block has been erased. The write end flag 305 is marked by overwriting when writing to the block is completed. Therefore, by examining the write end flag 305, it can be determined whether or not writing to the block has been interrupted.
That is, in the erased block, both the write start flag 301 and the write end flag 305 have no mark. The block for which writing has been completed has both the write start flag 301 and the write end flag 305 marked. For an unfinished block in which writing has been interrupted, the writing start flag 301 has a mark and the writing end flag 305 has no mark. The data of the unfinished block where the writing was interrupted is not used. It is erased for reuse and registered as erased in the erase management table.
[0013]
Next, an outline of a conventional method for creating an address conversion table and an erase management table at the time of initialization in a nonvolatile memory device having a nonvolatile memory having indirect addressing will be described.
In the following description, the level at the time of erasing the non-volatile memory is 1, the level of each flag with a mark is 0, and the flag of the erasure management table 113 is 1 when erased and 0 when in use.
First, the address conversion table 112 and the erasure management table 113 are initialized (details will be described later). Next, all physical blocks are inspected in order, and a table is created. In the address conversion table 112, if a block having the mark in the write end flag 305 and no mark in the address table invalidation flag 303 is found, the same logical address as the logical address of the address table 304 written in the redundant area is used. The physical block address is registered at the address (address conversion table 112). In the erase management table 113, a block without a mark is registered in the write start flag 301 (the flag is set to 0).
[0014]
Note that the bad block is not registered in the address conversion table 112 but is registered in the erasure management table 113 as unerased so as not to be written. An incomplete block in which writing has been interrupted is erased and registered in the erase management block as an erased block. Further, depending on the write interruption timing, two physical blocks can be redundantly associated with the same logical address in the address conversion table 112 (the address table 304 stored in each redundant area can be associated with the same logical address). There is. In this case, it is determined which address table is correct, the address of the selected physical block is registered in the address conversion table, and the non-selected block marks the address table invalidation flag (invalidates the address table 304). If it is valid data, it is left as it is, and if it is invalid data, it is deleted.
[0015]
In a system having the address conversion table 112 of the indirect addressing, there is a possibility that there is an invalid block in which writing has been completed. For example, a case where the address table data of the block having the address table becomes abnormal and the link is lost. This is a phenomenon at the time of an abnormality, in which data to be held is lost. If a block with a broken link is left as it is, a problem occurs that the writable memory capacity of the memory device is permanently reduced. However, it is not easy to determine whether a written block is valid. This is because which block address table is linked cannot be determined unless the link is checked from the address tables of all blocks.
Therefore, after checking all the physical blocks, a link check is performed using the address conversion table. Here, it is necessary to extract a block that is not linked, delete the block, and make it reusable.
[0016]
Next, in a nonvolatile memory device having a nonvolatile memory of indirect addressing, a conventional method of creating an address conversion table and an erase management table at initialization will be described with two examples.
A method of creating a table at the time of initialization of the first conventional example will be described with reference to FIGS. FIG. 19 is a schematic flowchart of a table creation method at the time of initialization in the nonvolatile memory device of Conventional Example 1. FIG. 20 is a diagram showing a process of a table creation method at the time of initialization in the nonvolatile memory device of Conventional Example 1. The underlined portions in FIG. 20 indicate operations in each step.
[0017]
The states of the physical blocks will be described by classifying them into four types: erased, valid data, invalid data, and bad blocks.
There are two types of valid data. One is a block in which the address table invalidation flag 303 is valid and has the address table 304. The other is a block (data is valid) in which the address table invalidation flag 303 is invalid but the address table invalidation flag 303 of another block is valid and linked from the address table of the other block.
There are two types of invalid data. One is a block in which the write start flag has a mark but a write end flag has no mark (a block in which data writing has not been completed). The other is a block in which both the write start flag and the write end flag have a mark (a block in which data writing has been completed) but are not linked and are not used as a result.
[0018]
19 and 20, when the power of the host 101 to which the nonvolatile memory device 102 is mounted is turned on or when the nonvolatile memory device 102 is inserted into the host, the address conversion table and the erase management table are initialized in step 1901. Be converted to In some systems, the entire memory is divided into large blocks and the table is initialized at the time of switching, but this is the same as the initialization at power-on. Specifically, the non-volatile memory device 102 sets all of the address conversion table 112 to unallocated, and sets 1 (erased) to all of the erasure management table 113.
In the steps 1902 and 1903, the purpose is to extract invalid data blocks with broken links.
In step 1902, the nonvolatile memory device 102 searches all physical blocks.
Specifically, the non-volatile memory device 102 creates the address conversion table 112 by reading the logical address 302 in the redundant area of all physical blocks, and assigns 0 ( In use). In the creation of the address conversion table 112, when an incomplete block or an address is duplicated, selection determination and invalidation processing are performed.
In step 1903, the nonvolatile memory device 102 performs an all logical link search. Specifically, the non-volatile memory device 102 follows links of all logical addresses, and sets 1 (erased) to a block of the erasure management table 113 corresponding to valid data. As a result, the blocks that are 0 (in use) in the erasure management table are bad blocks and invalid data blocks.
[0019]
In step 1904, the non-volatile memory device 102 sequentially searches the erasure management table, erases a block (invalid data block) in which the erasure management table is 0 (in use) and is not defective, and assigns 1 ( (Deleted) is set.
In step 1905, the non-volatile memory device 102 searches again for all logical links. Specifically, the nonvolatile memory device 102 follows the links of all logical addresses and sets 0 (in use) to the valid data of the erasure management table 113. Thus, the address conversion table 112 and the erasure management table 113 are completed.
[0020]
A method of creating a table at the time of initialization in Conventional Example 2 will be described with reference to FIGS. The creation method of the conventional example 2 requires only one search for all logical links, but requires a buffer table on the RAM having the same size as the erase management table. FIG. 21 is a schematic flowchart of a table creation method at the time of initialization in the nonvolatile memory device of Conventional Example 2. FIG. 22 is a diagram illustrating a process of a table creation method at the time of initialization in the nonvolatile memory device of Conventional Example 2. The underlined portions in FIG. 22 indicate operations in each step.
[0021]
21 and 22, when the power of the host 101 to which the nonvolatile memory device 102 is mounted is turned on or when the nonvolatile memory device 102 is inserted into the host, the address conversion table and the erase management table are initialized in step 2101. Be converted to Specifically, the non-volatile memory device 102 makes all of the address conversion table 112 unallocated, and sets 1 (erased) to all blocks of the erasure management table 113 and the buffer table.
In the processes of steps 2102 and 2103, the creation of the erasure management table 113 and the creation of a table of erased blocks in the buffer table for extracting invalid data blocks with broken links are simultaneously performed.
In step 2102, the nonvolatile memory device 102 searches all physical blocks.
Specifically, the non-volatile memory device 102 creates the address conversion table 112 by reading the logical address 302 in the redundant area of all physical blocks, and assigns 0 (in use) to the defective block in the erase management table 113. Is set, and 0 (in use) is set to all the blocks that have not been erased in the buffer table. In the creation of the address conversion table 112, when an incomplete block or an address duplication block is found, selection determination and invalidation processing are performed.
[0022]
In step 2103, the nonvolatile memory device 102 performs an all logical link search. Specifically, the non-volatile memory device 102 follows links of all logical addresses and sets 0 (in use) to a block of the erasure management table 113 corresponding to valid data. Thus, a block that is 1 (erased) in the erase management table and is 0 (in use) in the buffer table can be determined to be an invalid data block.
In step 2104, the nonvolatile memory device 102 compares the erase management table and the buffer table, and erases and erases a block (invalid data block) whose erase management table is 1 (erased) and whose buffer table is 0 (used). 1 (erased) is set for the block in the management table 113. Thus, the address conversion table 112 and the erasure management table 113 are completed.
[0023]
[Patent Document 1]
JP-A-11-110283
[0024]
[Problems to be solved by the invention]
However, with the recent increase in the capacity of the flash memory and the nonvolatile memory storage device, the processing time for creating the address conversion table and the erase management table at the time of initialization has increased. In order to speed up the table creation processing, search and deletion processing of unnecessary blocks is a major obstacle.
Although it is necessary to perform all physical block inspections and then inspect the links of all logical blocks, two logical block inspections are required to extract unnecessary blocks, which increases the initialization time. Alternatively, if a buffer table of the same size as the erasure management table can be used, it is possible to perform one test, but an increase in the RAM capacity causes a cost increase.
Also, when erasing unnecessary blocks, the erasing time requires a longer time than reading or flag marking (overwriting), which is an obstacle to shortening the initialization time.
The present invention has been made in view of such a problem, and an object of the present invention is to provide a control method of an indirect addressing type nonvolatile memory device that can quickly create an address conversion table and an erase management table at initialization. Aim.
An object of the present invention is to provide a control method for an indirect addressing type nonvolatile memory device that performs logical address / physical address conversion with a small RAM capacity.
[0025]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following configurations.
According to the first aspect of the present invention, there is provided a nonvolatile memory including a plurality of physical blocks, a first address translation table in which a plurality of logical addresses are assigned to one physical address, and an erasure management table in which erased blocks are registered. The physical block has a data area for storing data, and a redundant area for storing information for determining whether data written in the physical block is valid or not, and the first address The physical block specified by the translation table has a second address translation table in which a plurality of physical addresses are associated with a plurality of logical addresses. Control of a nonvolatile memory device in which a physical address and a logical address are indirectly associated with each other Invalid data is written at initialization or valid data is written at initialization, Registering an invalid physical block and an erased block that are not also associated with the erase management table as the erased block, and generating the first address conversion table; and A step of extracting an erased block from the erase management table to determine whether the erased block is really erased; an erasing step of erasing the block if the erased block has not been erased; and an erasing step. And a writing step of writing data later.
[0026]
According to a second aspect of the present invention, in the registration step, one fixed page capable of determining that the second address translation table of all physical blocks exists effectively is continuously read, and the next physical block is read. If the physical block before reading the previous fixed page is temporarily determined while reading the fixed page, and the previous physical block is temporarily determined to be a valid physical block having the second address conversion table, A temporary registration step of temporarily registering a previous physical block in the first address translation table, and after checking all physical blocks, reading out another fixed page only for the temporarily registered physical block, and reading the physical block in the first address translation table. Re-determine whether it is appropriate to register in the address translation table, and if it is not appropriate to register the physical block, And a temporary registration deletion step of dividing a control method of a nonvolatile memory device according to claim 1, further comprising a.
[0027]
According to a third aspect of the present invention, in the registering step, when a plurality of physical blocks are redundantly associated with one logical address, the redundant table registering step registers the duplicated physical blocks in a redundant table; After the temporary registration step or the temporary registration deletion step, the physical block registered in the spare table is read, an appropriate physical block is selected from the duplicated physical blocks, and the second physical block is registered in the first address translation table. 3. The method for controlling a nonvolatile memory device according to claim 2, further comprising a registering step.
[0028]
The invention according to claim 4, wherein in the second registration step, an address table associated with the second address translation table of a physical block that is not selected as an appropriate physical block among duplicate physical blocks. 4. The method according to claim 3, wherein the invalidation flag is invalidated and the physical block is not erased at the time of initialization.
[0029]
The present invention has an effect that a control method of an indirect addressing type non-volatile memory device that creates an address conversion table and an erase management table at high speed at initialization can be realized.
The present invention has an effect that a control method of an indirect addressing type nonvolatile memory device that performs logical address / physical address conversion with a small RAM capacity can be realized.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment that specifically shows the best mode for carrying out the present invention will be described with reference to the drawings.
[0031]
<< Example 1 >>
The initialization method in the nonvolatile memory device according to the first embodiment of the present invention will be described with reference to FIGS.
First, a configuration of the nonvolatile memory device according to the first embodiment will be described.
FIG. 1 is a block diagram illustrating a configuration of a nonvolatile memory device. FIG. 2 is a configuration diagram of the nonvolatile memory 117 (512 Mbit NAND flash memory) of the nonvolatile memory device 102. FIG. 3 is a configuration diagram of one physical block of the nonvolatile memory (indirect addressing system) of the nonvolatile memory device 102. FIG. 4 is a diagram showing the relationship between the address conversion table 112, the erasure management table 113, and the nonvolatile memory 117 in the nonvolatile memory device 102. The configuration (FIGS. 1 to 4) of the non-volatile memory device according to the first embodiment of the present invention is the same as that of the conventional example, and the description is omitted.
[0032]
Next, an outline of a method of creating the address conversion table and the erase management table at the time of initialization in the nonvolatile memory device of the first embodiment will be described.
FIG. 5 is a schematic flowchart of a table creation method at the time of initialization in the nonvolatile memory device according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating a process of a table creation method at the time of initialization in the nonvolatile memory device according to the first embodiment of the present invention.
[0033]
5 and 6, when the power of the host 101 to which the nonvolatile memory device 102 is mounted is turned on or when the nonvolatile memory device 102 is inserted into the host, the address conversion table and the erase management table are initialized in step 501. (See FIG. 7 for details). Specifically, the non-volatile memory device 102 sets all of the address conversion table 112 to unallocated, and sets 1 (erased) to all of the erasure management table 113.
In step 502, the non-volatile memory device 102 searches all physical blocks (for details, see FIGS. 8 and 9). Specifically, the non-volatile memory device 102 creates the address conversion table 112 by reading the logical address 302 in the redundant area of all the physical blocks, and assigns 0 (in use) to the bad block of the erase management table 113. Set.
In step 503, the non-volatile memory device 102 performs a full logical link search (see FIG. 10 for details). Specifically, the nonvolatile memory device 102 sets 0 (in use) to the valid data of the erasure management table 113. The definitions of erased, valid data, invalid data, and bad blocks have been described in the conventional example.
Invalid data is registered as 1 (erased) in the erasure management table 113. Invalid data is treated as an erased block when writing data, and is used for writing.
[0034]
Next, details of a method of creating the address conversion table and the erase management table at the time of initialization in the nonvolatile memory device of the first embodiment will be described.
7 to 10 are detailed flowcharts of FIG.
FIG. 7 is a detailed flowchart of the table initialization process (step 501) of the table creation method at the time of initialization in the nonvolatile memory device according to the first embodiment of the present invention. In FIG. 7, in step 701, the memory control unit 116 makes all the address conversion tables 112 unallocated. For example, 1 (unregistered) is set to a1 to a7. In step 702, the memory control unit 116 sets all the flags of the erasure management table 113 to the erased state. For example, a numerical value (for example, all bits “1”) indicating unassigned is set to b1 to b7.
[0035]
FIG. 8 is a detailed flowchart of the entire physical block search process (step 502) of the table creation method at the time of initialization in the nonvolatile memory device according to the first embodiment of the present invention. In the all physical block search process (step 502), an address translation table is created by sequentially examining all physical blocks, and 0 (in use) is set in the bad block erase management table.
[0036]
In FIG. 8, in step 801, the memory control unit 116 sets the head physical address as the inspection address. In step 802, the memory control unit 116 reads the information of the physical block of the test address and determines whether the physical block of the test address is a bad block. If the block is not a bad block, the process proceeds to step 803, and the memory control unit 116 determines whether or not the write start flag 301 of the physical block of the inspection address has a mark. If it is determined in step 803 that the write start flag 301 has a mark, the process proceeds to step 804, and the memory control unit 116 determines whether the write end flag 305 of the physical block at the check address has a mark. If it is determined in step 804 that the write end flag 305 has a mark, the process proceeds to step 805, and the memory control unit 116 determines whether the address table invalidation flag 303 of the physical block of the check address is valid.
[0037]
If the address table invalidation flag 303 is valid in step 805 (the write start flag is marked, the write end flag is marked, and the address table invalidation flag is valid), the process proceeds to step 806, and the memory control unit 116 The inspection address is registered in the address conversion table (for details, see FIG. 9).
If the block is a bad block in step 802, the process proceeds to step 807, and the memory control unit 116 sets 0 (in use) in the erasure management table. For example, 0 (in use) is set in the erase management table b5 corresponding to the defective block (physical address 0004) of the nonvolatile memory 117 in FIG.
Although a specific method of determining a defective block is not particularly performed in this description, there are a method of recording a defective block address and a method of marking a redundant area of the defective block by providing a flag indicating the defective block. In the present flowchart, the description is made with an image of investigating a bad block mark in each redundant area.
[0038]
If the write start flag is no mark in step 803, if the write end flag is no mark in step 804, if the address table invalidation flag is invalid in step 805, and if the test address is registered in step 806 and after step 807, After setting in the erasure management table, the process proceeds to step 808, and the memory control unit 116 updates the test address (sets the next physical address as the test address). In step 809, the memory control unit 116 determines whether all physical blocks have been checked. If all physical blocks have not been inspected, the process returns to step 802 and proceeds to the processing of the next physical block. When the inspection of all the physical blocks is completed, this flowchart ends.
[0039]
In the all physical block search process (step 502) of the present embodiment, the corresponding flag in the erase management table for the block (valid data) registered in the address conversion table remains 1 (erased) while the next step ( In the all logical link search process (step 503), 0 (in use) is set to the corresponding flag of the erasure management table. However, the corresponding flag of the erasure management table 113 may be set to 0 (in use) in the all physical block search process (step 502).
In the case of a system in which bad blocks are collectively subjected to address management, the flag of the erase management table of the addresses of the bad blocks managed in advance is set to 0 (in use), and all physical block search processing ( In step 502), if the flag of the erasure management table 113 is 0 (in use), the physical block may be passed the inspection as a defective block.
[0040]
There may be a case where two or more physical addresses associated with one logical address are duplicated due to a reason such as power-off during data overwriting. When registering overlapping physical addresses in the address translation table, it is necessary to compare both physical blocks. Also, if the duplicated state is left as it is, the other data exists even if the data is erased, so that there is a problem that the data is contained in the logical address that should have been erased from the viewpoint of the host. The inspection address registration processing (step 806) of the present embodiment solves the above-mentioned problem.
[0041]
FIG. 9 is a detailed flowchart of the test address registration process (step 806) of the table creation method at the time of initialization in the nonvolatile memory device according to the first embodiment of the present invention. In step 901, the memory control unit 116 determines whether the check address is a logical address already registered in the address conversion table 112. If it is a registered logical address, the process proceeds to step 902, where the memory control unit 116 compares both overlapping physical blocks and selects any one physical block. Selection procedures and criteria are not relevant to the present invention, and will not be described. In step 903, the memory control unit 116 registers the selected physical block address in the address conversion table.
In step 904, the memory control unit 116 sets the address table invalidation flag 303 of the non-selected physical block to invalid, and ends this flowchart.
[0042]
For example, assume that the logical addresses of the physical addresses 0003 and 0005 of the nonvolatile memory 117 in FIG. 11 are duplicated. If it is determined that the block at the physical address 0005 is correct data, 0005 (the physical address of the selected block) is set in the data a2 of the address conversion table 112. Further, the address table invalidation flag 303 of the block having the physical address 0003 (the physical address of the unselected block) is set to be invalid.
If the test address is an unregistered logical address in step 901, the process proceeds to step 905, where the memory control unit 116 registers the physical block address in the address conversion table, and ends this flowchart. For example, 0001 is set in the data a1 of the address conversion table 112 in FIG.
[0043]
FIG. 10 is a detailed flowchart of the all logical link search process (step 503) of the table creation method at the time of initialization in the nonvolatile memory device according to the first embodiment of the present invention. In the all logical link search process (step 503), 0 (in use) is set in the effective data erasure management table by checking all the logical links, and the erasure management table is completed.
In FIG. 10, in step 1001, the memory control unit 116 sets the data of the first logical address of the address conversion table 112 as the test address. In step 1002, the memory control unit 116 sets a check address as a link address. In step 1003, the memory control unit 116 sets 0 (in use) in the erasure management table 113 of the link address. In step 1004, the memory control unit 116 determines whether another link address is registered in the address table 304 of the redundant area of the physical block of the check address.
[0044]
If another link address is registered in step 1004, the process proceeds to step 1005. In step 1005, the memory control unit 116 sets another link address registered in the address table 304 as the link address, and returns to step 1003. The indirect addressing table may be formed not only in one stage but also in a plurality of stages. In any case, the linked block that can be read is set as being used and 0 (in use) is set in the erasure management table.
For example, it is assumed that the block of the physical address 0002 is linked to the block of the physical address 0001 as shown in FIG. In this case, 0 (in use) is set not only in the erase management table b2 corresponding to the block of the physical address 0001 but also in the erase management table b3 corresponding to the block of the physical address 0002.
[0045]
If another link address is not registered in step 1004 (if all the links for the inspection address have been inspected), the process proceeds to step 1006, where the memory control unit 116 updates the inspection address (the address conversion table of the address conversion table is added to the inspection address). Set the data of the next logical address.) In step 1007, the memory control unit 116 determines whether all the logical blocks have been checked. If all logical blocks have not been checked, the process returns to step 1002 and proceeds to the next logical block. When the inspection of all the logical blocks is completed, this flowchart ends.
[0046]
As shown in FIG. 6, the erase management table corresponding to the invalid data block is 1 (erased), and the invalid data block is treated the same as the erased block. In other words, it is registered as writable even though writing has been performed. If writing is performed as it is, overwriting will occur, mismatch of the write data will occur, and the area will be unusable as a defective block. Therefore, before writing, the writing start flag of the block is read once, and if writing has not been performed, writing is performed as it is, and if writing has been completed, the block is erased and then writing is performed.
As described above, reading is always performed before writing, and an erasing process is performed in some cases. However, erasing occurs only in an abnormal state such as an instantaneous power interruption or an abnormality in held address data, and steadily increases only the flag reading time. Since the read time is much shorter than the erase or write time, a decrease in the write speed has only a small effect on the system as compared with an increase in the time during initialization.
[0047]
According to the first embodiment, it is possible to shorten the initialization time without increasing the RAM capacity by setting the invalid data block to be erased instead of erasing it at the time of initialization, and determining and erasing it before writing. It becomes.
[0048]
<< Example 2 >>
In the all physical block search process (step 502) of the first embodiment, the non-volatile memory device checks whether or not the block is to be registered in the address conversion table 112. The valid conditions for registration are that the write start flag 301 on the first page has a mark, the address table invalidation flag 303 is also valid, and the write end flag 305 on the last page has a mark. There is something. Strictly speaking, there are other conditions such as that the logical address 302 is within an address range that can be taken, and that no error has occurred in the error correction code of the address. In any case, it may be possible to determine that the address is not registered in the address conversion table 112 based on the flags 301 and 303 of the first page. Need to be inspected.
[0049]
While the data in the redundant area is being read, it is possible to determine the data read in parallel and perform the processing. For example, after the memory control unit 116 reads data in the redundant area, the next data reading is started immediately. In the meantime, the controller 111 determines the data read last time and registers it in the address conversion table 112 and the erasure management table 113. If the software processing of the controller 111 can be completed within the read time of the redundant area, the memory data read time of the memory control unit 116 will determine the entire processing time.
[0050]
The problem with this method is that the next block or page to be read cannot be known without first determining the contents of the first page. That is, when the first page is read, when the write start flag 301 is not marked, or when the address table invalidation flag 303 is marked, there is no possibility of registration in the address conversion table. The first page of the block will be read. When the conditions other than the above conditions are satisfied, the check address may be registered in the address conversion table 112, so that the write end flag 305 of the last page needs to be checked.
If the first page and the last page are always read alternately, the read start page is determined. However, in a system in which the number of blocks registered in the address translation table 112 by indirect addressing is only a fraction of the whole, according to such a method, two pages must be read for one block without fail. Unnecessary page reading increases the initialization time. The all-physical-block search processing according to the present embodiment solves the above-described problem.
[0051]
The initialization method in the nonvolatile memory device according to the second embodiment of the present invention will be described with reference to FIGS. 1 to 7 and FIGS.
First, the configuration of the nonvolatile memory device according to the second embodiment will be described.
FIG. 1 is a block diagram illustrating a configuration of a nonvolatile memory device. FIG. 2 is a configuration diagram of the nonvolatile memory 117 (512 Mbit NAND flash memory) of the nonvolatile memory device 102. FIG. 3 is a configuration diagram of one physical block of the nonvolatile memory (indirect addressing) of the nonvolatile memory device 102. FIG. 4 is a diagram showing the relationship between the address conversion table 112, the erasure management table 113, and the nonvolatile memory 117 in the nonvolatile memory device 102. The configuration (FIGS. 1 to 4) of the non-volatile memory device according to the second embodiment of the present invention is the same as that of the conventional example, and a description thereof will be omitted.
[0052]
Next, an outline of a method of creating the address conversion table 112 and the erase management table 113 at the time of initialization in the nonvolatile memory device of the second embodiment will be described.
FIG. 5 is a schematic flowchart of a table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention. FIG. 6 is a diagram illustrating a process of a table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention. The outline (FIGS. 5 and 6) of the method of initializing the nonvolatile memory device according to the second embodiment of the present invention is the same as that of the first embodiment, and thus the description is omitted.
[0053]
Next, details of a method of creating the address conversion table and the erase management table at the time of initialization in the nonvolatile memory device of the second embodiment will be described.
FIGS. 7, 10, 12 to 14, 16, and 17 are detailed flowcharts of FIG. The table initialization process (FIG. 7) of the table creation process at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention is the same as that of the first embodiment, and therefore the description is omitted.
FIG. 12 is a detailed flowchart 1 of the entire physical block search process (step 502) of the table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention. FIG. 13 is a detailed flowchart 2 of the entire physical block search process (step 502) of the table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention. In the all physical block search process (step 502), an address translation table 112 is created by sequentially examining all physical blocks, and 0 (in use) is set in the bad block erasure management table 113.
[0054]
In FIG. 12, in step 1201, the memory control unit 116 sets the first physical address as the test address (initial value i = 0). In step 1202, the memory control unit 116 reads the first page of the physical block at the check address (i = 0). In step 1203, the memory control unit 116 updates the test address (sets the next physical address as the test address) (i = i + 1). In step 1204, the memory control unit 116 reads the first page of the physical block at the check address (i). In step 1205, the memory control unit 116 determines only the information of the first page. If the write start flag 301 is marked and the address table invalidation flag 303 is valid, the previous check address (i-1) is used. It is temporarily registered in the address conversion table (for details, see FIG. 14). Steps 1204 and 1205 are performed in parallel. In step 1206, the memory control unit 116 determines whether all physical blocks have been checked. If all the physical blocks have not been checked, the process returns to step 1203 and proceeds to the processing of the next physical block (the memory control unit 116 continuously reads the first page). When the inspection of all the physical blocks is completed, this flowchart ends.
[0055]
In FIG. 13, in step 1301, the memory control unit 116 sets the head (j = 0) data temporarily registered in the address conversion table as the inspection address. In step 1302, the memory control unit 116 reads the last page of the physical block at the check address (the first (j = 0) data temporarily registered in the address conversion table). In step 1303, the memory control unit 116 updates the test address (sets the next (j (= j + 1)) data temporarily registered in the address conversion table as the test address).
[0056]
In step 1304, the memory control unit 116 reads the last page of the physical block at the test address (the j-th data in the address conversion table). In step 1305, the memory control unit 116 determines based on the information of the last page (write end flag 305). If the write end flag 305 is not marked, the previous check address (temporarily registered (j- The temporary registration of the (1) -th data) in the address conversion table is canceled and returned to the non-registered one (for details, see FIG. 16). Steps 1304 and 1305 are performed in parallel.
In step 1306, the memory control unit 116 determines whether the inspection of all the temporarily registered blocks has been completed. If the inspection of all the temporarily registered blocks has not been completed, the process returns to step 1303 and proceeds to the processing of the next temporarily registered block. When the inspection of all the temporarily registered blocks is completed, the process proceeds to step 1307, where the preliminary table is determined (for details, see FIG. 17), and this flowchart ends.
[0057]
There may be a case where two or more physical addresses associated with one logical address are duplicated due to a reason such as power-off during data overwriting. Judging only from the information of the first page and temporarily registering it in the address translation table, when registering duplicate physical addresses in the address translation table, both physical blocks are selected as to which physical block to select. Need to compare. First, it is necessary to read the last page and determine whether or not the block has been written. If both blocks are completed (if the write end flag 305 is marked), another page, different data, etc. are used for determination, and one of them is finally selected. This selection method is omitted in this description.
However, when the overlap is noticed, the hardware is reading the first page of the next block. If the first page of the next block is interrupted and the last page or the like is read, a loss occurs for the time. The temporary registration process and the preliminary table determination process of the present embodiment solve the above-mentioned problems.
[0058]
FIG. 14 is a detailed flowchart of the test address temporary registration process (step 1205) of the table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention. In step 1401, the memory control unit 116 determines whether or not the write start flag 301 of the physical block at the previous check address (i-1) has a mark. If it is determined in step 1401 that the write start flag 301 has a mark, the process proceeds to step 1402, and the memory control unit 116 determines whether the address table invalidation flag 303 of the physical block of the previous check address (i-1) is valid. I do. If the address table invalidation flag 303 is valid in step 1402 (if the write start flag 301 has a mark and the address table invalidation flag 303 is valid), the process proceeds to step 1403, and the memory control unit 116 It is determined whether the logical address is already registered. If it is an unregistered logical address, the process proceeds to step 1404, where the memory control unit 116 registers the physical block address in the address conversion table 112, and ends this flowchart.
[0059]
If the logical address is already registered in step 1403, the process proceeds to step 1405, where the memory control unit 116 registers the address of the duplicated address translation table and the physical block address to be registered in the spare table (FIG. 15) on the RAM. The flowchart ends. For example, assume that the logical addresses of the physical addresses 0003 and 0005 of the nonvolatile memory 117 in FIG. 11 are duplicated. As shown in FIG. 15, the physical address 0003 processed first is set in the address conversion table, and the physical address 0005 processed later is set in the spare table.
[0060]
FIG. 16 is a detailed flowchart of the temporary registration deletion processing (step 1305) of the table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention. In step 1601, the memory control unit 116 determines whether or not the write end flag 305 of the physical block at the previous check address (i-1) has a mark. If the write end flag 305 has no mark in step 1601, the process proceeds to step 1602, and the memory control unit 116 cancels the temporary registration of the physical block address in the address conversion table 112 and returns to the unregistered state. In step 1603, the memory control unit 116 sets the address table invalidation flag 303 of the physical block of the previous check address (i-1) to invalid, and ends this flowchart. This block cannot be made valid since the write end flag 305 has no mark.
However, since temporary registration and temporary registration deletion are performed each time initialization is performed, the address table invalidation flag 303 is invalidated. If it is determined in step 1601 that the write end flag 305 has a mark, the flowchart ends.
[0061]
FIG. 17 is a detailed flowchart of the preliminary table determination process (step 1307) of the table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention. In step 1701, the memory control unit 116 reads a spare table.
In step 1702, both overlapping physical blocks are compared, and one of the physical blocks is selected. Selection procedures and criteria are not relevant to the present invention, and will not be described. In step 1703, the memory control unit 116 registers the selected physical block address in the address conversion table 112. In step 1704, the memory control unit 116 sets the address table invalidation flag 303 of the non-selected physical block to invalid, and ends this flowchart.
[0062]
For example, assume that a logical address 2 and data 0005 are registered in the spare table as shown in FIG. In this case, data (0003) associated with the same logical address (2) is extracted from the address conversion table. The blocks of the physical addresses 0003 and 0005 are compared, and if it is determined that the block of the physical address 0005 is correct data, 0005 (the physical address of the selected block) is set in the data a2 of the address conversion table 112. Further, the address table invalidation flag 303 of the block having the physical address 0003 (the physical address of the unselected block) is set to be invalid.
[0063]
The all logical link search process (step 503; FIG. 10) of the table creation process at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention is the same as that of the first embodiment, and therefore the description is omitted.
The processing before writing in the nonvolatile memory device according to the second embodiment of the present invention is also the same as that of the first embodiment, and thus the description is omitted.
[0064]
The amount of RAM required to create a spare table increases. However, in the normal state, when writing is interrupted, only one set of tables overlaps. Further, once initialized, the address table invalidation flag 303 is marked and is cleared from the next time, so that duplicate addresses are not accumulated. Therefore, an increase in the required RAM capacity is not a problematic range.
In the above embodiment, the flag is represented by 1 or 0 with one bit, but the polarity can be changed by the flash erasing level (1 in the embodiment) or the allocation method. It is also possible to use a plurality of bits and perform a majority process to make a determination. Although the arrangement of flags and addresses in the redundant area is the first page and the last page, the same effect can be obtained by replacing the page with another page. Further, not only two pages but also three or more pages can be applied.
[0065]
According to the second embodiment, it is possible to shorten the entire physical block search time in the initialization by reading only the minimum necessary pages and performing the determination process in parallel during the reading.
According to the second embodiment, by providing the spare table, the processing is not interrupted during the search for all the physical blocks in the initialization, and the search time for the entire physical block can be reduced.
According to the second embodiment, by marking the address table invalidation flag of the unfinished block, the temporary registration is not performed at the time of the first page inspection from the next time, and the determination after searching all physical blocks becomes unnecessary. An increase in RAM capacity and an increase in initialization time can be prevented.
According to the second embodiment, the invalid data block is not erased at the time of initialization as in the first embodiment, but is determined and erased before writing, thereby making it possible to shorten the initialization time.
[0066]
【The invention's effect】
According to the present invention, there is obtained an advantageous effect that a control method of an indirect addressing type nonvolatile memory device that creates an address conversion table and an erase management table at high speed at initialization can be realized.
According to the present invention, there is obtained an advantageous effect that a control method of an indirect addressing type nonvolatile memory device that performs logical address / physical address conversion with a small RAM capacity can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a nonvolatile memory device according to a conventional example and an embodiment of the present invention.
FIG. 2 is a configuration diagram of a nonvolatile memory (512 Mbit NAND flash memory) of a nonvolatile memory device according to a conventional example and an embodiment of the present invention;
FIG. 3 is a configuration diagram of one physical block of a nonvolatile memory (indirect addressing) of a nonvolatile memory device according to a conventional example and an embodiment of the present invention;
FIG. 4 is a diagram showing a relationship between an address conversion table, an erase management table, and a nonvolatile memory in a nonvolatile memory device according to a conventional example and an embodiment of the present invention (after initialization).
FIG. 5 is a schematic flowchart of a table creation method at the time of initialization in the nonvolatile memory device according to the first embodiment of the present invention;
FIG. 6 is a diagram showing a process of a table creation method at the time of initialization in the nonvolatile memory device according to the first embodiment of the present invention;
FIG. 7 is a detailed flowchart of a table initialization process (step 501) of a table creation method at the time of initialization in the nonvolatile memory devices according to the first and second embodiments of the present invention.
FIG. 8 is a detailed flowchart of an all-physical block search process (step 502) of the table creation method at the time of initialization in the nonvolatile memory device according to the first embodiment of the present invention;
FIG. 9 is a detailed flowchart of a test address registration process (step 806) of the table creation method at the time of initialization in the nonvolatile memory device according to the first embodiment of the present invention.
FIG. 10 is a detailed flowchart of an all logical link search process (step 503) of the table creation method at the time of initialization in the nonvolatile memory devices according to the first and second embodiments of the present invention;
FIG. 11 is a diagram showing a relationship between an address conversion table, an erasure management table, and a nonvolatile memory in the nonvolatile memory device (during initialization).
FIG. 12 is a detailed flowchart 1 of the entire physical block search process (step 502) of the table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention.
FIG. 13 is a detailed flowchart 2 of the entire physical block search process (step 502) of the table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention.
FIG. 14 is a detailed flowchart of a test address temporary registration process (step 1205) of the table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention;
FIG. 15 is a diagram showing an address translation table and a spare table in a table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention;
FIG. 16 is a detailed flowchart of a temporary registration deletion process (step 1305) of the table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention.
FIG. 17 is a detailed flowchart of a preliminary table determination process (step 1307) of the table creation method at the time of initialization in the nonvolatile memory device according to the second embodiment of the present invention.
FIG. 18 is a configuration diagram of one physical block of a nonvolatile memory (direct addressing) of a conventional nonvolatile memory device;
FIG. 19 is a schematic flowchart of a table creation method at the time of initialization in the nonvolatile memory device of Conventional Example 1;
FIG. 20 is a diagram showing a process of a table creation method at the time of initialization in the nonvolatile memory device of Conventional Example 1;
FIG. 21 is a schematic flowchart of a table creation method at the time of initialization in the nonvolatile memory device of Conventional Example 2;
FIG. 22 is a diagram showing a process of a table creation method at the time of initialization in the nonvolatile memory device of Conventional Example 2;
[Explanation of symbols]
101 Host
102 Non-volatile memory device
111 controller
112 address conversion table
113 Erasure management table
114 Host I / F section
115 Data buffer
116 Memory control unit
117 Non-volatile memory
301 Write start flag
302 logical address
303 Address table invalidation flag
304 address table
305 Write end flag

Claims (4)

A nonvolatile memory including a plurality of physical blocks, a first address conversion table in which a plurality of logical addresses are assigned to one physical address, and an erasure management table in which erased blocks are registered;
The physical block has a data area for storing data, and a redundant area for storing information for determining whether data written in the physical block is valid,
The physical block specified in the first address translation table has a second address translation table in which a plurality of physical addresses are associated with a plurality of logical addresses.
A method of controlling a nonvolatile memory device in which a physical address and a logical address are indirectly associated with each other,
At the time of initialization, an invalid physical block to which invalid data has been written or valid data has been written but not associated with any logical address, and an erased block are erased in the erase management table. Registering as a completed block and generating the first address conversion table;
At the time of data writing, an erased block is extracted from the erase management table, and a determination step of determining whether the erased block is really erased,
An erasing step of erasing the block if it has not been erased in the determining step;
And a writing step of writing data after the erasing step. The registration step includes:
One fixed page capable of determining that the second address translation table of all physical blocks exists effectively is continuously read, and the previous fixed page was read while the fixed page of the next physical block was being read. If the previous physical block is provisionally determined and the previous physical block is provisionally determined to be a valid physical block having the second address translation table, the previous physical block is added to the first address translation table. A temporary registration step for temporary registration,
After all physical block inspections, another fixed page is read only for the temporarily registered physical block, and it is determined again whether or not it is appropriate to register the physical block in the first address translation table, and the physical block is registered. 2. The method according to claim 1, further comprising: a temporary registration deletion step of deleting the temporary registration if the registration is not appropriate. The registration step includes:
When a plurality of physical blocks are redundantly associated with one logical address, a spare table registration step of registering the duplicated physical blocks in a spare table;
After the temporary registration step or the temporary registration deletion step, a physical block registered in the spare table is read out, an appropriate physical block is selected from the duplicated physical blocks, and the physical block is registered in the first address conversion table. 3. The method according to claim 2, further comprising the step of: registering the nonvolatile memory device. In the second registration step, an address table invalidation flag associated with the second address translation table of a physical block that is not selected as an appropriate physical block among duplicate physical blocks is invalidated and initialized. 4. The method according to claim 3, wherein the physical block is not erased sometimes.

Images