JP2010501916A5 - - Google Patents

Claims (33)

A controller having a serial channel output port for supplying a serial bitstream command packet and a serial channel input port for receiving a serial bitstream read data packet, wherein the serial bitstream command packet includes an operation code and a device address. When,
A memory device having an input port for receiving the serial bitstream command packet from the controller, executing the operation code when the device address corresponds to the memory device, and via the output port the serial bit A memory device that provides a stream command packet and subsequently provides the serial bitstream read data packet via the output port when the operation code corresponds to a read function. Further comprising at least one intervening memory device coupled in series between the memory device and the controller;
The at least one intervening memory device has an input port for receiving the serial bitstream command packet and passing it to the memory device;
2. The memory system of claim 1, wherein the serial bitstream read data packet is provided downstream when the device address corresponds to the at least one intervening memory device and the operation code corresponds to a read function. . The memory system of claim 2, wherein a complementary clock signal is provided in parallel to the memory device and the at least one intervening memory device. The memory of claim 2, wherein a complementary clock signal is provided to the at least one intervening memory device, passed to the memory device by the at least one intervening memory device, and passed to the controller by the memory device. system. The memory system of claim 2, further comprising an expansion link between the controller and the memory device that receives one of an expansion module and a jumper. Wherein the at least one intervening memory device is part of the extended module having a coupling means configured for electrical coupling with the extended link, the memory system according to claim 5. The memory device and the at least one intervening memory device each include a native memory core and a serial interface and control logic block that controls the native memory core in response to the serial bitstream command packet. 2. The memory system according to 2. 8. The memory system of claim 7, wherein the memory device native memory core and the at least one intervening memory device native memory core are NAND flash based. 8. The memory system of claim 7, wherein the memory device native memory core and the at least one intervening memory device native memory core are different. The memory system of claim 2, wherein the native memory core comprises one of a DRAM memory core, an SRAM memory core, a NAND flash memory core, and a NOR flash memory core.   2. The memory system according to claim 1, wherein the serial bit stream command packet has a modular structure in which a size of the serial bit stream command packet is variable. 12. The memory system of claim 11, wherein the serial bitstream command packet includes a command field that provides the operation code and the device address. 13. The memory system according to claim 12, wherein the command field includes a first subfield that provides the operation code and a second subfield that provides the device address. 12. The memory system of claim 11, wherein the serial bitstream command packet includes a command field that provides the operation code and the device address, and an address field that provides one of a row address and a column address. The serial bitstream command packet includes a command field that provides the operation code and the device address, an address field that provides one of a row address and a column address, and a data field that provides write data. The memory system according to claim 11. 12. The memory system of claim 11, wherein the controller provides a command strobe in parallel with the serial bitstream command packet, and the command strobe has an active level that matches a length of the serial bitstream command packet. 17. The controller of claim 16, wherein the controller provides a data input strobe in parallel with the serial bitstream read data packet, the data input strobe having an active level that matches a length of the serial bitstream read data packet. Memory system. 18. The memory system of claim 17, wherein the memory device latches the serial bitstream command packet in response to the active level of the command strobe when the device address corresponds to the memory device. The memory system of claim 18, wherein the memory device output port is enabled in response to the active level of the data input strobe. 20. The memory system according to claim 19, wherein the command strobe and the data input strobe are non-overlapping signals. 20. The memory system of claim 19, wherein the command strobe and the data input strobe are separated by at least one data latching clock edge. 20. The memory system of claim 19, wherein the command strobe is separated from adjacent command strobes by at least one data latching clock edge. 20. The memory system of claim 19, wherein the data input strobe is separated from adjacent data input strobes by at least one data latching clock edge. A command field that selects the memory devices of the serially connected memory devices to perform a specific memory operation
  A command packet including a series of bits for a memory system having the memory devices connected in series. 25. The command of claim 24, wherein the command field includes a first subfield that provides a device address for selecting the memory device and a second subfield that provides an operation code corresponding to the particular memory operation. packet. The command packet further includes an address field following the command field that provides one of a row address and a column address when the operation code corresponds to a read operation or a write operation, the address field comprising: 26. The command packet according to claim 25, wherein the command packet has a bit length corresponding to a row address or the column address. The command packet further includes a data field following the address field that provides write data for storage in the memory device when the operation code corresponds to the write operation, the data field comprising the write field 27. The command packet according to claim 26, wherein the command packet has a bit length corresponding to data . A memory system including a plurality of memory devices and a controller that controls the devices,
The controller has an output port for providing a bitstream command packet to a first device of the plurality of memory devices, the bitstream command packet including an operation code and a device address;
Each of the plurality of memory devices receives the bitstream command packet from one of the controller and a previous memory device and executes the operation code when the device address corresponds to the plurality of memory devices; Each of the devices provides the bitstream command packet to one of the next memory device and the controller, and the bitstream read data packet is the plurality of memory devices when the operation code corresponds to a read function. A memory system provided to the controller from the last memory device. 30. The memory system of claim 28 , wherein the plurality of memory devices are connected in series, and a first memory device and a last memory device are connected to the controller. 30. The memory system of claim 28 , wherein the controller sends a bitstream data packet to a first device of the plurality of memory devices. 32. The memory system of claim 30 , wherein the bitstream data packet from the controller and the bitstream read data packet comprise a serial bitstream. 32. The memory system of claim 30 , wherein the bitstream data packet from the controller and the bitstream read data packet include parallel bitstreams. 30. The memory system of claim 28 , wherein the plurality of memory devices are the same type or a mixture of different types of memory devices.