JP2010287644A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, along with a manufacturing method therefor which has a high ESD-resistance value before mounting, and which can prevent breakage of an ESD protective element caused by latch up and the surge voltage generated due to internal circuit actuation after mounting. <P>SOLUTION: An ESD protective element equipped with a fuse element for high ESD-resistance value is arranged parallel to a normal ESD protective element. After mounting, the ESD protective element of high ESD-resistance value acts because of surge voltage and latch up, and cuts the fuse element for allowing a conduction current to flow. As a result, the ESD protective element having high ESD-resistance value is isolated and burn out of the ESD protective element. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a protection circuit for protecting an internal circuit from electrostatic breakdown and a method for manufacturing the same.

  A protection circuit for protecting an internal circuit from a high voltage input due to an electrostatic discharge (Electro-Static Discharge: hereinafter referred to as ESD) applied to an input / output signal terminal of a semiconductor device is further increased as the integration degree of the semiconductor device is improved. Its role is important.

  The ESD protection circuit has a function of suppressing the internal potential difference to a predetermined voltage or less by distributing the charge injected by the ESD to the inside of the semiconductor device. This function has two functions: a function of supplying injected charges to a plurality of power supplies, and a function of preventing a voltage exceeding the element breakdown voltage of the internal circuit from being generated between the power supplies by a clamp element inserted between the power supplies.

  The destruction of a semiconductor device due to ESD is highly likely to occur in a process in which the semiconductor device is handled as a single unit, that is, in an assembly process, a sorting process, a packaging process, and the like of a semiconductor chip. Therefore, the ESD protection circuit before the semiconductor device is mounted on the substrate needs to have as much ESD tolerance as possible.

  However, once a semiconductor device is mounted on a substrate and then housed in a housing, the risk of failure due to ESD from the outside is reduced, and conversely, some factor (internal circuit generated during the operation of the internal circuit) The ESD protection element having a high ESD tolerance operates due to a surge generated from the power source, a surge in the power supply line, etc., and there is a high risk of destruction due to overcurrent. Thus, after mounting the semiconductor device, a protective element having a large ESD resistance is not necessarily required.

  As shown in FIG. 4, as a conventional ESD protection circuit, a technique for disconnecting the ESD protection element from the circuit by disconnecting the fuse element by applying current from outside the LSI after mounting is disclosed in order to prevent high-speed operation and latch-up. (For example, refer to Patent Document 1).

JP 2001-244338 A

  However, in the conventional method described in Patent Document 1, when the fuse element is cut, the ESD protection element is disconnected from the semiconductor device, so that there is a problem that the internal circuit is destroyed by slight ESD.

  In view of this point, the present invention realizes high electrostatic resistance before the semiconductor device is mounted, retains a certain level of electrostatic resistance after mounting, and protects against ESD caused by the operation of the internal circuit. An object of the present invention is to provide a semiconductor device capable of preventing element destruction and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device according to claim 1 is a semiconductor device having a protection circuit for protecting an internal circuit from electrostatic breakdown on a semiconductor substrate. The fuse element has at least two different ESD protection elements and a fuse element, and the fuse element is connected in series to an ESD protection element other than the ESD protection element having the smallest electrostatic resistance of the ESD protection element having a different electrostatic resistance. The fuse element has a structure in which a conduction current due to a voltage generated during operation of the internal circuit flows through at least one of the ESD protection elements connected to the fuse element.

  A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the fuse element is cut.

  According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a semiconductor substrate having a protection circuit for protecting an internal circuit from electrostatic breakdown; and the protection circuit on the semiconductor substrate. Forming at least two ESD protection elements having different electrostatic immunity, and among the ESD protection elements having different electrostatic immunity, the ESD protection elements other than the ESD protection element having the smallest electrostatic immunity A step of connecting in series a fuse element having a structure that blows when a conduction current caused by a voltage generated during operation of the circuit flows, and the ESD protection element; and the semiconductor device including the fuse element is mounted on a substrate. And a step of cutting the fuse element.

  According to the present invention, an internal circuit can be protected from ESD by an ESD protection element having a high electrostatic resistance before mounting a semiconductor device. Then, after mounting, the protective element with high electrostatic resistance can be electrically disconnected from the internal circuit, so that the ESD protective element with high electrostatic resistance can be prevented from being destroyed by a surge or the like generated from the internal circuit. Even if the ESD protection element with high electrostatic resistance is electrically disconnected, the internal circuit can be protected from ESD because the ESD protection element with low electrostatic resistance is connected to the internal circuit. Moreover, since the ESD resistance of the ESD protection element is low, the ESD protection element does not break down in response to a surge caused by the operation of the internal circuit.

It is explanatory drawing of this invention. 1 is a circuit diagram showing a first embodiment according to the present invention. It is a graph which shows the TLP (Transmission Line Pulse) measurement result of an ESD protection element. It is the figure which showed the ESD protection circuit provided with the conventional fuse element.

The present invention relates to an ESD protection circuit having ESD protection elements and fuse elements having different electrostatic resistances, and after mounting the semiconductor device, the ESD protection elements other than the ESD protection element having the smallest electrostatic resistance are electrically separated from the internal circuit. The present invention relates to a semiconductor device and a method for manufacturing the same, and will be described below with reference to the drawings.
First, the electrostatic resistance of the ESD protection element will be described. Currently, several test methods for measuring the electrostatic resistance of ESD protection elements have been defined (for example, MM (machine model) method, HBM (human body model) method, CDM (charged device model) method, etc.). The comparison of the “electrostatic resistance” according to the present invention is based on values measured by these test methods.
In order to quantitatively consider the electrostatic resistance, FIG. 3 shows current-voltage characteristics of the ESD protection element 1 and the ESD protection element 2 by TLP (Transmission Line Pulse) measurement. Since the first breakdown voltage of the ESD protection element 2 is lower than that of the ESD protection element 1 (V1 <V2), the response speed during ESD application is faster than that of the ESD protection element 1. Further, since the secondary breakdown current is high (I1> I2), a larger current than that of the ESD protection element 1 can be passed. As a result, the ESD protection element 2 exhibits a larger electrostatic resistance than the ESD protection element 1.

FIG. 1 is an explanatory diagram of the present invention. First, the invention according to claim 1 of the present invention will be described.
In FIG. 1, the ESD protection elements connected between the input / output terminals and the VDD terminal are denoted as 11a and 12a, the fuse element is denoted as 13a, and the ESD protection elements connected between the input / output terminals and the VSS terminal are denoted as 11b, 12b, the fuse element is indicated as 13b.
In this way, even if the lowercase alphabets in the code are different, the function of the element is the same if the numbers are the same. In the description below, lower case alphabets in the reference numerals are omitted.
The first ESD protection element 11 is connected between the input / output terminal and the power supply terminal (VDD terminal / VSS terminal), similarly to a normal ESD protection circuit. In parallel with the first ESD protection element 11, a second ESD protection element 12 having an ESD resistance larger than that of the first ESD protection element is connected, and the second ESD protection element 12 is electrically disconnected from the internal circuit 14. The fuse element 13 is provided.

The fuse element 13 uses a metal wiring layer having a low resistance value, and a critical current (breakdown current) necessary for cutting the wiring layer is proportional to the cross-sectional area of the metal wiring layer.
Therefore, the current value flowing through the fuse element is estimated.
First, before mounting on the substrate, the current flowing through the fuse element by applying ESD has a waveform in which the peak of the current value is several A and the half-value width is about 100 nS. Not done.
Further, since the critical current for cutting the fuse element must be equal to or less than the current value at which the ESD protection element connected to the fuse element is destroyed, it is necessary to set it to be equal to or less than the secondary breakdown current value shown in FIG. .
Considering such conditions, the cross-sectional area of the fuse element that the fuse element cuts without the ESD protection element breaking is set.

Before the mounting of the semiconductor device, when ESD is applied, the second ESD protection element 12 responds before the first ESD protection element 11 having a relatively low electrostatic resistance, and the input / output terminal to the power source Make a current path. Therefore, the internal circuit 14 is protected from destruction by ESD.
With the configuration described above, the semiconductor device according to claim 1 of the present invention can be configured. The semiconductor device according to claim 1 of the present invention can be said to be a structure before completion of the semiconductor device according to claim 2 described later.

Next, an invention according to claim 2 of the present invention will be described.
After the semiconductor device is mounted, the ESD protection element may operate due to some factor (surge generated from the internal circuit, surge in the power supply line, etc.) during the operation of the internal circuit 14. Also in this case, the second ESD protection element 12 having a relatively high electrostatic resistance is responded before the first ESD protection element 11 and becomes conductive. Thereafter, when the current flowing through the fuse element 13 exceeds the critical current, the fuse element 13 is melted and the second ESD protection element 12 is electrically disconnected from the internal circuit 14. Thereafter, the internal circuit 14 is protected from ESD by the first ESD protection element 11. With the above configuration, the semiconductor device according to claim 2 of the present invention can be configured.
The ESD protection circuit 10 in FIG. 1 is inserted between the input / output terminal and the power supply (VDD terminal / VSS terminal), but may be inserted between the power supply (VDD terminal / VSS terminal) as a power supply clamp. .

Next, an invention according to claim 3 of the present invention will be described.
First, a method for manufacturing a semiconductor device according to claim 2 will be described. According to the semiconductor device manufacturing method of the present invention, first, the semiconductor device according to claim 1 is formed by the same method as that of a normal semiconductor device. Thereafter, the fuse element 13 is cut after mounting on the substrate. The fuse element 13 needs to be designed in a desired shape so that it is not cut before mounting but is cut after mounting.

  Next, a first embodiment of the present invention will be described with reference to FIG. This is an ESD protection circuit inserted as a power supply clamp between a power supply (VDD terminal / VSS terminal). The thyristor type ESD protection element 16 is provided as a large ESD protection element. However, since the GGNMOS transistor 15 has a gate and a source terminal connected to the VSS power supply, it cannot be inserted between the input / output terminal and VDD like the ESD protection circuit 10a of FIG.

  The thyristor type ESD protection element 16 can be designed to have a high electrostatic resistance by designing the primary breakdown voltage (trigger voltage) shown in FIG. 3 to be low. However, since the thyristor type ESD protection element 16 has low latch-up resistance, the latch-up may occur due to some factor (surge generated from the internal circuit, surge in the power supply line, etc.) during the operation of the internal circuit 14 and may be destroyed. Is expensive. Therefore, the thyristor type ESD protection element 16 having a large electrostatic resistance is provided with the fuse element 13 so that the thyristor type ESD protection element 16 is electrically disconnected from the internal circuit 14 before being destroyed due to latch-up. It is.

10a, 10b, 10c; ESD protection circuit, 11a, 11b; first ESD protection element,
12a, 12b; second ESD protection element, 13a, 13b, 13c; fuse element, 14; internal circuit, 15; GGNMOS transistor, 16; thyristor type ESD protection element

Claims (3)

In a semiconductor device having a protection circuit for protecting an internal circuit from electrostatic breakdown on a semiconductor substrate,
The protection circuit includes at least two ESD protection elements and fuse elements having different electrostatic resistance,
Among the ESD protection elements having different electrostatic resistance, the fuse element is connected in series to an ESD protection element other than the ESD protection element having the smallest electrostatic resistance,
2. The semiconductor device according to claim 1, wherein the fuse element has a structure in which a conduction current due to a voltage generated during operation of the internal circuit flows through at least one of the ESD protection elements connected to the fuse element.   The semiconductor device according to claim 1, wherein the fuse element is cut. In a method for manufacturing a semiconductor device having a protection circuit for protecting an internal circuit from electrostatic breakdown on a semiconductor substrate,
Forming on the semiconductor substrate at least two ESD protection elements having different electrostatic resistances constituting the protection circuit;
Of the ESD protection elements having different electrostatic immunity, a fuse element having a structure that blows when a conduction current caused by a voltage generated during operation of the internal circuit flows through an ESD protection element other than the ESD protection element having the smallest electrostatic immunity A step of connecting them in series,
A method of manufacturing a semiconductor device, comprising: mounting the ESD protection element and the semiconductor device including the fuse element on a substrate and then cutting the fuse element.

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