JP2010287018A - Timing verification method, library creation method, and logic synthesis method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing verification method which can perform timing guarantee for all ranges by verification of two corner conditions even if delay of a cell changes nonlinearly to a delay variation factor. <P>SOLUTION: Static timing analysis is performed by approximating restriction values of delay time of each timing arc of each cell, and setup time and hold time of the cell which performs storing by a nonlinear approximate expression of the Nth order function using parameters P of voltage V, temperature T and a transistor as elements respectively, by creating a maximum value library and a minimum value library in which values of the nonlinear approximate expression relative to a combination of V, T, and P which makes the value of the Nth order function maximum and minimum, are registered respectively, and by reading the delay time of the timing arc of the cell which forms a path of an analysis target, from the maximum value library or the minimum value library. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a timing verification method, a library creation method, and a logic synthesis method for a semiconductor integrated circuit.

  One method for verifying the timing of a logic circuit formed as a semiconductor integrated circuit is static timing analysis (STA). In the STA, the timing of circuit operation is verified based on the delay assigned to the logic design cell. At this time, the signal propagation path to be analyzed is extracted, the delay of the cell of the path is read from the library in which the delay value of each cell is registered, and verification is performed by adding the value.

  In general, the delay of a semiconductor integrated circuit varies depending on the ambient temperature, power supply voltage, transistor element characteristics, and the like. Therefore, when performing STA, the delay value read from the library is multiplied by a coefficient according to the conditions such as ambient temperature, power supply voltage, transistor element characteristics, etc., and the delay value corresponding to each condition is calculated. Has been done.

  At that time, in the past, timing verification was performed only under two corner conditions where the delay value of the signal path is maximum and minimum, assuming that the delay changes linearly.

  However, in recent years, as the miniaturization of elements has made it necessary to lower the power supply voltage, the number of cases in which the conventional linear model does not match the actual delay has increased.

  For example, the delay of a transistor tended to increase as the temperature increased before the 100 nm generation, but as the power supply voltage decreased with miniaturization, the effect of an increase in the threshold voltage of the transistor due to a decrease in temperature increased. In some cases, the lower the value, the larger.

  In response to such a situation, conventionally, the corner accuracy for performing timing verification has been increased to improve the analysis accuracy. For example, there has been proposed a timing verification method for performing multi-corner verification under conditions other than the best condition and the worst condition by using the temperature coefficient in each corner condition in which the temperatures of the best condition and the worst condition are reversed (see Patent Document 1). .)

  However, the above-described proposed method has a problem that time required for timing verification increases because verification at many corners is necessary.

JP 2007-272687 A (page 7-9, FIG. 1)

  Accordingly, an object of the present invention is to provide a timing verification method capable of guaranteeing the timing of the entire range by verifying two corner conditions even when the cell delay changes nonlinearly with respect to the delay variation element. There is to do.

  In accordance with one aspect of the present invention, the constraint values for the timing arc delay time, storage cell setup time and hold time for all cells used in the logic design, voltage, temperature and transistor parameters. A maximum value library in which the values of the nonlinear approximation formulas for the combination of the elements having the maximum value as the function value are registered, and the function values are minimized. Create a minimum value library in which the values of the nonlinear approximation formulas for the combinations of elements to be values are registered, and the combinations of the elements having the maximum value of the function and the elements having the minimum value of the function. Using the combination as a corner condition, the delay time of the timing arc of the cells forming the path to be analyzed is the maximum value library. Timing verification method and performing a static timing analysis by reading from said minimum value library is provided.

  According to another aspect of the present invention, the delay time of each timing arc of all the cells used in the logic design is expressed by a nonlinear approximate expression of a function having voltage, temperature, and transistor parameters as elements. Create a library to be used in a timing verification method that performs static timing analysis using the combination of the elements having the maximum value of the function and the combination of the elements having the minimum value of the function as corner conditions. A method for approximating a delay time of a timing arc of a cell so as to be sandwiched between a first nonlinear approximation expression and a second nonlinear approximation expression of a function having voltage, temperature, and transistor parameters as elements. The value of the first and second nonlinear approximation formulas for the combination of elements having the maximum value of A library creation method characterized by creating a value library and creating a minimum value library for registering values of the first and second nonlinear approximation formulas for the combination of elements having the function value as a minimum value Provided.

  According to the present invention, even when the cell delay changes nonlinearly with respect to the delay variation element, the timing of the entire range can be guaranteed by verifying the two corner conditions.

The flowchart which shows the basic concept of the timing verification method which concerns on Example 1 of this invention. FIG. 6 is a diagram illustrating an example of a nonlinear approximation expression used in timing verification according to the first embodiment. The figure which shows the example which approximates the delay time of a timing arc with two nonlinear approximation formulas. The flowchart which shows the example of the flow of a process of the library production method which concerns on Example 2 of this invention. The circuit diagram which shows the example of the path | pass which performs timing verification. FIG. 9 is a flowchart showing an example of a verification procedure related to setup time performed using the library of the second embodiment. FIG. 10 is a flowchart showing an example of verification procedure regarding hold time performed using the library according to the second embodiment. The flowchart which shows the basic concept of the logic synthesis method which concerns on Example 3 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  FIG. 1 is a flowchart showing the basic concept of the timing verification method according to the first embodiment of the present invention.

  In the timing verification of the present embodiment, the delay time D of the timing arc of each cell used in the logic design, the set-up time constraint value S and the hold time constraint value H of the cell to be stored are set to the voltage V , A maximum value library in which values of a nonlinear approximation expression that maximizes the value of the N-order function are registered, and an N-order function When a minimum value library in which the value of a nonlinear approximation expression that minimizes the value is registered in advance and timing analysis is performed, static timing analysis (STA) is performed using the maximum value library and the minimum value library. .

Therefore, in the flow shown in FIG. 1, first, the delay time D of the timing arcs of all the cells used in the logic design, the constraint value S of the setup time of the cell to be stored, and the constraint value H of the hold time are set. , A non-linear approximation formula D = K1d * f (x) + K0d, using an N-order function f (V, T, P) whose elements are voltage V, temperature T and transistor parameter P.
S = K1s * f (x) + K0s
H = K1h * f (x) + K0h
Respectively. However, K1d, K0d, K1s, K0s, K1h and K0h represent coefficients, and x = (V, T, P) (step S01).

  By using the above-mentioned nonlinear approximation formula, for example, as shown in FIG. 2, even when the delay time D of the timing arc shows a nonlinear change with respect to the voltage V, the temperature T, and the parameter P of the transistor, the accuracy can be improved. A high approximation can be obtained.

Next, assuming that the combination of the voltage V, the temperature T, and the transistor parameter P having the maximum value of the function f (x) is xmax, the value Dmax = K1d * f (xmax) + K0d
Smax = K1s * f (xmax) + K0s
Hmax = K1h * f (xmax) + K0h
Is registered in the maximum value library (step S02).

Further, the combination of the voltage V, the temperature T, and the transistor parameter P that minimizes the value of the function f (x) is xmin, and the value Dmin = K1d * f (xmin) + K0d of the above-described nonlinear approximation expression for this xmin.
Smin = K1s * f (xmin) + K0s
Hmin = K1h * f (xmin) + K0h
Is registered in the minimum value library (step S03).

  As described above, after preparing the maximum value library and the minimum value library, regarding the analysis target path of the logic circuit formed as the semiconductor integrated circuit, the delay time of the timing arc of the cell forming the path is determined from the maximum value library. The STA that is read and executed is executed (step S04). Similarly, the STA that is executed by reading the delay time of the timing arc of the cell forming the analysis target path from the minimum value library is executed (step S05).

  At this time, in this embodiment, it is possible to calculate the path delay of the analysis target path only by adding the delay times read from the maximum value library and the minimum value library.

  In addition, since the maximum value library and the minimum value library are created for the combination of the voltage V, the temperature T, and the transistor parameter P that maximize and minimize the value of the function f (x), the maximum value library and the minimum value library are generated. Execution of the STA using the value library corresponds to the STA in the two corner conditions of the voltage V, the temperature T, and the transistor parameter P.

  Therefore, according to the present embodiment, by performing STA using the maximum value library and the minimum value library, it is possible to guarantee timing within the entire guaranteed range of voltage, temperature, and transistor parameters.

  Further, since the path delay of the analysis target path can be calculated simply by adding the delay times read from the maximum value library and the minimum value library, the time required for timing verification can be shortened.

  FIG. 2 shows an example in which the delay time D of the timing arc is approximated by one non-linear approximation formula. However, when the delay time D shows the variation in the chip, or the delay time D of the timing arc of all the cells is stored. When the error in approximating the constraint value S of the set-up time S and the constraint value H of the hold time by an expression of the {K1 * f (x) + K0} format cannot be ignored, as shown in FIG. And approximating with two approximation formulas that sandwich the error range, more accurate approximation can be performed.

In FIG. 3, the delay time D of the timing arc is expressed by a first non-linear approximation formula D = K1dMAX * f (x) + K0dMAX that approximates the variation in delay time and the maximum error.
And the second nonlinear approximation formula D = K1dMIN * f (x) + K0dMIN that approximates the minimum value of variation and error
And an approximate example.

  In the present embodiment, as described above, a method for creating the maximum value library and the minimum value library when the variation in the delay time D of the timing arc and the error range are approximated so as to be sandwiched between two approximate expressions will be described.

  FIG. 4 is a flowchart showing an example of the processing flow of the library creation method according to the second embodiment of the present invention.

  In creating the library, first, as described above, the delay time D of the timing arc is approximated by sandwiching between the first nonlinear approximation formula and the second nonlinear approximation formula of the Nth order function f (x) (step S11). ).

That is, the delay time D of the timing arc is
K1dMIN * f (x) + K0dMIN <D <K1dMAX * f (x) + K0dMAX
It is expressed.

Subsequently, the value Dmax1 = K1dMAX * f (xmax) + K0dMAX of the first and second nonlinear approximation formulas for the combination xmax of the voltage V, the temperature T and the transistor parameter P that maximize the function f (x).
Dmax2 = K1dMIN * f (xmax) + K0dMIN
Are registered in the maximum value library (step S12).

The value Dmin1 = K1dMAX * f (xmin) + K0dMAX of the first and second nonlinear approximation formulas for the combination xmin of the voltage V, the temperature T and the transistor parameter P that minimizes the function f (x)
Dmin2 = K1dMIN * f (xmin) + K0dMIN
Are registered in the minimum value library (step S13).

  As described above, in the maximum value library and the minimum value library, values that cover the variation of the timing arc delay time D and the approximate error range are registered for the corner condition of the combination of the voltage V, the temperature T, and the transistor parameter P. Is done.

  Next, an example of timing verification using the maximum value library and the minimum value library will be described.

  Here, regarding data transmission between flip-flops such as the flip-flop FF1 and flip-flop FF2 shown in FIG. An example of performing time verification and hold time verification will be described.

  First, the procedure for verifying the setup time will be described with reference to the flowchart of FIG.

  Regarding the setup time, the data system path delay Dar is larger and the clock system path delay Drc is smaller in terms of timing. Therefore, in this case, the data system path delay Dar is calculated by using a value based on the first nonlinear approximation formula that approximates the maximum variation of the delay time D of the timing arc, and for calculating the clock system path delay Drc, A value based on the second nonlinear approximation formula that approximates the minimum value of the variation in the delay time D is used.

That is, first, using the maximum value library, the sum (Σ) of values Dmax1 according to the first nonlinear approximation expression of the timing arc of the data path and the value Dmax2 according to the second nonlinear approximation expression of the timing arc of the clock path. Find the sum,
DarMAX = ΣDmax1
DrcMAX = ΣDmax2
Is calculated (step S21).

Next, using the setup time constraint value Smax registered in the maximum value library, where T is the clock cycle, the setup time margin setup slackMAX = DrcMAX−DarMAX + T−Smax
Is calculated (step S22).

Further, using the minimum value library, the sum of the values Dmin1 according to the first nonlinear approximation expression of the timing arc of the data path and the sum of the values Dmin2 according to the second nonlinear approximation expression of the timing arc of the clock path are obtained.
DarMIN = ΣDmin1
DrcMIN = ΣDmin2
Is calculated (step S23).

Next, using the setup time constraint value Smin registered in the minimum value library, the setup time margin setup slackMIN = DrcMIN−DarMIN + T−Smin
Is calculated (step S24).

Finally, whether the calculated setup time margins are both 0 or more, that is,
setup_slackMAX ≧ 0 & setup_slackMIN ≧ 0
Is verified (step S25).

  As a result, if both of the above-described setup time margins are 0 or more (YES), it is possible to determine that the data transmission to be analyzed is “there is setup time”, otherwise (NO), the data transmission to be analyzed. Can be determined as “timing violation at setup time”.

  Next, the procedure for verifying the hold time will be described with reference to the flowchart of FIG.

  Regarding the hold time, the smaller the data system path delay Dar and the larger the clock system path delay Drc, the stricter the timing. Therefore, in this case, the data system path delay Dar is calculated by using a value by the second nonlinear approximation formula that approximates the minimum value of the variation in the delay time D of the timing arc, and the clock system path delay Drc is calculated by A value based on the first nonlinear approximation formula that approximates the maximum value of the variation in the delay time D is used.

That is, first, using the maximum value library, the sum of the values Dmax2 of the data system path timing arc by the second nonlinear approximation expression and the sum of the values Dmax1 of the clock system path timing arc by the first nonlinear approximation expression are obtained. ,
DarMAX = ΣDmax2
DrcMAX = ΣDmax1
Is calculated (step S31).

Subsequently, the hold time margin hold slack = DarMAX−DrcMAX−Hmax using the hold time constraint value Hmax registered in the maximum value library.
Is calculated (step S32).

Further, using the minimum value library, the sum of the values Dmin2 by the second nonlinear approximation formula of the timing arc of the data path and the sum of the values Dmin1 by the first nonlinear approximation formula of the timing arc of the clock path are obtained.
DarMIN = ΣDmin2
DrcMIN = ΣDmin1
Is calculated (step S33).

Subsequently, by using the hold time constraint value Hmin registered in the minimum value library, the hold time margin hold slackMIN = DarMIN−DrcMIN−Hmin
Is calculated (step S34).

Finally, whether the calculated hold time margins are both 0 or more, that is,
hold slackMAX ≧ 0 & hold slackMIN ≧ 0
Is verified (step S35).

  As a result, if both of the above hold time margins are 0 or more (YES), it is possible to determine that the analysis target data transmission is “the hold time has margin”, otherwise (NO), the analysis target data transmission. Can be determined as “timing violation in hold time”.

  According to the present embodiment, the delay time of the timing arc is determined with respect to the two corner conditions of the combination of the voltage V, the temperature T, and the transistor parameter P that maximize and minimize the value of the function f (x). Values that approximate the upper and lower limits of variation are registered in the maximum value library and the minimum value library. Therefore, by executing the STA using the maximum value library and the minimum value library, the timing is guaranteed within the entire guaranteed range of the voltage, temperature, and transistor parameters within the range of the delay time of the timing arc. be able to.

  In this embodiment, a method for performing logic synthesis using the maximum value library and the minimum value library shown in the second embodiment will be described.

  In the maximum value library and the minimum value library shown in the second embodiment, the variation of the delay time D of the timing arc and the first nonlinear approximation formula that approximates the upper limit of the error, the variation of the delay time D, and the lower limit of the error are approximated. Two approximate values calculated by the second nonlinear approximation formula are registered respectively. Therefore, if the variation and error of the delay time D of the timing arc are large, the difference between the two approximate values becomes large.

  On the other hand, when logic synthesis is performed, if the cells used in the logic synthesis result include cells with large variations in the delay time D of the timing arc and large errors, it may be difficult to adjust the timing. .

  Therefore, in this embodiment, when performing logic synthesis, the difference between the above two approximate values registered in the maximum value library and the minimum value library is obtained, and a cell having a large difference is determined from a cell used for logic synthesis. Exclude it.

  FIG. 8 is a flowchart showing the basic concept of the logic synthesis method according to the third embodiment of the present invention.

  In the present embodiment, in the logic synthesis, first, in the maximum value library shown in the second embodiment, a difference (Dmax1-Dmax2) between two values Dmax1 and Dmax2 registered in each timing arc of each cell is obtained. A cell having a timing arc with a large value of (Dmax1-Dmax2) is extracted (step S41).

  For the minimum value library shown in the second embodiment, the difference (Dmin1-Dmin2) between the two values Dmin1 and Dmin2 registered in each timing arc of each cell is obtained, and the value of this (Dmin1-Dmin2) is obtained. A cell having a large timing arc is extracted (step S42).

  Based on the above extraction results, the cells extracted from the maximum value library or the minimum value library are excluded from the cells used for logic synthesis (step S43), and logic synthesis is executed (step S44).

  According to the present embodiment, cells having timing arcs with large variations in delay time can be excluded from cells used for logic synthesis, so that timing adjustment during logic synthesis can be easily performed.

FF1, FF2 flip-flop

Claims (5)

A common N-order function with the voltage, temperature, and transistor parameters as the constraints for the delay time of each timing arc of all cells used in the logic design, the setup time and hold time of the storing cell. Approximate each with a nonlinear approximation formula of
A maximum value library in which the value of the nonlinear approximation expression for the combination of elements having the maximum value of the function is registered, and a value of the nonlinear approximation expression for the combination of elements having the minimum value of the function are registered. Created the minimum value library,
The combination of the elements having the maximum value of the function and the combination of the elements having the minimum value of the function as a corner condition, the delay time of the timing arc of the cell forming the path to be analyzed is the maximum value. A timing verification method comprising: reading from a library or the minimum value library and performing a static timing analysis. When there is variation and approximation error in the delay time of the timing arc,
The delay time is approximated so as to be sandwiched between a first nonlinear approximation formula that approximates the maximum value of the variation and the approximation error and a second nonlinear approximation formula that approximates the minimum value of the variation and the approximation error. The timing verification method according to claim 1. When performing the static timing analysis,
Whether to use an approximate value based on the first nonlinear approximate expression or an approximate value based on the second nonlinear approximate expression is selected for each path to be analyzed according to the analysis purpose. The timing verification method according to claim 2. The delay time of each timing arc of all cells used in the logic design is approximated by a common non-linear approximation formula of functions having voltage, temperature, and transistor parameters as elements, and the value of the function is set to the maximum value. A method of creating a library for use in a timing verification method for performing a static timing analysis with a combination of the elements to be used and a combination of the elements having a minimum value of the function as a corner condition,
Approximating the delay time of the cell timing arc so as to be sandwiched between the first nonlinear approximation and the second nonlinear approximation of a function whose elements are voltage, temperature and transistor parameters,
Creating a maximum value library for registering the values of the first and second nonlinear approximation formulas for the combination of the elements having the function value as the maximum value;
A library creation method, comprising: creating a minimum value library for registering values of the first and second nonlinear approximation formulas for the combination of elements having a minimum value of the function. From the maximum value library and the minimum value library created by the library creation method according to claim 4,
Extracting a cell having a timing arc having a large difference between the value of the first nonlinear approximation formula and the value of the second nonlinear approximation formula;
A logic synthesis method, wherein the extracted cells are excluded from cells used for logic synthesis.

Images