JP2010283532A - Semiconductor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor circuit performing a stable operation. <P>SOLUTION: The circuit has: a first p-channel transistor (201) with a source connected to a first potential node; a first n-channel transistor (202) with a source connected to a second potential node; a second p-channel transistor (203) with a gate connected to a drain of the first n-channel transistor and a drain connected with a gate of the first n-channel transistor; a second n-channel transistor (204) with a gate connected with a drain of the first p-channel transistor and a drain connected with a gate of the first p-channel transistor; first resistors (301, 302) connected between the drains of the first p-channel transistor and the first n-channel transistor; and second resistors (303, 304) connected between the drains of the second p-channel transistor and the second n-channel transistor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor circuit.

  As the operation speed of a semiconductor circuit is improved by the advancement of semiconductor microfabrication technology, a high-speed and high-quality clock signal is required inside the semiconductor chip. Since it is difficult to generate a clock signal with a frequency exceeding GHz, which is the same as the operation speed inside the semiconductor chip, and input it to the semiconductor chip, a low-speed clock signal is usually sent from the crystal oscillator on the mounting chip to the semiconductor chip. And multiplying by a PLL (phase locked loop) circuit inside the semiconductor chip to generate a high-speed clock signal. In order to generate a high-quality clock signal at a frequency exceeding GHz, an oscillation circuit in the PLL circuit is particularly important, and in recent years, a so-called LC oscillator using an inductor and a variable capacitor is often used. Among them, the CMOS flip-flop type oscillation circuit has advantages such as a small number of large inductors and a small current consumption.

  There is also known a bi-CMOS output circuit that can increase the driving force during the switching operation in which the output voltage changes from the “H” level to the “L” level, and can suppress the fluctuation of the ground potential during the switching operation. (For example, refer to JP-A-5-37346).

  In addition, a semiconductor memory device that can ensure high-speed operation while improving soft error resistance is known (see, for example, JP-A-2005-302121).

JP-A-5-37346 JP-A-2005-302121

  An object of the present invention is to provide a semiconductor circuit capable of performing stable operation.

  The semiconductor circuit includes a first p-channel field effect transistor having a source connected to a first potential node, a first n-channel field effect transistor having a source connected to a second potential node, and a source connected to the first potential node. A second p-channel field effect transistor having a gate connected to the drain of the first n-channel field effect transistor and a drain connected to the gate of the first n-channel field effect transistor. And a source connected to the second potential node, a gate connected to the drain of the first p-channel field effect transistor, and a drain connected to the gate of the first p-channel field effect transistor. N-channel field effect transistor, the drain of the first p-channel field effect transistor, and the first And a second resistor connected between the drain of the second p-channel field effect transistor and the drain of the second n-channel field effect transistor. And a resistor.

  By providing the first resistor and the second resistor, the gate-source voltage of the field-effect transistor can be increased, the amplification gain of the field-effect transistor can be increased, and stable operation can be performed. Can do.

It is a circuit diagram which shows the structural example of a CMOS flip-flop type | mold LC oscillation circuit. FIG. 2 is a circuit diagram illustrating a detailed configuration example of the oscillation circuit of FIG. 1. 1 is a circuit diagram showing a configuration example of a CMOS flip-flop type LC oscillation circuit (semiconductor circuit) according to a first embodiment of the present invention. It is a figure which shows the voltage waveform example of the node of the oscillation circuit of FIG. It is a figure which shows the structural example of the resistance using a transfer gate. It is a circuit diagram which shows the structural example of the CMOS flip-flop type | mold LC oscillation circuit (semiconductor circuit) by the 2nd Embodiment of this invention. It is a block diagram which shows the structural example of the divide-by-2 circuit (semiconductor circuit) by the 3rd Embodiment of this invention. FIG. 8 is a circuit diagram illustrating a configuration example of a latch circuit (semiconductor circuit) in FIG. 7.

(Reference technology)
FIG. 1 is a circuit diagram showing a configuration example of a CMOS flip-flop type LC oscillation circuit. The inverting amplifier 101 has an input terminal connected to the inverting output terminal OUTX and an output terminal connected to the normal output terminal OUT. The inverting amplifier 102 has an input terminal connected to the normal output terminal OUT, and an output terminal connected to the inverting output terminal OUTX. The inductor 103 is connected between the normal output terminal OUT and the inverted output terminal OUTX. The variable capacitor 104 is connected between the normal output terminal OUT and the inverted output terminal OUTX. The inverting amplifiers 101 and 102 constitute a flip-flop circuit. If the gains of the inverting amplifiers 101 and 102 are large to some extent, the normal output terminal OUT oscillates by alternately repeating the transition between the high level and the low level. The oscillation frequency f is 1 / {2π√ (LC)}. Here, L is the inductance of the inductor 103, and C is the capacitance value of the variable capacitor 104. The normal output terminal OUT outputs an oscillation signal. The inverting output terminal OUTX outputs an oscillation signal having a phase opposite to that of the oscillation output terminal OUT.

  FIG. 2 is a circuit diagram showing a detailed configuration example of the oscillation circuit of FIG. The inverting amplifier 101 includes a first p-channel field effect transistor 201 and a first n-channel field effect transistor 202. The inverting amplifier 102 includes a second p-channel field effect transistor 203 and a second n-channel field effect transistor 204. The first p-channel field effect transistor 201 has a source connected to the power supply potential node Vdd, a gate connected to the normal output terminal OUT, and a drain connected to the inverted output terminal OUTX. The first n-channel field effect transistor 202 has a source connected to the reference potential node via the current source 205, a gate connected to the normal output terminal OUT, and a drain connected to the inverted output terminal OUTX. The second p-channel field effect transistor 203 has a source connected to the power supply potential node Vdd, a gate connected to the inverting output terminal OUTX, and a drain connected to the normal output terminal OUT. The second n-channel field effect transistor 204 has a source connected to the reference potential node via the current source 205, a gate connected to the inverting output terminal OUTX, and a drain connected to the normal output terminal OUT. Providing the current source 205 can suppress deterioration of characteristics due to manufacturing variations.

  In the oscillation circuit, when the gains of the inverting amplifiers 101 and 102 are small, the normal output terminal OUT and the inverting output terminal OUTX are fixed at the same intermediate potential and do not oscillate. Further, when the technology advances and the power supply voltage of the circuit decreases or the threshold voltage Vth of the transistors 201 to 204 increases to suppress the leakage current of the transistors 201 to 204, the p-channel electric field is increased with respect to the intermediate potential. A region where both the effect transistors 201 and 203 and the n-channel field effect transistors 202 and 204 are not sufficiently turned on is generated, and the gains of the inverting amplifiers 101 and 102 are lowered. At that time, in order to oscillate the oscillation circuit, it is necessary to ensure the gain by enlarging the size of the transistors 201 to 204, resulting in an increase in manufacturing cost and current consumption.

  In addition, if the parasitic capacitance of the gates of the transistors 201 to 204 becomes too large, the variable capacitance 104 and the parasitic capacitances of the gates of the transistors 201 to 204 are connected in parallel. The frequency cannot be obtained.

  Similarly, when the inductor 103 having a low Q factor (Quality Factor) is used, it becomes difficult to oscillate, and the size of the transistors 201 to 204 needs to be increased. In order to increase the Q value of the inductor 103 and make it easy to oscillate, the size of the inductor 103 is increased, the number of metal wiring layers is increased, or the film pressure is increased, which increases the manufacturing cost.

  Hereinafter, an embodiment of a semiconductor circuit capable of performing a stable operation will be described.

(First embodiment)
FIG. 3 is a circuit diagram showing a configuration example of the CMOS flip-flop LC oscillator circuit (semiconductor circuit) according to the first embodiment of the present invention. The oscillation circuit (FIG. 3) of this embodiment is obtained by adding resistors 301 to 304 to the oscillation circuit of FIG.

  The inverting amplifier 101 includes a first p-channel field effect transistor 201, resistors 301 and 302, and a first n-channel field effect transistor 202. The inverting amplifier 102 includes a second p-channel field effect transistor 203, resistors 303 and 304, and a second n-channel field effect transistor 204.

  The first p-channel field effect transistor 201 has a source connected to the power supply potential node Vdd, a gate connected to the node NBN, and a drain connected to the node NAP. The first n-channel field effect transistor 202 has a source connected to the drain of the third n-channel field effect transistor 305, a gate connected to the node NBP, and a drain connected to the node NAN. The second p-channel field effect transistor 203 has a source connected to the power supply potential node Vdd, a gate connected to the node NAN, and a drain connected to the node NBP. The second n-channel field effect transistor 204 has a source connected to the drain of the third n-channel field effect transistor 305, a gate connected to the node NAP, and a drain connected to the node NBN. The third n-channel field effect transistor 305 has a gate connected to the control terminal PDX and a source connected to a reference potential node (for example, a ground potential node).

  The inductor 103 is connected between the normal output terminal OUT and the inverted output terminal OUTX. The variable capacitor 104 is connected between the normal output terminal OUT and the inverted output terminal OUTX. The resistor 301 is connected between the node NAP and the inverting output terminal OUTX. The resistor 302 is connected between the inverting output terminal OUTX and the node NAN. The resistor 303 is connected between the node NBP and the normal output terminal OUT. The resistor 304 is connected between the normal output terminal OUT and the node NBN.

  The inverting amplifiers 101 and 102 constitute a flip-flop circuit. By the inverting amplification of the inverting amplifiers 101 and 102, the normal output terminal OUT oscillates by alternately repeating the transition between the high level and the low level. The oscillation frequency f is 1 / {2π√ (LC)}. Here, L is the inductance of the inductor 103, and C is the capacitance value of the variable capacitor 104. The oscillation frequency f can be changed by changing the capacitance of the variable capacitor 104. The normal output terminal OUT outputs an oscillation signal. The inverting output terminal OUTX outputs an oscillation signal having a phase opposite to that of the oscillation output terminal OUT.

  When a fixed bias voltage is applied to the control terminal PDX, the third n-channel field effect transistor 305 functions as a current source. By providing the current source of the transistor 305, characteristic deterioration due to manufacturing variation can be suppressed.

  Even when a current source is not required, the transistor 305 can function as a transistor for cutting off a current path during power-down. At the time of power-down, the transistor 305 is turned off and the current path can be cut off by connecting the control terminal PDX to the reference potential node. At other times, similarly to the above, a bias voltage (power supply voltage or intermediate voltage) can be applied to the control terminal PDX.

  The same effect can be obtained when the transistor 305 is provided not on the reference potential node side but on the power supply potential node Vdd side. That is, a p-channel field effect transistor having a source connected to the power supply potential node Vdd, a gate connected to the control terminal PDX, and a drain connected to the interconnection point of the sources of the transistors 201 and 203 is provided. The source can be connected directly to the reference potential node.

  Alternatively, the transistor 305 may be omitted, and the sources of the transistors 202 and 204 may be directly connected to the reference potential node.

  For example, the power supply potential node Vdd is 1.2V, and the reference potential node is 0V. At the initial stage of oscillation, both the normal output terminal OUT and the inverted output terminal OUTX have the same intermediate potential of, for example, 0.6V.

  In the case of the oscillation circuit of FIG. 2, when both the normal output terminal OUT and the inverted output terminal OUTX are 0.6V, the gate voltages of the transistors 201 to 204 are all 0.6V. Then, the source-gate voltage of the p-channel field effect transistors 201 and 203 becomes 1.2V−0.6V = 0.6V. Further, the source-gate voltage of the n-channel field effect transistors 202 and 204 is 0.6V-0V = 0.6V.

  FIG. 4 is a diagram illustrating voltage waveform examples of nodes NAP, NAN, NBP, and NBN of the oscillation circuit of FIG. For example, the power supply potential node Vdd is 1.2V, and the reference potential node is 0V. The maximum voltage of the nodes NAP and NBP is around 1.2V, and the minimum voltage of the nodes NAN and NBN is around 0V. In the oscillation circuit of FIG. 3, when both the normal output terminal OUT and the inverted output terminal OUTX become 0.6V, for example, the node NAP is 0.7V, the node NAN is 0.5V, due to the voltage drop of the resistors 301 to 304, Node NBP is 0.7V and node NBN is 0.5V. As a result, the gate voltages of the p-channel field effect transistors 201 and 203 are each 0.5V, and the gate voltages of the n-channel field effect transistors 202 and 204 are respectively 0.7V. Then, the source-gate voltage of the p-channel field effect transistors 201 and 203 becomes 1.2V−0.5V = 0.7V, which is higher than that of the oscillation circuit of FIG. Further, the source-gate voltage of the n-channel field effect transistors 202 and 204 is 0.7V-0V = 0.7V, which is higher than that of the oscillation circuit of FIG.

  In this state, it is uncertain which of the normal output terminal OUT and the inverted output terminal OUTX is at a high level, but eventually either the normal output terminal OUT or the inverted output terminal OUTX is high due to noise. Level, and the other goes low.

  As described above, the source-gate voltage of the p-channel field effect transistors 201 and 203 increases, and the source-gate voltage of the n-channel field effect transistors 202 and 204 increases. As a result, the current that can flow through the transistors 201 to 204 is increased, and the gains of the inverting amplifiers 101 and 102 are increased. Since the gains of the inverting amplifiers 101 and 102 are increased, the oscillation circuit can stably start oscillation even if the size of the transistors 201 to 204 is small. Further, even when the power supply voltage is low, the oscillation circuit can stably start oscillation.

  When the resistors 301 to 304 are provided, the parasitic capacitances of the gates of the transistors 201 to 204 are connected to the variable capacitor 104 via the resistors 301 to 304, respectively. Therefore, in the oscillation circuit of FIG. 3, the variable range of the capacitance value by the variable capacitor 104 is wider than that of the oscillation circuit of FIG. 2, and the oscillation frequency range can be widened. However, if the resistance values of the resistors 301 to 304 are excessively increased, the high frequency characteristics of the oscillation circuit deteriorate due to RC delay.

  Note that the same effect can be obtained even if the resistors 302 and 304 are omitted in the oscillation circuit of FIG. In that case, the resistor 301 is connected between the drain of the first p-channel field effect transistor 201 and the inverting output terminal OUTX. The resistor 303 is connected between the drain of the second p-channel field effect transistor 203 and the normal output terminal OUT. The inverting output terminal OUTX is connected to the drain of the first n-channel field effect transistor 202. The normal output terminal OUT is connected to the drain of the second n-channel field effect transistor 204.

  Further, even if the resistors 301 and 303 are omitted from the oscillation circuit of FIG. In that case, the resistor 302 is connected between the drain of the first n-channel field effect transistor 202 and the inverting output terminal OUTX. The resistor 304 is connected between the drain of the second n-channel field effect transistor 204 and the normal output terminal OUT. The inverting output terminal OUTX is connected to the drain of the first p-channel field effect transistor 201. The normal output terminal OUT is connected to the drain of the second p-channel field effect transistor 203.

  The resistors 301 to 304 can be configured by passive elements such as polysilicon resistors, metal (metal) resistors, and diffused resistors, but the on-resistance of the transfer gate as shown in FIG. 5 may be used as the resistor elements.

  FIG. 5 is a diagram illustrating a configuration example of the resistor 301 using a transfer gate. The p-channel field effect transistor 501 has a source connected to the node NAP, a gate connected to the reference potential node, and a drain connected to the inverting output terminal OUTX. The n-channel field effect transistor 502 has a source connected to the inverting output terminal OUTX, a gate connected to the power supply potential node Vdd, and a drain connected to the node NAP. The transistors 501 and 502 are both turned on, and can function as resistors due to their on-resistance. The resistors 302 to 304 can also be configured by transfer gates, similarly to the resistor 301 of FIG.

(Second Embodiment)
FIG. 6 is a circuit diagram showing a configuration example of a CMOS flip-flop type LC oscillation circuit (semiconductor circuit) according to the second embodiment of the present invention. The oscillation circuit (FIG. 6) of the present embodiment is obtained by providing transistors 601 to 604 instead of the transistor 305 and the resistors 301 to 304 with respect to the oscillation circuit of FIG. Hereinafter, the points of the present embodiment different from the first embodiment will be described.

  The p-channel field effect transistor 601 has a source connected to the node NAP, a gate connected to the reference potential node, and a drain connected to the inverting output terminal OUTX. The n-channel field effect transistor 602 has a source connected to the node NAN, a gate connected to the control terminal PDX, and a drain connected to the inverting output terminal OUTX. The p-channel field effect transistor 603 has a source connected to the node NBP, a gate connected to the reference potential node, and a drain connected to the normal output terminal OUT. The n-channel field effect transistor 604 has a source connected to the node NBN, a gate connected to the control terminal PDX, and a drain connected to the normal output terminal OUT. The sources of n-channel field effect transistors 202 and 204 are connected to a reference potential node.

  The transistors 601 and 603 are both turned on, and can function as resistors due to their on-resistance.

  The transistors 602 and 604 have the functions of the resistors 302 and 304 and the transistor 305 in FIG. Normally, the control terminal PDX is connected to the power supply potential node Vdd, and both the transistors 602 and 604 are turned on and function as resistors by their on resistance. At power-down, the control terminal PDX is connected to the reference potential node, and both the transistors 602 and 604 are turned off to cut off the current path.

  When the transistors 601 to 604 function as the resistors 301 to 304 in FIG. 3, the voltages of the nodes NAP, NAN, NBP, and NBN do not have full amplitude compared with the case of using the transfer gate of FIG. However, there is an advantage that the size can be reduced. 6 may be provided with the current source 205 shown in FIG.

(Third embodiment)
FIG. 7 is a block diagram showing a configuration example of a divide-by-2 circuit (semiconductor circuit) according to the third embodiment of the present invention. In the latch circuit 701, the normal input terminal D is connected to the inverted frequency divided output terminal DIVOUTX, the inverted input terminal DX is connected to the normal frequency divided output terminal DIVOUT, and the normal clock signal is supplied to the normal clock terminal CK. The inverted clock signal is supplied to the inverted clock terminal CKX. The normal output terminal OUT of the latch circuit 701 is connected to the normal input terminal D of the latch circuit 702, and the inverted output terminal OUTX of the latch circuit 701 is connected to the inverted input terminal DX of the latch circuit 702. In the latch circuit 702, the normal clock signal is supplied to the normal clock terminal CK, the inverted clock signal is supplied to the inverted clock terminal CKX, the normal output terminal OUT is connected to the normal frequency division output terminal DIVOUT, The inverted output terminal OUTX is connected to the inverted divided output terminal DIVOUTX.

  FIG. 8 is a circuit diagram showing a configuration example of the latch circuits (semiconductor circuits) 701 and 702 in FIG. The latch circuit of FIG. 8 is obtained by deleting the inductor 103, the variable capacitor 104, the resistors 302 and 304, and the transistor 305 and adding transistors 801 to 804 to the oscillation circuit of FIG.

  The first p-channel field effect transistor 201 has a source connected to the power supply potential node Vdd, a gate connected to the node NBN, and a drain connected to the node NAP. The first n-channel field effect transistor 202 has a source connected to the reference potential node, a gate connected to the node NBP, and a drain connected to the node NAN. The second p-channel field effect transistor 203 has a source connected to the power supply potential node Vdd, a gate connected to the node NAN, and a drain connected to the node NBP. The second n-channel field effect transistor 204 has a source connected to the reference potential node, a gate connected to the node NAP, and a drain connected to the node NBN.

  The n-channel field effect transistor 801 has a source connected to the normal input terminal D, a gate connected to the normal clock terminal CK, and a drain connected to the node NAP. The p-channel field effect transistor 802 has a source connected to the normal input terminal D, a gate connected to the inverted clock terminal CKX, and a drain connected to the node NAN.

  The n-channel field effect transistor 803 has a source connected to the inverting input terminal DX, a gate connected to the normal clock terminal CK, and a drain connected to the node NBP. In the p-channel field effect transistor 804, the source is connected to the inverting input terminal DX, the gate is connected to the inverting clock terminal CKX, and the drain is connected to the node NBN.

  The resistor 301 is connected between the nodes NAP and NAN. Resistor 302 is connected between nodes NBP and NBN. The normal output terminal OUT is connected to the node NAN. The inverting output terminal OUTX is connected to the node NBN.

  By making the driving power of the transistors 801 to 804 sufficiently larger than the driving power of the transistors 201 to 204, data in the latch circuit can be rewritten. The normal clock signal at the normal clock terminal CK and the inverted clock signal at the inverted clock terminal CKX are mutually inverted clock signals. When the normal clock signal is at a high level, the inverted clock signal is at a low level, and when the normal clock signal is at a low level, the inverted clock signal is at a high level.

  First, the write mode of the latch circuit will be described. When the normal clock terminal CK is at a high level and the inverted clock terminal CKX is at a low level, the transistors 801 to 804 are turned on, the normal input terminal D is connected to the nodes NAP and NAN, and the inverted input terminal DX is connected to the nodes NBP and NBN. Connected to. The signal at the normal input terminal D is written to the nodes NAP and NAN, and the signal at the inverted input terminal DX is written to the nodes NBP and NBN.

  The normal input signal of the normal input terminal D and the inverted input signal of the inverted input terminal DX are signals inverted from each other. The transistors 201 and 202 constitute an inverting amplifier, invert and amplify the input signals of the nodes NBP and NBN, and output them to the nodes NAP and NAN. Similarly, the transistors 203 and 204 constitute an inverting amplifier, invert and amplify the input signals of the nodes NAP and NAN, and output the signals to the nodes NBP and NBN. By the above writing, the signal at the normal output terminal OUT and the signal at the inverted output terminal OUTX are inverted from each other.

  Next, the holding mode of the latch circuit will be described. When the normal clock terminal CK is at a low level and the inverted clock terminal CKX is at a high level, the transistors 801 to 804 are turned off. As a result, the signals at the normal output terminal OUT and the inverted output terminal OUTX are held.

  In the divide-by-2 circuit of FIG. 7, a divided signal is output from the forward divided output terminal DIVOUT and the inverted divided output terminal DIVOUTX. The frequency-divided signals of the normal frequency division output terminal DIVOUT and the inverted frequency division output terminal DIVOUTX are signals that are inverted with each other, and have a frequency that is ½ of the frequency of the clock signal of the normal frequency clock terminal CK and the inverted clock terminal CKX. Have. That is, the divide-by-2 circuit receives the clock signals of the clock terminals CK and CKX, divides the clock signal by two, and outputs the divided signals from the divided output terminals DIVOUT and DIVOUTX.

  Since the input terminals D and DX of the latch circuits 701 and 702 are for inputting signals by a feedback loop, at the initial stage, both the input terminals D and DX have the same intermediate potential as in the first embodiment. Sometimes. For example, when the power supply potential node Vdd is 1.2V and the reference potential node is 0V, both the input terminals D and DX are 0.6V at the initial stage.

  As in the first embodiment, by providing the resistors 301 and 302, for example, the node NAP is 0.7V, the node NAN is 0.5V, the node NBP is 0.7V, and the node NBN is 0.5V. Then, the source-gate voltage of the p-channel field effect transistors 201 and 203 is 1.2V−0.5V = 0.7V, and the source-gate voltage of the n-channel field effect transistors 202 and 204 is 0.7V−. 0V = 0.7V. In the latch circuit of FIG. 8, the source-gate voltages of the transistors 201 to 204 are higher and the gain is higher than when the resistors 301 and 302 are not provided. In this state, it is uncertain which of the normal output terminal OUT and the inverted output terminal OUTX is at a high level, but eventually either the normal output terminal OUT or the inverted output terminal OUTX is high due to noise. Level, and the other goes low.

  As described above, since the gain of the inverting amplifier of the transistors 201 to 204 is increased, the latch circuit can hold a stable level signal even if the size of the transistors 201 to 204 is small. Further, even when the power supply voltage is low, the latch circuit can hold a stable level signal. Further, it is possible to realize a broadband latch circuit that can operate at a high operating frequency such that the nodes NAP, NAN, NBP, and NBN cannot have full amplitude. The latch circuit of this embodiment can be latched even when the input signal has a small amplitude with a low power supply voltage.

  The divide-by-2 circuit is difficult to operate when the input terminals D and DX have an intermediate potential. The divide-by-2 circuit of this embodiment can be operated with a low power supply voltage by using the latch circuit of FIG. Further, it is possible to realize a broadband divide-by-2 circuit that can operate even at a high operating frequency such that the internal node cannot have full amplitude.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1)
A first p-channel field effect transistor having a source connected to the first potential node;
A first n-channel field effect transistor having a source connected to a second potential node;
A second p having a source connected to the first potential node, a gate connected to the drain of the first n-channel field effect transistor, and a drain connected to the gate of the first n-channel field effect transistor. A channel field effect transistor;
A second n having a source connected to the second potential node, a gate connected to the drain of the first p-channel field effect transistor, and a drain connected to the gate of the first p-channel field effect transistor. A channel field effect transistor;
A first resistor connected between a drain of the first p-channel field effect transistor and a drain of the first n-channel field effect transistor;
A semiconductor circuit comprising: a second resistor connected between a drain of the second p-channel field effect transistor and a drain of the second n-channel field effect transistor.
(Appendix 2)
Furthermore, a normal output terminal for outputting an oscillation signal,
An inverting output terminal for outputting an oscillation signal having a reverse phase to the oscillation signal of the forward rotation output terminal;
An inductor connected between the normal output terminal and the inverted output terminal;
A capacitor connected between the normal output terminal and the inverted output terminal;
A third resistor connected between the drain of the first n-channel field effect transistor and the inverting output terminal;
A fourth resistor connected between the drain of the second n-channel field effect transistor and the normal output terminal;
The first resistor is connected between a drain of the first p-channel field effect transistor and the inverting output terminal;
The semiconductor circuit according to claim 1, wherein the second resistor is connected between a drain of the second p-channel field effect transistor and the normal output terminal.
(Appendix 3)
Furthermore, a normal output terminal for outputting an oscillation signal,
An inverting output terminal for outputting an oscillation signal having a reverse phase to the oscillation signal of the forward rotation output terminal;
An inductor connected between the normal output terminal and the inverted output terminal;
A capacitor connected between the normal output terminal and the inverted output terminal;
The first resistor is connected between a drain of the first p-channel field effect transistor and the inverting output terminal;
The second resistor is connected between the drain of the second p-channel field effect transistor and the normal output terminal,
The inverting output terminal is connected to a drain of the first n-channel field effect transistor;
The semiconductor circuit according to claim 1, wherein the normal output terminal is connected to a drain of the second n-channel field effect transistor.
(Appendix 4)
Furthermore, a normal output terminal for outputting an oscillation signal,
An inverting output terminal for outputting an oscillation signal having a reverse phase to the oscillation signal of the forward rotation output terminal;
An inductor connected between the normal output terminal and the inverted output terminal;
A capacitor connected between the normal output terminal and the inverted output terminal;
The first resistor is connected between a drain of the first n-channel field effect transistor and the inverting output terminal;
The second resistor is connected between a drain of the second n-channel field effect transistor and the normal output terminal,
The inverting output terminal is connected to a drain of the first p-channel field effect transistor;
The semiconductor circuit according to claim 1, wherein the normal output terminal is connected to a drain of the second p-channel field effect transistor.
(Appendix 5)
In addition, a drain is connected to an interconnection point between the source of the first n-channel field effect transistor and the source of the second n-channel field effect transistor, and the source is connected to a third potential node. 5. The semiconductor circuit according to any one of appendices 1 to 4, further comprising a channel field effect transistor.
(Appendix 6)
The semiconductor circuit according to any one of appendices 1 to 5, wherein each of the first resistor and the second resistor is configured by a field effect transistor that is turned off at the time of power-down.
(Appendix 7)
A non-inverting output terminal connected to the gate of the second p-channel field effect transistor and outputting a latched signal;
An inverting output terminal connected to a gate of the first p-channel field effect transistor and outputting a signal having a phase opposite to the output signal of the normal output terminal;
A forward rotation input terminal for inputting an input signal;
An inverting input terminal for inputting a signal having a reverse phase with respect to an input signal of the forward rotation input terminal;
A first switch for connecting the normal input terminal to a drain of the first p-channel field effect transistor and a drain of the first n-channel field effect transistor;
2. The semiconductor according to claim 1, further comprising a second switch for connecting the inverting input terminal to the drain of the second p-channel field effect transistor and the drain of the second n-channel field effect transistor. circuit.

101, 102 Inverting amplifier 103 Inductor 104 Variable capacitor 201 First p-channel field effect transistor 202 First n-channel field effect transistor 203 Second p-channel field effect transistor 204 Second n-channel field effect transistors 301 to 304 Resistance 305 n-channel field effect transistor

Claims (5)

A first p-channel field effect transistor having a source connected to the first potential node;
A first n-channel field effect transistor having a source connected to a second potential node;
A second p having a source connected to the first potential node, a gate connected to the drain of the first n-channel field effect transistor, and a drain connected to the gate of the first n-channel field effect transistor. A channel field effect transistor;
A second n having a source connected to the second potential node, a gate connected to the drain of the first p-channel field effect transistor, and a drain connected to the gate of the first p-channel field effect transistor. A channel field effect transistor;
A first resistor connected between a drain of the first p-channel field effect transistor and a drain of the first n-channel field effect transistor;
A semiconductor circuit comprising: a second resistor connected between a drain of the second p-channel field effect transistor and a drain of the second n-channel field effect transistor. Furthermore, a normal output terminal for outputting an oscillation signal,
An inverting output terminal for outputting an oscillation signal having a reverse phase to the oscillation signal of the forward rotation output terminal;
An inductor connected between the normal output terminal and the inverted output terminal;
A capacitor connected between the normal output terminal and the inverted output terminal;
A third resistor connected between the drain of the first n-channel field effect transistor and the inverting output terminal;
A fourth resistor connected between the drain of the second n-channel field effect transistor and the normal output terminal;
The first resistor is connected between a drain of the first p-channel field effect transistor and the inverting output terminal;
The semiconductor circuit according to claim 1, wherein the second resistor is connected between a drain of the second p-channel field effect transistor and the normal output terminal. Furthermore, a normal output terminal for outputting an oscillation signal,
An inverting output terminal for outputting an oscillation signal having a reverse phase to the oscillation signal of the forward rotation output terminal;
An inductor connected between the normal output terminal and the inverted output terminal;
A capacitor connected between the normal output terminal and the inverted output terminal;
The first resistor is connected between a drain of the first p-channel field effect transistor and the inverting output terminal;
The second resistor is connected between the drain of the second p-channel field effect transistor and the normal output terminal,
The inverting output terminal is connected to a drain of the first n-channel field effect transistor;
2. The semiconductor circuit according to claim 1, wherein the normal output terminal is connected to a drain of the second n-channel field effect transistor. Furthermore, a normal output terminal for outputting an oscillation signal,
An inverting output terminal for outputting an oscillation signal having a reverse phase to the oscillation signal of the forward rotation output terminal;
An inductor connected between the normal output terminal and the inverted output terminal;
A capacitor connected between the normal output terminal and the inverted output terminal;
The first resistor is connected between a drain of the first n-channel field effect transistor and the inverting output terminal;
The second resistor is connected between a drain of the second n-channel field effect transistor and the normal output terminal,
The inverting output terminal is connected to a drain of the first p-channel field effect transistor;
2. The semiconductor circuit according to claim 1, wherein the normal output terminal is connected to a drain of the second p-channel field effect transistor. A non-inverting output terminal connected to the gate of the second p-channel field effect transistor and outputting a latched signal;
An inverting output terminal connected to a gate of the first p-channel field effect transistor and outputting a signal having a phase opposite to the output signal of the normal output terminal;
A forward rotation input terminal for inputting an input signal;
An inverting input terminal for inputting a signal in reverse phase with respect to the input signal of the forward rotation input terminal;
A first switch for connecting the normal input terminal to a drain of the first p-channel field effect transistor and a drain of the first n-channel field effect transistor;
2. The second switch for connecting the inverting input terminal to the drain of the second p-channel field effect transistor and the drain of the second n-channel field effect transistor. Semiconductor circuit.

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