JP2010282284A5 - - Google Patents

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Publication number
JP2010282284A5
JP2010282284A5 JP2009133213A JP2009133213A JP2010282284A5 JP 2010282284 A5 JP2010282284 A5 JP 2010282284A5 JP 2009133213 A JP2009133213 A JP 2009133213A JP 2009133213 A JP2009133213 A JP 2009133213A JP 2010282284 A5 JP2010282284 A5 JP 2010282284A5
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JP
Japan
Prior art keywords
bus
internal memory
internal
control unit
construction data
Prior art date
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Application number
JP2009133213A
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English (en)
Japanese (ja)
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JP2010282284A (ja
JP5401700B2 (ja
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Application filed filed Critical
Priority to JP2009133213A priority Critical patent/JP5401700B2/ja
Priority claimed from JP2009133213A external-priority patent/JP5401700B2/ja
Publication of JP2010282284A publication Critical patent/JP2010282284A/ja
Publication of JP2010282284A5 publication Critical patent/JP2010282284A5/ja
Application granted granted Critical
Publication of JP5401700B2 publication Critical patent/JP5401700B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009133213A 2009-06-02 2009-06-02 マイクロコンピュータ Expired - Fee Related JP5401700B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009133213A JP5401700B2 (ja) 2009-06-02 2009-06-02 マイクロコンピュータ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009133213A JP5401700B2 (ja) 2009-06-02 2009-06-02 マイクロコンピュータ

Publications (3)

Publication Number Publication Date
JP2010282284A JP2010282284A (ja) 2010-12-16
JP2010282284A5 true JP2010282284A5 (OSRAM) 2012-04-12
JP5401700B2 JP5401700B2 (ja) 2014-01-29

Family

ID=43538982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009133213A Expired - Fee Related JP5401700B2 (ja) 2009-06-02 2009-06-02 マイクロコンピュータ

Country Status (1)

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JP (1) JP5401700B2 (OSRAM)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012158947A2 (en) 2011-05-17 2012-11-22 Altera Corporation Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device
CN108134683B (zh) * 2016-12-01 2021-06-11 腾讯科技（深圳）有限公司 一种终端及总线架构的实现方法
DE102018215881B3 (de) * 2018-09-19 2020-02-06 Siemens Aktiengesellschaft Vorrichtung und Verfahren zum Koppeln zweier Gleichstromnetze

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63214995A (ja) * 1987-03-04 1988-09-07 Ando Electric Co Ltd メモリ選択回路
JPH03263185A (ja) * 1990-03-14 1991-11-22 Hitachi Ltd 随時書込可能なインタフエース回路付きのｌｓｉ
JP3191996B2 (ja) * 1992-08-27 2001-07-23 株式会社リコー 外部メモリ制御方法
JP2001175586A (ja) * 1999-12-21 2001-06-29 Hitachi Ltd データプロセッサ及びデータ処理システム
JP2001265647A (ja) * 2000-03-17 2001-09-28 Mitsubishi Electric Corp 基板システム、基板システムにおけるメモリ制御方法および基板システムにおけるメモリ置換方法
JP2001290758A (ja) * 2000-04-10 2001-10-19 Nec Corp コンピュータシステム
JP3904493B2 (ja) * 2002-07-24 2007-04-11 株式会社ルネサステクノロジ 半導体装置
JP4453271B2 (ja) * 2003-04-25 2010-04-21 コニカミノルタホールディングス株式会社 コンピュータシステム及びメモリの接続方法
JP4892970B2 (ja) * 2005-12-27 2012-03-07 富士ゼロックス株式会社 電子回路及びプログラマブル論理デバイスの使用方法
JP2008009564A (ja) * 2006-06-27 2008-01-17 Fujitsu Ltd メモリアクセス装置、メモリアクセス方法、メモリ製造方法およびプログラム
JP4659774B2 (ja) * 2007-03-07 2011-03-30 三菱電機株式会社 電気機器
JP2008293096A (ja) * 2007-05-22 2008-12-04 Shinko Electric Ind Co Ltd メモリインタフェースおよびメモリシステム

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