JP2010278483A - Device and method for synchronizing signals - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and method for synchronizing signals, capable of efficiently detecting the synchronizing position of reception signals, even under an inferior transmission and reception environment, wherein the power of delay waves or interference waves or noise power is large. <P>SOLUTION: The signal synchronizing device 1 executes hard decision of source signals A(t) in a signal decision unit 11, outputs reception signals I(t), outputs decision error signals J(t) based on the absolute value of a difference between the amplitude of the source signals and the amplitude of the reception signals, and outputs matching signals E(t) indicating the matching degree of a reception signal sequence and a known signal sequence in a matching detection unit 12. On the basis of state signals C(t) output from a prescribed signal generation unit 13, the decision error signals J(t) and the matching signals E(t), in a signal holding part 14, holding signals P(t) indicating the time when the matching signals E(T) become maximum within a prescribed time section are output. On the basis of the holding signals P(t) and the state signals C(t), in a signal selection part 18, the synchronizing position of the reception signals I(t) is determined and synchronization detection signals S(t) are output. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a signal synchronization apparatus and a signal synchronization method used for detecting a synchronization position of a received signal.

  When a sender performs communication, an information signal in which a control signal is multiplexed may be transmitted in order to enable the receiver to identify a communication partner, to determine a communication means, and to specify the reception timing of the received signal. There is a known signal sequence as one of control signals for performing information recognition between such transmission and reception, and a pattern matching method is often used as means for identifying a signal using this known signal sequence.

  The pattern matching method is a method in which a known signal sequence is multiplexed on a transmission signal sequence in advance, and a transmission signal sequence received by a receiving apparatus (hereinafter sometimes referred to as “received signal sequence”) is checked against a known signal sequence. Or the degree of coincidence exceeds a predetermined threshold value.

  The known signal sequence is, for example, a digital signal that periodically changes two or more codes according to time, and has various uses depending on a system to be communicated. In particular, in a communication system that transmits and receives a signal in which an identification signal describing a communication method and a communication speed and an information signal to be transmitted are multiplexed, the receiver must discriminate between the identification signal and the information signal. The sender inserts a known signal sequence in the identification signal. Thus, the receiver can distinguish the identification signal from the information signal by recognizing the position of the known signal sequence inserted in the identification signal.

  When detecting the known signal sequence from the identification signal, if the signal power of the desired signal among the received signals is sufficiently large compared to the noise power, the received signal sequence and the known signal sequence can be relatively easily obtained by the pattern matching method. Can be verified. However, in a weak electric field environment, since the electric field level of the received signal is very small, the signal power of the desired wave is only about the same as or lower than the noise power. Therefore, even if the known signal sequence is inserted into the transmission signal sequence, the known signal sequence is buried in the noise of the received signal, and the received signal sequence, which is the received transmission signal sequence, is correctly collated with the known signal sequence. There are many cases where this is not possible.

  Also, in a multipath environment where there is a delayed wave, the signal power of the delayed wave is large. For example, Non-Patent Document 1 quantitatively shows the influence.

  Therefore, in a multipath environment where there is a delayed wave, there is a case where the received signal sequence and the known signal sequence cannot be correctly matched in the pattern matching method even when the received power is relatively large.

  For example, Patent Document 1 discloses a technique for re-synchronizing when a matching between a received signal sequence and a known signal sequence in the pattern matching method is erroneous due to weak electric field or multipath interference. Is disclosed.

  Further, for example, in Patent Document 2, the number of protection stages is obtained by adaptively changing the number of synchronizations necessary for establishing synchronization and the number of asynchronouss necessary for recognizing that the synchronization has been lost. A technique for optimizing the above and efficiently recognizing a synchronous state and an asynchronous state is disclosed.

  Further, for example, in Patent Document 3, the number of synchronizations necessary for establishing synchronization and the number of asynchronouss necessary for recognizing that synchronization has been lost are set by the front protection circuit and the rear protection circuit, and continued. A technique for reducing the case of an erroneous synchronization state is disclosed.

  Further, as a technique for efficiently collating a received signal sequence and a known signal sequence in a pattern matching method, there is a technique for providing an allowable number of bit errors when collating. In this technique, for example, when the number of bits of a known signal sequence to be matched is A bits, if the transmission path environment is good, synchronization is established when all the A bits match, and the transmission path environment is poor. For example, the synchronization is determined when the B bit (B <A) of the A bits matches. For example, Patent Document 4 discloses a technique for keeping the synchronization state stable by adaptively changing the number of allowable bit errors when collating according to the received electric field strength.

JP 2004-193758 A (FIG. 1) JP 2007-258792 (FIG. 3) Japanese Patent No. 3322599 Japanese Patent No. 3182312

Yoshio Karasawa, “Radio wave propagation basics for digital mobile communications”, Corona, March 2003, p. 149-154

  As described above, Patent Document 1 discloses a technique for re-synchronizing when collation is incorrect, but a technique for reducing errors when collating a received signal sequence with a known signal sequence. Is not disclosed.

  Patent Document 2 discloses a technique for optimizing the number of protection stages in order to efficiently recognize the synchronous state and the asynchronous state. However, the synchronization establishment timing is delayed as the number of protection circuit stages increases. There is a problem.

  Further, in the technology disclosed in Patent Document 3, the front protection circuit and the rear protection circuit are used. However, if the rear protection circuit is applied when synchronization is established in a poor reception environment, synchronization is achieved for a long time. There is a possibility that the state that cannot be taken will continue.

  As described above, since the signal power of the delayed wave is large in the multipath environment where the delayed wave exists, even if the signal power of the desired wave among the received signals is relatively large with respect to the noise power, The received signal is distorted. Therefore, as in the technique disclosed in Patent Document 4, if the allowable number of bit errors is set in consideration of the large amplitude and power of the received signal, the received signal sequence and the known signal sequence in the pattern matching method are set. In some cases, it is not possible to verify correctly.

  In a mobile reception environment, the phase of the received signal changes from time to time without depending on the received power due to the Doppler frequency shift, so that many signal errors occur even when the received power is relatively large. There is a case. If the allowable number of bit errors is set small in such a reception environment, there is a case where normal collation cannot be performed as in the multipath environment.

  Therefore, it is not sufficient to determine the allowable number of bit errors when matching is based on the received power or the received electric field as in the technique disclosed in Patent Document 4.

  Further, in the verification of the received signal sequence and the known signal sequence in the pattern matching method, there are cases where the verification can be performed at a plurality of locations due to the influence of the signal error due to the variation of the received power. In this case, it is impossible to determine which position among the plurality of collation positions is an accurate collation position or whether any position is collated in error. This problem cannot be solved by using any of the techniques disclosed in Patent Documents 1 to 4 described above.

  From the above, even in a poor transmission / reception environment with large delay wave or interference wave power or noise power, a known signal sequence contained in the received signal is efficiently detected using the pattern matching method, Therefore, a mechanism for correctly reproducing the received signal is required.

  An object of the present invention is to provide a signal synchronization apparatus and a signal synchronization method capable of efficiently detecting the synchronization position of a received signal even in a poor transmission / reception environment with a large delay wave or interference wave power or noise power. is there.

  The signal synchronizer of the present invention receives from an original signal in a receiving apparatus that receives and communicates an original signal in which a known signal sequence composed of predetermined known signals is repeatedly inserted once or twice or more continuously. A signal synchronization device for detecting a synchronization position of an obtained reception signal, wherein the original signal is hard-decided and the reception signal is output, and the difference between the amplitude of the original signal and the amplitude of the reception signal A signal determination unit that outputs a value calculated based on an absolute value as a determination error signal; a reception signal sequence configured to hold the known signal sequence in advance, and is configured by the reception signal obtained within a predetermined time interval; and A coincidence detection unit that outputs a coincidence signal that represents the degree of coincidence with a known signal series, and a valid signal that represents a valid state and an invalid signal that represents an invalid state as a state signal that represents the predetermined time interval Represents a time when the match signal is maximized within the predetermined time interval based on the predetermined signal generation unit that alternately generates and outputs the determination error signal, the match signal, and the status signal. A signal holding unit that outputs a holding signal; a signal selection unit that determines a synchronization position of the reception signal based on the holding signal and the state signal; and outputs a synchronization detection signal that represents the synchronization position of the reception signal; It is characterized by providing.

  In the signal synchronization method of the present invention, the original signal in the receiving apparatus that performs communication by receiving an original signal in which a known signal sequence composed of predetermined known signals is repeatedly inserted once or twice or more continuously is received. A signal synchronization method for detecting a synchronization position of a received signal obtained from a known signal holding step for holding the known signal sequence in advance, and making a hard decision on the original signal and outputting the received signal, A signal determination step for outputting, as a determination error signal, a value calculated based on the absolute value of the difference between the amplitude of the original signal and the amplitude of the reception signal, and the reception signal obtained within a predetermined time interval. A match detection step for outputting a match signal representing the degree of coincidence between the received signal sequence and the known signal sequence held in the known signal holding step, and a state representing the predetermined time interval As a signal, a predetermined signal generation step for alternately generating and outputting a valid signal indicating the valid state and an invalid signal indicating the invalid state, the determination error signal, the match signal, and the state signal, And a signal holding step for outputting a holding signal indicating a time when the matching signal becomes maximum within the predetermined time interval, and synchronization of the received signal based on the holding signal and the state signal. A signal selection step of determining a position and outputting a synchronization detection signal representing a synchronization position of the received signal.

  According to the signal synchronizer of the present invention, the signal synchronizer includes the signal determination unit, the match detection unit, the predetermined signal generation unit, the signal holding unit, and the signal selection unit. The signal determination unit makes a hard decision on the original signal into which the known signal sequence is inserted and outputs a reception signal, and also outputs a determination error signal. Further, the match detection unit outputs a match signal representing the degree of match between the received signal sequence and the known signal sequence obtained within a predetermined time interval. A valid signal and an invalid signal are alternately generated and output by the predetermined signal generator as a state signal representing the predetermined time interval. Based on the status signal, the determination error signal, and the match signal, the signal holding unit outputs a hold signal that indicates the time when the match signal becomes maximum within the predetermined time interval. Based on the hold signal and the status signal, the signal selection unit determines the synchronization position of the received signal and outputs a synchronization detection signal representing the synchronization position.

  Since the determination error signal is a value calculated based on the absolute value of the difference between the amplitude of the original signal and the amplitude of the received signal, it can be used as a measure of the reliability of the received signal. Since a holding signal is output based on the determination error signal, the match signal, and the status signal, for example, when a plurality of times at which the match signal is maximum are detected, the most reliable received signal among those times It is possible to output the time detected based on the hold signal. Since the synchronization position of the received signal is determined based on the hold signal and the status signal and the synchronization detection signal is output, the most reliable matching position among the matching positions of the received signal sequence and the known signal sequence Can be determined as the synchronization position of the received signal.

  As a result, the synchronization position of the received signal can be efficiently detected without depending on the nature of the received signal, such as amplitude and power. Therefore, it is possible to efficiently detect the synchronization position of the received signal even in a poor transmission / reception environment where the power of the delay wave or the interference wave or the noise power is large.

  According to the signal synchronization method of the present invention, the known signal sequence is held in advance in the known signal holding step, and the original signal into which the known signal sequence is inserted is hard-decided in the signal determining step, and the received signal is output. A determination error signal is output. In the coincidence detection step, a coincidence signal representing the degree of coincidence between the received signal sequence and the known signal sequence obtained within a predetermined time interval is output. As a status signal representing this predetermined time interval, a valid signal and an invalid signal are alternately generated and output in a predetermined signal generation step. Based on the state signal, the determination error signal, and the match signal, a holding signal representing the time when the match signal becomes maximum within the predetermined time interval is output in the signal holding step. Based on the hold signal and the status signal, the synchronization position of the received signal is determined in the signal selection step, and a synchronization detection signal representing the synchronization position is output.

  Since the determination error signal is a value calculated based on the absolute value of the difference between the amplitude of the original signal and the amplitude of the received signal, it can be used as a measure of the reliability of the received signal. Since a holding signal is output based on the determination error signal, the match signal, and the status signal, for example, when a plurality of times at which the match signal is maximum are detected, the most reliable received signal among those times It is possible to output the time detected based on the hold signal. Since the synchronization position of the received signal is determined based on the hold signal and the status signal and the synchronization detection signal is output, the most reliable matching position among the matching positions of the received signal sequence and the known signal sequence Can be determined as the synchronization position of the received signal.

  As a result, the synchronization position of the received signal can be efficiently detected without depending on the nature of the received signal, such as amplitude and power. Therefore, it is possible to efficiently detect the synchronization position of the received signal even in a poor transmission / reception environment where the power of the delay wave or the interference wave or the noise power is large.

It is a block diagram which shows the structure of the signal synchronizer 1 which is the 1st Embodiment of this invention. 3 is a block diagram illustrating a configuration of a signal determination unit 11. FIG. 3 is a block diagram illustrating a configuration of a match detection unit 12. FIG. 3 is a block diagram illustrating a configuration of a comparison unit 33. FIG. 3 is a block diagram showing a configuration of a determiner 34. FIG. FIG. 7 is a block diagram showing a specific configuration of the match detection unit 12 when the number of bits X of the received signal sequence F ₁ (t) is 7 and the predetermined value in the determiner 34 is 8. 3 is a flowchart showing an operation procedure of a count value update unit 16. 3 is a flowchart showing an operation procedure of a time update unit 15. 5 is a flowchart showing an operation procedure of a holding value update unit 17. It is a figure which shows an example of the coincidence signal E (t), the state signal C (t), the determination error signal J (t), the internal signal of the signal holding unit 14, and the time relationship between these signals. 3 is a block diagram illustrating a configuration of a signal selection unit 18. FIG. 4 is a timing chart showing the operation timing of the signal selector 18. It is a graph which shows an example of the relationship between SN ratio (Signal to Noise ratio) which is a ratio with respect to noise power of received signal power, and a synchronization success rate. It is a flowchart which shows the operation | movement procedure of the time update part 15 of the signal holding | maintenance part 14 in the 2nd Embodiment of this invention. It is a block diagram which shows the structure of 18 A of signal selection parts of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of 34 A of determination devices which comprise the coincidence detection part 12 in the 3rd Embodiment of this invention. It is a timing chart which shows the output timing of the coincidence signal E (t) in the determination device 34 of the 1st Embodiment of this invention. It is a timing chart which shows the output timing of the coincidence signal E (t) in the determination device 34A of the 3rd Embodiment of this invention.

<First Embodiment>
FIG. 1 is a block diagram showing a configuration of a signal synchronizer 1 according to the first embodiment of the present invention. The signal synchronization apparatus 1 according to the present embodiment detects a known signal sequence from a received signal including a signal in which the known signal sequence is repeatedly inserted once or twice or more, and detects a synchronization position of the received signal. . The signal synchronization apparatus 1 includes an input terminal 10, a signal determination unit 11, a match detection unit 12, a predetermined signal generation unit 13, a signal holding unit 14, a signal selection unit 18, and an output terminal 19. The signal holding unit 14 includes a time update unit 15, a count value update unit 16, and a hold value update unit 17.

  The signal determination unit 11 makes a hard decision on the original signal A (t) input from the input terminal 10, outputs the hard decision signal as a received signal I (t), and gives it to the match detection unit 12. The signal determination unit 11 obtains a value obtained by averaging a value obtained by normalizing the absolute value of the difference between the amplitude of the original signal A (t) and the amplitude of the reception signal I (t) with a predetermined threshold value a predetermined number of times. This is output as the determination error signal J (t) and given to the hold value updating unit 17 of the signal holding unit 14. The operation of outputting the reception signal I (t) and the determination error signal J (t) by the signal determination unit 11 in this way corresponds to a signal determination step.

  FIG. 2 is a block diagram illustrating a configuration of the signal determination unit 11. The signal determination unit 11 includes a threshold generation unit 21, a threshold determination unit 22, a normalization unit 23, an averaging unit 24, and an output adjustment unit 25. The threshold determination unit 22 and the output adjustment unit 25 correspond to a reception signal output unit, and the normalization unit 23 and the averaging unit 24 correspond to an error signal output unit. The original signal A (t) input from the input terminal 10 to the signal determination unit 11 is given to the threshold determination unit 22. The threshold generation unit 21 generates and outputs a predetermined threshold (hereinafter sometimes referred to as “signal threshold”). The signal threshold output from the threshold generation unit 21 is given to the threshold determination unit 22 and the normalization unit 23.

  When the original signal A (t) exceeds the signal threshold, the threshold determination unit 22 outputs a predetermined first state value as the original reception signal I ′ (t), and the original signal A (t) is equal to or less than the signal threshold. In this case, the predetermined second state value is output as the original received signal I ′ (t). The original received signal I ′ (t) output from the threshold determination unit 22 is given to the output adjustment unit 25. In addition, when the original signal A (t) exceeds the signal threshold, the threshold determination unit 22 outputs the absolute value of the difference between the original signal A (t) and the first state value as the original determination error signal J ′ (t). When the original signal A (t) is less than or equal to the signal threshold, the absolute value of the difference between the original signal A (t) and the second state value is output as the original determination error signal J ′ (t). The original determination error signal J ′ (t) output from the threshold determination unit 22 is given to the normalization unit 23.

  The normalization unit 23 outputs, as a normalization error signal, a value obtained by dividing the original determination error signal J ′ (t) given from the threshold judgment unit 22 by the signal threshold given from the threshold generation unit 21. To give. The averaging unit 24 outputs a value obtained by adding the normalized error signal value given from the normalizing unit 23 a predetermined number of times as the determination error signal J (t). Adding the value of the normalized error signal given from the normalizing unit 23 a predetermined number of times is equivalent to averaging the value of the normalized error signal. The averaging unit 24 may output a value obtained by averaging the values of the normalized error signal output from the normalizing unit 23 in a predetermined time interval as the determination error signal J (t).

  The output adjustment unit 25 outputs a signal obtained by delaying the original reception signal I ′ (t) output from the threshold determination unit 22 by a predetermined time as the reception signal I (t). The predetermined time here is preferably equal to the time required when the averaging unit 24 performs the averaging.

  With the configuration described above, the signal determination unit 11 converts the original signal A (t) into a binary value and outputs it as a received signal I (t), and as an index representing the reliability at the time of conversion. The determination error signal J (t) can be output.

  For example, when the first state value is 1, the second state value is 0, the signal threshold is 0.5, and the averaging unit 24 performs averaging once, time t = 1 If the value of the original signal A (t) at 0.9 is 0.9 (A (1) = 0.9), the value of the received signal I (t) is 1, and the value of the determination error signal J (t) is 0.1 / 0.5 = 0.2.

  For example, when the first state value is 1, the second state value is 0, the signal threshold is 0.5, and the averaging unit 24 performs averaging once, the time t = If the value of the original signal A (t) at 1 is 0.4 (A (1) = 0.4), the value of the received signal I (t) is 0, and the value of the determination error signal J (t) is 0.4 / 0.5 = 0.8.

  As described above, when the value of the original signal A (t) at time t = 1 is 0.9 (A (1) = 0.9), the value of the original signal A (t) is regarded as 1. When the received signal I (t) is output and when the value of the original signal A (t) at time t = 1 is 0.4 (A (1) = 0.4), the original signal A ( It is clear that the former is more reliable than the latter when the value of t) is regarded as 0 and output as the received signal I (t). In the former case, the value of the determination error signal J (t) is 0.2, and in the latter case, the value of the determination error signal J (t) is 0.8. Therefore, the value of the determination error signal J (t) can be used as a measure of the reliability of the reception signal I (t). The smaller the value of the determination error signal J (t), the smaller the reception signal. The reliability of I (t) will be high.

  Returning to FIG. 1, the match detection unit 12 compares the received signal sequence configured by the received signal I (t), which is given from the signal determination unit 11 and obtained within a predetermined time interval, with a predetermined known signal sequence. Then, the comparison result is determined, and a coincidence signal E (t) representing the degree of coincidence between the received signal sequence and the known signal sequence is output. The match signal E (t) output from the match detection unit 12 is given to the signal holding unit 14, specifically, the count value updating unit 16 and the holding value updating unit 17 of the signal holding unit 14. The operation of outputting the match signal E (t) by the match detection unit 12 in this way corresponds to a match detection step.

  FIG. 3 is a block diagram illustrating a configuration of the match detection unit 12. The match detection unit 12 includes a conversion unit 31, a sequence generation unit 32, a comparison unit 33, and a determination unit 34. In the match detection unit 12, the reception signal I (t) given from the signal determination unit 11 is given to the conversion unit 31.

The converter 31 performs signal conversion for simultaneously processing a sequence of received signals I (t) obtained within a predetermined time interval (hereinafter referred to as “received signal sequence”). Specifically, the conversion unit 31 simultaneously outputs X (X is a positive integer) -bit received signal sequence R ₁ (t) to R _X (t) obtained within a predetermined period. That is, the conversion unit 31 converts the received signals obtained within a predetermined time interval so that they can be processed at the same time, and receives the received signal sequences R ₁ (t) to R _X as converted signal sequences composed of the obtained converted signals. (T) is output. Hereinafter, the X-bit received signal series R ₁ (t) to R _X (t) may be collectively referred to as “F ₁ (t)”. The received signal sequence F ₁ (t) output from the conversion unit 31 is given to the comparison unit 33.

  The sequence generator 32 holds in advance a known signal sequence included in the original signal A (t) and outputs it. The operation of holding the known signal sequence in advance by the sequence generator 32 in this way corresponds to a known signal holding step.

Specifically, the sequence generation unit 32 generates a predetermined known signal sequence corresponding to each reception signal R ₁ (t) to R _X (t) of the reception signal sequence F ₁ (t) converted by the conversion unit 31. Generate and output at the same time. For example, when X-bit received signal sequences R ₁ (t) to R _X (t) are output from the converting unit 31 as described above, the sequence generating unit 32 uses the X-bit known signal sequence B ₁ (t). ~ B _X (t) is output simultaneously. Hereinafter, the X-bit known signal series B ₁ (t) to B _X (t) may be collectively referred to as “F ₂ (t)”. The known signal sequence F ₂ (t) output from the sequence generator 32 is given to the comparator 33.

The comparison unit 33 compares the received signal sequence F ₁ (t) given from the conversion unit 31 with the known signal sequence F ₂ (t) given from the sequence generation unit 32 in 1-bit units, and based on the comparison result The number of bits having different signal values (hereinafter sometimes referred to as “different number of bits”) is output. The number of different bits output from the comparison unit 33 is given to the determiner 34.

FIG. 4 is a block diagram illustrating a configuration of the comparison unit 33. The comparison unit 33 includes a plurality of calculation units 41 and a processing unit 42. In the comparison unit 33, the signal F ₁ (t) that is the received signal sequence R _W (t) (1 ≦ W ≦ X) given from the conversion unit 31 and the known signal sequence B _W (t) given from the sequence generation unit 32. ) (XOR) with the signal F ₂ (t) satisfying (1 ≦ W ≦ X) is calculated in the calculation unit 41. The calculation unit 41 is provided with a number equal to or greater than the number of bits X of the received signal sequence F ₁ (t) given from the conversion unit 31. Then, calculation results in each calculation unit 41, that is, X types of calculation results obtained by the plurality of calculation units 41 are given to the processing unit 42. The processing unit 42 outputs a value obtained by adding the calculation results given from the calculation unit 41 as the number of different bits. The number of different bits output from the processing unit 42 is output from the comparison unit 33 and given to the determination unit 34.

FIG. 5 is a block diagram showing a configuration of the determiner 34. The determiner 34 includes a subtractor 51 and a predetermined value storage unit 52. The number of different bits given from the comparator 33 to the determiner 34 is given to the subtractor 51. The predetermined value storage unit 52 stores a predetermined value (hereinafter sometimes referred to as “determination reference value”) as a reference value used for determination. The subtractor 51 outputs a value obtained by subtracting the number of different bits, which is an output value from the comparison unit 33, from the determination reference value stored in the predetermined value storage unit 52 as a match signal E (t). At this time, it is desirable that the determination reference value, which is a predetermined value, be set to a value equal to or greater than the number of bits X of the received signal sequence F ₁ (t) output from the conversion unit 31. The match signal E (t) output from the determiner 34 is output from the match detection unit 12 and is provided to the signal holding unit 14.

Next, the bit number X of the received signal sequence F ₁ (t) obtained within a predetermined period is set to 7, and the determination reference value that is a predetermined value stored in the predetermined value storage unit 52 of the determination unit 34 is set to 8. A specific operation of the match detection unit 12 will be described. FIG. 6 is a block diagram showing a specific configuration of the match detection unit 12 when the number of bits X of the received signal sequence F ₁ (t) is 7 and the predetermined value in the determiner 34 is 8.

For example, the signal of the received signal sequence F ₁ (t) output from the conversion unit 31 is F ₁ (t) = {1, 0, 1, 1, 0, 1, 0}, and is output from the sequence generation unit 32. Consider the case where the signal of the known signal sequence F ₂ (t) to be performed is F ₂ (t) = {1, 1, 1, 0, 0, 1, 0}. In this case, the comparison unit 33 uses each signal value of the received signal sequence F ₁ (t) output from the conversion unit 31 and each signal value of the known signal sequence F ₂ (t) output from the sequence generation unit 32. In comparison, it is determined that the new signal value of the received signal sequence F ₁ (t) and the signal value of the known signal sequence F ₂ (t) are different between the second bit and the fourth bit from the head. The number of bits, that is, “2” is output as the number of different bits. The determiner 34 subtracts the value “2” of the number of different bits that is the output result of the comparison unit 33 from the determination reference value “8” that is a predetermined value stored in the predetermined value storage unit 52, and the subtraction result “6” is output as the match signal E (t).

  Considering similarly, for example, if the output result of the comparison unit 33 is “3”, “3” that is the output result of the comparison unit 33 is subtracted from the predetermined value “8” stored in the predetermined value storage unit 52. As a result, E (t) = 5. If the output result of the comparison unit 33 is “6”, “6” that is the output result of the comparison unit 33 is subtracted from the predetermined value “8” stored in the predetermined value storage unit 52 to obtain E (T) = 2.

As described above, the value of the match signal E (t) includes the received signal sequence F ₁ (t) that is the output result of the conversion unit 31, and the known signal sequence F ₂ (t) that is the output result of the sequence generation unit 32. The higher the degree of coincidence, the smaller the value. Therefore, the coincidence signal E (t) indicates the degree of coincidence between the received signal sequence F ₁ (t) that is the output result of the conversion unit 31 and the known signal sequence F ₂ (t) that is the output result of the sequence generation unit 32. It can be used as an index to represent.

  Returning to FIG. 1, the predetermined signal generation unit 13 performs predetermined signal management (hereinafter referred to as “the state management of the valid state and the invalid state” required for controlling the operations of the signal holding unit 14 and the signal selection unit 18. It may be referred to as a “status signal”) and output. Specifically, the predetermined signal generator 13 alternately generates a valid signal indicating the valid state and an invalid signal indicating the invalid state, and sets the generated signal, that is, the valid signal or the invalid signal. Output as signal C (t). More specifically, the predetermined signal generation unit 13 outputs a valid signal or an invalid signal as a state signal C (t) that defines the predetermined time interval in which the received signal sequence is obtained. The state signal C (t) output from the predetermined signal generation unit 13 is given to the signal holding unit 14 and the signal selection unit 18. The operation of outputting the state signal C (t) by the predetermined signal generator 13 in this way corresponds to a predetermined signal generation step.

  The signal holding unit 14 includes a determination error signal J (t) given from the signal decision unit 11, a match signal E (t) given from the match detection unit 12, and a state signal C (t) given from the predetermined signal generation unit 13. ), A holding signal P (t) representing the time when the matching signal becomes maximum within a predetermined time interval in which the above-described received signal sequence is obtained is output. The operation of outputting the holding signal P (t) by the signal holding unit 14 in this way corresponds to a signal holding step.

  As described above, the signal holding unit 14 includes the time update unit 15, the count value update unit 16, and the hold value update unit 17. The state signal C (t) given from the predetermined signal generation unit 13 to the signal holding unit 14 is given to the time updating unit 15, the count value updating unit 16, and the holding value updating unit 17, respectively. The match signal E (t) given from the match detection unit 12 to the signal holding unit 14 is given to the count value update unit 16 and the hold value update unit 17, respectively.

  The time updating unit 15 outputs a signal representing an effective elapsed time, which is an elapsed time from the time when the effective state is reached, in accordance with the state signal C (t) given from the predetermined signal generating unit 13. The time update unit 15 provides the hold value update unit 17 with a signal representing the output valid elapsed time. More specifically, the time update unit 15 is activated when the invalid state changes to the valid state, that is, when the state signal C (t) given from the predetermined signal generation unit 13 changes from the invalid signal to the valid signal. A signal that initializes the time, measures the elapsed time from the time point when the state signal C (t) changes from the valid signal to the invalid signal, and represents the valid elapsed time with the measured value as the valid elapsed time. Is output. At this time, the initialization value of the effective elapsed time is preferably “1”.

  The count value update unit 16 holds, as a count value, the maximum value of the match signal E (t) output within a predetermined time interval in which the above-described received signal sequence is obtained. The count value update unit 16 converts the match signal E (t) given from the match detection unit 12, the status signal C (t) given from the predetermined signal generation unit 13, and the count value output and fed back previously. Based on this, the count value is maintained or updated and output. The count value update unit 16 feeds back the output count value to itself and supplies it to the hold value update unit 17.

  More specifically, the count value update unit 16 changes the state from the invalid state to the valid state, that is, when the state signal C (t) given from the predetermined signal generation unit 13 changes from the invalid signal to the valid signal. When the count value of the time is the value of the coincidence signal E (t) and the state is invalid, that is, when the state signal C (t) is an invalid signal, the following operations (A1) and (A2) are performed.

  (A1) When the match signal E (t) input at the current time is larger than the count value at the current time, the count value at the next time is set as the value of the match signal E (t).

  (A2) When the match signal E (t) input at the current time is equal to or less than the count value at the current time, the count value at the next time is set as the count value at the current time.

  The interval between the current time and the next time is preferably an interval obtained by multiplying the reciprocal of the operating frequency at which the signal holding unit 14 operates by an integer.

  The hold value update unit 17 holds the time when the match signal E (t) becomes maximum within a predetermined time interval in which the above-described received signal sequence is obtained as a hold value. When the state signal C (t) given from the predetermined signal generator 13 is a valid signal, the hold value update unit 17 updates the hold value after outputting the hold value, and the state signal C (t) is invalid. In the case of a signal, based on the determination error signal J (t) given from the signal decision unit 11, the match signal E (t) given from the match detection unit 12, and the count value given from the count value update unit 16. , Maintain or update the hold value.

  Specifically, the hold value update unit 17 changes the hold value to the hold signal P (t) when the invalid state changes to the valid state, that is, when the state signal C (t) changes from the invalid signal to the valid signal. As a result, the hold value at the next time is set as the value of the effective elapsed time at the next time, and the error hold value at the next time is set as the value of the determination error signal J (t) at the next time. In addition, when the status signal C (t) is an invalid signal, the hold value update unit 17 performs the operations shown in the following (B1) to (B3).

  (B1) When the match signal E (t) input at the current time is larger than the count value at the current time, the hold value at the next time is set as the value of the effective elapsed time at the next time, and the error hold value at the next time is set as the next The value of the determination error signal J (t) at the time is assumed.

(B2) When the match signal E (t) input at the current time is equal to the count value at the current time,
(B21) If the error hold value at the current time is larger than the value of the determination error signal J (t) at the current time, the hold value at the next time is set as the value of the effective elapsed time at the next time, and the error hold value at the next time is set to the next The value of the determination error signal J (t) at time is
(B22) If the error hold value at the current time is equal to or less than the determination error signal J (t) at the current time, the hold value at the next time is set as the hold value at the current time.

  (B3) If the match signal E (t) input at the current time is smaller than the count value at the current time, the held value at the next time is set as the held value at the current time.

  The interval between the current time and the next time is preferably an interval obtained by multiplying the reciprocal of the operating frequency at which the signal holding unit 14 operates by an integer.

  FIG. 7 is a flowchart showing an operation procedure of the count value update unit 16. FIG. 8 is a flowchart showing an operation procedure of the time update unit 15. FIG. 9 is a flowchart showing an operation procedure of the hold value update unit 17. FIG. 10 is a diagram illustrating an example of the match signal E (t), the state signal C (t), the determination error signal J (t), the internal signal of the signal holding unit 14, and the time relationship between these signals. In this embodiment, the current time is t, the next time is t + 1, the effective elapsed time at the current time is INT (t), the held value at the current time is KEP (t), the count value at the current time is CNT (t), The error holding value at the current time is referred to as EAV (t).

  The processing of each step in the flowchart shown in FIG. 7 is processed by the count value update unit 16. The processing of the flowchart shown in FIG. 7 is started when the match signal E (t) is given from the match detection unit 12 and the state signal C (t) is given from the predetermined signal generation unit 13, and the process proceeds to step a1.

  In step a1, the count value updating unit 16 determines whether or not the status signal C (t) at the current time is an invalid signal, and if it is determined to be an invalid signal, the process proceeds to step a2 and is not an invalid signal. In other words, if it is determined that the signal is a valid signal, the process proceeds to step a3.

  In step a2, the count value update unit 16 determines whether the match signal E (t) at the current time is less than the count value CNT (t) at the current time (E (t) <CNT (t)). When it is determined that the match signal E (t) is less than the count value CNT (t), all processing procedures are terminated, and the E match signal (t) is equal to or greater than the count value CNT (t) (E (t) ≧ CNT ( If it is determined that t)), the process proceeds to step a3.

  In step a3, the count value update unit 16 sets the match signal E (t) at the current time as the count value CNT (t + 1) at the next time, and then ends all processing procedures.

  The processing of each step in the flowchart shown in FIG. The process of the flowchart shown in FIG. 8 is started when the state signal C (t) is given from the predetermined signal generator 13, and the process proceeds to step b1.

  In step b1, the time updating unit 15 determines whether or not the status signal C (t) at the current time is an invalid signal, and if it is determined to be an invalid signal, the time update unit 15 proceeds to step b2 and is not an invalid signal. If it is determined that it is a valid signal, the process proceeds to step b3.

  In step b2, the time update unit 15 updates the valid elapsed time INT (t + 1) at the next time, that is, continuously measures the elapsed time from the time when the state signal C (t) changes from the valid signal to the invalid signal. Then, the measured value is set as the effective elapsed time INT (t + 1) at the next time, and then all processing procedures are terminated. In step b3, the time update unit 15 sets the effective elapsed time INT (t + 1) at the next time to “1” and ends all processing procedures.

  Each step in the flowchart shown in FIG. 9 is processed by the hold value update unit 17. 9, the determination error signal J (t) is given from the signal decision unit 11, the match signal E (t) is given from the match detection unit 12, and the state signal C ( t), a valid elapsed time INT (t) is given from the time update unit 15, and a count value CNT (t) is given from the count value update unit 16, and the process proceeds to step c1.

  In step c1, the holding value update unit 17 determines whether or not the status signal C (t) is an invalid signal. If it is determined that the status signal is an invalid signal, the process proceeds to step c2 and is not an invalid signal. If it is determined that the signal is a valid signal, the process proceeds to step c4.

  In step c2, the hold value update unit 17 determines whether or not the match signal E (t) at the current time matches the count value CNT (t) at the current time (E (t) = CNT (t)). If it is determined that the match signal E (t) and the count value CNT (t) match, the process proceeds to step c3. If it is determined that the match signal E (t) and the count value CNT (t) do not match, the process proceeds to step c5. Transition.

  In step c3, the hold value update unit 17 determines whether or not the determination error signal J (t) at the current time is less than the error hold value EAV (t) at the current time (J (t) <EAV (t)). If it is determined that the determination error signal J (t) is less than the error holding value EAV (t), the process proceeds to step c6, and the determination error signal J (t) is equal to or greater than the error holding value EAV (t) (J (t ) ≧ EAV (t)), the process proceeds to step c8.

  In step c4, the hold value update unit 17 outputs the hold value KEP (t) at the current time, and proceeds to step c6. In step c5, the hold value update unit 17 determines whether or not the match signal E (t) at the current time is larger than the count value CNT (t) at the current time (E (t)> CNT (t)). If the match signal E (t) is determined to be greater than the count value CNT (t), the process proceeds to step c6, where the match signal E (t) is not greater than the count value CNT (t). If it is determined that (t) is equal to or less than the count value CNT (t) (E (t) ≦ CNT (t)), the process proceeds to step c7.

  In step c6, the hold value update unit 17 sets the effective elapsed time INT (t) at the current time as the hold value KEP (t + 1) at the next time, and proceeds to step c7. In step c7, the determination error signal J (t) at the current time is set to the error holding value EAV (t + 1) at the next time, and the process proceeds to step c8. In step c8, the hold value update unit 17 updates the time t to the next time t + 1, and then ends all processing procedures.

  For example, when the match signal E (t), the state signal C (t), and the determination error signal J (t) are given to the signal holding unit 14 in a time relationship as shown in FIG. The signal changes.

  First, at time t = 3, the signal of the signal holding unit 14 changes as in the following (a) to (f). Here, it demonstrates with the operation | movement of the signal holding | maintenance part 14 in the time t = 3.

  (A) Since the state signal C (t) is an invalid signal and is in an invalid state, the time update unit 15 shifts from step b1 to step b2 in FIG. 8 and the valid progress at t = 4, which is the next time. The time INT (t + 1) is updated to “4”, and the processing procedure ends. The count value updating unit 16 proceeds from step a1 in FIG. 7 to step a2, and the hold value updating unit 17 proceeds from step c1 to step c2 in FIG.

  (B) Since the match signal E (t) = 2 and the count value CNT (t) = 1, E (3)> CNT (3), and the count value update unit 16 performs steps a2 to a3 in FIG. The holding value update unit 17 proceeds from step c2 to step c5 and step c6 in FIG.

  (C) In step c6 of FIG. 9, the hold value update unit 17 changes the hold value KEP (t + 1) at t = 4, which is the next time, to the effective elapsed time INT (t) at t = 3, which is the current time. Value "3" and the process proceeds to step c7.

  (D) In step a3 of FIG. 7, the count value updating unit 16 uses the count value CNT (t + 1) at the next time t = 4 as the match signal E (t) at the current time t = 3. The value “2” is set and the processing procedure is terminated.

  (E) In step c7 of FIG. 9, the hold value update unit 17 uses the error hold value EAV (t + 1) at t = 4, which is the next time, as the determination error signal J (t at t = 3, which is the current time. ) Value “0.5”, and the process proceeds to step c8.

  (F) In step c8 of FIG. 9, the hold value update unit 17 updates the time from t = 3 to t = 4, and ends the processing procedure.

  Next, a change in the signal of the signal holding unit 14 at time t = 4 will be described.

  (A) Since the state signal C (t) is an invalid signal and is in an invalid state, the valid elapsed time INT (t) at t = 5 is set to “5” by the time update unit 15 in step b2 of FIG. It becomes.

  (B) Since the coincidence signal E (t) = 3 and the count value CNT (t) = 2, E (4)> CNT (4), and the count value update unit 16 performs steps a2 to a3 in FIG. The held value update unit 17 proceeds from step c2 in FIG. 9 to steps c5 and c6.

  (C) In step c6 of FIG. 9, the hold value update unit 17 sets the hold value KEP (t) at t = 5 to “4”, which is the effective elapsed time INT (t) at t = 4.

  (D) In step c7 of FIG. 9, the hold value update unit 17 causes the error hold value EAV (t) at t = 5 to be the value of the determination error signal J (t) at t = 4 “1. 2 ”.

  (E) In step a3 of FIG. 7, the count value update unit 16 causes the count value CNT (t) at t = 5 to be “3”, which is the value of the match signal E (t) at t = 4. .

  (F) In step c8 of FIG. 9, the hold value update unit 17 updates the time from t = 4 to t = 5.

  Next, a change in the signal of the signal holding unit 14 at time t = 5 will be described.

  (A) Since the state signal C (t) is an invalid signal and is in an invalid state, the valid elapsed time INT (t) at t = 6 is “6”.

  (B) Since the match signal E (t) = 3 and the count value CNT (t) = 3, E (5) = CNT (5). Accordingly, the count value update unit 16 proceeds from step a2 in FIG. 7 to step a3, and the hold value update unit 17 proceeds from step c2 in FIG. 9 to step c3.

  (C) Since the determination error signal J (t) = 1.5 and the error holding value EAV (t) = 1.2, J (5)> EAV (5). Therefore, the hold value update unit 17 proceeds from step c3 to step c8 in FIG.

  (D) Since the process does not proceed to step c6 in FIG. 9, the hold value KEP (t + 1) at t = 6 is maintained at “4”.

  (E) In step a3 of FIG. 7, the count value CNT (t) at t = 6 is “3” which is the value of the match signal E (t) at t = 5.

  (F) Since the process does not proceed to step c7 in FIG. 9, the error holding value EAV (t + 1) at t = 6 is maintained at “1.2”.

  (G) In step c8 of FIG. 9, the time is updated from t = 5 to t = 6.

  Next, a change in the signal of the signal holding unit 14 at time t = 6 will be described.

  (A) Since the state signal C (t) is an invalid signal and is in an invalid state, the valid elapsed time INT (t) at t = 7 becomes “7” in step b2 of FIG.

  (B) Since E (t) = 5 and the count value CNT (t) = 3, E (6)> CNT (6), and the count value update unit 16 proceeds from step a2 to step a3 in FIG. Then, the hold value update unit 17 proceeds from step c2 to step c6 in FIG.

  (C) In step c6 of FIG. 9, the hold value KEP (t) at t = 7 becomes “6” which is the effective elapsed time INT (t) at t = 6.

  (D) In step a3 of FIG. 7, the count value CNT (t) at t = 7 becomes “5” which is the value of the match signal E (t) at t = 6.

  (E) In step c7 of FIG. 9, the error holding value EAV (t) at t = 7 becomes “1.7” which is the value of the determination error signal J (t) at t = 6.

  (F) In step c8 of FIG. 9, the time is updated from t = 6 to t = 7.

  Next, a change in the signal of the signal holding unit 14 at time t = 7 will be described.

  (A) Since the state signal C (t) is in an invalid state, the effective elapsed time INT (t) at t = 8 is “8” in step b2 of FIG.

  (B) Since the coincidence signal E (t) = 1 and the count value CNT (t) = 5, E (7) <CNT (7) is satisfied, and the count value update unit 16 performs the process after step a2 in FIG. The processing procedure ends, and the hold value update unit 17 proceeds from step c2 to step c5 and step c8 in FIG.

  (C) Since the process does not proceed to step c6 in FIG. 9, the hold value KEP (t + 1) at t = 8 is maintained at “6”.

  (D) Since the process does not proceed to step a3 in FIG. 7, the count value CNT (t + 1) at t = 8 is maintained at “5”.

  (E) Since the process does not proceed to step c7 in FIG. 9, the error holding value EAV (t + 1) at t = 8 is maintained at “1.7”.

  (F) In step c8 of FIG. 9, the time is updated from t = 7 to t = 8.

  Next, a change in the signal of the signal holding unit 14 at time t = 8 will be described.

  (A) Since the state signal C (t) is in an invalid state, the valid elapsed time INT (t) at t = 9 is “9”.

  (B) Since the coincidence signal E (t) = 5 and the count value CNT (t) = 5, E (8) = CNT (8), and the process proceeds from step a2 to step a3 in FIG. The process proceeds from step c2 to step c3.

  (C) Since the determination error signal J (t) = 0.3 and the error holding value EAV (t) = 1.7, J (8) <EAV (8), and the process proceeds from step c3 to step c6 in FIG. Transition.

  (D) In step c6 of FIG. 9, the hold value KEP (t) at t = 9 becomes “8” which is the effective elapsed time INT (t) at t = 8.

  (E) In step a3 of FIG. 7, the count value CNT (t) at t = 9 becomes “5” which is the value of the match signal E (t) at t = 8.

  (F) In step c7 of FIG. 9, the error holding value EAV (t) at t = 9 becomes “0.3” which is the value of the determination error signal J (t) at t = 8.

  (G) In step c8 of FIG. 9, the time is updated from t = 8 to t = 9.

  Next, a change in the signal of the signal holding unit 14 at time t = 9 will be described.

  (A) Since the state signal C (t) is in an invalid state, the valid elapsed time INT (t) at t = 10 is “10”.

  (B) Since the coincidence signal E (t) = 4 and the count value CNT (t) = 5, E (9) <CNT (9) is satisfied, and the count value update unit 16 performs the process after step a2 in FIG. The processing procedure ends, and the hold value update unit 17 proceeds from step c2 to step c5 and step c8 in FIG.

  (C) Since the process does not proceed to step c6 in FIG. 9, the hold value KEP (t + 1) at t = 10 is maintained at “8”.

  (D) Since the process does not proceed to step a3 in FIG. 7, the count value CNT (t + 1) at t = 10 is maintained at “5”.

  (E) Since the process does not proceed to step c7 in FIG. 9, the error holding value EAV (t + 1) at t = 10 is maintained at “0.3”.

  (F) In step c8 of FIG. 9, the time is updated from t = 9 to t = 10.

  Next, a change in the signal of the signal holding unit 14 at t = 10 will be described.

  (A) Since the state signal C (t) is a valid signal and is in a valid state, the valid elapsed time INT (t) at t = 11 becomes “1” in step b3 of FIG.

  (B) In step c4 of FIG. 9, the hold value update unit 17 outputs “8” that is the hold value KEP (t) at t = 10 as the hold signal P (t).

  (C) In step c6 of FIG. 9, the hold value KEP (t) at t = 11 becomes “1” which is the effective elapsed time INT (t) at t = 10.

  (D) In step a3 of FIG. 7, the count value CNT (t) at t = 11 becomes “2” which is the value of the match signal E (t) at t = 10.

  (E) In step c7 of FIG. 9, the error holding value EAV (t) at t = 11 becomes “0.9” which is the value of the determination error signal J (t) at t = 10.

  (F) In step c8 in FIG. 9, the time is updated from t = 10 to t = 11.

  Similarly, the signal holding unit 14 operates adaptively according to changes in the state signal C (t), the match signal E (t), and the count value CNT (t). By performing the determination process as described above, the signal holding unit 14 detects a case where the match signal E (t) input from a certain valid state to the next valid state becomes the maximum value. be able to. The signal holding unit 14 outputs the time when the maximum value is obtained as the holding signal P (t).

  For example, when the signal changes as shown in FIG. 10, the maximum value of the match signal E (t) input until the valid signal is generated is “5”, but the value is the time t = 6 and t It occurs twice at = 8. The value of the determination error signal J (t) at both times t = 6 and t = 8 is “1.7” when t = 6, and “0.3” when t = 8. The value of the determination error signal J (t) at t = 8 is more reliable. Therefore, the holding signal P (t) is “8”. In this way, the signal holding unit 14 can correctly output a highly reliable signal at the time when the match signal E (t) becomes maximum.

  Returning to FIG. 1, the signal selection unit 18 receives the received signal I (() based on the holding signal P (t) given from the signal holding unit 14 and the state signal C (t) given from the predetermined signal generating unit 13. The synchronization position of t) is determined, and a synchronization detection signal S (t) representing the synchronization position of the reception signal I (t) is output. The operation of determining the synchronization position of the reception signal I (t) by the signal selection unit 18 and outputting the synchronization detection signal S (t) in this way corresponds to a signal selection step.

  FIG. 11 is a block diagram illustrating a configuration of the signal selection unit 18. The signal selection unit 18 includes a synchronization signal generation unit 61, a delay addition unit 62, and a delay adjustment unit 63. The synchronization signal generator 61 outputs a detection signal indicating a synchronization state based on the state signal C (t) given from the predetermined signal generator 13. The detection signal output from the synchronization signal generation unit 61 is given to the delay adjustment unit 63.

  The delay adder 62 adds a predetermined time (hereinafter sometimes referred to as “addition time”) to the holding signal P (t) given from the signal holding unit 14 and outputs the addition result. The delay addition unit 62 gives the output addition result to the delay adjustment unit 63. The delay adjustment unit 63 delays the synchronization signal provided from the synchronization signal generation unit 61 based on the addition result provided from the delay addition unit 62, and outputs it as a synchronization detection signal S (t).

  According to the signal selection unit 18, first, when the state signal C (t) is a valid signal, the synchronization signal generation unit 61 outputs a detection signal indicating that the state signal C (t) is synchronized, and the state signal C (t) is an invalid signal. In the case of, a detection signal indicating that there is no synchronization is output. The delay adding unit 62 adds an addition time which is a predetermined time to the hold signal P (t), and outputs the addition result. Then, the output of the synchronization signal generation unit 61 is delayed by a time corresponding to the output of the delay addition unit 62 in the delay adjustment unit 63, and the result is output as the synchronization detection signal S (t). The addition time added by the delay adder 62 is preferably the time from the end of the known signal sequence to the synchronization position that is actually desired to be detected.

  FIG. 12 is a timing chart showing the operation timing of the signal selection unit 18. FIG. 12 shows a case where the head position of the information signal portion is detected as the synchronization position. In FIG. 12, a detection signal indicating synchronization is represented by a mark (|), a detection signal indicating non-synchronization is represented by a space (), and the synchronization detection signal S (t) is composed of these two values. It is supposed to be done.

  In the example shown in FIG. 12, it is assumed that an identification signal including a known signal sequence is periodically inserted into the received signal I (t). In addition, a valid signal in the state signal C (t) is represented by a mark (|), an invalid signal is represented by a space (), and the state signal C (t) is composed of these two values. The effective signal is a periodic signal, and the period is equal to the time length represented by the sum of the time length of the identification signal and the time length of the information signal. Furthermore, the addition time added by the delay addition unit 62 is assumed to be the time from the end of the known signal sequence to the synchronization position that is actually desired to be detected, and the time length is set to “1”.

  According to FIG. 12, the time interval between the signal start positions of adjacent identification signals is “10”, and the status signal C (t) becomes a valid signal at times t = 10, t = 20, and t = 30. At this time, the signal selection unit 18 outputs the synchronization detection signal S (t) through the following procedures (a) to (g).

  (A) When the match signal E (t) becomes maximum at time t = 14 in the previous procedure, the value of the match signal E (t) is “4”, and the synchronization position is at the position of time t = 14. Is confirmed.

  (B) At time t = 20, the hold signal P (t) = 4 is input to the delay adder 62 of the signal selector 18.

  (C) At time t = 20, the output of the synchronization signal generator 61 becomes “1”. That is, a detection signal indicating that synchronization has occurred is output from the synchronization signal generator 61.

  (D) The delay adding unit 62 adds a predetermined addition time “1” to the hold signal P (t) = 4, and outputs “5”.

  (E) In the delay adjustment unit 63, the detection signal output from the synchronization signal generation unit 61 is delayed by the time “5” that is the output result of the delay addition unit 62.

  (F) The synchronization detection signal S (t) becomes “1” at t = 25 and is output.

  From the above, (g) it can be detected that the time t = 25 is the head of the information signal portion, that is, the synchronization position to be detected.

  In FIG. 12, the time at the head of the information signal portion is t = 25, and the desired synchronization position can be correctly detected by configuring the signal selector 18 as described above. Thus, according to the present embodiment, it is possible to accurately detect the synchronization position of the received signal.

  Unlike the present embodiment, when synchronizing the received signal using the pattern matching method, applying the conventional technique for determining the allowable number of bit errors based on the power and amplitude of the received signal results in a delayed wave having a large power. In a multipath environment where the received signal power is present, the received signal power is relatively large, so that the number of allowable bit errors is set to a small value even though many errors occur. Therefore, there is a problem that it takes time to establish signal synchronization.

  In addition, even in a mobile reception environment where the phase of the received signal changes from moment to moment due to Doppler frequency shift accompanying movement, the number of allowable bit errors is set low despite the fact that many errors occur. There is a problem that it takes time to establish signal synchronization.

  On the other hand, in the signal synchronization apparatus 1 according to the present embodiment, even if many errors occur in the known signal sequence included in the received signal under the poor multipath environment as described above, the match signal E (t ) Only decreases. Similarly, in a poor mobile reception environment, even if many errors occur in the known signal sequence included in the received signal, the value of the match signal E (t) is only small. Therefore, by using the signal holding unit 14 and the signal selection unit 18, it is possible to continue to detect the maximum value of the match signal E (t) and increase the possibility of detecting synchronization.

  Further, according to the signal synchronization apparatus 1 of the present embodiment, even when the pattern matching method is used in a weak electric field environment in which the signal power of the desired wave of the received signal is about the same as or smaller than the noise power. Only the value of the match signal E (t) becomes small. Therefore, by using the signal holding unit 14 and the signal selection unit 18, it is possible to continue to detect the maximum value of the match signal E (t) and increase the possibility of detecting synchronization.

  Further, when the signal synchronization apparatus 1 according to the present embodiment is used, as a result of collation between the received signal sequence and the known signal sequence, collation is obtained at a plurality of positions due to the influence of signal error due to variation in received power. Even if it is a case, the degree of reliability can be determined by referring to the value of the determination error signal J (t) at the matching position. Therefore, the synchronization position of the received signal can be efficiently detected by determining the collation position with the highest reliability as the collation result that is estimated to be an accurate collation position.

  FIG. 13 is a graph showing an example of the relationship between the SN ratio (Signal to Noise ratio), which is the ratio of the received signal power to the noise power, and the synchronization success rate. The horizontal axis in FIG. 13 represents the SN ratio [dB], and the vertical axis represents the synchronization success rate [%]. The graph shown in FIG. 13 is a result of simple numerical calculation with the sequence length of the known signal sequence as “13” as an example, and the received signal sequence and the known signal sequence are collated using the pattern matching method. When the number of bit errors is less than or equal to the allowable number of bit errors p (p is an integer greater than or equal to 0), synchronization is considered successful. In FIG. 13, the result of the conventional technique in which the allowable number of bit errors p is fixed is indicated by a reference sign “A”, and the result of applying the signal synchronizer 1 of the present embodiment is indicated by a reference sign “B”.

  As shown in FIG. 13, in the conventional technique, when the allowable number of bit errors p is set to “0”, the synchronization success rate is not 100% when the SN ratio is 4 dB, and the synchronization success rate decreases as the SN ratio decreases. Gradually decreases. When the allowable bit error number p is set to “1” or “2”, the synchronization success rate at the same SN ratio becomes higher than when the allowable bit error number p is set to “0”, and the synchronization success rate is improved. .

  When the allowable bit error number p is set to “3”, the allowable bit error number p is set to another value “0”, “1” or “2” in an area where the SN ratio is less than −3 dB. However, in the region where the SN ratio is −3 dB or more, the synchronization success rate is not so improved as compared with the case where the other values are set. This is because, by setting the allowable number of bit errors p large, it is possible to establish synchronization in a weaker electric field, specifically, less than about −3 dB, but the normal electric field strength, specifically about − This is because the number of cases where synchronization is established at an incorrect position starts to increase at 3 dB or more.

  On the other hand, when the signal synchronizer 1 of the present embodiment is applied, the synchronization success rate is improved as compared with the case where the conventional technique for fixing the allowable bit error number p is applied, as shown in FIG. It turns out that it has improved. In addition, in the present embodiment, it is not necessary to use any information regarding the amplitude and power of the received signal in order to obtain the effect of improving the synchronization success rate. That is, according to the signal synchronization apparatus 1 of the present embodiment, the allowable bit error number p is set to an appropriate value according to the amplitude and power of the received signal without referring to any information regarding the amplitude and power of the received signal. Will be. Therefore, the synchronization position of the reception signal can be detected efficiently without depending on the nature of the reception signal.

As described above, according to the present embodiment, the signal synchronization apparatus 1 includes the signal determination unit 11, the match detection unit 12, the predetermined signal generation unit 13, the signal holding unit 14, and the signal selection unit 18. The signal determination unit 11 makes a hard decision on the original signal A (t) with the known signal sequence inserted and outputs the reception signal I (t), and also outputs the determination error signal J (t). Further, the match detection unit 12 outputs a match signal E (t) representing the degree of match between the received signal sequence F ₁ (t) and the known signal sequence F ₂ (t) obtained within a predetermined time interval. As the state signal C (t) representing the predetermined time interval, the predetermined signal generating unit 13 alternately generates and outputs a valid signal and an invalid signal.

  Based on the state signal C (t), the determination error signal J (t), and the match signal E (t), the signal holding unit 14 maximizes the match signal E (t) within the predetermined time interval. A holding signal P (t) representing the time of the hour is output. Based on the hold signal P (t) and the state signal C (t), the signal selector 18 determines the synchronization position of the reception signal I (t), and the synchronization detection signal S (t) representing the synchronization position. Is output.

  As described above, the determination error signal J (t) is a value calculated based on the absolute value of the difference between the amplitude of the original signal A (t) and the amplitude of the reception signal I (t). It can be used as a measure of the reliability of I (t). Since the hold signal P (t) is output based on the determination error signal J (t), the match signal E (t), and the state signal C (t), for example, the time when the match signal E (t) becomes maximum. Is detected, the time detected based on the most reliable received signal I (t) among these times can be output as the hold signal P (t).

Based on the hold signal P (t) and the state signal C (t), the synchronization position of the reception signal I (t) is determined and the synchronization detection signal S (t) is output. Therefore, the reception signal sequence F ₁ Of the collation positions between (t) and the known signal sequence F ₂ (t), the collation position with the highest reliability can be determined as the synchronization position of the received signal I (t).

  As a result, the synchronization position of the reception signal I (t) can be efficiently detected without depending on the nature of the reception signal I (t), such as amplitude and power. Therefore, the synchronization position of the received signal I (t) can be efficiently detected even in a poor transmission / reception environment where the power of the delay wave or the interference wave or the noise power is large.

  Specifically, according to the present embodiment, the number of allowable bit errors is set to an appropriate value according to the amplitude and power of the received signal without referring to any information regarding the amplitude and power of the received signal. Will be. Therefore, the synchronization position of the reception signal can be detected efficiently without depending on the nature of the reception signal.

  Further, according to the present embodiment, the received signal sequence and the known signal in the pattern matching method are used in a weak electric field environment in which the desired wave in the received signal, that is, the signal power of the information signal is approximately equal to or smaller than the noise power. Since the allowable number of bit errors when collating with the sequence is automatically set large, the synchronization position of the received signal can be detected efficiently.

  Further, according to the present embodiment, even when the received signal power is relatively large, the allowable bit error when collating the received signal sequence with the known signal sequence without using any information on the transmission path environment. The number will automatically be adjusted to the appropriate value. Therefore, even in a multipath environment where there is a delayed wave, or in a mobile reception environment where the phase of the received signal changes from moment to moment due to a Doppler frequency shift accompanying movement, the received signal is synchronized. The position can be detected efficiently.

  According to the present embodiment, as a result of collation between the received signal sequence and the known signal sequence, even when collation is obtained at a plurality of positions, information on reliability of a plurality of collation results, for example, determination By referring to the error signal J (t), it is possible to determine only one collation result that is estimated to be an accurate collation position. Therefore, the synchronization position of the received signal can be detected efficiently.

  By configuring such a receiver with such a signal synchronizer 1, the received signal can be accurately demodulated and reproduced.

  In the present embodiment, the signal determination unit 11 includes a threshold determination unit 22 and an output adjustment unit 25 as reception signal output units, and includes a normalization unit 23 and an averaging unit 24 as error signal output units. As a result, the signal synchronization apparatus 1 that can efficiently detect the synchronization position of the received signal as described above can be realized.

  In the present embodiment, the signal holding unit 14 includes a time update unit 15, a count value update unit 16, and a hold value update unit 17. As a result, the signal synchronization apparatus 1 that can efficiently detect the synchronization position of the received signal as described above can be realized.

  In the present embodiment, the time updating unit 15 initializes the valid elapsed time when the status signal is a valid signal, and represents the elapsed time from the initialized time when the status signal is an invalid signal. It has a function of outputting a signal as a signal representing an effective elapsed time. Further, if the status signal is a valid signal, the hold value update unit 17 outputs the hold value as a hold signal, then sets the hold value as a valid elapsed time, and outputs the value of the determination error signal as an error hold value. If the signal is an invalid signal and the match signal is equal to the count value, and the decision error signal is smaller than the error hold value, the hold value is the valid elapsed time, the error hold value is the decision error signal value, and the status signal Is an invalid signal and the match signal is larger than the count value, the holding value is set as the valid elapsed time, and the error holding value is set as the value of the determination error signal.

  The count value updating unit 16 sets the count value as the match signal value when the status signal is a valid signal, and sets the count value as the match signal when the status signal is an invalid signal and the match signal is greater than the count value. It has the function to do. As a result, the signal synchronizer 1 that can efficiently detect the synchronization position of the received signal as described above can be realized with a simple configuration.

  In the present embodiment, the match detection unit 12 includes a conversion unit 31, a sequence generation unit 32, a comparison unit 33, and a determiner 34. As a result, the signal synchronization apparatus 1 that can efficiently detect the synchronization position of the received signal as described above can be realized.

In the present embodiment, as shown in FIG. 4, the comparison unit 33 calculates an exclusive OR of the converted received signal sequence F ₁ (t) and the known signal sequence F ₂ (t), A value calculated based on the calculation result is output to the determination unit 34 as a comparison result signal. Thereby, the comparison unit 33 can be realized with a simple configuration.

  In the present embodiment, the determiner 34 includes a subtractor 51. In the subtractor 51, the value of the output signal from the comparison unit 33, which is a comparison result signal, is subtracted from the determination reference value, and the value is matched with the match signal. Output as E (t). As a result, the determiner 34 can be realized with a simple configuration.

  Further, in the present embodiment, the signal selection unit 18 starts to measure the elapsed time based on the case where the state signal changes from the invalid signal to the valid signal or when the status signal changes from the valid signal to the invalid signal. When the elapsed time is equal to the value obtained by adding a predetermined time to the value of the holding signal, the synchronization detection signal is output. Thus, the signal selection unit 18 can be realized with a simple configuration.

<Second Embodiment>
Next, the signal synchronizer which is the 2nd Embodiment of this invention is demonstrated. The signal synchronization apparatus according to the present embodiment has the same configuration as the signal synchronization apparatus 1 according to the first embodiment described above except for the signal holding unit 14 and the signal selection unit 18. The same reference numerals are attached, and illustration and common description are omitted. Since the configuration of the signal holding unit in the present embodiment is the same as the configuration of the signal holding unit 14 in the first embodiment described above, illustration and common description are omitted. The operation of the signal holding unit 14 in the present embodiment is different from that of the signal holding unit 14 in the first embodiment. Each operation procedure of the count value update unit 16 and the hold value update unit 17 in the signal holding unit 14 is the same as the operation procedure of the flowcharts shown in FIGS. 7 and 9 of the first embodiment described above. The common explanation is omitted.

  In the signal holding unit 14 according to the present embodiment, when the state signal C (t) is a valid signal in the time updating unit 15, the initial value when initializing the valid elapsed time of the next time is “−1”. This is different from the signal holding unit 14 in the first embodiment.

  FIG. 14 is a flowchart showing an operation procedure of the time update unit 15 of the signal holding unit 14 according to the second embodiment of the present invention. Processing of each step in the flowchart shown in FIG. 14 is processed by the time update unit 15. The process of the flowchart shown in FIG. 14 is started when the state signal C (t) is given from the predetermined signal generator 13, and proceeds to step d1.

  In step d1, the time updating unit 15 determines whether or not the status signal C (t) is an invalid signal, as in step b1 shown in FIG. 8. If it is determined that it is an invalid signal, the time update unit 15 proceeds to step d2. If it is determined that the signal is not an invalid signal, in other words, a valid signal, the process proceeds to step d3.

  In step d2, the time update unit 15 updates the valid elapsed time INT (t + 1) at the next time, similarly to step b2 shown in FIG. 8, and then ends all processing procedures. In step d3, the time updating unit 15 sets the effective elapsed time INT (t + 1) at the next time to “−1”, and ends all processing procedures.

  FIG. 15 is a block diagram illustrating a configuration of the signal selection unit 18A according to the second embodiment of this invention. Since the signal selection unit 18A of the present embodiment is similar in configuration to the signal selection unit 18 of the first embodiment described above, the corresponding parts are denoted by the same reference numerals and are described in common. Omitted and different parts will be described.

  The signal selection unit 18A includes a non-negative determination unit 64 in addition to the synchronization signal generation unit 61, the delay addition unit 62, and the delay adjustment unit 63 that constitute the signal selection unit 18 of the first embodiment described above. The non-negative determination unit 64 can temporarily stop the output from the delay adjustment unit 63 according to the sign of the holding signal P (t) given from the signal holding unit 14. More specifically, when the hold signal P (t) is “−1”, the non-negative determination unit 64 stops the output from the delay adjustment unit 63 and the hold signal P (t) is “−1”. When the value is other than the value, the output from the delay adjustment unit 63 is output as the synchronization detection signal S (t).

  For example, in the above-described first embodiment, when the signal holding unit 14 operates according to the operation procedure of the flowcharts shown in FIGS. 7 to 9 and the signal selection unit 18 is configured as shown in FIG. When P (t) is “0”, it is impossible to determine whether the position where the state signal C (t) is a valid signal is equal to the synchronous position or the asynchronous state.

  On the other hand, if the holding signal P (t) is “−1” by adopting the configuration as in the present embodiment, the position where the state signal C (t) becomes an effective signal is defined as the synchronization detection position. If the holding signal P (t) is “0”, it can be determined that the state is asynchronous. Therefore, it is possible to distinguish between the case where the position where the state signal C (t) is a valid signal is equal to the synchronous position and the case where the state signal C (t) is an asynchronous state. In the present embodiment, the initial value “−1” of the holding signal P (t) is shown as an example of a negative number, and is not limited to this value.

  As described above, according to the present embodiment, the signal selection unit 18A is either in the case where the state signal C (t) changes from the invalid signal to the valid signal or in the case where the valid signal changes from the valid signal to the invalid signal. Measure the elapsed time from the base point, and output the synchronization detection signal S (t) when the elapsed time is equal to a value obtained by adding a predetermined time to the value of the holding signal and the holding signal is a predetermined value. To do. As a result, it is possible to distinguish between the case where the position where the state signal C (t) becomes a valid signal is equal to the synchronous position and the case where the state signal C (t) is in the asynchronous state. Therefore, the synchronization position of the reception signal I (t) can be detected accurately.

<Third Embodiment>
Next, the signal synchronizer which is the 3rd Embodiment of this invention is demonstrated. The signal synchronization apparatus according to the present embodiment has the same configuration as that of the signal synchronization apparatus 1 according to the first embodiment described above except for the determination unit 34 of the match detection unit 12. Reference numerals are attached, and illustration and common description are omitted. FIG. 16 is a block diagram illustrating a configuration of the determination unit 34A included in the match detection unit 12 according to the third embodiment of the present invention. Since the determination unit 34A of the present embodiment is similar in configuration to the determination unit 34 of the first embodiment described above, the same reference numerals are given to corresponding portions, and common description is omitted. The different parts will be described.

  The determination unit 34A includes a delay unit 53 and a comparison determination unit 54 in addition to the subtractor 51 and the predetermined value storage unit 52 that constitute the determination unit 34 of the first embodiment. The delay unit 53 outputs a delay signal D (t) obtained by delaying the output signal Q (t) output from the subtractor 51 using one or more types of predetermined delay times. The comparison / determination unit 54 uses the output signal Q (t) from the subtractor 51 and a part or all of the delay signal D (t), which is the output signal from the delay unit 53, from among these values. The minimum value is determined, and the value of the determination result is output as the match signal E (t). The value of the output signal Q (t) output from the subtractor 51 is a value obtained by subtracting the output value of the comparison unit 33 shown in FIG. 3 from the determination reference value that is a predetermined value stored in the predetermined value storage unit 52. is there.

  More specifically, the comparison / determination unit 54 delays the value of the output signal Q (t) from the subtractor 51 and the value of the output signal Q (t) from the subtractor 51 by a delay unit 53 by a predetermined time. The logical product operation with the value of the signal D (t) is performed, and the value of the operation result is output as the match signal E (t).

  FIG. 17 is a timing chart illustrating the output timing of the match signal E (t) in the determination unit 34 according to the first embodiment of this invention. FIG. 18 is a timing chart showing the output timing of the match signal E (t) in the determiner 34A according to the third embodiment of this invention. FIG. 18 shows a case where a known signal sequence is inserted twice in succession, and the time length of the known signal sequence is “3”. In FIG. 18, the delay signal D (t), which is the output signal of the delay unit 53 shown in FIG. 16, is one type, and the predetermined delay time is equal to the time length of the known signal sequence and is “3”.

  As shown in FIG. 17, in the first embodiment, at time t = 5, which is the end point of the known signal sequence, the match signal E (t) takes the maximum value “6”, but the information signal is Even during reception, the value of the match signal E (t) increases due to the influence of noise, and the match signal E (t) is “6” by chance at time t = 24. In addition, since these occur simultaneously in the adjacent valid signal section of the state signal C (t), the maximum value of the coincidence signal E (t) is detected twice in the valid signal section. At this time, when the signal holding unit 14 operates according to the flowcharts shown in FIGS. 7 to 9, the value of the determination error signal J (t) is detected out of the two times when the maximum value of the match signal E (t) is detected. The smaller one is detected as the synchronization position.

  On the other hand, in the present embodiment, as shown in FIG. 18, since the known signal sequence is continuously inserted twice, the output signal Q that is the output of the subtractor 51 in the determiner 34A shown in FIG. (T) takes a maximum value at time t = 5 and time t = 8, which are the end points of the known signal series. However, since the influence of noise is different at different times, Q (t) = 6 at time t = 5 and Q (t) = 7 at time t = 8 so as not to lose generality.

  Also in the case shown in FIG. 18, similarly to the case shown in FIG. 17, even when the information signal is being received, the output signal Q (t ) Is “6”. At this time, the determiner 34A compares the output signal Q (t) of the subtractor 51 with the signal Q (t-3) obtained by delaying the output signal Q (t) by time “3”, and the smaller of them. Is output as the match signal E (t), the signal sequence of the match signal E (t) is as shown in FIG.

  As a result, the match signal E (t) takes the maximum value “6” at time t = 8, which is the time point when the known signal series is detected twice. At time t = 30, the output signal Q (t) from the subtractor 51 at time t = 27 is compared with the output signal Q (t) from the subtractor 51 at time t = 30, so that the match signal E ( t) is "3". Therefore, the maximum value of the coincidence signal E (t) detected in the adjacent valid signal section of the state signal C (t) is only the value “6” at time t = 8.

  As described above, according to the present embodiment, the determination unit 34A is configured as shown in FIG. 16, and communication is performed using a signal in which a known signal sequence is repeatedly inserted twice or more continuously. The accuracy of establishment of synchronization can be further increased.

  In the present embodiment, the delay signal D (t) that is the output signal of the delay unit 53 in FIG. 16 is one type. However, in another embodiment of the present invention, the number of repetitions for inserting a known signal sequence is further increased. The delay signal D (t) may be increased to two or more types by increasing the number. By setting the delay signal D (t) to two or more types, the number of cases where the synchronization position can be detected can be further increased. More specifically, if the known signal series is repeated indefinitely and the number of types of the delay signal D (t) is the same as the number of repetitions, only the correct synchronization position can be detected. Accordingly, it is possible to reduce the case where an accurate synchronization position and an erroneous synchronization position are detected at the same time, and it is possible to improve the accuracy of detection of the accurate synchronization position.

  DESCRIPTION OF SYMBOLS 1 Signal synchronizer, 11 Signal determination part, 12 Match detection part, 13 Predetermined signal generation part, 14 Signal holding part, 15 Time update part, 16 Count value update part, 17 Hold value update part, 18, 18A Signal selection part, 21 threshold generation unit, 22 threshold determination unit, 23 normalization unit, 24 averaging unit, 25 output adjustment unit, 31 conversion unit, 32 series generation unit, 33 comparison unit, 34, 34A determination unit, 41 calculation unit, 42 processing Unit 51 subtractor 52 predetermined value storage unit 53 delay unit 54 comparison determination unit 61 synchronization signal generation unit 62 delay addition unit 63 delay adjustment unit 64 non-negative determination unit

Claims (11)

A synchronization position of a received signal obtained from the original signal in a receiving apparatus that receives and communicates an original signal in which a known signal sequence composed of a predetermined known signal is repeatedly inserted once or continuously twice A signal synchronizer for detecting,
A signal determination unit that hard-determines the original signal and outputs the received signal, and outputs a value calculated based on the absolute value of the difference between the amplitude of the original signal and the amplitude of the received signal as a determination error signal When,
A match detection unit that holds the known signal sequence in advance, and outputs a match signal that represents the degree of match between the received signal sequence composed of the received signal obtained in a predetermined time interval and the known signal sequence;
As the state signal representing the predetermined time interval, a predetermined signal generation unit that alternately generates and outputs an effective signal indicating an effective state and an invalid signal indicating an invalid state; and
Based on the determination error signal, the match signal, and the status signal, a signal holding unit that outputs a hold signal indicating a time when the match signal becomes maximum within the predetermined time interval;
A signal synchronization apparatus comprising: a signal selection unit that determines a synchronization position of the reception signal based on the hold signal and the state signal and outputs a synchronization detection signal representing the synchronization position of the reception signal . The signal determination unit
When the original signal exceeds a predetermined threshold, a predetermined first state value is output as the received signal, and when the original signal is equal to or less than the predetermined threshold, a predetermined second state value is output as the received signal. Receiving signal output means,
Error signal output means for outputting, as the determination error signal, a value obtained by averaging a value obtained by normalizing an absolute value of a difference between the amplitude of the original signal and the amplitude of the received signal with the predetermined threshold value a predetermined number of times; The signal synchronizer according to claim 1, further comprising: The signal holding unit is
A time updating unit that outputs a signal representing an effective elapsed time from the time when the effective state is reached;
A count value update unit that holds the maximum value of the match signal output within the predetermined time interval as a count value;
The signal synchronization apparatus according to claim 1, further comprising: a hold value update unit that holds a time when the match signal becomes maximum within the predetermined time interval as a hold value. The match detection unit
A converter that converts the received signal obtained in the predetermined time interval so as to be simultaneously processable, and outputs a converted signal sequence composed of the obtained converted signal;
A sequence generator for holding and outputting the known signal sequence in advance;
A comparison unit that compares the converted signal sequence with the known signal sequence and outputs the comparison result as a comparison result signal;
4. The apparatus according to claim 1, further comprising: a determinator that compares a value of the comparison result signal with a predetermined determination reference value and outputs the comparison result as the match signal. 5. Signal synchronizer.   The comparison unit calculates an exclusive OR of the converted signal sequence and the known signal sequence, and outputs a value calculated based on the calculation result as the comparison result signal. A signal synchronizer according to claim 1.   The signal synchronizer according to claim 4, wherein the determination unit includes a subtracter that outputs a value obtained by subtracting the value of the comparison result signal from the determination reference value as the match signal. The determiner is
A subtractor that outputs a value obtained by subtracting the value of the comparison result signal from the determination reference value as an output signal;
Comparing an output signal from the subtractor with a delayed signal obtained by delaying the output signal from the subtractor by a predetermined time, and a comparison / determination unit that outputs the comparison result as the match signal. 6. The signal synchronizer according to claim 4 or 5, characterized in that: The time update unit initializes the valid elapsed time when the state signal is a valid signal, and when the state signal is an invalid signal, the time update unit outputs a signal representing the elapsed time from the initialized time. It has a function to output as a signal indicating elapsed time,
The holding value update unit
When the status signal is a valid signal, the holding value is output as the holding signal, the holding value is set as the effective elapsed time, and the value of the determination error signal is output as an error holding value.
When the status signal is an invalid signal and the match signal is equal to the count value, and the determination error signal is smaller than the error holding value, the error holding value is set to the holding value as the effective elapsed time. The value of the determination error signal,
When the status signal is an invalid signal and the match signal is greater than the count value, the holding value is the valid elapsed time, and the error holding value is a value of the determination error signal,
The count value updating unit sets the count value as the value of the match signal when the status signal is a valid signal, and when the status signal is an invalid signal and the match signal is greater than the count value, The signal synchronizer according to claim 3, which has a function of using a count value as the match signal.   The signal selection unit starts to measure the elapsed time when the state signal changes from the invalid signal to the valid signal or when the status signal changes from the valid signal to the invalid signal. 9. The signal synchronization apparatus according to claim 1, wherein the synchronization detection signal is output when the value is equal to a value obtained by adding a predetermined time to the value of the holding signal.   The signal selection unit starts to measure the elapsed time when the state signal changes from the invalid signal to the valid signal or when the status signal changes from the valid signal to the invalid signal. The synchronization detection signal is output when the holding signal is equal to a value obtained by adding a predetermined time to the value of the holding signal, and the holding signal is a predetermined value. The signal synchronizer of description. A synchronization position of a received signal obtained from the original signal in a receiving apparatus that receives and communicates an original signal in which a known signal sequence composed of a predetermined known signal is repeatedly inserted once or continuously twice A signal synchronization method for detecting,
A known signal holding step for holding the known signal sequence in advance;
A signal determination step of hard-decisioning the original signal and outputting the received signal, and outputting a value calculated based on an absolute value of a difference between the amplitude of the original signal and the amplitude of the received signal as a determination error signal When,
A coincidence detecting step for outputting a coincidence signal representing a degree of coincidence between the received signal sequence composed of the received signal obtained in a predetermined time interval and the known signal sequence held in the known signal holding step;
A predetermined signal generating step for alternately generating and outputting an effective signal indicating that it is in an effective state and an invalid signal indicating that it is in an inactive state as a state signal indicating the predetermined time interval;
Based on the determination error signal, the match signal, and the status signal, a signal holding step for outputting a hold signal that represents a time when the match signal becomes maximum within the predetermined time interval;
A signal synchronization method comprising: a signal selection step of determining a synchronization position of the reception signal based on the holding signal and the state signal and outputting a synchronization detection signal representing the synchronization position of the reception signal. .

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